Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12797752	1			T1	32626		T2	11945		T3	648
all_pins[1]	12797752	1			T1	32626		T2	11945		T3	648
all_pins[2]	12797752	1			T1	32626		T2	11945		T3	648

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	36360478	1			T1	79251		T2	35799		T3	1305
values[0x1]	2032778	1			T1	18627		T2	36		T3	639
transitions[0x0=>0x1]	2032666	1			T1	18627		T2	36		T3	639
transitions[0x1=>0x0]	2032685	1			T1	18627		T2	36		T3	639

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12754253	1			T1	32607		T2	11909		T3	648
all_pins[0]	values[0x1]	43499	1			T1	19		T2	36		T4	4
all_pins[0]	transitions[0x0=>0x1]	43442	1			T1	19		T2	36		T4	4
all_pins[0]	transitions[0x1=>0x0]	1988897	1			T1	18608		T3	639		T7	10872
all_pins[1]	values[0x0]	12797408	1			T1	32626		T2	11945		T3	648
all_pins[1]	values[0x1]	344	1			T17	3		T14	3		T20	1
all_pins[1]	transitions[0x0=>0x1]	319	1			T17	2		T14	3		T20	1
all_pins[1]	transitions[0x1=>0x0]	43474	1			T1	19		T2	36		T4	4
all_pins[2]	values[0x0]	10808817	1			T1	14018		T2	11945		T3	9
all_pins[2]	values[0x1]	1988935	1			T1	18608		T3	639		T7	10872
all_pins[2]	transitions[0x0=>0x1]	1988905	1			T1	18608		T3	639		T7	10872
all_pins[2]	transitions[0x1=>0x0]	314	1			T17	2		T14	3		T20	1