Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.93 92.46 85.24 100.00 76.32 85.93 99.49 69.08


Total test records in report: 727
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T535 /workspace/coverage/default/16.hmac_error.1133003344 Apr 18 12:56:13 PM PDT 24 Apr 18 12:57:34 PM PDT 24 19062423015 ps
T91 /workspace/coverage/default/16.hmac_stress_all.2313947031 Apr 18 12:56:24 PM PDT 24 Apr 18 12:56:53 PM PDT 24 7516980344 ps
T38 /workspace/coverage/default/4.hmac_sec_cm.902530099 Apr 18 12:55:47 PM PDT 24 Apr 18 12:55:48 PM PDT 24 187595356 ps
T536 /workspace/coverage/default/37.hmac_burst_wr.4024377248 Apr 18 12:57:52 PM PDT 24 Apr 18 12:58:44 PM PDT 24 8799340529 ps
T537 /workspace/coverage/default/13.hmac_smoke.2324480052 Apr 18 12:56:10 PM PDT 24 Apr 18 12:56:19 PM PDT 24 2817392010 ps
T538 /workspace/coverage/default/42.hmac_smoke.3728929469 Apr 18 12:58:19 PM PDT 24 Apr 18 12:58:24 PM PDT 24 268027988 ps
T539 /workspace/coverage/default/49.hmac_datapath_stress.444629724 Apr 18 12:58:53 PM PDT 24 Apr 18 12:59:08 PM PDT 24 1758955677 ps
T540 /workspace/coverage/default/42.hmac_long_msg.3814666692 Apr 18 12:58:22 PM PDT 24 Apr 18 12:58:58 PM PDT 24 9075180930 ps
T541 /workspace/coverage/default/41.hmac_long_msg.4132170246 Apr 18 12:58:13 PM PDT 24 Apr 18 12:58:46 PM PDT 24 595320587 ps
T542 /workspace/coverage/default/8.hmac_burst_wr.4171918126 Apr 18 12:56:01 PM PDT 24 Apr 18 12:56:32 PM PDT 24 6090774763 ps
T543 /workspace/coverage/default/34.hmac_test_sha_vectors.4008847992 Apr 18 12:57:43 PM PDT 24 Apr 18 01:06:41 PM PDT 24 42011547963 ps
T544 /workspace/coverage/default/49.hmac_burst_wr.2731182462 Apr 18 12:58:51 PM PDT 24 Apr 18 12:58:58 PM PDT 24 381399230 ps
T545 /workspace/coverage/default/47.hmac_test_sha_vectors.2285010513 Apr 18 12:58:44 PM PDT 24 Apr 18 01:05:32 PM PDT 24 7645770322 ps
T51 /workspace/coverage/default/1.hmac_error.967110327 Apr 18 12:55:34 PM PDT 24 Apr 18 12:56:22 PM PDT 24 9861226823 ps
T546 /workspace/coverage/default/40.hmac_burst_wr.56212833 Apr 18 12:58:09 PM PDT 24 Apr 18 12:58:14 PM PDT 24 324995814 ps
T547 /workspace/coverage/default/24.hmac_back_pressure.932764452 Apr 18 12:56:58 PM PDT 24 Apr 18 12:57:44 PM PDT 24 1304834595 ps
T548 /workspace/coverage/default/19.hmac_alert_test.1688664176 Apr 18 12:56:39 PM PDT 24 Apr 18 12:56:40 PM PDT 24 24254011 ps
T549 /workspace/coverage/default/21.hmac_error.2697423118 Apr 18 12:56:52 PM PDT 24 Apr 18 12:57:35 PM PDT 24 2798595580 ps
T550 /workspace/coverage/default/44.hmac_back_pressure.2566043133 Apr 18 12:58:24 PM PDT 24 Apr 18 12:59:05 PM PDT 24 20902743993 ps
T551 /workspace/coverage/default/5.hmac_datapath_stress.3665685545 Apr 18 12:56:02 PM PDT 24 Apr 18 12:58:31 PM PDT 24 16967283302 ps
T552 /workspace/coverage/default/49.hmac_wipe_secret.3593446956 Apr 18 12:58:54 PM PDT 24 Apr 18 12:59:10 PM PDT 24 5046145059 ps
T553 /workspace/coverage/default/17.hmac_test_hmac_vectors.70269632 Apr 18 12:56:20 PM PDT 24 Apr 18 12:56:23 PM PDT 24 57381939 ps
T554 /workspace/coverage/default/5.hmac_test_hmac_vectors.4094871833 Apr 18 12:55:46 PM PDT 24 Apr 18 12:55:48 PM PDT 24 152732585 ps
T555 /workspace/coverage/default/1.hmac_test_hmac_vectors.2857111951 Apr 18 12:55:42 PM PDT 24 Apr 18 12:55:44 PM PDT 24 547623918 ps
T556 /workspace/coverage/default/34.hmac_long_msg.4165915928 Apr 18 12:57:47 PM PDT 24 Apr 18 12:59:05 PM PDT 24 5781247105 ps
T557 /workspace/coverage/default/28.hmac_long_msg.1000826755 Apr 18 12:57:14 PM PDT 24 Apr 18 12:57:18 PM PDT 24 816442615 ps
T558 /workspace/coverage/default/2.hmac_burst_wr.973075012 Apr 18 12:55:36 PM PDT 24 Apr 18 12:56:17 PM PDT 24 2875783519 ps
T559 /workspace/coverage/default/25.hmac_burst_wr.1688450738 Apr 18 12:56:59 PM PDT 24 Apr 18 12:57:39 PM PDT 24 2097594045 ps
T560 /workspace/coverage/default/23.hmac_alert_test.1131817301 Apr 18 12:56:58 PM PDT 24 Apr 18 12:57:00 PM PDT 24 13099556 ps
T561 /workspace/coverage/default/19.hmac_back_pressure.2649433661 Apr 18 12:56:32 PM PDT 24 Apr 18 12:57:20 PM PDT 24 5128997407 ps
T562 /workspace/coverage/default/12.hmac_burst_wr.4008226836 Apr 18 12:56:09 PM PDT 24 Apr 18 12:56:32 PM PDT 24 1089247696 ps
T563 /workspace/coverage/default/48.hmac_test_sha_vectors.1377491822 Apr 18 12:58:49 PM PDT 24 Apr 18 01:07:22 PM PDT 24 143387739600 ps
T564 /workspace/coverage/default/21.hmac_smoke.2574465097 Apr 18 12:56:45 PM PDT 24 Apr 18 12:56:49 PM PDT 24 518295619 ps
T565 /workspace/coverage/default/7.hmac_error.2825688210 Apr 18 12:55:59 PM PDT 24 Apr 18 12:57:02 PM PDT 24 2474801224 ps
T566 /workspace/coverage/default/31.hmac_long_msg.1294796417 Apr 18 12:57:24 PM PDT 24 Apr 18 12:58:15 PM PDT 24 14506012315 ps
T567 /workspace/coverage/default/48.hmac_datapath_stress.1257007664 Apr 18 12:58:46 PM PDT 24 Apr 18 01:00:41 PM PDT 24 8633271662 ps
T568 /workspace/coverage/default/45.hmac_datapath_stress.1966919126 Apr 18 12:58:28 PM PDT 24 Apr 18 12:58:38 PM PDT 24 191721614 ps
T569 /workspace/coverage/default/12.hmac_smoke.3955875424 Apr 18 12:56:13 PM PDT 24 Apr 18 12:56:18 PM PDT 24 345537331 ps
T570 /workspace/coverage/default/21.hmac_test_hmac_vectors.1840921718 Apr 18 12:56:44 PM PDT 24 Apr 18 12:56:46 PM PDT 24 198170335 ps
T571 /workspace/coverage/default/17.hmac_error.2874932325 Apr 18 12:56:26 PM PDT 24 Apr 18 12:57:02 PM PDT 24 7599770207 ps
T572 /workspace/coverage/default/36.hmac_wipe_secret.1335632176 Apr 18 12:57:47 PM PDT 24 Apr 18 12:58:38 PM PDT 24 4198389955 ps
T573 /workspace/coverage/default/22.hmac_burst_wr.2977383847 Apr 18 12:56:51 PM PDT 24 Apr 18 12:57:51 PM PDT 24 12786619453 ps
T574 /workspace/coverage/default/46.hmac_burst_wr.2218840784 Apr 18 12:58:33 PM PDT 24 Apr 18 12:58:45 PM PDT 24 494809164 ps
T575 /workspace/coverage/default/16.hmac_test_hmac_vectors.3483494139 Apr 18 12:56:20 PM PDT 24 Apr 18 12:56:23 PM PDT 24 1312714517 ps
T576 /workspace/coverage/default/29.hmac_burst_wr.1395809907 Apr 18 12:57:19 PM PDT 24 Apr 18 12:57:49 PM PDT 24 17938873131 ps
T577 /workspace/coverage/default/2.hmac_error.3093780695 Apr 18 12:55:35 PM PDT 24 Apr 18 12:58:32 PM PDT 24 14610166732 ps
T578 /workspace/coverage/default/35.hmac_error.4129314520 Apr 18 12:57:41 PM PDT 24 Apr 18 12:59:04 PM PDT 24 47969838615 ps
T579 /workspace/coverage/default/28.hmac_smoke.2663926285 Apr 18 12:57:14 PM PDT 24 Apr 18 12:57:19 PM PDT 24 158565515 ps
T580 /workspace/coverage/default/0.hmac_burst_wr.3619155180 Apr 18 12:55:28 PM PDT 24 Apr 18 12:56:05 PM PDT 24 2638531456 ps
T581 /workspace/coverage/default/15.hmac_back_pressure.1544725725 Apr 18 12:56:13 PM PDT 24 Apr 18 12:56:20 PM PDT 24 169196670 ps
T582 /workspace/coverage/default/4.hmac_alert_test.3357598651 Apr 18 12:55:49 PM PDT 24 Apr 18 12:55:50 PM PDT 24 61148082 ps
T583 /workspace/coverage/default/13.hmac_wipe_secret.444566827 Apr 18 12:56:11 PM PDT 24 Apr 18 12:57:14 PM PDT 24 1685151370 ps
T584 /workspace/coverage/default/29.hmac_test_sha_vectors.3224508517 Apr 18 12:57:17 PM PDT 24 Apr 18 01:04:35 PM PDT 24 149441519345 ps
T585 /workspace/coverage/default/4.hmac_error.2568855120 Apr 18 12:55:46 PM PDT 24 Apr 18 12:55:57 PM PDT 24 194154866 ps
T586 /workspace/coverage/default/39.hmac_test_sha_vectors.1070047422 Apr 18 12:58:05 PM PDT 24 Apr 18 01:05:22 PM PDT 24 32797085384 ps
T587 /workspace/coverage/default/0.hmac_long_msg.3800935290 Apr 18 12:55:33 PM PDT 24 Apr 18 12:55:48 PM PDT 24 2205063391 ps
T588 /workspace/coverage/default/11.hmac_back_pressure.2282340417 Apr 18 12:56:08 PM PDT 24 Apr 18 12:56:43 PM PDT 24 3055152703 ps
T589 /workspace/coverage/default/43.hmac_back_pressure.3445941424 Apr 18 12:58:18 PM PDT 24 Apr 18 12:58:59 PM PDT 24 8553243731 ps
T590 /workspace/coverage/default/41.hmac_stress_all.3185540372 Apr 18 12:58:13 PM PDT 24 Apr 18 01:02:37 PM PDT 24 152622291419 ps
T591 /workspace/coverage/default/38.hmac_long_msg.1523705688 Apr 18 12:57:52 PM PDT 24 Apr 18 12:58:46 PM PDT 24 4060077480 ps
T592 /workspace/coverage/default/38.hmac_smoke.3900307584 Apr 18 12:57:54 PM PDT 24 Apr 18 12:57:59 PM PDT 24 136689402 ps
T593 /workspace/coverage/default/12.hmac_alert_test.1402411262 Apr 18 12:56:06 PM PDT 24 Apr 18 12:56:08 PM PDT 24 17329168 ps
T73 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.516134999 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:29 PM PDT 24 51104525 ps
T69 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3322086903 Apr 18 01:50:23 PM PDT 24 Apr 18 01:50:25 PM PDT 24 72004383 ps
T74 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2981883078 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:29 PM PDT 24 29277767 ps
T92 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1951420800 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:33 PM PDT 24 60824630 ps
T76 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2001580832 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:36 PM PDT 24 453907507 ps
T70 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.232758410 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:14 PM PDT 24 188997638 ps
T98 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1830559950 Apr 18 01:50:19 PM PDT 24 Apr 18 01:50:22 PM PDT 24 1594174601 ps
T594 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1857430636 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:29 PM PDT 24 21661182 ps
T71 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.602584509 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:32 PM PDT 24 571049206 ps
T93 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3108118368 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:32 PM PDT 24 40061584 ps
T595 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.217940748 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:34 PM PDT 24 150579968 ps
T596 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.642454602 Apr 18 01:50:18 PM PDT 24 Apr 18 01:50:20 PM PDT 24 112207074 ps
T122 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1592624173 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:31 PM PDT 24 298362275 ps
T597 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2203521357 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:38 PM PDT 24 325827763 ps
T598 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1333035237 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:31 PM PDT 24 201319083 ps
T599 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2588303592 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:34 PM PDT 24 50007942 ps
T600 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3699716623 Apr 18 01:50:17 PM PDT 24 Apr 18 01:50:20 PM PDT 24 92722998 ps
T601 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2576753711 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:29 PM PDT 24 61429172 ps
T108 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2615529382 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:33 PM PDT 24 14960634 ps
T109 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2276089640 Apr 18 01:50:15 PM PDT 24 Apr 18 01:50:19 PM PDT 24 3273575444 ps
T602 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4071238969 Apr 18 01:50:32 PM PDT 24 Apr 18 01:50:34 PM PDT 24 213417575 ps
T603 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3179109192 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:31 PM PDT 24 41135085 ps
T604 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3795301891 Apr 18 01:50:07 PM PDT 24 Apr 18 01:50:10 PM PDT 24 498573123 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2047459543 Apr 18 01:50:07 PM PDT 24 Apr 18 01:50:08 PM PDT 24 102125581 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1879527062 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:31 PM PDT 24 83670862 ps
T111 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3172410427 Apr 18 01:50:23 PM PDT 24 Apr 18 01:50:27 PM PDT 24 393580573 ps
T606 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3001634503 Apr 18 01:50:20 PM PDT 24 Apr 18 01:50:22 PM PDT 24 93023906 ps
T607 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2922415409 Apr 18 01:50:17 PM PDT 24 Apr 18 01:50:21 PM PDT 24 186126476 ps
T608 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2878427907 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:30 PM PDT 24 40864836 ps
T112 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2680772728 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:35 PM PDT 24 23614539 ps
T609 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1794124272 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:12 PM PDT 24 44550829 ps
T132 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1297796351 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:31 PM PDT 24 180200559 ps
T610 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3414255598 Apr 18 01:50:34 PM PDT 24 Apr 18 01:50:37 PM PDT 24 606665060 ps
T611 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.60905729 Apr 18 01:50:25 PM PDT 24 Apr 18 01:50:28 PM PDT 24 607058247 ps
T612 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3541727440 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:34 PM PDT 24 176046207 ps
T613 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2432852078 Apr 18 01:50:26 PM PDT 24 Apr 18 02:01:41 PM PDT 24 182736137163 ps
T614 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1113295798 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:35 PM PDT 24 15050887 ps
T615 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.777720199 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:29 PM PDT 24 184870572 ps
T123 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.463701903 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:26 PM PDT 24 191275190 ps
T616 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2943897738 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:33 PM PDT 24 14315181 ps
T617 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.154358584 Apr 18 01:50:32 PM PDT 24 Apr 18 01:50:36 PM PDT 24 581716173 ps
T128 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3544931453 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:34 PM PDT 24 183477203 ps
T618 /workspace/coverage/cover_reg_top/6.hmac_intr_test.4227295850 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:28 PM PDT 24 18913168 ps
T125 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4114817059 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:33 PM PDT 24 1871087992 ps
T619 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2302697096 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:11 PM PDT 24 27089543 ps
T620 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2795464289 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:31 PM PDT 24 15744101 ps
T621 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3986329382 Apr 18 01:50:24 PM PDT 24 Apr 18 01:50:27 PM PDT 24 49227613 ps
T113 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.780525491 Apr 18 01:50:23 PM PDT 24 Apr 18 01:50:26 PM PDT 24 209138276 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1888643616 Apr 18 01:50:20 PM PDT 24 Apr 18 01:50:24 PM PDT 24 51120934 ps
T623 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4008844645 Apr 18 01:50:39 PM PDT 24 Apr 18 01:56:26 PM PDT 24 418534764810 ps
T624 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3620479610 Apr 18 01:50:17 PM PDT 24 Apr 18 01:50:18 PM PDT 24 221467217 ps
T130 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4017797066 Apr 18 01:50:11 PM PDT 24 Apr 18 01:50:15 PM PDT 24 240442184 ps
T625 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4123337240 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:35 PM PDT 24 17180321 ps
T626 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2841573153 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:38 PM PDT 24 227097303 ps
T627 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1064228188 Apr 18 01:50:07 PM PDT 24 Apr 18 01:50:10 PM PDT 24 111359022 ps
T129 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.501551079 Apr 18 01:50:09 PM PDT 24 Apr 18 01:50:11 PM PDT 24 161126293 ps
T628 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1984449369 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:22 PM PDT 24 53377697 ps
T629 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3031669461 Apr 18 01:50:18 PM PDT 24 Apr 18 01:50:20 PM PDT 24 45920426 ps
T630 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.463805771 Apr 18 01:50:12 PM PDT 24 Apr 18 01:50:14 PM PDT 24 31728144 ps
T631 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1420570058 Apr 18 01:50:19 PM PDT 24 Apr 18 01:50:20 PM PDT 24 44654100 ps
T131 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3278545847 Apr 18 01:50:21 PM PDT 24 Apr 18 01:50:26 PM PDT 24 2740131513 ps
T632 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3278332662 Apr 18 01:50:35 PM PDT 24 Apr 18 01:50:36 PM PDT 24 102758958 ps
T633 /workspace/coverage/cover_reg_top/12.hmac_intr_test.209103349 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:33 PM PDT 24 20662057 ps
T634 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1410291716 Apr 18 01:50:25 PM PDT 24 Apr 18 01:50:27 PM PDT 24 43831941 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_intr_test.94974057 Apr 18 01:50:09 PM PDT 24 Apr 18 01:50:10 PM PDT 24 15375389 ps
T636 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1242505882 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:30 PM PDT 24 672145442 ps
T637 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1408411081 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:23 PM PDT 24 51071188 ps
T638 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1801463957 Apr 18 01:50:11 PM PDT 24 Apr 18 02:06:04 PM PDT 24 64269669951 ps
T114 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3574780098 Apr 18 01:50:25 PM PDT 24 Apr 18 01:50:27 PM PDT 24 204228281 ps
T639 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1940182698 Apr 18 01:50:03 PM PDT 24 Apr 18 01:50:04 PM PDT 24 67641476 ps
T115 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3817880762 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:30 PM PDT 24 20912830 ps
T640 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2032997260 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:13 PM PDT 24 384584248 ps
T126 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.949303874 Apr 18 01:50:06 PM PDT 24 Apr 18 01:50:10 PM PDT 24 160811791 ps
T641 /workspace/coverage/cover_reg_top/38.hmac_intr_test.117356018 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:33 PM PDT 24 60547713 ps
T642 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4122171956 Apr 18 01:50:24 PM PDT 24 Apr 18 01:50:28 PM PDT 24 136552723 ps
T643 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2592371670 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:29 PM PDT 24 61474594 ps
T644 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2744999331 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:31 PM PDT 24 15517864 ps
T645 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2137571254 Apr 18 01:50:08 PM PDT 24 Apr 18 01:50:13 PM PDT 24 294709392 ps
T646 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.138454379 Apr 18 01:50:23 PM PDT 24 Apr 18 01:50:26 PM PDT 24 36077979 ps
T116 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3905611460 Apr 18 01:50:20 PM PDT 24 Apr 18 01:50:21 PM PDT 24 26682967 ps
T647 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2456512813 Apr 18 01:50:34 PM PDT 24 Apr 18 01:50:35 PM PDT 24 52019947 ps
T648 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3408696943 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:13 PM PDT 24 90305885 ps
T649 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1188179390 Apr 18 01:50:11 PM PDT 24 Apr 18 01:50:12 PM PDT 24 27456864 ps
T650 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2718713186 Apr 18 01:50:12 PM PDT 24 Apr 18 01:50:22 PM PDT 24 216540787 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.491605258 Apr 18 01:50:12 PM PDT 24 Apr 18 01:50:16 PM PDT 24 614749950 ps
T651 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1101236767 Apr 18 01:50:16 PM PDT 24 Apr 18 01:50:20 PM PDT 24 208336307 ps
T652 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2299246933 Apr 18 01:50:08 PM PDT 24 Apr 18 01:50:10 PM PDT 24 261028172 ps
T653 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1700111231 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:31 PM PDT 24 150750826 ps
T654 /workspace/coverage/cover_reg_top/28.hmac_intr_test.400237538 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:31 PM PDT 24 25365867 ps
T655 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1031687996 Apr 18 01:50:25 PM PDT 24 Apr 18 01:50:26 PM PDT 24 18020225 ps
T656 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3971563099 Apr 18 01:50:40 PM PDT 24 Apr 18 01:50:41 PM PDT 24 14271734 ps
T657 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4126601734 Apr 18 01:50:32 PM PDT 24 Apr 18 01:50:33 PM PDT 24 27180289 ps
T658 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.149367440 Apr 18 01:50:26 PM PDT 24 Apr 18 01:50:27 PM PDT 24 22829964 ps
T118 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.478561600 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:16 PM PDT 24 429805891 ps
T659 /workspace/coverage/cover_reg_top/35.hmac_intr_test.393454271 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:35 PM PDT 24 11602402 ps
T660 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.660342009 Apr 18 01:50:20 PM PDT 24 Apr 18 01:50:22 PM PDT 24 130645200 ps
T661 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1986072766 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:14 PM PDT 24 187927686 ps
T662 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2453860247 Apr 18 01:50:21 PM PDT 24 Apr 18 01:50:26 PM PDT 24 220759228 ps
T663 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1815270298 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:33 PM PDT 24 64654965 ps
T664 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2917040846 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:29 PM PDT 24 95599427 ps
T124 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2215147726 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:34 PM PDT 24 89103485 ps
T665 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3091779635 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:33 PM PDT 24 566855892 ps
T666 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1671113152 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:30 PM PDT 24 24540611 ps
T667 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3193646705 Apr 18 01:50:12 PM PDT 24 Apr 18 01:50:13 PM PDT 24 29391974 ps
T668 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.9222511 Apr 18 01:50:13 PM PDT 24 Apr 18 01:50:16 PM PDT 24 295476194 ps
T669 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2314854971 Apr 18 01:50:41 PM PDT 24 Apr 18 01:50:42 PM PDT 24 11163849 ps
T670 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2765766665 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:33 PM PDT 24 27442638 ps
T671 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2614928966 Apr 18 01:50:18 PM PDT 24 Apr 18 01:50:19 PM PDT 24 51815191 ps
T672 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2889872584 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:29 PM PDT 24 16651277 ps
T673 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.636840902 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:30 PM PDT 24 78634075 ps
T674 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3551753696 Apr 18 01:50:32 PM PDT 24 Apr 18 01:50:58 PM PDT 24 1612011898 ps
T675 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1958525600 Apr 18 01:50:10 PM PDT 24 Apr 18 01:50:27 PM PDT 24 6245102210 ps
T127 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.28346905 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:32 PM PDT 24 91078401 ps
T676 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1738988469 Apr 18 01:50:35 PM PDT 24 Apr 18 01:50:36 PM PDT 24 32301484 ps
T677 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1892633038 Apr 18 01:50:03 PM PDT 24 Apr 18 01:50:09 PM PDT 24 528712289 ps
T678 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2032083981 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:28 PM PDT 24 57611966 ps
T679 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2068347507 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:36 PM PDT 24 256915332 ps
T680 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2693051921 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:28 PM PDT 24 60353948 ps
T681 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1689939989 Apr 18 01:50:28 PM PDT 24 Apr 18 01:50:31 PM PDT 24 241830656 ps
T682 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2634644085 Apr 18 01:50:25 PM PDT 24 Apr 18 01:50:27 PM PDT 24 31181735 ps
T683 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3882093328 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:28 PM PDT 24 770043032 ps
T684 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3079983223 Apr 18 01:50:26 PM PDT 24 Apr 18 01:50:29 PM PDT 24 135711910 ps
T685 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1925170656 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:34 PM PDT 24 12726324 ps
T686 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2125236126 Apr 18 01:50:17 PM PDT 24 Apr 18 01:50:19 PM PDT 24 122093977 ps
T687 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.849732428 Apr 18 01:50:32 PM PDT 24 Apr 18 01:50:35 PM PDT 24 390118138 ps
T688 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3555749398 Apr 18 01:50:19 PM PDT 24 Apr 18 01:50:20 PM PDT 24 12822386 ps
T689 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.418241208 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:35 PM PDT 24 160649070 ps
T690 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1533509979 Apr 18 01:50:11 PM PDT 24 Apr 18 01:50:16 PM PDT 24 423849902 ps
T691 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3103365384 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:23 PM PDT 24 14217993 ps
T692 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2848495555 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:30 PM PDT 24 49348855 ps
T693 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2464917355 Apr 18 01:50:34 PM PDT 24 Apr 18 01:50:36 PM PDT 24 53821279 ps
T694 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.610800947 Apr 18 01:50:21 PM PDT 24 Apr 18 01:50:23 PM PDT 24 107369757 ps
T695 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3830020969 Apr 18 01:50:25 PM PDT 24 Apr 18 01:50:27 PM PDT 24 11805078 ps
T696 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3766563955 Apr 18 01:50:13 PM PDT 24 Apr 18 01:50:15 PM PDT 24 145397770 ps
T697 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1438153017 Apr 18 01:50:24 PM PDT 24 Apr 18 01:50:25 PM PDT 24 35231052 ps
T698 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2651843473 Apr 18 01:50:21 PM PDT 24 Apr 18 01:50:22 PM PDT 24 40262389 ps
T699 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3324287224 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:29 PM PDT 24 114554046 ps
T700 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1030831849 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:33 PM PDT 24 12509111 ps
T701 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.428591970 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:35 PM PDT 24 134757909 ps
T702 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3050067427 Apr 18 01:50:34 PM PDT 24 Apr 18 01:50:38 PM PDT 24 676426009 ps
T703 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.735384593 Apr 18 01:50:08 PM PDT 24 Apr 18 01:50:09 PM PDT 24 81923330 ps
T704 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1601737182 Apr 18 01:50:13 PM PDT 24 Apr 18 01:50:20 PM PDT 24 1699505224 ps
T705 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3163667790 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:25 PM PDT 24 439612082 ps
T706 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1789162000 Apr 18 01:50:03 PM PDT 24 Apr 18 01:50:04 PM PDT 24 67415018 ps
T707 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2317066832 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:35 PM PDT 24 12346527 ps
T708 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2871693118 Apr 18 01:50:01 PM PDT 24 Apr 18 01:50:05 PM PDT 24 185460947 ps
T709 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3354587443 Apr 18 01:50:31 PM PDT 24 Apr 18 01:50:32 PM PDT 24 50258518 ps
T710 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1949474234 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:32 PM PDT 24 65958656 ps
T711 /workspace/coverage/cover_reg_top/10.hmac_intr_test.668149183 Apr 18 01:50:20 PM PDT 24 Apr 18 01:50:21 PM PDT 24 24717960 ps
T712 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1790748179 Apr 18 01:50:24 PM PDT 24 Apr 18 01:50:25 PM PDT 24 35295731 ps
T713 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2555682718 Apr 18 01:50:05 PM PDT 24 Apr 18 01:50:07 PM PDT 24 346191943 ps
T714 /workspace/coverage/cover_reg_top/5.hmac_intr_test.4136532989 Apr 18 01:50:27 PM PDT 24 Apr 18 01:50:28 PM PDT 24 71485874 ps
T715 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3220376168 Apr 18 01:50:34 PM PDT 24 Apr 18 01:50:35 PM PDT 24 14710609 ps
T716 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2381658108 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:32 PM PDT 24 50297982 ps
T717 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2857404355 Apr 18 01:50:19 PM PDT 24 Apr 18 01:50:21 PM PDT 24 160342736 ps
T718 /workspace/coverage/cover_reg_top/9.hmac_intr_test.805961058 Apr 18 01:50:20 PM PDT 24 Apr 18 01:50:21 PM PDT 24 42267453 ps
T719 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1725762725 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:31 PM PDT 24 17139420 ps
T720 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.482778224 Apr 18 01:50:25 PM PDT 24 Apr 18 01:50:26 PM PDT 24 34326813 ps
T721 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3568274322 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:23 PM PDT 24 135396124 ps
T722 /workspace/coverage/cover_reg_top/36.hmac_intr_test.59677873 Apr 18 01:50:30 PM PDT 24 Apr 18 01:50:31 PM PDT 24 13460031 ps
T723 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1413361909 Apr 18 01:50:22 PM PDT 24 Apr 18 01:50:24 PM PDT 24 62107650 ps
T724 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2795643145 Apr 18 01:50:29 PM PDT 24 Apr 18 01:50:30 PM PDT 24 32979247 ps
T725 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1294713095 Apr 18 01:50:05 PM PDT 24 Apr 18 01:50:10 PM PDT 24 1925958885 ps
T726 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1115868755 Apr 18 01:50:33 PM PDT 24 Apr 18 01:50:34 PM PDT 24 91362561 ps
T727 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.365109449 Apr 18 01:50:27 PM PDT 24 Apr 18 02:04:21 PM PDT 24 77700270151 ps

Test location /workspace/coverage/default/13.hmac_datapath_stress.2055508466
Short name T2
Test name
Test status
Simulation time 1388106042 ps
CPU time 73.62 seconds
Started Apr 18 12:56:11 PM PDT 24
Finished Apr 18 12:57:26 PM PDT 24
Peak memory 199596 kb
Host smart-bc43a123-e2a5-4a17-af38-443eb513a485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055508466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2055508466
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.2569783186
Short name T8
Test name
Test status
Simulation time 115118644997 ps
CPU time 1432.69 seconds
Started Apr 18 12:58:57 PM PDT 24
Finished Apr 18 01:22:51 PM PDT 24
Peak memory 231296 kb
Host smart-757448ad-f755-4d6d-996f-804ca5eb1b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569783186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.2569783186
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_error.1169413235
Short name T1
Test name
Test status
Simulation time 12728270487 ps
CPU time 170.36 seconds
Started Apr 18 12:57:27 PM PDT 24
Finished Apr 18 01:00:18 PM PDT 24
Peak memory 199660 kb
Host smart-4f5099c7-88b5-4339-8520-7ed9a2c53b48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169413235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1169413235
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3140373424
Short name T56
Test name
Test status
Simulation time 20465290684 ps
CPU time 1070.2 seconds
Started Apr 18 12:58:19 PM PDT 24
Finished Apr 18 01:16:10 PM PDT 24
Peak memory 208868 kb
Host smart-cf1772db-ddeb-4dee-832d-21cfcecdbc5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140373424 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3140373424
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3921941494
Short name T34
Test name
Test status
Simulation time 753777575 ps
CPU time 0.96 seconds
Started Apr 18 12:55:36 PM PDT 24
Finished Apr 18 12:55:38 PM PDT 24
Peak memory 219092 kb
Host smart-4be91a9a-adeb-4090-a05b-e46d36ce13a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921941494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3921941494
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.1859946403
Short name T12
Test name
Test status
Simulation time 125460469756 ps
CPU time 2263.03 seconds
Started Apr 18 12:59:03 PM PDT 24
Finished Apr 18 01:36:47 PM PDT 24
Peak memory 261052 kb
Host smart-5988e171-2684-4df1-94c5-71020903ecb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859946403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.1859946403
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.232758410
Short name T70
Test name
Test status
Simulation time 188997638 ps
CPU time 3.06 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:14 PM PDT 24
Peak memory 199232 kb
Host smart-a9aea23b-86b2-49a8-a441-f5c6a02081d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232758410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.232758410
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1036956305
Short name T14
Test name
Test status
Simulation time 244975164331 ps
CPU time 1257.03 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 01:17:14 PM PDT 24
Peak memory 238180 kb
Host smart-5dc4155f-d103-4243-9903-3a387847637f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036956305 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1036956305
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1615033201
Short name T23
Test name
Test status
Simulation time 28271667 ps
CPU time 0.55 seconds
Started Apr 18 12:56:50 PM PDT 24
Finished Apr 18 12:56:52 PM PDT 24
Peak memory 195176 kb
Host smart-6ca283d9-6e1b-4fe5-b42a-e80cf4bc4833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615033201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1615033201
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4114817059
Short name T125
Test name
Test status
Simulation time 1871087992 ps
CPU time 3.97 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 199220 kb
Host smart-60ee7863-84dd-45d5-9d7c-669a31a50ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114817059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4114817059
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3108118368
Short name T93
Test name
Test status
Simulation time 40061584 ps
CPU time 1.01 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:32 PM PDT 24
Peak memory 198384 kb
Host smart-b07defc7-9204-4d21-9e4a-3c55d53478de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108118368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3108118368
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/24.hmac_stress_all.663580764
Short name T49
Test name
Test status
Simulation time 41397623757 ps
CPU time 292.76 seconds
Started Apr 18 12:56:59 PM PDT 24
Finished Apr 18 01:01:53 PM PDT 24
Peak memory 208008 kb
Host smart-9fcb8648-fe0e-4d8f-a636-7d9e645113ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663580764 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.663580764
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.463701903
Short name T123
Test name
Test status
Simulation time 191275190 ps
CPU time 3.2 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:26 PM PDT 24
Peak memory 199248 kb
Host smart-236803f2-2068-4eb2-8f9e-f98910201139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463701903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.463701903
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3544931453
Short name T128
Test name
Test status
Simulation time 183477203 ps
CPU time 3.05 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 199192 kb
Host smart-0cc09427-6528-4ba6-aa36-8f2c0af37971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544931453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3544931453
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2408922443
Short name T279
Test name
Test status
Simulation time 34846764653 ps
CPU time 469.82 seconds
Started Apr 18 12:56:12 PM PDT 24
Finished Apr 18 01:04:03 PM PDT 24
Peak memory 199732 kb
Host smart-dec06979-7e81-4bc3-a2ba-497d33838aa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408922443 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2408922443
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.602584509
Short name T71
Test name
Test status
Simulation time 571049206 ps
CPU time 4.3 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:32 PM PDT 24
Peak memory 199196 kb
Host smart-2e531d01-75f2-432a-843f-183a296b0f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602584509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.602584509
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2871693118
Short name T708
Test name
Test status
Simulation time 185460947 ps
CPU time 3.39 seconds
Started Apr 18 01:50:01 PM PDT 24
Finished Apr 18 01:50:05 PM PDT 24
Peak memory 198172 kb
Host smart-1ba11876-1d44-4574-acf7-dca7c74ddbe3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871693118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2871693118
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1892633038
Short name T677
Test name
Test status
Simulation time 528712289 ps
CPU time 5.86 seconds
Started Apr 18 01:50:03 PM PDT 24
Finished Apr 18 01:50:09 PM PDT 24
Peak memory 199200 kb
Host smart-6874c8a9-d1ec-44f1-9e6d-b5613a9896b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892633038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1892633038
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.365109449
Short name T727
Test name
Test status
Simulation time 77700270151 ps
CPU time 833.15 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 02:04:21 PM PDT 24
Peak memory 215724 kb
Host smart-d91ba5f7-a4bd-455c-865a-f97f5299cb1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365109449 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.365109449
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1789162000
Short name T706
Test name
Test status
Simulation time 67415018 ps
CPU time 0.96 seconds
Started Apr 18 01:50:03 PM PDT 24
Finished Apr 18 01:50:04 PM PDT 24
Peak memory 198664 kb
Host smart-ec892e0d-9d35-4d6e-a7c8-7e8225a553af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789162000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1789162000
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3103365384
Short name T691
Test name
Test status
Simulation time 14217993 ps
CPU time 0.6 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:23 PM PDT 24
Peak memory 193860 kb
Host smart-7a79dc25-1911-46f3-b29e-2442c29e65c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103365384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3103365384
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2555682718
Short name T713
Test name
Test status
Simulation time 346191943 ps
CPU time 1.63 seconds
Started Apr 18 01:50:05 PM PDT 24
Finished Apr 18 01:50:07 PM PDT 24
Peak memory 199220 kb
Host smart-cd2bb541-363a-4fdc-a762-899da12534b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555682718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2555682718
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.610800947
Short name T694
Test name
Test status
Simulation time 107369757 ps
CPU time 1.75 seconds
Started Apr 18 01:50:21 PM PDT 24
Finished Apr 18 01:50:23 PM PDT 24
Peak memory 199220 kb
Host smart-9721b49c-f00e-42cd-b766-23765c0f6884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610800947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.610800947
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1294713095
Short name T725
Test name
Test status
Simulation time 1925958885 ps
CPU time 4.87 seconds
Started Apr 18 01:50:05 PM PDT 24
Finished Apr 18 01:50:10 PM PDT 24
Peak memory 199244 kb
Host smart-c0189625-a488-428b-b14d-47b31b27484e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294713095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1294713095
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2276089640
Short name T109
Test name
Test status
Simulation time 3273575444 ps
CPU time 3.33 seconds
Started Apr 18 01:50:15 PM PDT 24
Finished Apr 18 01:50:19 PM PDT 24
Peak memory 198920 kb
Host smart-adfae4e0-693c-4a2b-986f-48f0641bc12e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276089640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2276089640
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1601737182
Short name T704
Test name
Test status
Simulation time 1699505224 ps
CPU time 5.92 seconds
Started Apr 18 01:50:13 PM PDT 24
Finished Apr 18 01:50:20 PM PDT 24
Peak memory 197996 kb
Host smart-b207842e-e373-4f84-a296-eae455504ab5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601737182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1601737182
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1940182698
Short name T639
Test name
Test status
Simulation time 67641476 ps
CPU time 0.77 seconds
Started Apr 18 01:50:03 PM PDT 24
Finished Apr 18 01:50:04 PM PDT 24
Peak memory 196780 kb
Host smart-4ed88a6b-e350-4d2f-9871-c80e7c860e8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940182698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1940182698
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1794124272
Short name T609
Test name
Test status
Simulation time 44550829 ps
CPU time 1.2 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:12 PM PDT 24
Peak memory 199212 kb
Host smart-4186e1da-3694-4297-bd11-97e12f04bd5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794124272 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1794124272
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1408411081
Short name T637
Test name
Test status
Simulation time 51071188 ps
CPU time 0.72 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:23 PM PDT 24
Peak memory 196988 kb
Host smart-3007db39-224d-44f7-afa4-87ac4485b2e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408411081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1408411081
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3555749398
Short name T688
Test name
Test status
Simulation time 12822386 ps
CPU time 0.63 seconds
Started Apr 18 01:50:19 PM PDT 24
Finished Apr 18 01:50:20 PM PDT 24
Peak memory 193856 kb
Host smart-92decbac-54ea-4809-b144-79f90abe80d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555749398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3555749398
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1064228188
Short name T627
Test name
Test status
Simulation time 111359022 ps
CPU time 2.35 seconds
Started Apr 18 01:50:07 PM PDT 24
Finished Apr 18 01:50:10 PM PDT 24
Peak memory 199200 kb
Host smart-8fe1c8d5-205f-454e-b88b-b1aa03654791
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064228188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1064228188
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.660342009
Short name T660
Test name
Test status
Simulation time 130645200 ps
CPU time 1.7 seconds
Started Apr 18 01:50:20 PM PDT 24
Finished Apr 18 01:50:22 PM PDT 24
Peak memory 199324 kb
Host smart-157afc76-7255-4246-b8ae-0c48c0c0551b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660342009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.660342009
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1949474234
Short name T710
Test name
Test status
Simulation time 65958656 ps
CPU time 1.77 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:32 PM PDT 24
Peak memory 199152 kb
Host smart-11ffc3f7-7c9d-4f0b-8fce-9a97686cb0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949474234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1949474234
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.642454602
Short name T596
Test name
Test status
Simulation time 112207074 ps
CPU time 1.84 seconds
Started Apr 18 01:50:18 PM PDT 24
Finished Apr 18 01:50:20 PM PDT 24
Peak memory 199336 kb
Host smart-969b1cd2-5049-4ec8-9b2d-3f879c3bd3b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642454602 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.642454602
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2615529382
Short name T108
Test name
Test status
Simulation time 14960634 ps
CPU time 0.68 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 196872 kb
Host smart-6b51ec2a-910f-4d16-8e18-ca452b46bcc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615529382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2615529382
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.668149183
Short name T711
Test name
Test status
Simulation time 24717960 ps
CPU time 0.56 seconds
Started Apr 18 01:50:20 PM PDT 24
Finished Apr 18 01:50:21 PM PDT 24
Peak memory 193568 kb
Host smart-ec8c8b79-35c3-4783-8184-1a4dbc78985d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668149183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.668149183
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3079983223
Short name T684
Test name
Test status
Simulation time 135711910 ps
CPU time 2.29 seconds
Started Apr 18 01:50:26 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 199072 kb
Host smart-5f22a89e-5293-4fd8-9981-73fd9a2a17a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079983223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3079983223
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4122171956
Short name T642
Test name
Test status
Simulation time 136552723 ps
CPU time 4.13 seconds
Started Apr 18 01:50:24 PM PDT 24
Finished Apr 18 01:50:28 PM PDT 24
Peak memory 199244 kb
Host smart-c42d3a1f-2ec9-4f99-8184-9b1d19e1d46a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122171956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4122171956
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.636840902
Short name T673
Test name
Test status
Simulation time 78634075 ps
CPU time 1.87 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:30 PM PDT 24
Peak memory 198832 kb
Host smart-26624eac-587c-4499-b180-3924b9422467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636840902 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.636840902
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3905611460
Short name T116
Test name
Test status
Simulation time 26682967 ps
CPU time 0.67 seconds
Started Apr 18 01:50:20 PM PDT 24
Finished Apr 18 01:50:21 PM PDT 24
Peak memory 196756 kb
Host smart-b9acd7c3-96b6-4beb-bd09-fcc514b35ef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905611460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3905611460
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1420570058
Short name T631
Test name
Test status
Simulation time 44654100 ps
CPU time 0.63 seconds
Started Apr 18 01:50:19 PM PDT 24
Finished Apr 18 01:50:20 PM PDT 24
Peak memory 193864 kb
Host smart-f8baf5f2-2cb6-40aa-8df4-07a275dcab43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420570058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1420570058
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2125236126
Short name T686
Test name
Test status
Simulation time 122093977 ps
CPU time 2.27 seconds
Started Apr 18 01:50:17 PM PDT 24
Finished Apr 18 01:50:19 PM PDT 24
Peak memory 198932 kb
Host smart-ea7938e5-8281-49f8-9bbc-5307a68c046c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125236126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2125236126
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3766563955
Short name T696
Test name
Test status
Simulation time 145397770 ps
CPU time 1.32 seconds
Started Apr 18 01:50:13 PM PDT 24
Finished Apr 18 01:50:15 PM PDT 24
Peak memory 199304 kb
Host smart-a2c1f9de-1f66-4d26-9c68-0d1912b0f27f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766563955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3766563955
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.217940748
Short name T595
Test name
Test status
Simulation time 150579968 ps
CPU time 1.75 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 199248 kb
Host smart-e6c43f86-3399-45d6-a0a3-ca903a5230f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217940748 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.217940748
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3817880762
Short name T115
Test name
Test status
Simulation time 20912830 ps
CPU time 0.73 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:30 PM PDT 24
Peak memory 196560 kb
Host smart-2a8edba3-2240-47ef-bac1-a07e0344c334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817880762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3817880762
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.209103349
Short name T633
Test name
Test status
Simulation time 20662057 ps
CPU time 0.6 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 193844 kb
Host smart-86806611-0be1-4867-96f9-3f09a1a15387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209103349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.209103349
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2857404355
Short name T717
Test name
Test status
Simulation time 160342736 ps
CPU time 1.76 seconds
Started Apr 18 01:50:19 PM PDT 24
Finished Apr 18 01:50:21 PM PDT 24
Peak memory 198944 kb
Host smart-32934baa-9eee-4036-af5e-41e64d504d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857404355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2857404355
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1830559950
Short name T98
Test name
Test status
Simulation time 1594174601 ps
CPU time 3.08 seconds
Started Apr 18 01:50:19 PM PDT 24
Finished Apr 18 01:50:22 PM PDT 24
Peak memory 199328 kb
Host smart-bf49031d-0b21-48f9-8f1d-b448b12ce78f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830559950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1830559950
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2848495555
Short name T692
Test name
Test status
Simulation time 49348855 ps
CPU time 1.82 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:30 PM PDT 24
Peak memory 199180 kb
Host smart-155c2795-1a44-40e1-869b-64592b522ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848495555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2848495555
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2432852078
Short name T613
Test name
Test status
Simulation time 182736137163 ps
CPU time 674.34 seconds
Started Apr 18 01:50:26 PM PDT 24
Finished Apr 18 02:01:41 PM PDT 24
Peak memory 208104 kb
Host smart-60ec1f78-b5a1-42ce-91ba-85c62cf3ff72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432852078 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2432852078
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2765766665
Short name T670
Test name
Test status
Simulation time 27442638 ps
CPU time 0.84 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 198636 kb
Host smart-e4c813e7-1f62-4638-9a79-d3a055abb47c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765766665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2765766665
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2317066832
Short name T707
Test name
Test status
Simulation time 12346527 ps
CPU time 0.57 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 194144 kb
Host smart-54a8c7a8-332e-4150-a76f-5c39461baaba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317066832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2317066832
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1671113152
Short name T666
Test name
Test status
Simulation time 24540611 ps
CPU time 1.11 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:30 PM PDT 24
Peak memory 197224 kb
Host smart-1a3a5aae-86da-455b-b9f5-8eabf39228c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671113152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1671113152
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2001580832
Short name T76
Test name
Test status
Simulation time 453907507 ps
CPU time 4.69 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:36 PM PDT 24
Peak memory 199276 kb
Host smart-eccf9623-e60a-4690-b3a2-e3b6f1f51b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001580832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2001580832
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.777720199
Short name T615
Test name
Test status
Simulation time 184870572 ps
CPU time 1.85 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 199180 kb
Host smart-7135fc11-dbe3-4dec-b13a-1fe6cec37996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777720199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.777720199
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1815270298
Short name T663
Test name
Test status
Simulation time 64654965 ps
CPU time 1.95 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 199348 kb
Host smart-c5c89c09-d799-4eed-9d11-85e666b3e81a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815270298 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1815270298
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2464917355
Short name T693
Test name
Test status
Simulation time 53821279 ps
CPU time 0.82 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:50:36 PM PDT 24
Peak memory 198544 kb
Host smart-19139df3-7d1d-497a-8ae3-c229b2a43e31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464917355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2464917355
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1725762725
Short name T719
Test name
Test status
Simulation time 17139420 ps
CPU time 0.6 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 193980 kb
Host smart-b92fdfae-090d-4f89-9b68-0dddaa0871a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725762725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1725762725
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.463805771
Short name T630
Test name
Test status
Simulation time 31728144 ps
CPU time 1.6 seconds
Started Apr 18 01:50:12 PM PDT 24
Finished Apr 18 01:50:14 PM PDT 24
Peak memory 198552 kb
Host smart-acbd2a31-3985-4716-a208-3c13a17db50d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463805771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.463805771
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3882093328
Short name T683
Test name
Test status
Simulation time 770043032 ps
CPU time 5.35 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:28 PM PDT 24
Peak memory 199320 kb
Host smart-c656d9a6-b990-4938-902c-aded9ff16c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882093328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3882093328
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3551753696
Short name T674
Test name
Test status
Simulation time 1612011898 ps
CPU time 25.05 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:58 PM PDT 24
Peak memory 214968 kb
Host smart-79b20146-bac1-4e29-9ac8-5790e2dec868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551753696 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3551753696
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3324287224
Short name T699
Test name
Test status
Simulation time 114554046 ps
CPU time 1.01 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 198604 kb
Host smart-bea5658c-eaeb-4ecb-8809-396d6e9892f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324287224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3324287224
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3568274322
Short name T721
Test name
Test status
Simulation time 135396124 ps
CPU time 0.6 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:23 PM PDT 24
Peak memory 193864 kb
Host smart-f2c7a694-e7fc-4e15-ac1c-e5d188acb545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568274322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3568274322
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1242505882
Short name T636
Test name
Test status
Simulation time 672145442 ps
CPU time 1.93 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:30 PM PDT 24
Peak memory 198980 kb
Host smart-3958c49f-8f66-4900-bd48-7a868e74cee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242505882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1242505882
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.9222511
Short name T668
Test name
Test status
Simulation time 295476194 ps
CPU time 2.59 seconds
Started Apr 18 01:50:13 PM PDT 24
Finished Apr 18 01:50:16 PM PDT 24
Peak memory 199304 kb
Host smart-2dc37e62-1db4-44b8-8870-6c0363194516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9222511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.9222511
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1297796351
Short name T132
Test name
Test status
Simulation time 180200559 ps
CPU time 1.72 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 199284 kb
Host smart-891463f0-a00c-408e-9ad2-dadca68e2c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297796351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1297796351
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4008844645
Short name T623
Test name
Test status
Simulation time 418534764810 ps
CPU time 346.59 seconds
Started Apr 18 01:50:39 PM PDT 24
Finished Apr 18 01:56:26 PM PDT 24
Peak memory 216004 kb
Host smart-1eae5214-e2a3-43d3-bd82-b8192e1dd0a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008844645 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4008844645
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.149367440
Short name T658
Test name
Test status
Simulation time 22829964 ps
CPU time 0.75 seconds
Started Apr 18 01:50:26 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 196852 kb
Host smart-19702b74-5d48-42d2-9b08-91ff2d4ffa68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149367440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.149367440
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3830020969
Short name T695
Test name
Test status
Simulation time 11805078 ps
CPU time 0.6 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 193868 kb
Host smart-b53f587b-f8c9-4daa-9ac7-c9131def6107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830020969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3830020969
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.60905729
Short name T611
Test name
Test status
Simulation time 607058247 ps
CPU time 2.17 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:50:28 PM PDT 24
Peak memory 199204 kb
Host smart-e585ebfa-4fae-471a-bb88-f5374403a4ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60905729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_
outstanding.60905729
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1333035237
Short name T598
Test name
Test status
Simulation time 201319083 ps
CPU time 3.2 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 199332 kb
Host smart-7eae91bc-d8e2-43b0-8f6b-6a65f81e3fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333035237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1333035237
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3541727440
Short name T612
Test name
Test status
Simulation time 176046207 ps
CPU time 2.81 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 199224 kb
Host smart-e1ee22e6-53d2-496a-b6c4-a7016af7baae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541727440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3541727440
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3091779635
Short name T665
Test name
Test status
Simulation time 566855892 ps
CPU time 2.61 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 199292 kb
Host smart-cdc41339-5430-43c2-a6a9-9c33b2a5ddad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091779635 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3091779635
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2981883078
Short name T74
Test name
Test status
Simulation time 29277767 ps
CPU time 1.03 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 198660 kb
Host smart-a8547dc5-2cb3-412d-affd-22be6377721c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981883078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2981883078
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1031687996
Short name T655
Test name
Test status
Simulation time 18020225 ps
CPU time 0.54 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:50:26 PM PDT 24
Peak memory 193880 kb
Host smart-9d4f5870-30f8-4b2c-88f0-3f3ba40194ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031687996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1031687996
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3163667790
Short name T705
Test name
Test status
Simulation time 439612082 ps
CPU time 2.35 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:25 PM PDT 24
Peak memory 199240 kb
Host smart-27f656f8-bd2d-40bb-ac9b-adb7590b566a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163667790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3163667790
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2841573153
Short name T626
Test name
Test status
Simulation time 227097303 ps
CPU time 3.45 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:38 PM PDT 24
Peak memory 199324 kb
Host smart-f8c91595-9a35-4c80-b4cb-a9ef62c7216b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841573153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2841573153
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3322086903
Short name T69
Test name
Test status
Simulation time 72004383 ps
CPU time 1.8 seconds
Started Apr 18 01:50:23 PM PDT 24
Finished Apr 18 01:50:25 PM PDT 24
Peak memory 199212 kb
Host smart-63dc9465-1fbe-48bf-8dd5-a747e0fbe469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322086903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3322086903
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2922415409
Short name T607
Test name
Test status
Simulation time 186126476 ps
CPU time 3.13 seconds
Started Apr 18 01:50:17 PM PDT 24
Finished Apr 18 01:50:21 PM PDT 24
Peak memory 207564 kb
Host smart-400f390a-e32b-4350-ad07-3bf86c7fa4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922415409 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2922415409
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2614928966
Short name T671
Test name
Test status
Simulation time 51815191 ps
CPU time 0.81 seconds
Started Apr 18 01:50:18 PM PDT 24
Finished Apr 18 01:50:19 PM PDT 24
Peak memory 198056 kb
Host smart-b5186834-3910-414f-a3bb-a2804c80e290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614928966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2614928966
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2576753711
Short name T601
Test name
Test status
Simulation time 61429172 ps
CPU time 0.62 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 193896 kb
Host smart-9a4cde83-5adc-4f3e-9608-0efdd2c6701a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576753711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2576753711
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.849732428
Short name T687
Test name
Test status
Simulation time 390118138 ps
CPU time 2.31 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 199196 kb
Host smart-468893dd-14b1-4adf-a58d-0a48c7e08f3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849732428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.849732428
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1689939989
Short name T681
Test name
Test status
Simulation time 241830656 ps
CPU time 1.68 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 199320 kb
Host smart-813b87b5-6d6e-427b-90d6-8cef61fb57b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689939989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1689939989
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3050067427
Short name T702
Test name
Test status
Simulation time 676426009 ps
CPU time 3.14 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:50:38 PM PDT 24
Peak memory 199236 kb
Host smart-f421a0a5-d743-4573-9cdb-d3c4d9912c99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050067427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3050067427
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1410291716
Short name T634
Test name
Test status
Simulation time 43831941 ps
CPU time 1.21 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 199124 kb
Host smart-38069be3-bdfd-4e40-9014-d7043bc3a6a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410291716 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1410291716
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.428591970
Short name T701
Test name
Test status
Simulation time 134757909 ps
CPU time 0.93 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 198640 kb
Host smart-257cd17c-78b7-4516-9b23-e50b229ab65b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428591970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.428591970
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1438153017
Short name T697
Test name
Test status
Simulation time 35231052 ps
CPU time 0.57 seconds
Started Apr 18 01:50:24 PM PDT 24
Finished Apr 18 01:50:25 PM PDT 24
Peak memory 193872 kb
Host smart-22ba1d5f-ff98-4ac9-b793-6e160d674957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438153017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1438153017
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.418241208
Short name T689
Test name
Test status
Simulation time 160649070 ps
CPU time 1.17 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 198744 kb
Host smart-f47d4e96-94ef-4d9b-a95f-717815745dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418241208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.418241208
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.154358584
Short name T617
Test name
Test status
Simulation time 581716173 ps
CPU time 3.2 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:36 PM PDT 24
Peak memory 199292 kb
Host smart-566e6bbc-f40b-42a4-b36f-9a0e6b2b5297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154358584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.154358584
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2215147726
Short name T124
Test name
Test status
Simulation time 89103485 ps
CPU time 2.84 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 199244 kb
Host smart-4be66588-a154-42a0-96c0-6c3c6c56a288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215147726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2215147726
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.780525491
Short name T113
Test name
Test status
Simulation time 209138276 ps
CPU time 2.99 seconds
Started Apr 18 01:50:23 PM PDT 24
Finished Apr 18 01:50:26 PM PDT 24
Peak memory 199160 kb
Host smart-c9d592c5-19ee-49c5-aed1-4f679be5d4f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780525491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.780525491
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.478561600
Short name T118
Test name
Test status
Simulation time 429805891 ps
CPU time 5.3 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:16 PM PDT 24
Peak memory 199180 kb
Host smart-dec7338b-cc09-4d59-bba6-c193872d6371
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478561600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.478561600
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2302697096
Short name T619
Test name
Test status
Simulation time 27089543 ps
CPU time 0.89 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:11 PM PDT 24
Peak memory 198300 kb
Host smart-7173cdcf-b036-4679-98c6-c0cb9ad47ae9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302697096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2302697096
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1801463957
Short name T638
Test name
Test status
Simulation time 64269669951 ps
CPU time 952.13 seconds
Started Apr 18 01:50:11 PM PDT 24
Finished Apr 18 02:06:04 PM PDT 24
Peak memory 215748 kb
Host smart-e6e4c726-8dfd-4491-9b8a-15b483bbe507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801463957 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1801463957
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.516134999
Short name T73
Test name
Test status
Simulation time 51104525 ps
CPU time 0.78 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 197720 kb
Host smart-673d0c4c-ebb0-4a4c-9fb6-f33ce03553be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516134999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.516134999
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.94974057
Short name T635
Test name
Test status
Simulation time 15375389 ps
CPU time 0.61 seconds
Started Apr 18 01:50:09 PM PDT 24
Finished Apr 18 01:50:10 PM PDT 24
Peak memory 194132 kb
Host smart-67dc2f1f-2e7c-4946-9653-f012fa36c40e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94974057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.94974057
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1413361909
Short name T723
Test name
Test status
Simulation time 62107650 ps
CPU time 1.68 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:24 PM PDT 24
Peak memory 199260 kb
Host smart-e1675cfa-9511-4296-a847-33a09e69b9a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413361909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1413361909
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3986329382
Short name T621
Test name
Test status
Simulation time 49227613 ps
CPU time 2.76 seconds
Started Apr 18 01:50:24 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 199320 kb
Host smart-b6f9e9c3-7f0d-421b-aac8-6e92be61bbdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986329382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3986329382
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.501551079
Short name T129
Test name
Test status
Simulation time 161126293 ps
CPU time 1.93 seconds
Started Apr 18 01:50:09 PM PDT 24
Finished Apr 18 01:50:11 PM PDT 24
Peak memory 199220 kb
Host smart-f84684e9-f2b0-4ff4-9cef-bfb0df1ff2a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501551079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.501551079
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1857430636
Short name T594
Test name
Test status
Simulation time 21661182 ps
CPU time 0.62 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 194116 kb
Host smart-c0ad43df-6093-4e36-bfc5-44aa2e646444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857430636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1857430636
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3220376168
Short name T715
Test name
Test status
Simulation time 14710609 ps
CPU time 0.61 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 193896 kb
Host smart-26639568-d97c-44ec-941c-898a59e43b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220376168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3220376168
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2795464289
Short name T620
Test name
Test status
Simulation time 15744101 ps
CPU time 0.59 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 193876 kb
Host smart-cbad14bd-831d-4ac6-922a-fc126378cad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795464289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2795464289
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4126601734
Short name T657
Test name
Test status
Simulation time 27180289 ps
CPU time 0.62 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 194152 kb
Host smart-03cb6781-1b1f-4e5f-962c-7b680855d348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126601734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4126601734
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1984449369
Short name T628
Test name
Test status
Simulation time 53377697 ps
CPU time 0.55 seconds
Started Apr 18 01:50:22 PM PDT 24
Finished Apr 18 01:50:22 PM PDT 24
Peak memory 193876 kb
Host smart-37b3ad97-fd01-45c4-9023-9b786a0640e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984449369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1984449369
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2588303592
Short name T599
Test name
Test status
Simulation time 50007942 ps
CPU time 0.6 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 193904 kb
Host smart-a6895f68-3104-4fe2-9659-f036d6555cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588303592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2588303592
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2917040846
Short name T664
Test name
Test status
Simulation time 95599427 ps
CPU time 0.62 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 193924 kb
Host smart-4660319d-d897-40ff-a617-2ef828a8bcfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917040846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2917040846
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4123337240
Short name T625
Test name
Test status
Simulation time 17180321 ps
CPU time 0.62 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 194068 kb
Host smart-79c0b23f-f0dc-44ba-92a9-42e3158b8642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123337240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4123337240
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.400237538
Short name T654
Test name
Test status
Simulation time 25365867 ps
CPU time 0.61 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 194124 kb
Host smart-7e018de0-bd8f-45f6-b549-1180dae0ee25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400237538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.400237538
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3354587443
Short name T709
Test name
Test status
Simulation time 50258518 ps
CPU time 0.59 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:32 PM PDT 24
Peak memory 193936 kb
Host smart-1a12328d-e209-4158-8f4f-59d0e73c6c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354587443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3354587443
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3172410427
Short name T111
Test name
Test status
Simulation time 393580573 ps
CPU time 3.61 seconds
Started Apr 18 01:50:23 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 199216 kb
Host smart-0206ef40-c863-4dce-b8f6-6d53d9a829a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172410427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3172410427
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2718713186
Short name T650
Test name
Test status
Simulation time 216540787 ps
CPU time 5.41 seconds
Started Apr 18 01:50:12 PM PDT 24
Finished Apr 18 01:50:22 PM PDT 24
Peak memory 197864 kb
Host smart-218944e5-4878-4589-8ee2-2287709e410e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718713186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2718713186
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2047459543
Short name T110
Test name
Test status
Simulation time 102125581 ps
CPU time 0.87 seconds
Started Apr 18 01:50:07 PM PDT 24
Finished Apr 18 01:50:08 PM PDT 24
Peak memory 198460 kb
Host smart-1c49f0f7-ead1-4849-b7aa-3751dce46631
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047459543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2047459543
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1879527062
Short name T605
Test name
Test status
Simulation time 83670862 ps
CPU time 1.24 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 199460 kb
Host smart-46465683-0f3e-45e0-8087-5cb1caf38f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879527062 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1879527062
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2634644085
Short name T682
Test name
Test status
Simulation time 31181735 ps
CPU time 0.85 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 198044 kb
Host smart-4efd9e77-29aa-4ace-9b2b-d6227c4fdf3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634644085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2634644085
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2651843473
Short name T698
Test name
Test status
Simulation time 40262389 ps
CPU time 0.61 seconds
Started Apr 18 01:50:21 PM PDT 24
Finished Apr 18 01:50:22 PM PDT 24
Peak memory 194056 kb
Host smart-f7abcecb-5f03-4ab3-ae80-ff0f415d1cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651843473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2651843473
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3001634503
Short name T606
Test name
Test status
Simulation time 93023906 ps
CPU time 1.73 seconds
Started Apr 18 01:50:20 PM PDT 24
Finished Apr 18 01:50:22 PM PDT 24
Peak memory 199216 kb
Host smart-27e91939-fac0-4fae-9107-5710d7f26ef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001634503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3001634503
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2032997260
Short name T640
Test name
Test status
Simulation time 384584248 ps
CPU time 2.15 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:13 PM PDT 24
Peak memory 199304 kb
Host smart-5c785339-0318-452f-b8c0-b11c2a3a2cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032997260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2032997260
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2795643145
Short name T724
Test name
Test status
Simulation time 32979247 ps
CPU time 0.64 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:30 PM PDT 24
Peak memory 193876 kb
Host smart-72679904-bcc5-4a0c-bc3a-855fc985219a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795643145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2795643145
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2456512813
Short name T647
Test name
Test status
Simulation time 52019947 ps
CPU time 0.6 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 194136 kb
Host smart-3d0322b6-fdec-405a-9576-1ac1468fc212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456512813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2456512813
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2878427907
Short name T608
Test name
Test status
Simulation time 40864836 ps
CPU time 0.57 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:30 PM PDT 24
Peak memory 193876 kb
Host smart-806172ac-e3ba-4e6d-8fa2-e3f58e33d3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878427907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2878427907
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3971563099
Short name T656
Test name
Test status
Simulation time 14271734 ps
CPU time 0.58 seconds
Started Apr 18 01:50:40 PM PDT 24
Finished Apr 18 01:50:41 PM PDT 24
Peak memory 193980 kb
Host smart-0620c12e-66be-4726-9536-62e62ceaad41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971563099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3971563099
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2889872584
Short name T672
Test name
Test status
Simulation time 16651277 ps
CPU time 0.59 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 193936 kb
Host smart-d82558ad-f614-45e5-87df-33b13d37927b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889872584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2889872584
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.393454271
Short name T659
Test name
Test status
Simulation time 11602402 ps
CPU time 0.66 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 193864 kb
Host smart-0f90b6e7-5d79-48a1-bab3-1e8b6668e307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393454271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.393454271
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.59677873
Short name T722
Test name
Test status
Simulation time 13460031 ps
CPU time 0.6 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 193804 kb
Host smart-65f6fe91-57e3-4a72-b0ae-e7833ccd3f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59677873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.59677873
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3179109192
Short name T603
Test name
Test status
Simulation time 41135085 ps
CPU time 0.63 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 193888 kb
Host smart-bfd00eca-ee29-426b-bf49-bbad5ae378ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179109192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3179109192
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.117356018
Short name T641
Test name
Test status
Simulation time 60547713 ps
CPU time 0.59 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 193860 kb
Host smart-e61138f9-a6a0-42e3-a797-0cfafd2c0fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117356018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.117356018
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2943897738
Short name T616
Test name
Test status
Simulation time 14315181 ps
CPU time 0.59 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 194112 kb
Host smart-1dc2e500-de66-43a2-94c6-a93c5bfd1063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943897738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2943897738
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.491605258
Short name T117
Test name
Test status
Simulation time 614749950 ps
CPU time 3.06 seconds
Started Apr 18 01:50:12 PM PDT 24
Finished Apr 18 01:50:16 PM PDT 24
Peak memory 198220 kb
Host smart-a8c0f6b9-de9d-43bb-ad94-8c3c96b1a3ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491605258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.491605258
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1958525600
Short name T675
Test name
Test status
Simulation time 6245102210 ps
CPU time 16.95 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 198472 kb
Host smart-5117e03a-2d7c-450c-9158-97b2c3487e45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958525600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1958525600
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1188179390
Short name T649
Test name
Test status
Simulation time 27456864 ps
CPU time 0.85 seconds
Started Apr 18 01:50:11 PM PDT 24
Finished Apr 18 01:50:12 PM PDT 24
Peak memory 198368 kb
Host smart-85678557-808c-4986-87cc-825f54a826fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188179390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1188179390
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1101236767
Short name T651
Test name
Test status
Simulation time 208336307 ps
CPU time 3.42 seconds
Started Apr 18 01:50:16 PM PDT 24
Finished Apr 18 01:50:20 PM PDT 24
Peak memory 199364 kb
Host smart-d29fd19b-e178-47ef-9165-a198e684ab33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101236767 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1101236767
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2680772728
Short name T112
Test name
Test status
Simulation time 23614539 ps
CPU time 0.67 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 196704 kb
Host smart-759305c3-4d62-43e3-9eb7-16825fa69e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680772728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2680772728
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2693051921
Short name T680
Test name
Test status
Simulation time 60353948 ps
CPU time 0.63 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:28 PM PDT 24
Peak memory 193788 kb
Host smart-f20ed21c-a976-41e4-b3b0-08254a088d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693051921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2693051921
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3031669461
Short name T629
Test name
Test status
Simulation time 45920426 ps
CPU time 2.05 seconds
Started Apr 18 01:50:18 PM PDT 24
Finished Apr 18 01:50:20 PM PDT 24
Peak memory 199244 kb
Host smart-1a02059d-4f37-4b62-8cfb-cd56356d26c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031669461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3031669461
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1986072766
Short name T661
Test name
Test status
Simulation time 187927686 ps
CPU time 3.58 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:14 PM PDT 24
Peak memory 199300 kb
Host smart-54c7fa8a-5e8e-4bc0-9a0a-96ed4fd04435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986072766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1986072766
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.949303874
Short name T126
Test name
Test status
Simulation time 160811791 ps
CPU time 2.98 seconds
Started Apr 18 01:50:06 PM PDT 24
Finished Apr 18 01:50:10 PM PDT 24
Peak memory 199224 kb
Host smart-65ca593f-adc8-46a4-a665-12174a7e964a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949303874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.949303874
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2381658108
Short name T716
Test name
Test status
Simulation time 50297982 ps
CPU time 0.6 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:32 PM PDT 24
Peak memory 193940 kb
Host smart-54de90cd-375f-4c9a-bbda-df033b3cf4c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381658108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2381658108
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2032083981
Short name T678
Test name
Test status
Simulation time 57611966 ps
CPU time 0.61 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:28 PM PDT 24
Peak memory 193944 kb
Host smart-8f43b05e-c57e-4c48-92f8-99b951c07924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032083981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2032083981
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1925170656
Short name T685
Test name
Test status
Simulation time 12726324 ps
CPU time 0.59 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 194104 kb
Host smart-f1c7e1be-9038-4850-b3cc-a300eeb8a246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925170656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1925170656
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2592371670
Short name T643
Test name
Test status
Simulation time 61474594 ps
CPU time 0.59 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:29 PM PDT 24
Peak memory 193900 kb
Host smart-bf180d25-dec5-416b-b026-0e7496826c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592371670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2592371670
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3278332662
Short name T632
Test name
Test status
Simulation time 102758958 ps
CPU time 0.59 seconds
Started Apr 18 01:50:35 PM PDT 24
Finished Apr 18 01:50:36 PM PDT 24
Peak memory 193840 kb
Host smart-e9ea97d3-c1aa-452c-ba81-2adaeeddeb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278332662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3278332662
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2314854971
Short name T669
Test name
Test status
Simulation time 11163849 ps
CPU time 0.61 seconds
Started Apr 18 01:50:41 PM PDT 24
Finished Apr 18 01:50:42 PM PDT 24
Peak memory 193788 kb
Host smart-d0da8f4b-d2b3-41a3-942e-0626d400bce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314854971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2314854971
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1113295798
Short name T614
Test name
Test status
Simulation time 15050887 ps
CPU time 0.58 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:35 PM PDT 24
Peak memory 194128 kb
Host smart-f91e9995-5c5f-4cda-a14a-ae50456ab7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113295798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1113295798
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1738988469
Short name T676
Test name
Test status
Simulation time 32301484 ps
CPU time 0.59 seconds
Started Apr 18 01:50:35 PM PDT 24
Finished Apr 18 01:50:36 PM PDT 24
Peak memory 193948 kb
Host smart-d947a3a1-4517-4b3a-9855-b3c3bc361b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738988469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1738988469
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1951420800
Short name T92
Test name
Test status
Simulation time 60824630 ps
CPU time 0.59 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 193896 kb
Host smart-25ec17c1-e00a-429b-91d9-612a8000eebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951420800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1951420800
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2744999331
Short name T644
Test name
Test status
Simulation time 15517864 ps
CPU time 0.57 seconds
Started Apr 18 01:50:30 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 193864 kb
Host smart-4f3cd9a4-5f6a-4815-aca2-bc01b26ddc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744999331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2744999331
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1888643616
Short name T622
Test name
Test status
Simulation time 51120934 ps
CPU time 3.45 seconds
Started Apr 18 01:50:20 PM PDT 24
Finished Apr 18 01:50:24 PM PDT 24
Peak memory 199332 kb
Host smart-2f32829a-8469-4afa-8d3b-3057e7a2dc10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888643616 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1888643616
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.735384593
Short name T703
Test name
Test status
Simulation time 81923330 ps
CPU time 0.78 seconds
Started Apr 18 01:50:08 PM PDT 24
Finished Apr 18 01:50:09 PM PDT 24
Peak memory 199048 kb
Host smart-d7a78612-c245-4b7c-a379-eb617660fa39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735384593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.735384593
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.4136532989
Short name T714
Test name
Test status
Simulation time 71485874 ps
CPU time 0.62 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:28 PM PDT 24
Peak memory 193832 kb
Host smart-da76b03f-f826-4bf3-b882-cfff3a6d03b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136532989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.4136532989
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1700111231
Short name T653
Test name
Test status
Simulation time 150750826 ps
CPU time 2.58 seconds
Started Apr 18 01:50:28 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 198920 kb
Host smart-97a76d52-a063-43c1-8283-77f0fbfd1d93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700111231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1700111231
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3795301891
Short name T604
Test name
Test status
Simulation time 498573123 ps
CPU time 2.7 seconds
Started Apr 18 01:50:07 PM PDT 24
Finished Apr 18 01:50:10 PM PDT 24
Peak memory 199276 kb
Host smart-7c29563e-de3f-4832-b305-a740dccff590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795301891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3795301891
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.28346905
Short name T127
Test name
Test status
Simulation time 91078401 ps
CPU time 1.87 seconds
Started Apr 18 01:50:29 PM PDT 24
Finished Apr 18 01:50:32 PM PDT 24
Peak memory 199256 kb
Host smart-d330d7b5-2ad7-4c12-a6f2-8de9923c30a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28346905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.28346905
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2299246933
Short name T652
Test name
Test status
Simulation time 261028172 ps
CPU time 1.76 seconds
Started Apr 18 01:50:08 PM PDT 24
Finished Apr 18 01:50:10 PM PDT 24
Peak memory 199264 kb
Host smart-b4867105-8791-48e3-8c19-5f663bd3d073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299246933 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2299246933
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3193646705
Short name T667
Test name
Test status
Simulation time 29391974 ps
CPU time 0.86 seconds
Started Apr 18 01:50:12 PM PDT 24
Finished Apr 18 01:50:13 PM PDT 24
Peak memory 198252 kb
Host smart-92b57655-24af-4e7c-b937-c23532ecb3ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193646705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3193646705
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4227295850
Short name T618
Test name
Test status
Simulation time 18913168 ps
CPU time 0.67 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:28 PM PDT 24
Peak memory 193832 kb
Host smart-a288707f-9837-4331-9c25-86e9c70a721f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227295850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4227295850
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3408696943
Short name T648
Test name
Test status
Simulation time 90305885 ps
CPU time 1.72 seconds
Started Apr 18 01:50:10 PM PDT 24
Finished Apr 18 01:50:13 PM PDT 24
Peak memory 198972 kb
Host smart-f0f14a87-c50f-4531-9d06-7ada5f026875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408696943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3408696943
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2453860247
Short name T662
Test name
Test status
Simulation time 220759228 ps
CPU time 4.19 seconds
Started Apr 18 01:50:21 PM PDT 24
Finished Apr 18 01:50:26 PM PDT 24
Peak memory 199248 kb
Host smart-ab3e9b63-6596-4c16-ada7-bf54603436ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453860247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2453860247
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.138454379
Short name T646
Test name
Test status
Simulation time 36077979 ps
CPU time 2.52 seconds
Started Apr 18 01:50:23 PM PDT 24
Finished Apr 18 01:50:26 PM PDT 24
Peak memory 199292 kb
Host smart-8447d75d-36ed-4475-8ca2-a3c7f76b0beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138454379 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.138454379
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3574780098
Short name T114
Test name
Test status
Simulation time 204228281 ps
CPU time 0.74 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:50:27 PM PDT 24
Peak memory 196652 kb
Host smart-50810d27-8999-4fdb-8d3f-034050e446c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574780098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3574780098
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1790748179
Short name T712
Test name
Test status
Simulation time 35295731 ps
CPU time 0.55 seconds
Started Apr 18 01:50:24 PM PDT 24
Finished Apr 18 01:50:25 PM PDT 24
Peak memory 193864 kb
Host smart-b8136026-6d84-4d39-900b-0e8588831f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790748179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1790748179
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3699716623
Short name T600
Test name
Test status
Simulation time 92722998 ps
CPU time 2.38 seconds
Started Apr 18 01:50:17 PM PDT 24
Finished Apr 18 01:50:20 PM PDT 24
Peak memory 199004 kb
Host smart-aae2ae7f-5a18-4b62-8944-b494b753a802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699716623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3699716623
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2137571254
Short name T645
Test name
Test status
Simulation time 294709392 ps
CPU time 4.49 seconds
Started Apr 18 01:50:08 PM PDT 24
Finished Apr 18 01:50:13 PM PDT 24
Peak memory 199232 kb
Host smart-a4c0ec48-d083-40fb-8733-fc17d98d9b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137571254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2137571254
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1592624173
Short name T122
Test name
Test status
Simulation time 298362275 ps
CPU time 2.96 seconds
Started Apr 18 01:50:27 PM PDT 24
Finished Apr 18 01:50:31 PM PDT 24
Peak memory 199260 kb
Host smart-f280e9f0-f5a8-41a1-bb96-bf7471a62fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592624173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1592624173
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.482778224
Short name T720
Test name
Test status
Simulation time 34326813 ps
CPU time 1.09 seconds
Started Apr 18 01:50:25 PM PDT 24
Finished Apr 18 01:50:26 PM PDT 24
Peak memory 199168 kb
Host smart-a1103dd8-e93b-4e23-bcda-4a57405af8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482778224 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.482778224
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1030831849
Short name T700
Test name
Test status
Simulation time 12509111 ps
CPU time 0.67 seconds
Started Apr 18 01:50:31 PM PDT 24
Finished Apr 18 01:50:33 PM PDT 24
Peak memory 196832 kb
Host smart-9aec3290-e44a-47da-b196-4530fda16a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030831849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1030831849
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3620479610
Short name T624
Test name
Test status
Simulation time 221467217 ps
CPU time 0.6 seconds
Started Apr 18 01:50:17 PM PDT 24
Finished Apr 18 01:50:18 PM PDT 24
Peak memory 193944 kb
Host smart-d995c0c8-142c-416a-a786-0d21840ee17d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620479610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3620479610
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2068347507
Short name T679
Test name
Test status
Simulation time 256915332 ps
CPU time 2.18 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:36 PM PDT 24
Peak memory 198916 kb
Host smart-f6afa2f4-83ad-43d9-bd37-1168ed1017f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068347507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2068347507
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1533509979
Short name T690
Test name
Test status
Simulation time 423849902 ps
CPU time 4.09 seconds
Started Apr 18 01:50:11 PM PDT 24
Finished Apr 18 01:50:16 PM PDT 24
Peak memory 199296 kb
Host smart-56bfdd33-fcdd-424a-b241-2aa842b42070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533509979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1533509979
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4017797066
Short name T130
Test name
Test status
Simulation time 240442184 ps
CPU time 4.03 seconds
Started Apr 18 01:50:11 PM PDT 24
Finished Apr 18 01:50:15 PM PDT 24
Peak memory 199208 kb
Host smart-b83f0c3a-87e2-426c-a8ee-e31ee22144ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017797066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4017797066
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3414255598
Short name T610
Test name
Test status
Simulation time 606665060 ps
CPU time 2.38 seconds
Started Apr 18 01:50:34 PM PDT 24
Finished Apr 18 01:50:37 PM PDT 24
Peak memory 199228 kb
Host smart-ffaf8875-9c07-4dd4-89ab-ad1899fb5317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414255598 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3414255598
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1115868755
Short name T726
Test name
Test status
Simulation time 91362561 ps
CPU time 0.78 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 198120 kb
Host smart-30d3eae9-38e0-4305-9fe5-f7810e8520f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115868755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1115868755
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.805961058
Short name T718
Test name
Test status
Simulation time 42267453 ps
CPU time 0.56 seconds
Started Apr 18 01:50:20 PM PDT 24
Finished Apr 18 01:50:21 PM PDT 24
Peak memory 193876 kb
Host smart-8278a11d-5f0d-43d6-9fed-72c2fdff78a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805961058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.805961058
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4071238969
Short name T602
Test name
Test status
Simulation time 213417575 ps
CPU time 1.2 seconds
Started Apr 18 01:50:32 PM PDT 24
Finished Apr 18 01:50:34 PM PDT 24
Peak memory 199208 kb
Host smart-a91c5dae-00ef-408f-a037-3a5d5909a974
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071238969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4071238969
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2203521357
Short name T597
Test name
Test status
Simulation time 325827763 ps
CPU time 3.34 seconds
Started Apr 18 01:50:33 PM PDT 24
Finished Apr 18 01:50:38 PM PDT 24
Peak memory 199240 kb
Host smart-9572ca8c-1cac-4be0-885e-58a9bd0bfbb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203521357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2203521357
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3278545847
Short name T131
Test name
Test status
Simulation time 2740131513 ps
CPU time 4.27 seconds
Started Apr 18 01:50:21 PM PDT 24
Finished Apr 18 01:50:26 PM PDT 24
Peak memory 199368 kb
Host smart-ed0727e7-1847-4826-8d4d-959ad3dc8cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278545847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3278545847
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3578452947
Short name T243
Test name
Test status
Simulation time 43265986 ps
CPU time 0.58 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 12:55:43 PM PDT 24
Peak memory 195152 kb
Host smart-8598b225-ed05-4cde-b63f-39d94f757876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578452947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3578452947
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.124944946
Short name T57
Test name
Test status
Simulation time 3669967366 ps
CPU time 16.93 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:46 PM PDT 24
Peak memory 208892 kb
Host smart-c7f17912-c62f-412c-98b9-a87666b61d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124944946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.124944946
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3619155180
Short name T580
Test name
Test status
Simulation time 2638531456 ps
CPU time 36.99 seconds
Started Apr 18 12:55:28 PM PDT 24
Finished Apr 18 12:56:05 PM PDT 24
Peak memory 199668 kb
Host smart-f2ede2ed-fcf4-4a63-a78a-b7946bd49639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619155180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3619155180
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1102080005
Short name T216
Test name
Test status
Simulation time 2081720484 ps
CPU time 111.06 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:57:21 PM PDT 24
Peak memory 199592 kb
Host smart-ea36dcf4-0ae9-46c8-9b69-b77dc71a382d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102080005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1102080005
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3214511749
Short name T477
Test name
Test status
Simulation time 2391326201 ps
CPU time 42.48 seconds
Started Apr 18 12:55:32 PM PDT 24
Finished Apr 18 12:56:16 PM PDT 24
Peak memory 199724 kb
Host smart-bfadd972-9f9e-4e15-afab-3e5675db00fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214511749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3214511749
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3800935290
Short name T587
Test name
Test status
Simulation time 2205063391 ps
CPU time 14.63 seconds
Started Apr 18 12:55:33 PM PDT 24
Finished Apr 18 12:55:48 PM PDT 24
Peak memory 199680 kb
Host smart-5eecdc34-b1e7-4da3-9ee7-bb2c442968fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800935290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3800935290
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1736826970
Short name T35
Test name
Test status
Simulation time 65148219 ps
CPU time 0.78 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 218116 kb
Host smart-abfbeeb8-07b7-4d85-8def-e194f20410dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736826970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1736826970
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3935609937
Short name T418
Test name
Test status
Simulation time 37727759 ps
CPU time 0.94 seconds
Started Apr 18 12:55:33 PM PDT 24
Finished Apr 18 12:55:34 PM PDT 24
Peak memory 199236 kb
Host smart-62979786-6db9-4509-94b7-8c84a74604dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935609937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3935609937
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1243681515
Short name T88
Test name
Test status
Simulation time 101017174846 ps
CPU time 648.64 seconds
Started Apr 18 12:55:37 PM PDT 24
Finished Apr 18 01:06:26 PM PDT 24
Peak memory 240592 kb
Host smart-4358fe33-c6b2-4870-a2bb-66e7d4d944ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243681515 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1243681515
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2063133245
Short name T483
Test name
Test status
Simulation time 139839130 ps
CPU time 1.05 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 199036 kb
Host smart-c5d6fe6d-f4d9-46f3-ac7c-7998bf9830b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063133245 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2063133245
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.497296365
Short name T452
Test name
Test status
Simulation time 69679185951 ps
CPU time 422.74 seconds
Started Apr 18 12:55:30 PM PDT 24
Finished Apr 18 01:02:34 PM PDT 24
Peak memory 199628 kb
Host smart-70c4fea7-1f21-438f-af86-302cd7f537a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497296365 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.497296365
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2506274324
Short name T297
Test name
Test status
Simulation time 3768717289 ps
CPU time 73.76 seconds
Started Apr 18 12:55:33 PM PDT 24
Finished Apr 18 12:56:47 PM PDT 24
Peak memory 199712 kb
Host smart-e5c2b58a-3acb-4871-8651-9b2c5242d6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506274324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2506274324
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2173298850
Short name T315
Test name
Test status
Simulation time 37160331 ps
CPU time 0.54 seconds
Started Apr 18 12:55:35 PM PDT 24
Finished Apr 18 12:55:36 PM PDT 24
Peak memory 194132 kb
Host smart-2af309ba-5af8-4da7-a0a0-0c93f64c1e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173298850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2173298850
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2122188764
Short name T294
Test name
Test status
Simulation time 1209428064 ps
CPU time 21.41 seconds
Started Apr 18 12:55:33 PM PDT 24
Finished Apr 18 12:55:55 PM PDT 24
Peak memory 217832 kb
Host smart-83551c71-659c-41d8-921e-03cfbecff24e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122188764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2122188764
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.285940258
Short name T335
Test name
Test status
Simulation time 3687622942 ps
CPU time 53.06 seconds
Started Apr 18 12:55:38 PM PDT 24
Finished Apr 18 12:56:32 PM PDT 24
Peak memory 199680 kb
Host smart-109e8ea7-2c9f-4481-aac9-872703670118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285940258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.285940258
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2734326649
Short name T507
Test name
Test status
Simulation time 4607382289 ps
CPU time 130.98 seconds
Started Apr 18 12:55:44 PM PDT 24
Finished Apr 18 12:57:56 PM PDT 24
Peak memory 199700 kb
Host smart-faead3f0-4690-4135-9a0b-e87d835ddebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734326649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2734326649
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.967110327
Short name T51
Test name
Test status
Simulation time 9861226823 ps
CPU time 47.35 seconds
Started Apr 18 12:55:34 PM PDT 24
Finished Apr 18 12:56:22 PM PDT 24
Peak memory 199732 kb
Host smart-2de443af-d311-41f6-852f-fed38812ff14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967110327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.967110327
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.828416155
Short name T221
Test name
Test status
Simulation time 77123407613 ps
CPU time 74.03 seconds
Started Apr 18 12:55:44 PM PDT 24
Finished Apr 18 12:56:59 PM PDT 24
Peak memory 199660 kb
Host smart-48bfa5a0-6226-44e0-acc7-e64c3080da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828416155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.828416155
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3928072649
Short name T246
Test name
Test status
Simulation time 250085849 ps
CPU time 3.8 seconds
Started Apr 18 12:55:34 PM PDT 24
Finished Apr 18 12:55:39 PM PDT 24
Peak memory 199520 kb
Host smart-a053a0c3-9142-4433-a090-23fca064b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928072649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3928072649
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4259350943
Short name T47
Test name
Test status
Simulation time 49169256863 ps
CPU time 302.95 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 01:00:45 PM PDT 24
Peak memory 240256 kb
Host smart-21ec11df-b5f6-4af1-8ee4-7fabf20862ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259350943 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4259350943
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2857111951
Short name T555
Test name
Test status
Simulation time 547623918 ps
CPU time 1.03 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 12:55:44 PM PDT 24
Peak memory 198884 kb
Host smart-5f1b0195-6658-4e45-9d19-19dfa4d91bc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857111951 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2857111951
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2473479963
Short name T257
Test name
Test status
Simulation time 33617281189 ps
CPU time 429.93 seconds
Started Apr 18 12:55:33 PM PDT 24
Finished Apr 18 01:02:44 PM PDT 24
Peak memory 199700 kb
Host smart-d707d503-09fe-4cd4-8b84-73145838adc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473479963 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2473479963
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.574144532
Short name T445
Test name
Test status
Simulation time 400877996 ps
CPU time 7.87 seconds
Started Apr 18 12:55:34 PM PDT 24
Finished Apr 18 12:55:43 PM PDT 24
Peak memory 199508 kb
Host smart-01d745c0-1b83-4b01-b008-4ad60e184ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574144532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.574144532
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1751569885
Short name T107
Test name
Test status
Simulation time 11488636 ps
CPU time 0.57 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 12:56:11 PM PDT 24
Peak memory 194096 kb
Host smart-62ec3680-4b12-4930-90c4-3e0ac78bfdca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751569885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1751569885
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.929287233
Short name T416
Test name
Test status
Simulation time 854500004 ps
CPU time 26.81 seconds
Started Apr 18 12:56:06 PM PDT 24
Finished Apr 18 12:56:34 PM PDT 24
Peak memory 207808 kb
Host smart-12d4159f-9520-4b2d-88c9-9283848c1435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929287233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.929287233
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2510350322
Short name T394
Test name
Test status
Simulation time 2668111060 ps
CPU time 42.5 seconds
Started Apr 18 12:56:04 PM PDT 24
Finished Apr 18 12:56:48 PM PDT 24
Peak memory 199696 kb
Host smart-ff8959ee-7198-4efb-aece-894e0612c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510350322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2510350322
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2338448822
Short name T447
Test name
Test status
Simulation time 12569088744 ps
CPU time 83.85 seconds
Started Apr 18 12:56:05 PM PDT 24
Finished Apr 18 12:57:30 PM PDT 24
Peak memory 199736 kb
Host smart-4c989cce-7b28-4bc5-9a8e-8e5e9750990d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338448822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2338448822
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3167184426
Short name T465
Test name
Test status
Simulation time 386667776 ps
CPU time 7.62 seconds
Started Apr 18 12:56:19 PM PDT 24
Finished Apr 18 12:56:28 PM PDT 24
Peak memory 199596 kb
Host smart-dc0990a2-8b7c-4f0a-a095-1c00626a0f7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167184426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3167184426
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3954720557
Short name T379
Test name
Test status
Simulation time 24530579407 ps
CPU time 87.83 seconds
Started Apr 18 12:56:08 PM PDT 24
Finished Apr 18 12:57:36 PM PDT 24
Peak memory 199712 kb
Host smart-b05e3616-7a57-4fe3-a047-41f03f98675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954720557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3954720557
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.322112819
Short name T254
Test name
Test status
Simulation time 3042585758 ps
CPU time 3.05 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 12:56:07 PM PDT 24
Peak memory 199732 kb
Host smart-73e4a4c9-8d25-4c52-8a72-c931cc9ef5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322112819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.322112819
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.922478539
Short name T358
Test name
Test status
Simulation time 45878773 ps
CPU time 1.01 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:56:18 PM PDT 24
Peak memory 198856 kb
Host smart-00c34257-9685-415d-9181-db0e93392e52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922478539 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.922478539
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3949661753
Short name T106
Test name
Test status
Simulation time 28140675214 ps
CPU time 468.18 seconds
Started Apr 18 12:56:04 PM PDT 24
Finished Apr 18 01:03:53 PM PDT 24
Peak memory 199720 kb
Host smart-08581cc1-5e9a-456c-96ec-c268298e7f13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949661753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3949661753
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2523761489
Short name T45
Test name
Test status
Simulation time 2777331059 ps
CPU time 44.32 seconds
Started Apr 18 12:56:06 PM PDT 24
Finished Apr 18 12:56:52 PM PDT 24
Peak memory 199660 kb
Host smart-029d220f-49c1-4ebb-a7f0-d12fe410ad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523761489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2523761489
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1066743276
Short name T356
Test name
Test status
Simulation time 13877200 ps
CPU time 0.59 seconds
Started Apr 18 12:56:05 PM PDT 24
Finished Apr 18 12:56:06 PM PDT 24
Peak memory 195220 kb
Host smart-95a8fc5f-157d-4122-b34a-b2f12141f0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066743276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1066743276
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2282340417
Short name T588
Test name
Test status
Simulation time 3055152703 ps
CPU time 34.72 seconds
Started Apr 18 12:56:08 PM PDT 24
Finished Apr 18 12:56:43 PM PDT 24
Peak memory 236328 kb
Host smart-58eb6dc6-9020-472a-9bf5-f542f556977d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282340417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2282340417
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.509525029
Short name T499
Test name
Test status
Simulation time 10893485195 ps
CPU time 40.21 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 12:56:44 PM PDT 24
Peak memory 199636 kb
Host smart-84b8fed9-b463-4cb3-94a8-4db4573a9241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509525029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.509525029
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.788317238
Short name T322
Test name
Test status
Simulation time 10111879626 ps
CPU time 94.06 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:57:51 PM PDT 24
Peak memory 199620 kb
Host smart-b7a9bdd4-886e-49bf-b5e2-8afca4b3ffb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788317238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.788317238
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.216473588
Short name T144
Test name
Test status
Simulation time 2625636913 ps
CPU time 139.46 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:58:37 PM PDT 24
Peak memory 199612 kb
Host smart-db30c246-7676-43a2-b0ca-421c703c7d9a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216473588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.216473588
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.533443597
Short name T200
Test name
Test status
Simulation time 496665356 ps
CPU time 4.01 seconds
Started Apr 18 12:56:05 PM PDT 24
Finished Apr 18 12:56:09 PM PDT 24
Peak memory 199540 kb
Host smart-b7e0f348-9036-4ce6-a3fe-a5bc5c65a293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533443597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.533443597
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.4033744741
Short name T371
Test name
Test status
Simulation time 394594508 ps
CPU time 6.12 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:23 PM PDT 24
Peak memory 199480 kb
Host smart-e0422eb8-da96-4900-a92b-d30e00524129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033744741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.4033744741
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1623488715
Short name T415
Test name
Test status
Simulation time 119509904 ps
CPU time 1.06 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:19 PM PDT 24
Peak memory 199312 kb
Host smart-5cc7c1ac-aa37-48b2-8bc6-64f47a91003b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623488715 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1623488715
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1592319975
Short name T223
Test name
Test status
Simulation time 9154022605 ps
CPU time 476.05 seconds
Started Apr 18 12:56:07 PM PDT 24
Finished Apr 18 01:04:04 PM PDT 24
Peak memory 199672 kb
Host smart-0bb0fcba-60ae-4dc2-94e2-e70a36852791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592319975 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1592319975
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1659567164
Short name T30
Test name
Test status
Simulation time 2444907331 ps
CPU time 45.44 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:57:02 PM PDT 24
Peak memory 199608 kb
Host smart-dc7d7d5c-fd88-44e7-98c9-b5c80ecae28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659567164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1659567164
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1402411262
Short name T593
Test name
Test status
Simulation time 17329168 ps
CPU time 0.59 seconds
Started Apr 18 12:56:06 PM PDT 24
Finished Apr 18 12:56:08 PM PDT 24
Peak memory 195184 kb
Host smart-b4d4e380-12d5-4c7a-947e-7041389b766e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402411262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1402411262
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.546187040
Short name T392
Test name
Test status
Simulation time 1137576400 ps
CPU time 40.94 seconds
Started Apr 18 12:56:08 PM PDT 24
Finished Apr 18 12:56:50 PM PDT 24
Peak memory 225916 kb
Host smart-5ea97d00-7024-4177-a990-d216cd8b55a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546187040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.546187040
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4008226836
Short name T562
Test name
Test status
Simulation time 1089247696 ps
CPU time 21.98 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 12:56:32 PM PDT 24
Peak memory 199516 kb
Host smart-67e022f2-5de9-4567-97c5-192be72b9b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008226836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4008226836
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1271865647
Short name T210
Test name
Test status
Simulation time 1803402944 ps
CPU time 99.21 seconds
Started Apr 18 12:56:05 PM PDT 24
Finished Apr 18 12:57:46 PM PDT 24
Peak memory 199528 kb
Host smart-b546f36f-3d18-4f62-a28f-01fa3997fb27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271865647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1271865647
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2559723891
Short name T265
Test name
Test status
Simulation time 22181172379 ps
CPU time 96.83 seconds
Started Apr 18 12:56:05 PM PDT 24
Finished Apr 18 12:57:43 PM PDT 24
Peak memory 199660 kb
Host smart-6641c55b-ec62-488d-a511-c11d67b0d06e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559723891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2559723891
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3296273847
Short name T370
Test name
Test status
Simulation time 3426118888 ps
CPU time 59.79 seconds
Started Apr 18 12:56:07 PM PDT 24
Finished Apr 18 12:57:08 PM PDT 24
Peak memory 199740 kb
Host smart-a048fd6f-8710-4997-88d5-5be0de39fe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296273847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3296273847
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3955875424
Short name T569
Test name
Test status
Simulation time 345537331 ps
CPU time 2.84 seconds
Started Apr 18 12:56:13 PM PDT 24
Finished Apr 18 12:56:18 PM PDT 24
Peak memory 199488 kb
Host smart-0dee820a-2dfd-4745-8929-7bb4a389d302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955875424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3955875424
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3122607339
Short name T417
Test name
Test status
Simulation time 120486748692 ps
CPU time 1624.3 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 01:23:21 PM PDT 24
Peak memory 219064 kb
Host smart-302dee9e-b938-4e1f-92ae-ac595d04275a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122607339 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3122607339
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2644427413
Short name T135
Test name
Test status
Simulation time 234372107 ps
CPU time 1.19 seconds
Started Apr 18 12:56:05 PM PDT 24
Finished Apr 18 12:56:07 PM PDT 24
Peak memory 199480 kb
Host smart-215ce33f-5adc-463b-8a09-670f425d4b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644427413 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2644427413
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2602364038
Short name T314
Test name
Test status
Simulation time 166160532959 ps
CPU time 478.2 seconds
Started Apr 18 12:56:06 PM PDT 24
Finished Apr 18 01:04:05 PM PDT 24
Peak memory 199736 kb
Host smart-3d717ae4-fe18-4cdd-9b86-c1fabd24b919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602364038 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2602364038
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1400989524
Short name T383
Test name
Test status
Simulation time 2884261239 ps
CPU time 54.18 seconds
Started Apr 18 12:56:11 PM PDT 24
Finished Apr 18 12:57:06 PM PDT 24
Peak memory 199724 kb
Host smart-067e153f-ce46-4688-b6f2-abc4ed9e0892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400989524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1400989524
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1814558827
Short name T338
Test name
Test status
Simulation time 16827969 ps
CPU time 0.55 seconds
Started Apr 18 12:56:11 PM PDT 24
Finished Apr 18 12:56:13 PM PDT 24
Peak memory 194896 kb
Host smart-3ea2716b-b8df-4ea5-8ca5-94c84c0bbbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814558827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1814558827
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2722951481
Short name T293
Test name
Test status
Simulation time 2018382445 ps
CPU time 40.46 seconds
Started Apr 18 12:56:12 PM PDT 24
Finished Apr 18 12:56:54 PM PDT 24
Peak memory 234404 kb
Host smart-b55adcd9-2059-489a-af7a-8430df757391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722951481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2722951481
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2344514932
Short name T136
Test name
Test status
Simulation time 317425909 ps
CPU time 6.19 seconds
Started Apr 18 12:56:08 PM PDT 24
Finished Apr 18 12:56:16 PM PDT 24
Peak memory 199568 kb
Host smart-3359c145-4157-440c-b8b2-2e57c4c76a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344514932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2344514932
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_error.2776497130
Short name T319
Test name
Test status
Simulation time 843112835 ps
CPU time 23.01 seconds
Started Apr 18 12:56:12 PM PDT 24
Finished Apr 18 12:56:36 PM PDT 24
Peak memory 199564 kb
Host smart-304477e8-ba7f-40ec-81f1-6cc5757ee71b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776497130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2776497130
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.754749070
Short name T268
Test name
Test status
Simulation time 6370772241 ps
CPU time 116.96 seconds
Started Apr 18 12:56:10 PM PDT 24
Finished Apr 18 12:58:08 PM PDT 24
Peak memory 199720 kb
Host smart-96e4759a-c909-46a4-8fb0-d96f8dab12ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754749070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.754749070
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2324480052
Short name T537
Test name
Test status
Simulation time 2817392010 ps
CPU time 7.3 seconds
Started Apr 18 12:56:10 PM PDT 24
Finished Apr 18 12:56:19 PM PDT 24
Peak memory 199744 kb
Host smart-4b23a1d7-de9e-49b3-8d9f-84aa9c738976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324480052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2324480052
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2453813343
Short name T329
Test name
Test status
Simulation time 33107585323 ps
CPU time 1743.32 seconds
Started Apr 18 12:56:11 PM PDT 24
Finished Apr 18 01:25:15 PM PDT 24
Peak memory 248080 kb
Host smart-a73d8c00-d782-4a1c-856a-f4c13c96cad2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453813343 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2453813343
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2133862000
Short name T48
Test name
Test status
Simulation time 119839037 ps
CPU time 1.27 seconds
Started Apr 18 12:56:12 PM PDT 24
Finished Apr 18 12:56:14 PM PDT 24
Peak memory 199560 kb
Host smart-bd7b17bb-8113-47ff-b09f-01afa50dbac0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133862000 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2133862000
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3176648593
Short name T482
Test name
Test status
Simulation time 168198786555 ps
CPU time 502.11 seconds
Started Apr 18 12:56:13 PM PDT 24
Finished Apr 18 01:04:36 PM PDT 24
Peak memory 199736 kb
Host smart-f0a509b6-591f-4a18-a249-37d08b268325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176648593 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3176648593
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.444566827
Short name T583
Test name
Test status
Simulation time 1685151370 ps
CPU time 61.84 seconds
Started Apr 18 12:56:11 PM PDT 24
Finished Apr 18 12:57:14 PM PDT 24
Peak memory 199592 kb
Host smart-e04001fd-e390-40e3-94d6-8c416d63760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444566827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.444566827
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.2638165300
Short name T11
Test name
Test status
Simulation time 182541410700 ps
CPU time 2128.04 seconds
Started Apr 18 12:59:22 PM PDT 24
Finished Apr 18 01:34:51 PM PDT 24
Peak memory 232368 kb
Host smart-f55b156b-4822-42cc-8b5f-b752a401d314
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638165300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.2638165300
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2581189518
Short name T288
Test name
Test status
Simulation time 18584006 ps
CPU time 0.54 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:18 PM PDT 24
Peak memory 195048 kb
Host smart-5318008a-a866-40be-b08f-6e88bc616e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581189518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2581189518
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1796917503
Short name T175
Test name
Test status
Simulation time 194764252 ps
CPU time 7.65 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:25 PM PDT 24
Peak memory 199556 kb
Host smart-3d6ac257-7023-4377-ade9-466e4a2b966d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796917503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1796917503
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3844308489
Short name T349
Test name
Test status
Simulation time 76577930 ps
CPU time 3.71 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:56:21 PM PDT 24
Peak memory 199576 kb
Host smart-a7d6ddc3-bb8a-4543-88ad-884cbfe2a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844308489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3844308489
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3413543573
Short name T339
Test name
Test status
Simulation time 1811734684 ps
CPU time 105.21 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:58:02 PM PDT 24
Peak memory 199552 kb
Host smart-7b77adb5-d283-47ee-b961-0580c638690e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413543573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3413543573
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3305296865
Short name T328
Test name
Test status
Simulation time 14501938143 ps
CPU time 124.6 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 12:58:15 PM PDT 24
Peak memory 199664 kb
Host smart-919b723e-9beb-43b9-8ef0-596a65f1bd13
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305296865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3305296865
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2381457241
Short name T64
Test name
Test status
Simulation time 1574416773 ps
CPU time 20.16 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 12:56:30 PM PDT 24
Peak memory 199588 kb
Host smart-c0e4459b-e1f7-4669-b804-97ae991dfeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381457241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2381457241
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1824350592
Short name T271
Test name
Test status
Simulation time 191838159 ps
CPU time 3.1 seconds
Started Apr 18 12:56:10 PM PDT 24
Finished Apr 18 12:56:14 PM PDT 24
Peak memory 199536 kb
Host smart-f3a50bb3-3375-49e4-91cc-aa3b9525f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824350592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1824350592
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.995095651
Short name T382
Test name
Test status
Simulation time 10397486687 ps
CPU time 23.8 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:41 PM PDT 24
Peak memory 199692 kb
Host smart-730ef42c-abd4-4be7-9516-d019e43f7097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995095651 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.995095651
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1143585856
Short name T390
Test name
Test status
Simulation time 32678367 ps
CPU time 1.1 seconds
Started Apr 18 12:56:08 PM PDT 24
Finished Apr 18 12:56:10 PM PDT 24
Peak memory 199564 kb
Host smart-f2810b2c-fc16-4962-8e07-3f9d03d41177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143585856 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1143585856
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1308742746
Short name T137
Test name
Test status
Simulation time 37597902598 ps
CPU time 464.88 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 01:03:56 PM PDT 24
Peak memory 199640 kb
Host smart-2edd1d2d-4156-43ab-982b-1660cccb4f9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308742746 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1308742746
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2725602821
Short name T147
Test name
Test status
Simulation time 9652043922 ps
CPU time 31.37 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 12:56:42 PM PDT 24
Peak memory 199704 kb
Host smart-5824a335-60e4-453b-9e59-fa8e6d8ff1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725602821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2725602821
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2292032221
Short name T235
Test name
Test status
Simulation time 41557264 ps
CPU time 0.56 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:56:18 PM PDT 24
Peak memory 195056 kb
Host smart-08d3534d-3d37-4eb3-ab18-1305b75c5112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292032221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2292032221
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1544725725
Short name T581
Test name
Test status
Simulation time 169196670 ps
CPU time 5.73 seconds
Started Apr 18 12:56:13 PM PDT 24
Finished Apr 18 12:56:20 PM PDT 24
Peak memory 199624 kb
Host smart-14f8b78b-e92a-4233-955c-1713b5808ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544725725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1544725725
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.912172207
Short name T198
Test name
Test status
Simulation time 4318408577 ps
CPU time 14.92 seconds
Started Apr 18 12:56:12 PM PDT 24
Finished Apr 18 12:56:28 PM PDT 24
Peak memory 199648 kb
Host smart-801222f6-02ec-4c53-a5a2-b4def46ba748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912172207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.912172207
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2914815466
Short name T245
Test name
Test status
Simulation time 66607830 ps
CPU time 2.31 seconds
Started Apr 18 12:56:10 PM PDT 24
Finished Apr 18 12:56:14 PM PDT 24
Peak memory 199600 kb
Host smart-915d5426-274d-453d-b67e-774c800d4ea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914815466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2914815466
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.790136571
Short name T267
Test name
Test status
Simulation time 13520267960 ps
CPU time 198.74 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:59:35 PM PDT 24
Peak memory 199672 kb
Host smart-8efb4c08-6b63-428b-860a-758bed428778
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790136571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.790136571
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.688143948
Short name T523
Test name
Test status
Simulation time 955723611 ps
CPU time 52.29 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 12:57:03 PM PDT 24
Peak memory 199616 kb
Host smart-3a41a679-1dbd-4123-943e-c4742a8510e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688143948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.688143948
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2678414995
Short name T441
Test name
Test status
Simulation time 1089388719 ps
CPU time 2.76 seconds
Started Apr 18 12:56:11 PM PDT 24
Finished Apr 18 12:56:15 PM PDT 24
Peak memory 199624 kb
Host smart-c5f25bd2-d5dc-49f3-ac07-1386b32d031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678414995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2678414995
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.414339936
Short name T17
Test name
Test status
Simulation time 47162190840 ps
CPU time 168.48 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:59:06 PM PDT 24
Peak memory 199692 kb
Host smart-3ec3645f-aafc-4240-b841-366d420aa6fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414339936 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.414339936
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.265226019
Short name T461
Test name
Test status
Simulation time 115996123 ps
CPU time 1.26 seconds
Started Apr 18 12:56:09 PM PDT 24
Finished Apr 18 12:56:11 PM PDT 24
Peak memory 199568 kb
Host smart-188ab48f-8260-4f6f-bc68-a8a567cab8b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265226019 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.265226019
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.473056246
Short name T522
Test name
Test status
Simulation time 134335533769 ps
CPU time 422.23 seconds
Started Apr 18 12:56:16 PM PDT 24
Finished Apr 18 01:03:20 PM PDT 24
Peak memory 199576 kb
Host smart-f0e7d51c-8371-4425-94cf-7582b050028b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473056246 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.473056246
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2780047410
Short name T42
Test name
Test status
Simulation time 1398725449 ps
CPU time 20.2 seconds
Started Apr 18 12:56:10 PM PDT 24
Finished Apr 18 12:56:32 PM PDT 24
Peak memory 199536 kb
Host smart-ac6743a3-f9ca-447c-8553-eb3de5a3984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780047410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2780047410
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2028050124
Short name T376
Test name
Test status
Simulation time 31244245 ps
CPU time 0.54 seconds
Started Apr 18 12:56:20 PM PDT 24
Finished Apr 18 12:56:22 PM PDT 24
Peak memory 194040 kb
Host smart-95b97235-b554-4200-bcca-461b8f51ae12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028050124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2028050124
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2505796128
Short name T291
Test name
Test status
Simulation time 199944821 ps
CPU time 6.91 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:25 PM PDT 24
Peak memory 199516 kb
Host smart-1e9a9a64-43d7-490d-aaa2-d93be59bb46e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505796128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2505796128
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.538032613
Short name T414
Test name
Test status
Simulation time 541954486 ps
CPU time 2.39 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:20 PM PDT 24
Peak memory 199500 kb
Host smart-f39ba4bb-9111-478e-a4d5-33d4a2d2d847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538032613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.538032613
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1176732145
Short name T189
Test name
Test status
Simulation time 943214777 ps
CPU time 51.99 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:57:09 PM PDT 24
Peak memory 199488 kb
Host smart-e783eccb-7d6d-4084-a99e-5bc314264f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176732145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1176732145
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1133003344
Short name T535
Test name
Test status
Simulation time 19062423015 ps
CPU time 79.5 seconds
Started Apr 18 12:56:13 PM PDT 24
Finished Apr 18 12:57:34 PM PDT 24
Peak memory 199752 kb
Host smart-94a6fda4-398b-48a5-a624-a88c6373d7f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133003344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1133003344
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.41545208
Short name T486
Test name
Test status
Simulation time 50844434542 ps
CPU time 105.6 seconds
Started Apr 18 12:56:14 PM PDT 24
Finished Apr 18 12:58:02 PM PDT 24
Peak memory 199704 kb
Host smart-f867b16c-4935-44b5-8849-9f03c24baf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41545208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.41545208
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2228160364
Short name T6
Test name
Test status
Simulation time 1508937009 ps
CPU time 4.62 seconds
Started Apr 18 12:56:15 PM PDT 24
Finished Apr 18 12:56:23 PM PDT 24
Peak memory 199548 kb
Host smart-ba2c9dce-144b-4f08-959e-05f351f96cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228160364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2228160364
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2313947031
Short name T91
Test name
Test status
Simulation time 7516980344 ps
CPU time 28.33 seconds
Started Apr 18 12:56:24 PM PDT 24
Finished Apr 18 12:56:53 PM PDT 24
Peak memory 199688 kb
Host smart-c870d157-2d5a-4435-a147-07c25a9fb1a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313947031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2313947031
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3483494139
Short name T575
Test name
Test status
Simulation time 1312714517 ps
CPU time 1.21 seconds
Started Apr 18 12:56:20 PM PDT 24
Finished Apr 18 12:56:23 PM PDT 24
Peak memory 199628 kb
Host smart-d86aaf55-1fe6-4f6c-9470-622752d2bec5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483494139 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3483494139
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1055860599
Short name T281
Test name
Test status
Simulation time 35836741779 ps
CPU time 488.36 seconds
Started Apr 18 12:56:24 PM PDT 24
Finished Apr 18 01:04:34 PM PDT 24
Peak memory 199660 kb
Host smart-1247169e-9811-415a-ac15-77a998f402eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055860599 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1055860599
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1518021433
Short name T28
Test name
Test status
Simulation time 4842649252 ps
CPU time 61.63 seconds
Started Apr 18 12:56:22 PM PDT 24
Finished Apr 18 12:57:25 PM PDT 24
Peak memory 199716 kb
Host smart-b08a55dc-a8ca-46c3-b313-4a63521dbea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518021433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1518021433
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.3771477645
Short name T9
Test name
Test status
Simulation time 255796236971 ps
CPU time 1801.75 seconds
Started Apr 18 12:59:36 PM PDT 24
Finished Apr 18 01:29:39 PM PDT 24
Peak memory 260108 kb
Host smart-737e4799-2c23-432a-a1fe-6690e67a11f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771477645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.3771477645
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2533797023
Short name T79
Test name
Test status
Simulation time 13523611 ps
CPU time 0.55 seconds
Started Apr 18 12:56:27 PM PDT 24
Finished Apr 18 12:56:28 PM PDT 24
Peak memory 194140 kb
Host smart-04d34511-ddd5-4c12-a382-700f9421caae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533797023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2533797023
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2989410489
Short name T459
Test name
Test status
Simulation time 4796852530 ps
CPU time 42.34 seconds
Started Apr 18 12:56:21 PM PDT 24
Finished Apr 18 12:57:04 PM PDT 24
Peak memory 248220 kb
Host smart-f899f7e4-c7fe-483c-ad9a-7670525e3766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989410489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2989410489
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2947510938
Short name T5
Test name
Test status
Simulation time 2188150778 ps
CPU time 8.7 seconds
Started Apr 18 12:56:20 PM PDT 24
Finished Apr 18 12:56:30 PM PDT 24
Peak memory 199604 kb
Host smart-4e949f6c-69cc-4260-93ee-96e348718624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947510938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2947510938
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.236315473
Short name T134
Test name
Test status
Simulation time 3391020937 ps
CPU time 49.27 seconds
Started Apr 18 12:56:25 PM PDT 24
Finished Apr 18 12:57:15 PM PDT 24
Peak memory 199684 kb
Host smart-d6087e37-8123-43d9-8f1e-f12543a67df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236315473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.236315473
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2874932325
Short name T571
Test name
Test status
Simulation time 7599770207 ps
CPU time 35.61 seconds
Started Apr 18 12:56:26 PM PDT 24
Finished Apr 18 12:57:02 PM PDT 24
Peak memory 199512 kb
Host smart-36d980d4-e5e2-4541-8f05-9912d93df905
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874932325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2874932325
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3663376760
Short name T326
Test name
Test status
Simulation time 18675153720 ps
CPU time 87.28 seconds
Started Apr 18 12:56:22 PM PDT 24
Finished Apr 18 12:57:50 PM PDT 24
Peak memory 199664 kb
Host smart-eec2a652-534f-4012-9104-0b3621d1fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663376760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3663376760
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3478231714
Short name T44
Test name
Test status
Simulation time 48352762 ps
CPU time 0.75 seconds
Started Apr 18 12:56:20 PM PDT 24
Finished Apr 18 12:56:22 PM PDT 24
Peak memory 196996 kb
Host smart-bc4825c1-8e7c-4c9c-a99f-4df67ae1e9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478231714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3478231714
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.110829146
Short name T60
Test name
Test status
Simulation time 12283493535 ps
CPU time 71.85 seconds
Started Apr 18 12:56:20 PM PDT 24
Finished Apr 18 12:57:33 PM PDT 24
Peak memory 233000 kb
Host smart-d5593c40-5b6f-4cbf-88b1-146676991b46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110829146 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.110829146
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.70269632
Short name T553
Test name
Test status
Simulation time 57381939 ps
CPU time 1.23 seconds
Started Apr 18 12:56:20 PM PDT 24
Finished Apr 18 12:56:23 PM PDT 24
Peak memory 199556 kb
Host smart-b7d627a9-dd9a-4d2a-8f69-f29ab3c281d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70269632 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.hmac_test_hmac_vectors.70269632
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.575809779
Short name T94
Test name
Test status
Simulation time 36520476610 ps
CPU time 445.74 seconds
Started Apr 18 12:56:21 PM PDT 24
Finished Apr 18 01:03:48 PM PDT 24
Peak memory 199692 kb
Host smart-4c5272f2-c2e3-4412-86d5-7ae888e1f92b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575809779 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.575809779
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.22687310
Short name T504
Test name
Test status
Simulation time 2344565344 ps
CPU time 20.03 seconds
Started Apr 18 12:56:21 PM PDT 24
Finished Apr 18 12:56:42 PM PDT 24
Peak memory 199684 kb
Host smart-11f59e06-1d7d-4907-ab96-b7d60a9a2090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22687310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.22687310
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2450893830
Short name T24
Test name
Test status
Simulation time 11654610 ps
CPU time 0.56 seconds
Started Apr 18 12:56:33 PM PDT 24
Finished Apr 18 12:56:34 PM PDT 24
Peak memory 195096 kb
Host smart-ab917514-6e08-4229-9f7e-1c10a697e341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450893830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2450893830
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2018764552
Short name T517
Test name
Test status
Simulation time 3555554867 ps
CPU time 31.66 seconds
Started Apr 18 12:56:25 PM PDT 24
Finished Apr 18 12:56:57 PM PDT 24
Peak memory 207936 kb
Host smart-8b0ec2f3-a5c9-4cfd-aa36-e206a04edea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018764552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2018764552
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1498723280
Short name T365
Test name
Test status
Simulation time 11861035337 ps
CPU time 45.41 seconds
Started Apr 18 12:56:28 PM PDT 24
Finished Apr 18 12:57:14 PM PDT 24
Peak memory 199744 kb
Host smart-db7711d4-8ba0-4ab8-83e6-784914b985e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498723280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1498723280
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1116988523
Short name T375
Test name
Test status
Simulation time 1927815345 ps
CPU time 54.84 seconds
Started Apr 18 12:56:26 PM PDT 24
Finished Apr 18 12:57:21 PM PDT 24
Peak memory 199632 kb
Host smart-c83d5619-4641-4a02-bdec-05cd09fd1c21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116988523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1116988523
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.89754411
Short name T497
Test name
Test status
Simulation time 12975567089 ps
CPU time 213.45 seconds
Started Apr 18 12:56:26 PM PDT 24
Finished Apr 18 01:00:00 PM PDT 24
Peak memory 199636 kb
Host smart-147e0e8c-6517-4d5c-823c-5ba40d7b3952
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89754411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.89754411
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3417468588
Short name T468
Test name
Test status
Simulation time 6481484460 ps
CPU time 22.8 seconds
Started Apr 18 12:56:27 PM PDT 24
Finished Apr 18 12:56:51 PM PDT 24
Peak memory 199728 kb
Host smart-3b93b54f-629d-492a-89fe-a1eb1deb4780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417468588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3417468588
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.950689299
Short name T506
Test name
Test status
Simulation time 366176115 ps
CPU time 1.73 seconds
Started Apr 18 12:56:26 PM PDT 24
Finished Apr 18 12:56:29 PM PDT 24
Peak memory 199600 kb
Host smart-bd3c36ae-0d67-4b78-b072-7ead09c8908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950689299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.950689299
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1442168665
Short name T90
Test name
Test status
Simulation time 18748554477 ps
CPU time 145.15 seconds
Started Apr 18 12:56:28 PM PDT 24
Finished Apr 18 12:58:54 PM PDT 24
Peak memory 232472 kb
Host smart-6395480f-0c58-48ba-89fc-ba717c50852a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442168665 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1442168665
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1334744
Short name T534
Test name
Test status
Simulation time 52186857 ps
CPU time 1.01 seconds
Started Apr 18 12:56:27 PM PDT 24
Finished Apr 18 12:56:29 PM PDT 24
Peak memory 199400 kb
Host smart-626d1d03-892f-414e-b883-d4342b07d56a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334744 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.hmac_test_hmac_vectors.1334744
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3215818157
Short name T280
Test name
Test status
Simulation time 27903698822 ps
CPU time 442.82 seconds
Started Apr 18 12:56:27 PM PDT 24
Finished Apr 18 01:03:51 PM PDT 24
Peak memory 199644 kb
Host smart-03c2d10a-893f-4991-a009-a3f0b2933133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215818157 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3215818157
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1633762109
Short name T285
Test name
Test status
Simulation time 95121058 ps
CPU time 2.78 seconds
Started Apr 18 12:56:27 PM PDT 24
Finished Apr 18 12:56:30 PM PDT 24
Peak memory 199600 kb
Host smart-4a068dea-1a30-44a9-a968-ca17ac4465b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633762109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1633762109
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.102097147
Short name T27
Test name
Test status
Simulation time 16967307672 ps
CPU time 908.92 seconds
Started Apr 18 12:59:53 PM PDT 24
Finished Apr 18 01:15:02 PM PDT 24
Peak memory 215684 kb
Host smart-e687cea3-11b5-43d3-8148-2593f8129c35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102097147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.102097147
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1688664176
Short name T548
Test name
Test status
Simulation time 24254011 ps
CPU time 0.58 seconds
Started Apr 18 12:56:39 PM PDT 24
Finished Apr 18 12:56:40 PM PDT 24
Peak memory 195372 kb
Host smart-1be1ed8b-e968-46db-a632-d7a451ba17ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688664176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1688664176
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2649433661
Short name T561
Test name
Test status
Simulation time 5128997407 ps
CPU time 46.92 seconds
Started Apr 18 12:56:32 PM PDT 24
Finished Apr 18 12:57:20 PM PDT 24
Peak memory 221260 kb
Host smart-477c0852-c876-41af-8c3e-ffc71679f719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649433661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2649433661
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2162171168
Short name T509
Test name
Test status
Simulation time 2339598004 ps
CPU time 16.62 seconds
Started Apr 18 12:56:34 PM PDT 24
Finished Apr 18 12:56:51 PM PDT 24
Peak memory 199736 kb
Host smart-e8a0118f-9187-418d-a155-2e60f1eb767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162171168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2162171168
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1495335021
Short name T96
Test name
Test status
Simulation time 2613750213 ps
CPU time 153.21 seconds
Started Apr 18 12:56:33 PM PDT 24
Finished Apr 18 12:59:07 PM PDT 24
Peak memory 199684 kb
Host smart-cd69ad18-267b-4bbc-bceb-29f291909556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495335021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1495335021
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1094791598
Short name T218
Test name
Test status
Simulation time 908544735 ps
CPU time 8.71 seconds
Started Apr 18 12:56:36 PM PDT 24
Finished Apr 18 12:56:45 PM PDT 24
Peak memory 199564 kb
Host smart-499954ab-f312-459b-b5ac-934175fa37ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094791598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1094791598
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2831612474
Short name T492
Test name
Test status
Simulation time 6819461049 ps
CPU time 92.83 seconds
Started Apr 18 12:56:33 PM PDT 24
Finished Apr 18 12:58:06 PM PDT 24
Peak memory 199724 kb
Host smart-0f3e7ce9-ad13-4a8d-ad78-0640978f3769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831612474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2831612474
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.228762970
Short name T286
Test name
Test status
Simulation time 228360999 ps
CPU time 1.09 seconds
Started Apr 18 12:56:32 PM PDT 24
Finished Apr 18 12:56:34 PM PDT 24
Peak memory 199092 kb
Host smart-062532fa-76c7-440b-8227-38763898984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228762970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.228762970
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2289611325
Short name T525
Test name
Test status
Simulation time 62451704900 ps
CPU time 531.04 seconds
Started Apr 18 12:56:39 PM PDT 24
Finished Apr 18 01:05:31 PM PDT 24
Peak memory 236548 kb
Host smart-99798c89-1c46-4fec-9619-1b232510a4ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289611325 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2289611325
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3122283262
Short name T41
Test name
Test status
Simulation time 80962170 ps
CPU time 1 seconds
Started Apr 18 12:56:34 PM PDT 24
Finished Apr 18 12:56:36 PM PDT 24
Peak memory 199388 kb
Host smart-48a49cfa-8c84-49d5-8078-a8b2902ff693
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122283262 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3122283262
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2850103573
Short name T453
Test name
Test status
Simulation time 30818709925 ps
CPU time 399.77 seconds
Started Apr 18 12:56:32 PM PDT 24
Finished Apr 18 01:03:13 PM PDT 24
Peak memory 199628 kb
Host smart-4a75c72b-9e98-415a-84ef-b5d419122ea1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850103573 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2850103573
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1472112253
Short name T133
Test name
Test status
Simulation time 4457322027 ps
CPU time 36.19 seconds
Started Apr 18 12:56:33 PM PDT 24
Finished Apr 18 12:57:09 PM PDT 24
Peak memory 199648 kb
Host smart-a57ae439-a2c4-4ad2-a4b4-098e014952ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472112253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1472112253
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.405244626
Short name T463
Test name
Test status
Simulation time 37159369 ps
CPU time 0.53 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 12:55:43 PM PDT 24
Peak memory 193992 kb
Host smart-5bc3992f-10fb-4dcb-8df8-46d38da2e6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405244626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.405244626
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3008001209
Short name T62
Test name
Test status
Simulation time 1332222331 ps
CPU time 41.92 seconds
Started Apr 18 12:55:36 PM PDT 24
Finished Apr 18 12:56:19 PM PDT 24
Peak memory 215928 kb
Host smart-d7729867-7e3c-4bb5-a211-061fb17f73fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008001209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3008001209
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.973075012
Short name T558
Test name
Test status
Simulation time 2875783519 ps
CPU time 39.9 seconds
Started Apr 18 12:55:36 PM PDT 24
Finished Apr 18 12:56:17 PM PDT 24
Peak memory 199704 kb
Host smart-c090952a-8648-4bcb-9449-6518bd473b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973075012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.973075012
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1940434597
Short name T162
Test name
Test status
Simulation time 2995501874 ps
CPU time 167.75 seconds
Started Apr 18 12:55:36 PM PDT 24
Finished Apr 18 12:58:25 PM PDT 24
Peak memory 199600 kb
Host smart-1ced9713-28c8-44bf-aa3b-247ddb5b60a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940434597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1940434597
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3093780695
Short name T577
Test name
Test status
Simulation time 14610166732 ps
CPU time 176.38 seconds
Started Apr 18 12:55:35 PM PDT 24
Finished Apr 18 12:58:32 PM PDT 24
Peak memory 199700 kb
Host smart-ca6419bc-1c4c-43e9-ba47-d654e9c5d213
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093780695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3093780695
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2387502445
Short name T215
Test name
Test status
Simulation time 8238288984 ps
CPU time 85.63 seconds
Started Apr 18 12:55:38 PM PDT 24
Finished Apr 18 12:57:04 PM PDT 24
Peak memory 199700 kb
Host smart-423d249a-4611-43b8-9306-bd40a0b6a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387502445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2387502445
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1488287084
Short name T37
Test name
Test status
Simulation time 62253580 ps
CPU time 0.86 seconds
Started Apr 18 12:55:40 PM PDT 24
Finished Apr 18 12:55:41 PM PDT 24
Peak memory 218088 kb
Host smart-8fc58422-3e89-40cc-bad5-b3de9e565887
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488287084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1488287084
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.759319028
Short name T170
Test name
Test status
Simulation time 1322120098 ps
CPU time 4.87 seconds
Started Apr 18 12:55:34 PM PDT 24
Finished Apr 18 12:55:40 PM PDT 24
Peak memory 199580 kb
Host smart-a011fa6e-546f-4ec1-a201-81c3395d3e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759319028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.759319028
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1381550666
Short name T20
Test name
Test status
Simulation time 12204339267 ps
CPU time 658.02 seconds
Started Apr 18 12:55:40 PM PDT 24
Finished Apr 18 01:06:39 PM PDT 24
Peak memory 199728 kb
Host smart-065a1670-be9d-4f09-b480-26d331348a87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381550666 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1381550666
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.476262048
Short name T152
Test name
Test status
Simulation time 58858982 ps
CPU time 1.18 seconds
Started Apr 18 12:55:35 PM PDT 24
Finished Apr 18 12:55:37 PM PDT 24
Peak memory 199300 kb
Host smart-2e862798-50a2-4b5d-a7bd-8d24681265a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476262048 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.476262048
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3807220131
Short name T519
Test name
Test status
Simulation time 26031207009 ps
CPU time 429.02 seconds
Started Apr 18 12:55:35 PM PDT 24
Finished Apr 18 01:02:44 PM PDT 24
Peak memory 199608 kb
Host smart-52659da6-b8c1-4e65-b333-f2b7077aa4c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807220131 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3807220131
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4268795993
Short name T342
Test name
Test status
Simulation time 4731975489 ps
CPU time 95.54 seconds
Started Apr 18 12:55:36 PM PDT 24
Finished Apr 18 12:57:12 PM PDT 24
Peak memory 199624 kb
Host smart-272629a2-b37d-43ce-8139-aced8247ddf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268795993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4268795993
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2631643310
Short name T530
Test name
Test status
Simulation time 35275667 ps
CPU time 0.52 seconds
Started Apr 18 12:56:44 PM PDT 24
Finished Apr 18 12:56:45 PM PDT 24
Peak memory 195028 kb
Host smart-acc64695-72dd-4a65-8a3a-14ecad78c7ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631643310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2631643310
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2217858492
Short name T374
Test name
Test status
Simulation time 2439756471 ps
CPU time 39.66 seconds
Started Apr 18 12:56:38 PM PDT 24
Finished Apr 18 12:57:18 PM PDT 24
Peak memory 222052 kb
Host smart-f1cc5d76-80ff-497d-a1d2-e5ef2cdbee3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217858492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2217858492
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1335263462
Short name T484
Test name
Test status
Simulation time 1861624636 ps
CPU time 27.53 seconds
Started Apr 18 12:56:40 PM PDT 24
Finished Apr 18 12:57:08 PM PDT 24
Peak memory 199540 kb
Host smart-0f5edc5b-7b4f-4a1b-a472-076d3cf2de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335263462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1335263462
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3810937833
Short name T167
Test name
Test status
Simulation time 1577488373 ps
CPU time 36.38 seconds
Started Apr 18 12:56:38 PM PDT 24
Finished Apr 18 12:57:15 PM PDT 24
Peak memory 199568 kb
Host smart-e7894f4d-7f58-4046-848d-ac05778c5d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810937833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3810937833
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3743933006
Short name T192
Test name
Test status
Simulation time 71969510 ps
CPU time 0.64 seconds
Started Apr 18 12:56:39 PM PDT 24
Finished Apr 18 12:56:41 PM PDT 24
Peak memory 195512 kb
Host smart-a62f1504-47ca-4e59-aba5-ba6ed0ebfbfe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743933006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3743933006
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3803823483
Short name T524
Test name
Test status
Simulation time 3077097977 ps
CPU time 44.68 seconds
Started Apr 18 12:56:37 PM PDT 24
Finished Apr 18 12:57:23 PM PDT 24
Peak memory 199668 kb
Host smart-8a651086-b680-4d57-b76c-07456673042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803823483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3803823483
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4291024461
Short name T381
Test name
Test status
Simulation time 219030601 ps
CPU time 2.39 seconds
Started Apr 18 12:56:40 PM PDT 24
Finished Apr 18 12:56:43 PM PDT 24
Peak memory 199536 kb
Host smart-92400f5d-7809-42f2-b1a2-266134ea8403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291024461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4291024461
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1526071700
Short name T436
Test name
Test status
Simulation time 577872623967 ps
CPU time 628.64 seconds
Started Apr 18 12:56:52 PM PDT 24
Finished Apr 18 01:07:22 PM PDT 24
Peak memory 199676 kb
Host smart-2e315efb-7a61-4bf2-89f7-4d85e38440bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526071700 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1526071700
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3432408665
Short name T340
Test name
Test status
Simulation time 63270015 ps
CPU time 1.25 seconds
Started Apr 18 12:56:46 PM PDT 24
Finished Apr 18 12:56:48 PM PDT 24
Peak memory 199548 kb
Host smart-d3a22598-23df-468b-8b5e-01276aba119e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432408665 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3432408665
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1342865605
Short name T308
Test name
Test status
Simulation time 181404778930 ps
CPU time 551.24 seconds
Started Apr 18 12:56:40 PM PDT 24
Finished Apr 18 01:05:51 PM PDT 24
Peak memory 199680 kb
Host smart-aa0a3bbd-aed3-48f1-989d-f667b374fede
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342865605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1342865605
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4105065414
Short name T428
Test name
Test status
Simulation time 5157212913 ps
CPU time 104.87 seconds
Started Apr 18 12:56:42 PM PDT 24
Finished Apr 18 12:58:27 PM PDT 24
Peak memory 199736 kb
Host smart-43e2347d-f7ad-4816-a4e7-7e152ef5410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105065414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4105065414
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2133092445
Short name T442
Test name
Test status
Simulation time 246955504 ps
CPU time 8.85 seconds
Started Apr 18 12:56:54 PM PDT 24
Finished Apr 18 12:57:04 PM PDT 24
Peak memory 215420 kb
Host smart-8380f099-1731-4ad6-b804-bbb54d9434b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133092445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2133092445
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1081586918
Short name T455
Test name
Test status
Simulation time 6013295205 ps
CPU time 34.65 seconds
Started Apr 18 12:56:54 PM PDT 24
Finished Apr 18 12:57:29 PM PDT 24
Peak memory 199676 kb
Host smart-53ed8d99-c51c-4d38-95a5-93cf1b60f7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081586918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1081586918
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1643927739
Short name T296
Test name
Test status
Simulation time 11310662854 ps
CPU time 113.07 seconds
Started Apr 18 12:56:45 PM PDT 24
Finished Apr 18 12:58:38 PM PDT 24
Peak memory 199616 kb
Host smart-a3d68e04-f368-4cf8-99c7-d8c92a4c8208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643927739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1643927739
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2697423118
Short name T549
Test name
Test status
Simulation time 2798595580 ps
CPU time 42.33 seconds
Started Apr 18 12:56:52 PM PDT 24
Finished Apr 18 12:57:35 PM PDT 24
Peak memory 199672 kb
Host smart-d6f689aa-8334-414c-9212-27a40cfc3be8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697423118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2697423118
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2155437355
Short name T68
Test name
Test status
Simulation time 30193905326 ps
CPU time 93.38 seconds
Started Apr 18 12:56:45 PM PDT 24
Finished Apr 18 12:58:19 PM PDT 24
Peak memory 199708 kb
Host smart-f83def8c-7384-4ad3-a35f-447130cf45b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155437355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2155437355
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2574465097
Short name T564
Test name
Test status
Simulation time 518295619 ps
CPU time 3.18 seconds
Started Apr 18 12:56:45 PM PDT 24
Finished Apr 18 12:56:49 PM PDT 24
Peak memory 199588 kb
Host smart-0c709f2e-ca77-4d65-86cf-94872780121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574465097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2574465097
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.883040028
Short name T239
Test name
Test status
Simulation time 53110856063 ps
CPU time 636.93 seconds
Started Apr 18 12:56:46 PM PDT 24
Finished Apr 18 01:07:24 PM PDT 24
Peak memory 199664 kb
Host smart-a05b7dd3-0707-457e-85af-1dba0721e2a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883040028 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.883040028
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1840921718
Short name T570
Test name
Test status
Simulation time 198170335 ps
CPU time 1.03 seconds
Started Apr 18 12:56:44 PM PDT 24
Finished Apr 18 12:56:46 PM PDT 24
Peak memory 199416 kb
Host smart-1da80e57-37ed-471e-b840-071932a103b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840921718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1840921718
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2395404962
Short name T479
Test name
Test status
Simulation time 418866973981 ps
CPU time 456.64 seconds
Started Apr 18 12:56:45 PM PDT 24
Finished Apr 18 01:04:22 PM PDT 24
Peak memory 199700 kb
Host smart-96991b15-64e1-4afe-a10c-ef6c4f2ddf76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395404962 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2395404962
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4243676197
Short name T511
Test name
Test status
Simulation time 976535704 ps
CPU time 17.89 seconds
Started Apr 18 12:56:46 PM PDT 24
Finished Apr 18 12:57:04 PM PDT 24
Peak memory 199540 kb
Host smart-6bd9fa7e-0f57-40a8-a1f1-3bad590e8279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243676197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4243676197
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3043512319
Short name T303
Test name
Test status
Simulation time 15491242 ps
CPU time 0.56 seconds
Started Apr 18 12:56:52 PM PDT 24
Finished Apr 18 12:56:54 PM PDT 24
Peak memory 194820 kb
Host smart-3b6673a9-c361-4df1-b6d9-1f5d38972741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043512319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3043512319
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2128110128
Short name T22
Test name
Test status
Simulation time 1539827728 ps
CPU time 27.76 seconds
Started Apr 18 12:56:51 PM PDT 24
Finished Apr 18 12:57:20 PM PDT 24
Peak memory 215792 kb
Host smart-713ba284-b124-4093-aef9-e5c424d34664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128110128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2128110128
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2977383847
Short name T573
Test name
Test status
Simulation time 12786619453 ps
CPU time 58.9 seconds
Started Apr 18 12:56:51 PM PDT 24
Finished Apr 18 12:57:51 PM PDT 24
Peak memory 199616 kb
Host smart-95db2aed-3bbf-43c2-9d73-1f2a413b5c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977383847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2977383847
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1819527426
Short name T493
Test name
Test status
Simulation time 2516821229 ps
CPU time 140.47 seconds
Started Apr 18 12:56:53 PM PDT 24
Finished Apr 18 12:59:15 PM PDT 24
Peak memory 199724 kb
Host smart-8ed0bf3a-7fd0-44ce-8d8f-dd4fcfd51afa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819527426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1819527426
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2101737009
Short name T209
Test name
Test status
Simulation time 4995846124 ps
CPU time 16.84 seconds
Started Apr 18 12:56:51 PM PDT 24
Finished Apr 18 12:57:08 PM PDT 24
Peak memory 199728 kb
Host smart-571758fb-6025-4ed1-8f63-889f469835c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101737009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2101737009
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1542575501
Short name T363
Test name
Test status
Simulation time 2058415222 ps
CPU time 31.65 seconds
Started Apr 18 12:56:52 PM PDT 24
Finished Apr 18 12:57:24 PM PDT 24
Peak memory 199548 kb
Host smart-c3050661-b516-4fde-8c0e-9e2157ab11a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542575501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1542575501
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2933834066
Short name T146
Test name
Test status
Simulation time 131671643 ps
CPU time 0.94 seconds
Started Apr 18 12:56:50 PM PDT 24
Finished Apr 18 12:56:52 PM PDT 24
Peak memory 198216 kb
Host smart-b8ef99b9-e3e8-4451-9279-a2dc6ea5ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933834066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2933834066
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.214047632
Short name T153
Test name
Test status
Simulation time 215296201 ps
CPU time 1.09 seconds
Started Apr 18 12:56:51 PM PDT 24
Finished Apr 18 12:56:53 PM PDT 24
Peak memory 198984 kb
Host smart-d434a0fb-6bb9-41c6-be39-8548533a6954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214047632 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.214047632
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2624302078
Short name T172
Test name
Test status
Simulation time 176243413 ps
CPU time 1.05 seconds
Started Apr 18 12:56:52 PM PDT 24
Finished Apr 18 12:56:54 PM PDT 24
Peak memory 199100 kb
Host smart-13d09bb1-012a-48cb-8caa-19735cf3a140
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624302078 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2624302078
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1693023719
Short name T13
Test name
Test status
Simulation time 10289449896 ps
CPU time 450.14 seconds
Started Apr 18 12:56:51 PM PDT 24
Finished Apr 18 01:04:22 PM PDT 24
Peak memory 199640 kb
Host smart-6a8cc156-6a38-4848-8ba9-2ee701164d99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693023719 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1693023719
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1975639328
Short name T361
Test name
Test status
Simulation time 168096964 ps
CPU time 0.99 seconds
Started Apr 18 12:56:50 PM PDT 24
Finished Apr 18 12:56:51 PM PDT 24
Peak memory 199456 kb
Host smart-029edf6b-d40a-4b44-b7cb-3579377555ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975639328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1975639328
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1131817301
Short name T560
Test name
Test status
Simulation time 13099556 ps
CPU time 0.58 seconds
Started Apr 18 12:56:58 PM PDT 24
Finished Apr 18 12:57:00 PM PDT 24
Peak memory 195068 kb
Host smart-923621c3-9065-40b9-9f3d-892aef2eddd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131817301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1131817301
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1689266579
Short name T470
Test name
Test status
Simulation time 5147610769 ps
CPU time 20.28 seconds
Started Apr 18 12:56:52 PM PDT 24
Finished Apr 18 12:57:13 PM PDT 24
Peak memory 207896 kb
Host smart-9ed09ae4-e866-40c3-97be-6b5b4d2ec2d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689266579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1689266579
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4274065684
Short name T508
Test name
Test status
Simulation time 580456074 ps
CPU time 7.9 seconds
Started Apr 18 12:56:56 PM PDT 24
Finished Apr 18 12:57:06 PM PDT 24
Peak memory 199576 kb
Host smart-34a34893-65d6-4f8f-b53a-b6e366dbdbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274065684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4274065684
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.781359375
Short name T327
Test name
Test status
Simulation time 5446618663 ps
CPU time 74.34 seconds
Started Apr 18 12:56:53 PM PDT 24
Finished Apr 18 12:58:09 PM PDT 24
Peak memory 199720 kb
Host smart-8b6e053c-67a0-4cc8-afd7-7002c8623e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781359375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.781359375
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.203500027
Short name T201
Test name
Test status
Simulation time 3303578175 ps
CPU time 154.06 seconds
Started Apr 18 12:56:57 PM PDT 24
Finished Apr 18 12:59:32 PM PDT 24
Peak memory 199704 kb
Host smart-b7ccdc5e-491c-43a6-95d8-55f7c9cf646a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203500027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.203500027
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2816020774
Short name T368
Test name
Test status
Simulation time 8254178243 ps
CPU time 75.38 seconds
Started Apr 18 12:56:50 PM PDT 24
Finished Apr 18 12:58:06 PM PDT 24
Peak memory 199700 kb
Host smart-0e0da196-376d-4273-b149-80047e07b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816020774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2816020774
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.589737854
Short name T304
Test name
Test status
Simulation time 1015625622 ps
CPU time 5.65 seconds
Started Apr 18 12:56:50 PM PDT 24
Finished Apr 18 12:56:57 PM PDT 24
Peak memory 199592 kb
Host smart-7823c6ad-dbb5-49e1-a763-f60e79ca1af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589737854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.589737854
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3184841655
Short name T272
Test name
Test status
Simulation time 22336086529 ps
CPU time 80.57 seconds
Started Apr 18 12:56:58 PM PDT 24
Finished Apr 18 12:58:20 PM PDT 24
Peak memory 199712 kb
Host smart-c800bae8-649e-4647-bd64-7cd10058cf8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184841655 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3184841655
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.193053325
Short name T462
Test name
Test status
Simulation time 105732955 ps
CPU time 1.19 seconds
Started Apr 18 12:56:56 PM PDT 24
Finished Apr 18 12:56:59 PM PDT 24
Peak memory 199516 kb
Host smart-17955a31-64df-462f-97cd-45a16f9b3b1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193053325 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.193053325
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3387421803
Short name T78
Test name
Test status
Simulation time 107998650807 ps
CPU time 449.72 seconds
Started Apr 18 12:57:00 PM PDT 24
Finished Apr 18 01:04:31 PM PDT 24
Peak memory 199692 kb
Host smart-2e42e162-b72d-4286-9e52-8d723a14a1fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387421803 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3387421803
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2913912949
Short name T341
Test name
Test status
Simulation time 20371889551 ps
CPU time 38.11 seconds
Started Apr 18 12:56:57 PM PDT 24
Finished Apr 18 12:57:37 PM PDT 24
Peak memory 199728 kb
Host smart-c2bf9e4e-74b6-4438-b2d1-22a44fd7b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913912949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2913912949
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3210844605
Short name T521
Test name
Test status
Simulation time 38882724 ps
CPU time 0.55 seconds
Started Apr 18 12:56:55 PM PDT 24
Finished Apr 18 12:56:57 PM PDT 24
Peak memory 194008 kb
Host smart-b66a2a7d-64f8-42c4-85c4-2d78a0c29d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210844605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3210844605
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.932764452
Short name T547
Test name
Test status
Simulation time 1304834595 ps
CPU time 43.91 seconds
Started Apr 18 12:56:58 PM PDT 24
Finished Apr 18 12:57:44 PM PDT 24
Peak memory 207692 kb
Host smart-cd37365a-2764-4749-b559-4b99d3258d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932764452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.932764452
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3806388607
Short name T475
Test name
Test status
Simulation time 1025623392 ps
CPU time 50.87 seconds
Started Apr 18 12:56:56 PM PDT 24
Finished Apr 18 12:57:48 PM PDT 24
Peak memory 199588 kb
Host smart-2692701b-84ed-470a-b840-7aa4e0438815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806388607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3806388607
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3470182715
Short name T373
Test name
Test status
Simulation time 1726807702 ps
CPU time 89.57 seconds
Started Apr 18 12:56:57 PM PDT 24
Finished Apr 18 12:58:29 PM PDT 24
Peak memory 199608 kb
Host smart-86d9f11d-e84f-49fc-a037-65148345b511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470182715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3470182715
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.4294712304
Short name T369
Test name
Test status
Simulation time 70907968 ps
CPU time 4.14 seconds
Started Apr 18 12:56:58 PM PDT 24
Finished Apr 18 12:57:04 PM PDT 24
Peak memory 199436 kb
Host smart-a4f31510-b6ee-4fec-bf33-19442ad9d8cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294712304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4294712304
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1519468151
Short name T434
Test name
Test status
Simulation time 807212229 ps
CPU time 10.26 seconds
Started Apr 18 12:56:58 PM PDT 24
Finished Apr 18 12:57:10 PM PDT 24
Peak memory 199612 kb
Host smart-26afae72-055e-42b1-91ce-8a1fc1285095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519468151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1519468151
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3113346748
Short name T435
Test name
Test status
Simulation time 237663270 ps
CPU time 3.01 seconds
Started Apr 18 12:56:57 PM PDT 24
Finished Apr 18 12:57:01 PM PDT 24
Peak memory 199548 kb
Host smart-518b00cf-0fad-4795-9072-2a7d1c2b6695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113346748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3113346748
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2866766213
Short name T512
Test name
Test status
Simulation time 388532178 ps
CPU time 1.23 seconds
Started Apr 18 12:56:57 PM PDT 24
Finished Apr 18 12:56:59 PM PDT 24
Peak memory 199324 kb
Host smart-9bf99909-4032-4348-bdc4-fd5aa9382095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866766213 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2866766213
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1516236826
Short name T195
Test name
Test status
Simulation time 56712081398 ps
CPU time 443.05 seconds
Started Apr 18 12:56:56 PM PDT 24
Finished Apr 18 01:04:21 PM PDT 24
Peak memory 199624 kb
Host smart-b1f52fe1-a0a9-43ff-84ea-02e1166690bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516236826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1516236826
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.874704566
Short name T104
Test name
Test status
Simulation time 6513310008 ps
CPU time 22.38 seconds
Started Apr 18 12:56:57 PM PDT 24
Finished Apr 18 12:57:22 PM PDT 24
Peak memory 199744 kb
Host smart-8de8a279-e203-4e71-9155-2e7771a31493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874704566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.874704566
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.700855364
Short name T396
Test name
Test status
Simulation time 15010432 ps
CPU time 0.63 seconds
Started Apr 18 12:57:02 PM PDT 24
Finished Apr 18 12:57:03 PM PDT 24
Peak memory 194756 kb
Host smart-f41b833b-5d99-4080-a197-9a2b140a129f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700855364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.700855364
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3353769785
Short name T395
Test name
Test status
Simulation time 6621523413 ps
CPU time 61.54 seconds
Started Apr 18 12:56:58 PM PDT 24
Finished Apr 18 12:58:01 PM PDT 24
Peak memory 239560 kb
Host smart-32ec306b-b834-4dc7-a00e-ee31bf184d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353769785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3353769785
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1688450738
Short name T559
Test name
Test status
Simulation time 2097594045 ps
CPU time 38.54 seconds
Started Apr 18 12:56:59 PM PDT 24
Finished Apr 18 12:57:39 PM PDT 24
Peak memory 199592 kb
Host smart-4c56f46b-a813-4de8-bf98-f1976c508394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688450738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1688450738
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3218778883
Short name T325
Test name
Test status
Simulation time 2260302228 ps
CPU time 81.34 seconds
Started Apr 18 12:56:56 PM PDT 24
Finished Apr 18 12:58:19 PM PDT 24
Peak memory 199660 kb
Host smart-415153a4-5c3c-4079-965d-aa2b7ebee4bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218778883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3218778883
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4039752253
Short name T7
Test name
Test status
Simulation time 3531217203 ps
CPU time 97.48 seconds
Started Apr 18 12:56:56 PM PDT 24
Finished Apr 18 12:58:35 PM PDT 24
Peak memory 199624 kb
Host smart-64adfdfc-f1a8-4dd4-8823-eb3249d63a44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039752253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4039752253
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.340896089
Short name T306
Test name
Test status
Simulation time 3717843908 ps
CPU time 18.64 seconds
Started Apr 18 12:56:55 PM PDT 24
Finished Apr 18 12:57:15 PM PDT 24
Peak memory 199720 kb
Host smart-4b476f97-3d74-418b-8608-65b239d57845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340896089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.340896089
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3234337973
Short name T532
Test name
Test status
Simulation time 97833564 ps
CPU time 1.2 seconds
Started Apr 18 12:56:56 PM PDT 24
Finished Apr 18 12:56:59 PM PDT 24
Peak memory 199580 kb
Host smart-24ab9f34-2d6c-4894-af49-d5097fc3b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234337973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3234337973
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1890116346
Short name T89
Test name
Test status
Simulation time 634397030829 ps
CPU time 1716.6 seconds
Started Apr 18 12:57:03 PM PDT 24
Finished Apr 18 01:25:40 PM PDT 24
Peak memory 199724 kb
Host smart-2228d2a2-846e-44fe-9a03-9f7130367992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890116346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1890116346
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.217917197
Short name T185
Test name
Test status
Simulation time 177450550 ps
CPU time 1.01 seconds
Started Apr 18 12:57:02 PM PDT 24
Finished Apr 18 12:57:04 PM PDT 24
Peak memory 199100 kb
Host smart-b3a8b590-9644-48f5-846c-5170c028e683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217917197 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.217917197
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2001688498
Short name T224
Test name
Test status
Simulation time 84985536691 ps
CPU time 497.01 seconds
Started Apr 18 12:57:03 PM PDT 24
Finished Apr 18 01:05:20 PM PDT 24
Peak memory 199688 kb
Host smart-81d3fc6a-a711-4c6e-b425-90499799b35b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001688498 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2001688498
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1548560182
Short name T311
Test name
Test status
Simulation time 1529062397 ps
CPU time 69.54 seconds
Started Apr 18 12:57:02 PM PDT 24
Finished Apr 18 12:58:12 PM PDT 24
Peak memory 199564 kb
Host smart-3c960023-d8fe-4075-ae28-6dc3ff27fc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548560182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1548560182
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2953716507
Short name T222
Test name
Test status
Simulation time 15039082 ps
CPU time 0.59 seconds
Started Apr 18 12:57:09 PM PDT 24
Finished Apr 18 12:57:10 PM PDT 24
Peak memory 195136 kb
Host smart-0a745f00-7100-466a-b10e-3c639023299d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953716507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2953716507
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2101919097
Short name T307
Test name
Test status
Simulation time 1619583424 ps
CPU time 17.34 seconds
Started Apr 18 12:57:02 PM PDT 24
Finished Apr 18 12:57:20 PM PDT 24
Peak memory 207796 kb
Host smart-f69c5fa5-92c4-4251-87f9-317dbede37c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2101919097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2101919097
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3121312732
Short name T411
Test name
Test status
Simulation time 706275701 ps
CPU time 10.12 seconds
Started Apr 18 12:57:01 PM PDT 24
Finished Apr 18 12:57:12 PM PDT 24
Peak memory 199592 kb
Host smart-f722b4f8-d926-4f82-8753-fcad1f52d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121312732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3121312732
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.67479619
Short name T476
Test name
Test status
Simulation time 9362118274 ps
CPU time 61.65 seconds
Started Apr 18 12:57:03 PM PDT 24
Finished Apr 18 12:58:06 PM PDT 24
Peak memory 199672 kb
Host smart-b9223038-10f2-409b-862c-a21c51779a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67479619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.67479619
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1504751023
Short name T289
Test name
Test status
Simulation time 648980942 ps
CPU time 34.27 seconds
Started Apr 18 12:57:07 PM PDT 24
Finished Apr 18 12:57:42 PM PDT 24
Peak memory 199616 kb
Host smart-a0f749a3-ca5e-4935-8702-82c652f79ab1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504751023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1504751023
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.186667417
Short name T456
Test name
Test status
Simulation time 16559505959 ps
CPU time 50.97 seconds
Started Apr 18 12:57:02 PM PDT 24
Finished Apr 18 12:57:54 PM PDT 24
Peak memory 199576 kb
Host smart-0c0da9d8-a5fb-4d89-be1a-89ad977de99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186667417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.186667417
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1969144973
Short name T309
Test name
Test status
Simulation time 1133569088 ps
CPU time 4.09 seconds
Started Apr 18 12:57:01 PM PDT 24
Finished Apr 18 12:57:06 PM PDT 24
Peak memory 199576 kb
Host smart-b3f90789-f28c-46a3-812d-3ad4c73c8f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969144973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1969144973
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.375630286
Short name T446
Test name
Test status
Simulation time 14533311871 ps
CPU time 826.32 seconds
Started Apr 18 12:57:06 PM PDT 24
Finished Apr 18 01:10:53 PM PDT 24
Peak memory 199700 kb
Host smart-dc02a2f8-0560-4199-a4c9-c8ea1766a3ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375630286 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.375630286
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2608279636
Short name T501
Test name
Test status
Simulation time 183922440 ps
CPU time 1.16 seconds
Started Apr 18 12:57:06 PM PDT 24
Finished Apr 18 12:57:07 PM PDT 24
Peak memory 199524 kb
Host smart-2f17cb9b-54ae-4d99-a6e5-3f792a7f3b03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608279636 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2608279636
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2591421334
Short name T97
Test name
Test status
Simulation time 27537207131 ps
CPU time 451.34 seconds
Started Apr 18 12:57:07 PM PDT 24
Finished Apr 18 01:04:39 PM PDT 24
Peak memory 199696 kb
Host smart-dd9cb951-fce8-473b-9701-6ff898add614
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591421334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.2591421334
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.385773363
Short name T206
Test name
Test status
Simulation time 4475735132 ps
CPU time 78.29 seconds
Started Apr 18 12:57:08 PM PDT 24
Finished Apr 18 12:58:27 PM PDT 24
Peak memory 199704 kb
Host smart-bc51bd37-c7ad-47bd-bdf2-19c0310acb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385773363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.385773363
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1986070377
Short name T193
Test name
Test status
Simulation time 45998497 ps
CPU time 0.56 seconds
Started Apr 18 12:57:14 PM PDT 24
Finished Apr 18 12:57:15 PM PDT 24
Peak memory 195224 kb
Host smart-ae9ec934-fb44-4e08-a12e-703ec3136938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986070377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1986070377
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2358732783
Short name T199
Test name
Test status
Simulation time 4650630602 ps
CPU time 41 seconds
Started Apr 18 12:57:07 PM PDT 24
Finished Apr 18 12:57:49 PM PDT 24
Peak memory 207800 kb
Host smart-197c82b8-90d8-46c1-b73b-ffa78d7cac54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358732783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2358732783
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3759232087
Short name T485
Test name
Test status
Simulation time 441123663 ps
CPU time 21.01 seconds
Started Apr 18 12:57:08 PM PDT 24
Finished Apr 18 12:57:30 PM PDT 24
Peak memory 199576 kb
Host smart-c3bb9838-20e1-4da5-a8c3-15d59219b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759232087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3759232087
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.286812226
Short name T226
Test name
Test status
Simulation time 5335840342 ps
CPU time 150.98 seconds
Started Apr 18 12:57:07 PM PDT 24
Finished Apr 18 12:59:39 PM PDT 24
Peak memory 199712 kb
Host smart-015c6934-2b5e-40cc-8313-7aeed1a22bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286812226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.286812226
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3594679667
Short name T298
Test name
Test status
Simulation time 4635685819 ps
CPU time 57.89 seconds
Started Apr 18 12:57:10 PM PDT 24
Finished Apr 18 12:58:08 PM PDT 24
Peak memory 199680 kb
Host smart-7a965e8f-4b5b-47ce-888a-1ff727802fa3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594679667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3594679667
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2489560841
Short name T249
Test name
Test status
Simulation time 4639000339 ps
CPU time 23.83 seconds
Started Apr 18 12:57:10 PM PDT 24
Finished Apr 18 12:57:34 PM PDT 24
Peak memory 199684 kb
Host smart-9c49ed6f-ad43-4325-a538-6d96140f588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489560841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2489560841
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.677501542
Short name T270
Test name
Test status
Simulation time 473186447 ps
CPU time 5.44 seconds
Started Apr 18 12:57:08 PM PDT 24
Finished Apr 18 12:57:14 PM PDT 24
Peak memory 199556 kb
Host smart-c51a688b-cf4a-43c9-9ded-4ed56b7371c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677501542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.677501542
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.4175634086
Short name T344
Test name
Test status
Simulation time 316800884777 ps
CPU time 1061.69 seconds
Started Apr 18 12:57:12 PM PDT 24
Finished Apr 18 01:14:55 PM PDT 24
Peak memory 199704 kb
Host smart-f5aa0e5c-c7d2-45e3-945a-73b3f85b6740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175634086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.4175634086
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2774722172
Short name T212
Test name
Test status
Simulation time 98046855 ps
CPU time 0.97 seconds
Started Apr 18 12:57:15 PM PDT 24
Finished Apr 18 12:57:16 PM PDT 24
Peak memory 198816 kb
Host smart-0da223c2-a161-4ef3-86d7-18e29ba1f8e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774722172 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2774722172
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2696944797
Short name T207
Test name
Test status
Simulation time 42309695789 ps
CPU time 519.96 seconds
Started Apr 18 12:57:09 PM PDT 24
Finished Apr 18 01:05:50 PM PDT 24
Peak memory 199548 kb
Host smart-a79b820e-f5e0-422f-97fc-44e66318d9f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696944797 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2696944797
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.150269256
Short name T142
Test name
Test status
Simulation time 949969861 ps
CPU time 15.82 seconds
Started Apr 18 12:57:10 PM PDT 24
Finished Apr 18 12:57:27 PM PDT 24
Peak memory 199564 kb
Host smart-74f99c60-86fc-4b2d-a942-2af8d1a2360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150269256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.150269256
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.957909967
Short name T208
Test name
Test status
Simulation time 12326837 ps
CPU time 0.57 seconds
Started Apr 18 12:57:20 PM PDT 24
Finished Apr 18 12:57:21 PM PDT 24
Peak memory 195328 kb
Host smart-d4a0e4fa-9d2b-4633-b0b5-5e83c7e92b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957909967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.957909967
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2214412203
Short name T299
Test name
Test status
Simulation time 1882214706 ps
CPU time 67.91 seconds
Started Apr 18 12:57:11 PM PDT 24
Finished Apr 18 12:58:20 PM PDT 24
Peak memory 232104 kb
Host smart-87a9bfb2-dc30-4d5c-a303-98a1d47e52a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214412203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2214412203
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2492202912
Short name T454
Test name
Test status
Simulation time 3558801106 ps
CPU time 35.33 seconds
Started Apr 18 12:57:12 PM PDT 24
Finished Apr 18 12:57:48 PM PDT 24
Peak memory 199688 kb
Host smart-d09f656f-6e35-450c-a469-429e2330d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492202912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2492202912
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1192775011
Short name T503
Test name
Test status
Simulation time 30968655051 ps
CPU time 107.29 seconds
Started Apr 18 12:57:12 PM PDT 24
Finished Apr 18 12:59:00 PM PDT 24
Peak memory 199612 kb
Host smart-333d6d75-8cbb-4cbd-9fa0-c08dc6137951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192775011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1192775011
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.400926096
Short name T16
Test name
Test status
Simulation time 15069145969 ps
CPU time 103.12 seconds
Started Apr 18 12:57:15 PM PDT 24
Finished Apr 18 12:58:58 PM PDT 24
Peak memory 199628 kb
Host smart-ea418479-e5f3-489d-a988-67901baeff98
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400926096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.400926096
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1000826755
Short name T557
Test name
Test status
Simulation time 816442615 ps
CPU time 3.43 seconds
Started Apr 18 12:57:14 PM PDT 24
Finished Apr 18 12:57:18 PM PDT 24
Peak memory 199504 kb
Host smart-37da0277-0aa4-4207-b30c-c50b133914ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000826755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1000826755
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2663926285
Short name T579
Test name
Test status
Simulation time 158565515 ps
CPU time 4.59 seconds
Started Apr 18 12:57:14 PM PDT 24
Finished Apr 18 12:57:19 PM PDT 24
Peak memory 199612 kb
Host smart-841b2f05-6e4f-488e-b3a0-e4cadd79822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663926285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2663926285
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4229278261
Short name T59
Test name
Test status
Simulation time 55844086441 ps
CPU time 1417.9 seconds
Started Apr 18 12:57:19 PM PDT 24
Finished Apr 18 01:20:57 PM PDT 24
Peak memory 233592 kb
Host smart-59bab498-e65b-483c-a758-26bd16cf5ba4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229278261 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4229278261
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.4236682810
Short name T237
Test name
Test status
Simulation time 223314616 ps
CPU time 0.98 seconds
Started Apr 18 12:57:20 PM PDT 24
Finished Apr 18 12:57:22 PM PDT 24
Peak memory 197800 kb
Host smart-2e447c70-eca3-4abf-bcfc-8096991e8ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236682810 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.4236682810
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3667718074
Short name T312
Test name
Test status
Simulation time 28708715797 ps
CPU time 511.72 seconds
Started Apr 18 12:57:14 PM PDT 24
Finished Apr 18 01:05:47 PM PDT 24
Peak memory 199692 kb
Host smart-e55f9ee4-4d19-4eff-bf3b-e747ae849984
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667718074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3667718074
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3501879624
Short name T352
Test name
Test status
Simulation time 1911896617 ps
CPU time 8.88 seconds
Started Apr 18 12:57:14 PM PDT 24
Finished Apr 18 12:57:23 PM PDT 24
Peak memory 199588 kb
Host smart-fa2a7afd-ae51-4dea-9287-cb2612745d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501879624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3501879624
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1957514737
Short name T287
Test name
Test status
Simulation time 93675760 ps
CPU time 0.56 seconds
Started Apr 18 12:57:17 PM PDT 24
Finished Apr 18 12:57:19 PM PDT 24
Peak memory 195140 kb
Host smart-8ab2e08c-1891-4612-98ef-5592afc4ec49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957514737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1957514737
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.630163188
Short name T234
Test name
Test status
Simulation time 1592916970 ps
CPU time 14.14 seconds
Started Apr 18 12:57:18 PM PDT 24
Finished Apr 18 12:57:33 PM PDT 24
Peak memory 232320 kb
Host smart-07ff15c9-d8da-4f69-92a2-5ee90a7c4e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630163188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.630163188
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1395809907
Short name T576
Test name
Test status
Simulation time 17938873131 ps
CPU time 29.32 seconds
Started Apr 18 12:57:19 PM PDT 24
Finished Apr 18 12:57:49 PM PDT 24
Peak memory 199724 kb
Host smart-dd3546b4-d8a0-46ea-8bf0-8f17ad105e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395809907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1395809907
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2625081240
Short name T165
Test name
Test status
Simulation time 2599433846 ps
CPU time 35.03 seconds
Started Apr 18 12:57:22 PM PDT 24
Finished Apr 18 12:57:57 PM PDT 24
Peak memory 199700 kb
Host smart-5e93b9e4-7801-422b-ad3e-0fbcdfdbda60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625081240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2625081240
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2164556861
Short name T32
Test name
Test status
Simulation time 7969970553 ps
CPU time 136.96 seconds
Started Apr 18 12:57:19 PM PDT 24
Finished Apr 18 12:59:37 PM PDT 24
Peak memory 199912 kb
Host smart-1a54a949-30ad-4bb4-9a73-72acdc7769cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164556861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2164556861
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.99260181
Short name T161
Test name
Test status
Simulation time 9284288941 ps
CPU time 62.71 seconds
Started Apr 18 12:57:23 PM PDT 24
Finished Apr 18 12:58:27 PM PDT 24
Peak memory 199652 kb
Host smart-bb800df4-8292-4998-9217-098ea3150e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99260181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.99260181
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3358436464
Short name T316
Test name
Test status
Simulation time 76900523 ps
CPU time 1.59 seconds
Started Apr 18 12:57:18 PM PDT 24
Finished Apr 18 12:57:20 PM PDT 24
Peak memory 199604 kb
Host smart-5c5ffafb-ff65-48ba-b5f0-e69ae75a9e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358436464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3358436464
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2046037459
Short name T148
Test name
Test status
Simulation time 4591936119 ps
CPU time 83.13 seconds
Started Apr 18 12:57:19 PM PDT 24
Finished Apr 18 12:58:43 PM PDT 24
Peak memory 199660 kb
Host smart-ab2bab66-5546-4698-b1e3-78812efd4d67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046037459 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2046037459
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.953131179
Short name T156
Test name
Test status
Simulation time 59536624 ps
CPU time 1.28 seconds
Started Apr 18 12:57:20 PM PDT 24
Finished Apr 18 12:57:21 PM PDT 24
Peak memory 199612 kb
Host smart-60ab4812-d02d-4600-a175-ee7518be7a54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953131179 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.953131179
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3224508517
Short name T584
Test name
Test status
Simulation time 149441519345 ps
CPU time 437.6 seconds
Started Apr 18 12:57:17 PM PDT 24
Finished Apr 18 01:04:35 PM PDT 24
Peak memory 199736 kb
Host smart-861b7eb1-0504-4913-8ce6-ce19b2f55010
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224508517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3224508517
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2892840797
Short name T29
Test name
Test status
Simulation time 1678087349 ps
CPU time 24.38 seconds
Started Apr 18 12:57:18 PM PDT 24
Finished Apr 18 12:57:43 PM PDT 24
Peak memory 199528 kb
Host smart-ade1c411-e678-484e-9943-51b4645854d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892840797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2892840797
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1464144839
Short name T481
Test name
Test status
Simulation time 18349300 ps
CPU time 0.57 seconds
Started Apr 18 12:55:41 PM PDT 24
Finished Apr 18 12:55:43 PM PDT 24
Peak memory 195124 kb
Host smart-b03e2996-70ad-43c1-b440-b599accab994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464144839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1464144839
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1872557072
Short name T410
Test name
Test status
Simulation time 2038316917 ps
CPU time 33.13 seconds
Started Apr 18 12:55:41 PM PDT 24
Finished Apr 18 12:56:15 PM PDT 24
Peak memory 207804 kb
Host smart-2b92e4e8-8d59-481a-a853-ce4dcffad4b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872557072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1872557072
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2611278091
Short name T407
Test name
Test status
Simulation time 15065849501 ps
CPU time 52.8 seconds
Started Apr 18 12:55:40 PM PDT 24
Finished Apr 18 12:56:33 PM PDT 24
Peak memory 199624 kb
Host smart-610dfcc0-4b93-4331-b227-1b9767cb35d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611278091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2611278091
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.546582405
Short name T233
Test name
Test status
Simulation time 7734513928 ps
CPU time 110.41 seconds
Started Apr 18 12:55:40 PM PDT 24
Finished Apr 18 12:57:31 PM PDT 24
Peak memory 199720 kb
Host smart-8d12504c-d071-4f4f-9c46-2aae0001991e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546582405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.546582405
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.527407420
Short name T18
Test name
Test status
Simulation time 11681731762 ps
CPU time 144.26 seconds
Started Apr 18 12:55:45 PM PDT 24
Finished Apr 18 12:58:10 PM PDT 24
Peak memory 199736 kb
Host smart-941e0fb4-3982-4731-9a33-70b04b123848
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527407420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.527407420
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.856062879
Short name T490
Test name
Test status
Simulation time 83930037 ps
CPU time 1.32 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 12:55:45 PM PDT 24
Peak memory 199500 kb
Host smart-4e32d93b-cd89-44a8-b17c-a0d856d12b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856062879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.856062879
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.4018107668
Short name T36
Test name
Test status
Simulation time 1951031727 ps
CPU time 1 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 12:55:44 PM PDT 24
Peak memory 219120 kb
Host smart-222ec4a2-452e-4c9e-903e-cedc930cf174
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018107668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.4018107668
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.535056184
Short name T278
Test name
Test status
Simulation time 345002856 ps
CPU time 3.12 seconds
Started Apr 18 12:55:43 PM PDT 24
Finished Apr 18 12:55:48 PM PDT 24
Peak memory 199608 kb
Host smart-6f53f2e2-964d-4567-8ddd-147623fb4306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535056184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.535056184
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3131533076
Short name T61
Test name
Test status
Simulation time 18929154911 ps
CPU time 546.01 seconds
Started Apr 18 12:55:41 PM PDT 24
Finished Apr 18 01:04:47 PM PDT 24
Peak memory 216108 kb
Host smart-2841f40e-1d66-4e99-a525-8fe0c2579885
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131533076 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3131533076
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2015435302
Short name T10
Test name
Test status
Simulation time 76540947414 ps
CPU time 969.81 seconds
Started Apr 18 12:55:45 PM PDT 24
Finished Apr 18 01:11:56 PM PDT 24
Peak memory 232420 kb
Host smart-ce71b271-ac1b-48b2-aa27-662eb5623f8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015435302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2015435302
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2665527459
Short name T227
Test name
Test status
Simulation time 37057240 ps
CPU time 0.94 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 12:55:44 PM PDT 24
Peak memory 197992 kb
Host smart-08f2bdef-8702-4283-b6f2-ff20885aad8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665527459 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2665527459
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.739413250
Short name T65
Test name
Test status
Simulation time 55504222042 ps
CPU time 475.24 seconds
Started Apr 18 12:55:41 PM PDT 24
Finished Apr 18 01:03:36 PM PDT 24
Peak memory 199692 kb
Host smart-a64fc3b2-a42c-47f9-a500-ae80cf6b6a4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739413250 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.739413250
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1570378556
Short name T262
Test name
Test status
Simulation time 8363804308 ps
CPU time 86.09 seconds
Started Apr 18 12:55:41 PM PDT 24
Finished Apr 18 12:57:08 PM PDT 24
Peak memory 199728 kb
Host smart-071aacc3-4039-46cd-b96d-0f6866912cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570378556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1570378556
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1174905793
Short name T432
Test name
Test status
Simulation time 31645921 ps
CPU time 0.55 seconds
Started Apr 18 12:57:28 PM PDT 24
Finished Apr 18 12:57:29 PM PDT 24
Peak memory 195100 kb
Host smart-9b2e3549-2301-41dc-b8ef-66cba152fe35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174905793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1174905793
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1389827471
Short name T179
Test name
Test status
Simulation time 2668557022 ps
CPU time 20.67 seconds
Started Apr 18 12:57:26 PM PDT 24
Finished Apr 18 12:57:48 PM PDT 24
Peak memory 215940 kb
Host smart-e4895e7b-e519-442f-a51b-24f1bf1f1214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389827471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1389827471
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2139222999
Short name T240
Test name
Test status
Simulation time 4775942399 ps
CPU time 17.84 seconds
Started Apr 18 12:57:26 PM PDT 24
Finished Apr 18 12:57:44 PM PDT 24
Peak memory 199648 kb
Host smart-60256dce-ef17-40ab-8019-8ae11e6ef472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139222999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2139222999
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3985317415
Short name T188
Test name
Test status
Simulation time 1267987826 ps
CPU time 16.72 seconds
Started Apr 18 12:57:24 PM PDT 24
Finished Apr 18 12:57:42 PM PDT 24
Peak memory 199540 kb
Host smart-fd330200-6cb7-42e9-bd99-4ce7b9ce1b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985317415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3985317415
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3428650911
Short name T31
Test name
Test status
Simulation time 3194707619 ps
CPU time 55.23 seconds
Started Apr 18 12:57:28 PM PDT 24
Finished Apr 18 12:58:24 PM PDT 24
Peak memory 199660 kb
Host smart-34444551-4c37-4ca1-acb7-5891c3557b7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428650911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3428650911
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3231020015
Short name T305
Test name
Test status
Simulation time 1505437486 ps
CPU time 20.45 seconds
Started Apr 18 12:57:17 PM PDT 24
Finished Apr 18 12:57:38 PM PDT 24
Peak memory 199572 kb
Host smart-ac6fca40-0662-4500-9752-f8fb144d68e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231020015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3231020015
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3578812526
Short name T171
Test name
Test status
Simulation time 566657417 ps
CPU time 5.76 seconds
Started Apr 18 12:57:22 PM PDT 24
Finished Apr 18 12:57:28 PM PDT 24
Peak memory 199580 kb
Host smart-eec38a45-e6b4-44e1-8590-ab054b2460c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578812526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3578812526
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1968242897
Short name T121
Test name
Test status
Simulation time 276736679758 ps
CPU time 1183.55 seconds
Started Apr 18 12:57:23 PM PDT 24
Finished Apr 18 01:17:08 PM PDT 24
Peak memory 199684 kb
Host smart-b1f3a33b-0bba-4183-aaf9-6e6187a1152c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968242897 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1968242897
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2746425419
Short name T173
Test name
Test status
Simulation time 455254585 ps
CPU time 0.97 seconds
Started Apr 18 12:57:25 PM PDT 24
Finished Apr 18 12:57:26 PM PDT 24
Peak memory 199012 kb
Host smart-0ac74036-475d-4e3c-ba43-cf3ec24a09d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746425419 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2746425419
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2584401933
Short name T181
Test name
Test status
Simulation time 29815794204 ps
CPU time 505.51 seconds
Started Apr 18 12:57:24 PM PDT 24
Finished Apr 18 01:05:51 PM PDT 24
Peak memory 199660 kb
Host smart-66cff758-3d74-40f6-a487-7708a7c1e1cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584401933 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2584401933
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2442006697
Short name T105
Test name
Test status
Simulation time 4133315421 ps
CPU time 14.85 seconds
Started Apr 18 12:57:25 PM PDT 24
Finished Apr 18 12:57:40 PM PDT 24
Peak memory 199724 kb
Host smart-c8bf9ef7-76ec-4145-81ef-786e94004bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442006697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2442006697
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1501294151
Short name T160
Test name
Test status
Simulation time 60215301 ps
CPU time 0.52 seconds
Started Apr 18 12:57:31 PM PDT 24
Finished Apr 18 12:57:32 PM PDT 24
Peak memory 194148 kb
Host smart-95d8379d-c883-4d72-a7fb-181dbf33c983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501294151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1501294151
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.254400802
Short name T256
Test name
Test status
Simulation time 1394201944 ps
CPU time 32.02 seconds
Started Apr 18 12:57:26 PM PDT 24
Finished Apr 18 12:57:58 PM PDT 24
Peak memory 215752 kb
Host smart-24cb5b4e-33fe-4d64-9bd9-91e49622c1fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254400802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.254400802
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1925337905
Short name T228
Test name
Test status
Simulation time 2323802148 ps
CPU time 56.35 seconds
Started Apr 18 12:57:25 PM PDT 24
Finished Apr 18 12:58:22 PM PDT 24
Peak memory 199724 kb
Host smart-c4feeb8f-d258-4951-b66a-62326503e374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925337905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1925337905
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1180545554
Short name T157
Test name
Test status
Simulation time 2182185394 ps
CPU time 120.33 seconds
Started Apr 18 12:57:24 PM PDT 24
Finished Apr 18 12:59:24 PM PDT 24
Peak memory 199628 kb
Host smart-0090df60-eba0-4176-a3f5-7c11c7c57fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180545554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1180545554
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1294796417
Short name T566
Test name
Test status
Simulation time 14506012315 ps
CPU time 50.08 seconds
Started Apr 18 12:57:24 PM PDT 24
Finished Apr 18 12:58:15 PM PDT 24
Peak memory 199732 kb
Host smart-081068e3-fc40-4fc5-a883-1469ca7ca0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294796417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1294796417
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2372680459
Short name T266
Test name
Test status
Simulation time 458052861 ps
CPU time 5.5 seconds
Started Apr 18 12:57:25 PM PDT 24
Finished Apr 18 12:57:31 PM PDT 24
Peak memory 199592 kb
Host smart-13128270-02ee-4aa0-9907-96f5be57e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372680459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2372680459
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.213337661
Short name T15
Test name
Test status
Simulation time 360629550567 ps
CPU time 1594.58 seconds
Started Apr 18 12:57:30 PM PDT 24
Finished Apr 18 01:24:06 PM PDT 24
Peak memory 233220 kb
Host smart-0c873b90-e3a2-4df0-9951-b841647e3746
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213337661 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.213337661
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1628685449
Short name T4
Test name
Test status
Simulation time 64885499 ps
CPU time 0.97 seconds
Started Apr 18 12:57:30 PM PDT 24
Finished Apr 18 12:57:31 PM PDT 24
Peak memory 198940 kb
Host smart-8cc7123a-aed6-42bf-bf2c-f05c6478a25c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628685449 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1628685449
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2670843546
Short name T83
Test name
Test status
Simulation time 102832319506 ps
CPU time 442.44 seconds
Started Apr 18 12:57:31 PM PDT 24
Finished Apr 18 01:04:54 PM PDT 24
Peak memory 199624 kb
Host smart-f6d6c187-0f70-46d5-a492-7ce2fb72b16d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670843546 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2670843546
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.9620549
Short name T450
Test name
Test status
Simulation time 3969468378 ps
CPU time 33.51 seconds
Started Apr 18 12:57:27 PM PDT 24
Finished Apr 18 12:58:01 PM PDT 24
Peak memory 199696 kb
Host smart-614d7dbc-50f9-475a-a2c7-a24d1382bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9620549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.9620549
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.664666762
Short name T252
Test name
Test status
Simulation time 241275502 ps
CPU time 0.55 seconds
Started Apr 18 12:57:36 PM PDT 24
Finished Apr 18 12:57:38 PM PDT 24
Peak memory 195212 kb
Host smart-131a54f4-4d07-4704-84fc-35c7127a7428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664666762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.664666762
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1355083313
Short name T80
Test name
Test status
Simulation time 1613705906 ps
CPU time 11.91 seconds
Started Apr 18 12:57:29 PM PDT 24
Finished Apr 18 12:57:42 PM PDT 24
Peak memory 199592 kb
Host smart-28370632-82f8-410c-bec3-c2b7164338fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355083313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1355083313
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2313161708
Short name T346
Test name
Test status
Simulation time 5448988545 ps
CPU time 47.61 seconds
Started Apr 18 12:57:29 PM PDT 24
Finished Apr 18 12:58:17 PM PDT 24
Peak memory 199724 kb
Host smart-c8de1f2b-627f-4d42-9511-29656892a3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313161708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2313161708
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.317146525
Short name T520
Test name
Test status
Simulation time 4346782405 ps
CPU time 114.6 seconds
Started Apr 18 12:57:29 PM PDT 24
Finished Apr 18 12:59:25 PM PDT 24
Peak memory 199724 kb
Host smart-d5a19c14-dbb0-4205-9929-0e40cef68b14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317146525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.317146525
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1138831637
Short name T408
Test name
Test status
Simulation time 1879601809 ps
CPU time 96.03 seconds
Started Apr 18 12:57:29 PM PDT 24
Finished Apr 18 12:59:06 PM PDT 24
Peak memory 199588 kb
Host smart-a5b1fff1-0d6f-4954-a825-77fe938918e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138831637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1138831637
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.4030777626
Short name T119
Test name
Test status
Simulation time 269937121 ps
CPU time 15.08 seconds
Started Apr 18 12:57:29 PM PDT 24
Finished Apr 18 12:57:45 PM PDT 24
Peak memory 199596 kb
Host smart-61d14cf5-6eeb-4c8c-82fc-66d29c1cf04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030777626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4030777626
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2189831955
Short name T241
Test name
Test status
Simulation time 470223989 ps
CPU time 3 seconds
Started Apr 18 12:57:29 PM PDT 24
Finished Apr 18 12:57:33 PM PDT 24
Peak memory 199560 kb
Host smart-ac9d5d7c-ec5a-4848-821b-00df95513282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189831955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2189831955
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3070271380
Short name T429
Test name
Test status
Simulation time 48189695074 ps
CPU time 622.06 seconds
Started Apr 18 12:57:36 PM PDT 24
Finished Apr 18 01:07:58 PM PDT 24
Peak memory 207972 kb
Host smart-480df142-17a1-42ff-8892-c9984f0d026e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070271380 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3070271380
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.965360120
Short name T422
Test name
Test status
Simulation time 98328861 ps
CPU time 1.02 seconds
Started Apr 18 12:57:38 PM PDT 24
Finished Apr 18 12:57:40 PM PDT 24
Peak memory 198756 kb
Host smart-c277d287-4e03-45c6-aa27-6ff4cb8b8d2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965360120 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.965360120
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1660158167
Short name T43
Test name
Test status
Simulation time 39506562947 ps
CPU time 398.97 seconds
Started Apr 18 12:57:32 PM PDT 24
Finished Apr 18 01:04:11 PM PDT 24
Peak memory 199652 kb
Host smart-d640d4da-1d8b-49c6-892a-4acf0d8713f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660158167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1660158167
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2349880969
Short name T231
Test name
Test status
Simulation time 12165382476 ps
CPU time 32.5 seconds
Started Apr 18 12:57:29 PM PDT 24
Finished Apr 18 12:58:03 PM PDT 24
Peak memory 199696 kb
Host smart-82a7af83-19b7-4ff7-9d83-a94e9c392e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349880969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2349880969
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4140236517
Short name T491
Test name
Test status
Simulation time 13225190 ps
CPU time 0.57 seconds
Started Apr 18 12:57:39 PM PDT 24
Finished Apr 18 12:57:40 PM PDT 24
Peak memory 194112 kb
Host smart-18a77cbd-c9d7-471d-a1b4-a3e21120b570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140236517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4140236517
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.210668541
Short name T478
Test name
Test status
Simulation time 20724914934 ps
CPU time 60.91 seconds
Started Apr 18 12:57:39 PM PDT 24
Finished Apr 18 12:58:41 PM PDT 24
Peak memory 243724 kb
Host smart-b19422f3-d474-4a77-9d13-b13f6cb696a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210668541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.210668541
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2845331656
Short name T120
Test name
Test status
Simulation time 1158602640 ps
CPU time 22.26 seconds
Started Apr 18 12:57:35 PM PDT 24
Finished Apr 18 12:57:58 PM PDT 24
Peak memory 199816 kb
Host smart-1ffedf72-cd8f-4907-93ed-806346c0c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845331656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2845331656
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3132461140
Short name T66
Test name
Test status
Simulation time 2111469871 ps
CPU time 112.86 seconds
Started Apr 18 12:57:35 PM PDT 24
Finished Apr 18 12:59:28 PM PDT 24
Peak memory 199600 kb
Host smart-54cb9533-a727-445c-89be-858e70370b59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132461140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3132461140
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2301370615
Short name T50
Test name
Test status
Simulation time 39534647313 ps
CPU time 173.03 seconds
Started Apr 18 12:57:35 PM PDT 24
Finished Apr 18 01:00:29 PM PDT 24
Peak memory 199612 kb
Host smart-c1e3926e-4be4-453b-ab05-265bd2cfcec8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301370615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2301370615
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3292865092
Short name T496
Test name
Test status
Simulation time 1105725941 ps
CPU time 11.42 seconds
Started Apr 18 12:57:37 PM PDT 24
Finished Apr 18 12:57:49 PM PDT 24
Peak memory 199540 kb
Host smart-ecba0f2d-fa24-40eb-9dd8-baeef1f211b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292865092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3292865092
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1769873966
Short name T203
Test name
Test status
Simulation time 457138475 ps
CPU time 2.6 seconds
Started Apr 18 12:57:36 PM PDT 24
Finished Apr 18 12:57:39 PM PDT 24
Peak memory 199544 kb
Host smart-177f840a-dd50-4a3e-af81-5881745ec142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769873966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1769873966
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3077482293
Short name T52
Test name
Test status
Simulation time 10634389121 ps
CPU time 141.76 seconds
Started Apr 18 12:57:39 PM PDT 24
Finished Apr 18 01:00:02 PM PDT 24
Peak memory 199724 kb
Host smart-5c315d7c-036d-40a0-934e-d3fbbae7e01a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077482293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3077482293
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1217272591
Short name T458
Test name
Test status
Simulation time 150396621 ps
CPU time 0.95 seconds
Started Apr 18 12:57:34 PM PDT 24
Finished Apr 18 12:57:36 PM PDT 24
Peak memory 198864 kb
Host smart-2bff6730-4751-46db-868c-7c8ad6e78447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217272591 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1217272591
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2383950273
Short name T191
Test name
Test status
Simulation time 8680067090 ps
CPU time 472.88 seconds
Started Apr 18 12:57:38 PM PDT 24
Finished Apr 18 01:05:32 PM PDT 24
Peak memory 199668 kb
Host smart-9a732c0e-ddff-4c97-a4d0-0180945d014d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383950273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2383950273
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.363560106
Short name T176
Test name
Test status
Simulation time 928371911 ps
CPU time 42.49 seconds
Started Apr 18 12:57:38 PM PDT 24
Finished Apr 18 12:58:21 PM PDT 24
Peak memory 199548 kb
Host smart-3a15bff0-f168-4b05-9d25-60022e1f2de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363560106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.363560106
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.723156707
Short name T140
Test name
Test status
Simulation time 34602359 ps
CPU time 0.57 seconds
Started Apr 18 12:57:42 PM PDT 24
Finished Apr 18 12:57:44 PM PDT 24
Peak memory 194796 kb
Host smart-372fb77f-b0bb-4b51-82ff-939a89d825d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723156707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.723156707
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3052741151
Short name T19
Test name
Test status
Simulation time 1535691258 ps
CPU time 62.91 seconds
Started Apr 18 12:57:41 PM PDT 24
Finished Apr 18 12:58:45 PM PDT 24
Peak memory 239136 kb
Host smart-bd2b93eb-a462-43d8-925e-46d25577cb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052741151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3052741151
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2014300743
Short name T72
Test name
Test status
Simulation time 6312859392 ps
CPU time 28.87 seconds
Started Apr 18 12:57:41 PM PDT 24
Finished Apr 18 12:58:11 PM PDT 24
Peak memory 199744 kb
Host smart-3c75c6c5-6ab3-432c-be4d-4ddcf3eea2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014300743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2014300743
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3421935158
Short name T430
Test name
Test status
Simulation time 2221469817 ps
CPU time 48.27 seconds
Started Apr 18 12:57:41 PM PDT 24
Finished Apr 18 12:58:30 PM PDT 24
Peak memory 199676 kb
Host smart-8733634b-c6fa-4781-bd91-55ca2e150887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421935158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3421935158
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1335171099
Short name T190
Test name
Test status
Simulation time 91466062102 ps
CPU time 134.4 seconds
Started Apr 18 12:57:42 PM PDT 24
Finished Apr 18 12:59:57 PM PDT 24
Peak memory 199720 kb
Host smart-832d34ad-4881-44a2-8b35-bb1cb56d36b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335171099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1335171099
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4165915928
Short name T556
Test name
Test status
Simulation time 5781247105 ps
CPU time 77.59 seconds
Started Apr 18 12:57:47 PM PDT 24
Finished Apr 18 12:59:05 PM PDT 24
Peak memory 199596 kb
Host smart-2d337e7b-a90a-4fcc-b592-eebfcacf592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165915928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4165915928
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.238375242
Short name T502
Test name
Test status
Simulation time 50502261 ps
CPU time 1.81 seconds
Started Apr 18 12:57:40 PM PDT 24
Finished Apr 18 12:57:43 PM PDT 24
Peak memory 199488 kb
Host smart-efda1894-6a21-44b9-b809-d5de1180da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238375242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.238375242
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1787324329
Short name T384
Test name
Test status
Simulation time 217871255004 ps
CPU time 2451.97 seconds
Started Apr 18 12:57:40 PM PDT 24
Finished Apr 18 01:38:33 PM PDT 24
Peak memory 236932 kb
Host smart-0719ff17-8abd-4f49-a61e-4980e5860e56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787324329 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1787324329
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3324028568
Short name T301
Test name
Test status
Simulation time 190171186 ps
CPU time 1.24 seconds
Started Apr 18 12:57:42 PM PDT 24
Finished Apr 18 12:57:45 PM PDT 24
Peak memory 199784 kb
Host smart-1ba8dac6-1806-4f93-81a1-d7d89e621c43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324028568 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3324028568
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.4008847992
Short name T543
Test name
Test status
Simulation time 42011547963 ps
CPU time 537.04 seconds
Started Apr 18 12:57:43 PM PDT 24
Finished Apr 18 01:06:41 PM PDT 24
Peak memory 199696 kb
Host smart-0c019878-bfe3-4d48-9477-dd4a8b534787
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008847992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.4008847992
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3802379919
Short name T100
Test name
Test status
Simulation time 3104607686 ps
CPU time 60.08 seconds
Started Apr 18 12:57:42 PM PDT 24
Finished Apr 18 12:58:43 PM PDT 24
Peak memory 199700 kb
Host smart-d4f229eb-c81f-4215-9b20-c53ba38d071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802379919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3802379919
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.783750592
Short name T343
Test name
Test status
Simulation time 18641505 ps
CPU time 0.55 seconds
Started Apr 18 12:57:48 PM PDT 24
Finished Apr 18 12:57:49 PM PDT 24
Peak memory 193996 kb
Host smart-92cb0ee4-3ce4-4fb7-af26-98f155504ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783750592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.783750592
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2853117800
Short name T355
Test name
Test status
Simulation time 3333864594 ps
CPU time 30.28 seconds
Started Apr 18 12:57:40 PM PDT 24
Finished Apr 18 12:58:11 PM PDT 24
Peak memory 238188 kb
Host smart-81524d74-8c94-4327-a8be-955a01d83bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853117800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2853117800
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1289316147
Short name T219
Test name
Test status
Simulation time 1550777590 ps
CPU time 76.16 seconds
Started Apr 18 12:57:41 PM PDT 24
Finished Apr 18 12:58:59 PM PDT 24
Peak memory 199612 kb
Host smart-788ef3e9-65ab-46a4-8497-0bda3a5bf830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289316147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1289316147
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1612390158
Short name T290
Test name
Test status
Simulation time 1884835299 ps
CPU time 20.2 seconds
Started Apr 18 12:57:43 PM PDT 24
Finished Apr 18 12:58:04 PM PDT 24
Peak memory 199544 kb
Host smart-a3db99b2-38bb-4fff-b4b6-77f9498185b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612390158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1612390158
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.4129314520
Short name T578
Test name
Test status
Simulation time 47969838615 ps
CPU time 82.41 seconds
Started Apr 18 12:57:41 PM PDT 24
Finished Apr 18 12:59:04 PM PDT 24
Peak memory 199724 kb
Host smart-438df9b2-2530-4c7a-800a-d1ab44371777
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129314520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.4129314520
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1493694098
Short name T393
Test name
Test status
Simulation time 5428747385 ps
CPU time 74.81 seconds
Started Apr 18 12:57:42 PM PDT 24
Finished Apr 18 12:58:58 PM PDT 24
Peak memory 199660 kb
Host smart-5693cd92-924a-462b-872e-7434aaa84d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493694098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1493694098
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3847580758
Short name T397
Test name
Test status
Simulation time 385307439 ps
CPU time 6.02 seconds
Started Apr 18 12:57:41 PM PDT 24
Finished Apr 18 12:57:48 PM PDT 24
Peak memory 199564 kb
Host smart-2c791110-3bf6-4688-ba81-eecf5632dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847580758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3847580758
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.147132423
Short name T400
Test name
Test status
Simulation time 5726722481 ps
CPU time 328.71 seconds
Started Apr 18 12:57:41 PM PDT 24
Finished Apr 18 01:03:11 PM PDT 24
Peak memory 199680 kb
Host smart-8dffcd46-3743-4eaf-b757-f55ef363990a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147132423 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.147132423
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2930515862
Short name T263
Test name
Test status
Simulation time 35844842 ps
CPU time 1.03 seconds
Started Apr 18 12:57:45 PM PDT 24
Finished Apr 18 12:57:46 PM PDT 24
Peak memory 199236 kb
Host smart-23c0308c-b97b-491d-9bb7-c82733db15ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930515862 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2930515862
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.676313893
Short name T247
Test name
Test status
Simulation time 33143822631 ps
CPU time 456.18 seconds
Started Apr 18 12:57:40 PM PDT 24
Finished Apr 18 01:05:17 PM PDT 24
Peak memory 199648 kb
Host smart-a11cff06-3ec2-4334-99cc-0a9fc7d8fe02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676313893 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.676313893
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.865362007
Short name T350
Test name
Test status
Simulation time 7640529568 ps
CPU time 52.79 seconds
Started Apr 18 12:57:42 PM PDT 24
Finished Apr 18 12:58:36 PM PDT 24
Peak memory 199724 kb
Host smart-3afdec93-6bf3-4555-a505-82b967bc6ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865362007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.865362007
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4145641778
Short name T102
Test name
Test status
Simulation time 46505265 ps
CPU time 0.55 seconds
Started Apr 18 12:57:53 PM PDT 24
Finished Apr 18 12:57:54 PM PDT 24
Peak memory 195156 kb
Host smart-a9f23ed0-ed27-4576-a18d-d70f7c0dc204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145641778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4145641778
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3782454702
Short name T467
Test name
Test status
Simulation time 23183553901 ps
CPU time 42.71 seconds
Started Apr 18 12:57:52 PM PDT 24
Finished Apr 18 12:58:35 PM PDT 24
Peak memory 240752 kb
Host smart-b38b727b-fd62-4125-a9f9-0821ed75ec3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782454702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3782454702
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.544264654
Short name T494
Test name
Test status
Simulation time 1336555951 ps
CPU time 62.66 seconds
Started Apr 18 12:57:50 PM PDT 24
Finished Apr 18 12:58:53 PM PDT 24
Peak memory 199540 kb
Host smart-64b13308-7c53-49fc-a41a-9bde5b9cd6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544264654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.544264654
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1207384313
Short name T186
Test name
Test status
Simulation time 32236314 ps
CPU time 0.67 seconds
Started Apr 18 12:57:49 PM PDT 24
Finished Apr 18 12:57:50 PM PDT 24
Peak memory 196756 kb
Host smart-67c7f3c2-c7f9-49ad-8a8d-89c80384bf3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207384313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1207384313
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3689826914
Short name T53
Test name
Test status
Simulation time 34706147949 ps
CPU time 213.45 seconds
Started Apr 18 12:57:48 PM PDT 24
Finished Apr 18 01:01:22 PM PDT 24
Peak memory 199736 kb
Host smart-430c66b6-70ed-4b78-84cb-703b18edfd38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689826914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3689826914
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.351100276
Short name T154
Test name
Test status
Simulation time 4921231926 ps
CPU time 44.19 seconds
Started Apr 18 12:57:49 PM PDT 24
Finished Apr 18 12:58:34 PM PDT 24
Peak memory 199720 kb
Host smart-5238ffdd-ffec-45ca-a8e8-ed402fbf7b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351100276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.351100276
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.336656331
Short name T46
Test name
Test status
Simulation time 1060359073 ps
CPU time 3.67 seconds
Started Apr 18 12:57:47 PM PDT 24
Finished Apr 18 12:57:51 PM PDT 24
Peak memory 199520 kb
Host smart-726273a9-7367-42bf-b8a9-a79da9309c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336656331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.336656331
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.774557662
Short name T513
Test name
Test status
Simulation time 52986080477 ps
CPU time 910.91 seconds
Started Apr 18 12:57:46 PM PDT 24
Finished Apr 18 01:12:58 PM PDT 24
Peak memory 199720 kb
Host smart-2ec318d9-dbe1-45f4-bf78-c71fb416fc4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774557662 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.774557662
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1278311256
Short name T419
Test name
Test status
Simulation time 29429008 ps
CPU time 1.05 seconds
Started Apr 18 12:57:49 PM PDT 24
Finished Apr 18 12:57:51 PM PDT 24
Peak memory 198800 kb
Host smart-802e6bf0-16e8-40d0-ab6a-2cd9b2cd737c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278311256 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1278311256
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2908312174
Short name T471
Test name
Test status
Simulation time 44615793418 ps
CPU time 499.13 seconds
Started Apr 18 12:57:46 PM PDT 24
Finished Apr 18 01:06:06 PM PDT 24
Peak memory 199588 kb
Host smart-3ba8a730-b567-48d8-8aac-1185ab43fdf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908312174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2908312174
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1335632176
Short name T572
Test name
Test status
Simulation time 4198389955 ps
CPU time 50.95 seconds
Started Apr 18 12:57:47 PM PDT 24
Finished Apr 18 12:58:38 PM PDT 24
Peak memory 199604 kb
Host smart-70e5be61-89f6-4ae4-befe-8d41f54f7aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335632176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1335632176
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.237965324
Short name T205
Test name
Test status
Simulation time 82633485 ps
CPU time 0.61 seconds
Started Apr 18 12:58:03 PM PDT 24
Finished Apr 18 12:58:04 PM PDT 24
Peak memory 195264 kb
Host smart-ea275426-eaaa-4725-9e57-b21db4cae2b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237965324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.237965324
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4107753714
Short name T320
Test name
Test status
Simulation time 1367841297 ps
CPU time 22.61 seconds
Started Apr 18 12:57:52 PM PDT 24
Finished Apr 18 12:58:16 PM PDT 24
Peak memory 207784 kb
Host smart-ff73d6bb-a232-44ad-8f9b-dbc86292987d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107753714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4107753714
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4024377248
Short name T536
Test name
Test status
Simulation time 8799340529 ps
CPU time 51.67 seconds
Started Apr 18 12:57:52 PM PDT 24
Finished Apr 18 12:58:44 PM PDT 24
Peak memory 199700 kb
Host smart-19aba046-eb64-45aa-9a0b-eeb5cd1faa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024377248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4024377248
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1103474302
Short name T387
Test name
Test status
Simulation time 8217880945 ps
CPU time 101.91 seconds
Started Apr 18 12:57:51 PM PDT 24
Finished Apr 18 12:59:33 PM PDT 24
Peak memory 199680 kb
Host smart-189f4265-1b2c-410e-b420-8bdbabc2c437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103474302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1103474302
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1099522919
Short name T3
Test name
Test status
Simulation time 283784047 ps
CPU time 3.93 seconds
Started Apr 18 12:57:54 PM PDT 24
Finished Apr 18 12:57:59 PM PDT 24
Peak memory 199484 kb
Host smart-d620a614-e5a5-41c3-a171-9bd47cc25f17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099522919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1099522919
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.967690258
Short name T324
Test name
Test status
Simulation time 472170399 ps
CPU time 25.84 seconds
Started Apr 18 12:58:03 PM PDT 24
Finished Apr 18 12:58:29 PM PDT 24
Peak memory 199592 kb
Host smart-729cff0a-a913-4abb-95b3-a3c38ec258b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967690258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.967690258
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.326045270
Short name T310
Test name
Test status
Simulation time 1485156732 ps
CPU time 5.49 seconds
Started Apr 18 12:57:53 PM PDT 24
Finished Apr 18 12:57:59 PM PDT 24
Peak memory 199568 kb
Host smart-1b00cc75-8125-47e4-bb10-da84e14639a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326045270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.326045270
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3817751105
Short name T103
Test name
Test status
Simulation time 623212123113 ps
CPU time 2553.18 seconds
Started Apr 18 12:57:52 PM PDT 24
Finished Apr 18 01:40:26 PM PDT 24
Peak memory 224256 kb
Host smart-0c786ac2-25f9-4ef4-b1e3-d426679dd303
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817751105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3817751105
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3556300912
Short name T213
Test name
Test status
Simulation time 214507881 ps
CPU time 1.04 seconds
Started Apr 18 12:57:55 PM PDT 24
Finished Apr 18 12:57:57 PM PDT 24
Peak memory 199148 kb
Host smart-9f50c771-3b93-4f68-95fa-95d9f0fbe76c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556300912 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3556300912
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2406901213
Short name T138
Test name
Test status
Simulation time 80178950932 ps
CPU time 451.03 seconds
Started Apr 18 12:57:52 PM PDT 24
Finished Apr 18 01:05:23 PM PDT 24
Peak memory 199616 kb
Host smart-e344c241-d35a-4ac4-8d60-12a50b8248e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406901213 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.2406901213
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1210764621
Short name T433
Test name
Test status
Simulation time 12090512542 ps
CPU time 86.33 seconds
Started Apr 18 12:57:54 PM PDT 24
Finished Apr 18 12:59:20 PM PDT 24
Peak memory 199728 kb
Host smart-57ba3914-e693-48b7-8ffb-9da73a4cb441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210764621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1210764621
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3114299418
Short name T264
Test name
Test status
Simulation time 47169401 ps
CPU time 0.6 seconds
Started Apr 18 12:57:59 PM PDT 24
Finished Apr 18 12:58:01 PM PDT 24
Peak memory 195300 kb
Host smart-2eb6eb06-276b-4352-8706-4aa172e62d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114299418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3114299418
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4294288257
Short name T421
Test name
Test status
Simulation time 7143576623 ps
CPU time 17.89 seconds
Started Apr 18 12:57:55 PM PDT 24
Finished Apr 18 12:58:13 PM PDT 24
Peak memory 215620 kb
Host smart-3e8ba771-5006-4685-bf94-44c5e6fe8dcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294288257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4294288257
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.431555887
Short name T351
Test name
Test status
Simulation time 173449257 ps
CPU time 8.08 seconds
Started Apr 18 12:58:00 PM PDT 24
Finished Apr 18 12:58:09 PM PDT 24
Peak memory 199592 kb
Host smart-1f43b0ba-af53-4bd1-a720-2b97367a3bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431555887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.431555887
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.277394006
Short name T180
Test name
Test status
Simulation time 27659221283 ps
CPU time 82.04 seconds
Started Apr 18 12:58:03 PM PDT 24
Finished Apr 18 12:59:26 PM PDT 24
Peak memory 199656 kb
Host smart-baf47b60-55df-438c-8591-4ea44ade7a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277394006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.277394006
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.4130310773
Short name T253
Test name
Test status
Simulation time 1247053355 ps
CPU time 66.61 seconds
Started Apr 18 12:57:59 PM PDT 24
Finished Apr 18 12:59:06 PM PDT 24
Peak memory 199560 kb
Host smart-bb701954-7a71-4fef-a0c9-abc491f68f62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130310773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.4130310773
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1523705688
Short name T591
Test name
Test status
Simulation time 4060077480 ps
CPU time 53.92 seconds
Started Apr 18 12:57:52 PM PDT 24
Finished Apr 18 12:58:46 PM PDT 24
Peak memory 199696 kb
Host smart-86007d5b-fe6d-4af0-b96d-3c829ec79360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523705688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1523705688
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3900307584
Short name T592
Test name
Test status
Simulation time 136689402 ps
CPU time 3.97 seconds
Started Apr 18 12:57:54 PM PDT 24
Finished Apr 18 12:57:59 PM PDT 24
Peak memory 199616 kb
Host smart-e3f40ab3-1ef9-4290-bcac-8677a8d3f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900307584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3900307584
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3239275422
Short name T86
Test name
Test status
Simulation time 41451701748 ps
CPU time 546.62 seconds
Started Apr 18 12:58:03 PM PDT 24
Finished Apr 18 01:07:10 PM PDT 24
Peak memory 232672 kb
Host smart-f47a5665-d60c-4929-8314-5c0c84858de1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239275422 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3239275422
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1580270474
Short name T158
Test name
Test status
Simulation time 173403340 ps
CPU time 1.03 seconds
Started Apr 18 12:57:59 PM PDT 24
Finished Apr 18 12:58:00 PM PDT 24
Peak memory 199012 kb
Host smart-cc988568-5912-468c-92f2-87cde12d8980
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580270474 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1580270474
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2079490663
Short name T380
Test name
Test status
Simulation time 7448659079 ps
CPU time 410.13 seconds
Started Apr 18 12:58:02 PM PDT 24
Finished Apr 18 01:04:53 PM PDT 24
Peak memory 199696 kb
Host smart-0a35970b-0734-4eb6-bcb8-b817711854a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079490663 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.2079490663
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2915601997
Short name T182
Test name
Test status
Simulation time 3822238177 ps
CPU time 35.72 seconds
Started Apr 18 12:57:59 PM PDT 24
Finished Apr 18 12:58:35 PM PDT 24
Peak memory 199652 kb
Host smart-2da2a9c4-2da2-4a23-b213-96cd5a83977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915601997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2915601997
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3367736389
Short name T526
Test name
Test status
Simulation time 19154581 ps
CPU time 0.57 seconds
Started Apr 18 12:58:05 PM PDT 24
Finished Apr 18 12:58:06 PM PDT 24
Peak memory 194804 kb
Host smart-f93609c0-aa60-4522-a4f8-1993f6226b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367736389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3367736389
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3525685390
Short name T457
Test name
Test status
Simulation time 711680628 ps
CPU time 26.7 seconds
Started Apr 18 12:57:59 PM PDT 24
Finished Apr 18 12:58:26 PM PDT 24
Peak memory 224144 kb
Host smart-6736b409-66ea-42ac-9724-cfdbd8e9fb02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525685390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3525685390
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1327789166
Short name T184
Test name
Test status
Simulation time 604223762 ps
CPU time 11.63 seconds
Started Apr 18 12:58:07 PM PDT 24
Finished Apr 18 12:58:19 PM PDT 24
Peak memory 199560 kb
Host smart-955293ad-5df6-44f5-bb57-e169aa8b16a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327789166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1327789166
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.281341486
Short name T63
Test name
Test status
Simulation time 3585523437 ps
CPU time 29.1 seconds
Started Apr 18 12:58:00 PM PDT 24
Finished Apr 18 12:58:30 PM PDT 24
Peak memory 199656 kb
Host smart-74aad86e-69b6-4048-bfb1-921e74205a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281341486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.281341486
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2991447303
Short name T33
Test name
Test status
Simulation time 38983334628 ps
CPU time 116.86 seconds
Started Apr 18 12:58:14 PM PDT 24
Finished Apr 18 01:00:12 PM PDT 24
Peak memory 199664 kb
Host smart-2a8a2120-6388-4474-b578-a6a301f48f3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991447303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2991447303
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2525906577
Short name T145
Test name
Test status
Simulation time 6648861096 ps
CPU time 26.06 seconds
Started Apr 18 12:58:00 PM PDT 24
Finished Apr 18 12:58:27 PM PDT 24
Peak memory 199760 kb
Host smart-0e822e48-8b1b-4680-904f-475421add8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525906577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2525906577
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2127305730
Short name T220
Test name
Test status
Simulation time 568677668 ps
CPU time 2.56 seconds
Started Apr 18 12:57:59 PM PDT 24
Finished Apr 18 12:58:03 PM PDT 24
Peak memory 199620 kb
Host smart-020fdadb-cd68-46d1-8e4d-a97ba19c46ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127305730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2127305730
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1380757556
Short name T26
Test name
Test status
Simulation time 4713356019 ps
CPU time 20.42 seconds
Started Apr 18 12:58:06 PM PDT 24
Finished Apr 18 12:58:27 PM PDT 24
Peak memory 199708 kb
Host smart-9bb492ce-52d9-426b-806b-e1e83f28a229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380757556 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1380757556
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3617342533
Short name T464
Test name
Test status
Simulation time 102877249 ps
CPU time 1.22 seconds
Started Apr 18 12:58:07 PM PDT 24
Finished Apr 18 12:58:09 PM PDT 24
Peak memory 199508 kb
Host smart-2ee782e5-0233-4725-8b21-a594a0617edb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617342533 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3617342533
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1070047422
Short name T586
Test name
Test status
Simulation time 32797085384 ps
CPU time 436.01 seconds
Started Apr 18 12:58:05 PM PDT 24
Finished Apr 18 01:05:22 PM PDT 24
Peak memory 199624 kb
Host smart-0e556a70-2ae0-4068-914a-a01a9077019b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070047422 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1070047422
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3363253081
Short name T353
Test name
Test status
Simulation time 4022519304 ps
CPU time 71.06 seconds
Started Apr 18 12:58:06 PM PDT 24
Finished Apr 18 12:59:18 PM PDT 24
Peak memory 199700 kb
Host smart-1559286e-3255-4783-9a54-ee1ff23a00ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363253081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3363253081
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3357598651
Short name T582
Test name
Test status
Simulation time 61148082 ps
CPU time 0.59 seconds
Started Apr 18 12:55:49 PM PDT 24
Finished Apr 18 12:55:50 PM PDT 24
Peak memory 195240 kb
Host smart-9de346c8-0e80-479b-a3bf-f4cd76f9e547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357598651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3357598651
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1803369538
Short name T323
Test name
Test status
Simulation time 1181179719 ps
CPU time 19.1 seconds
Started Apr 18 12:55:40 PM PDT 24
Finished Apr 18 12:55:59 PM PDT 24
Peak memory 208012 kb
Host smart-7fdc7745-1d81-48dc-ace5-d6e526762840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803369538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1803369538
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2362077192
Short name T300
Test name
Test status
Simulation time 7947941483 ps
CPU time 36.48 seconds
Started Apr 18 12:55:41 PM PDT 24
Finished Apr 18 12:56:18 PM PDT 24
Peak memory 199724 kb
Host smart-2b172206-72a2-4fed-83f0-4aaa8322b8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362077192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2362077192
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3537156631
Short name T292
Test name
Test status
Simulation time 4309427674 ps
CPU time 63.74 seconds
Started Apr 18 12:55:44 PM PDT 24
Finished Apr 18 12:56:49 PM PDT 24
Peak memory 199724 kb
Host smart-ece760b4-a9ab-45db-a249-98d3942c421e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537156631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3537156631
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2568855120
Short name T585
Test name
Test status
Simulation time 194154866 ps
CPU time 9.86 seconds
Started Apr 18 12:55:46 PM PDT 24
Finished Apr 18 12:55:57 PM PDT 24
Peak memory 199512 kb
Host smart-2e0cf48a-8519-43d2-b178-f804c2ec6c26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568855120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2568855120
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3818411171
Short name T495
Test name
Test status
Simulation time 909600090 ps
CPU time 16.95 seconds
Started Apr 18 12:55:41 PM PDT 24
Finished Apr 18 12:55:58 PM PDT 24
Peak memory 199524 kb
Host smart-91d982ef-56b7-48cf-8ed7-3b5ddd2994f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818411171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3818411171
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.902530099
Short name T38
Test name
Test status
Simulation time 187595356 ps
CPU time 0.81 seconds
Started Apr 18 12:55:47 PM PDT 24
Finished Apr 18 12:55:48 PM PDT 24
Peak memory 218036 kb
Host smart-6e6a77ad-da02-43c6-b856-730004263c45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902530099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.902530099
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.546552318
Short name T139
Test name
Test status
Simulation time 498893551 ps
CPU time 5.49 seconds
Started Apr 18 12:55:42 PM PDT 24
Finished Apr 18 12:55:49 PM PDT 24
Peak memory 199580 kb
Host smart-2dabebb9-148d-4c8d-839d-64af9cbe5482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546552318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.546552318
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2183513051
Short name T177
Test name
Test status
Simulation time 184454064886 ps
CPU time 663.4 seconds
Started Apr 18 12:55:49 PM PDT 24
Finished Apr 18 01:06:53 PM PDT 24
Peak memory 236992 kb
Host smart-35bb40fe-429c-4c26-9c07-b6f8322578f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183513051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2183513051
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1233637011
Short name T238
Test name
Test status
Simulation time 381792610 ps
CPU time 1.15 seconds
Started Apr 18 12:55:46 PM PDT 24
Finished Apr 18 12:55:48 PM PDT 24
Peak memory 199520 kb
Host smart-b51d83ce-5a6c-4947-a8a1-9153bf1fa076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233637011 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1233637011
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.334535982
Short name T431
Test name
Test status
Simulation time 128108149306 ps
CPU time 462.54 seconds
Started Apr 18 12:55:46 PM PDT 24
Finished Apr 18 01:03:30 PM PDT 24
Peak memory 199712 kb
Host smart-a36aedfb-649e-4e5b-a740-b77153e9f7d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334535982 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.334535982
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3326766590
Short name T284
Test name
Test status
Simulation time 13429030552 ps
CPU time 59.47 seconds
Started Apr 18 12:55:50 PM PDT 24
Finished Apr 18 12:56:50 PM PDT 24
Peak memory 199664 kb
Host smart-d73ac9f4-c83a-4a56-aef2-2f4572f3f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326766590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3326766590
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1216918099
Short name T194
Test name
Test status
Simulation time 17013022 ps
CPU time 0.57 seconds
Started Apr 18 12:58:12 PM PDT 24
Finished Apr 18 12:58:13 PM PDT 24
Peak memory 195160 kb
Host smart-ff07f436-9baf-4c65-9f24-356a79eba60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216918099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1216918099
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.4027370872
Short name T58
Test name
Test status
Simulation time 165577240 ps
CPU time 5.84 seconds
Started Apr 18 12:58:07 PM PDT 24
Finished Apr 18 12:58:14 PM PDT 24
Peak memory 199540 kb
Host smart-3fbb3e6c-aaa5-45ee-a492-4fb1a7f8643d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027370872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4027370872
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.56212833
Short name T546
Test name
Test status
Simulation time 324995814 ps
CPU time 3.62 seconds
Started Apr 18 12:58:09 PM PDT 24
Finished Apr 18 12:58:14 PM PDT 24
Peak memory 199608 kb
Host smart-68ef355f-22b5-4d4a-87ad-4854d41d3554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56212833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.56212833
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.524789495
Short name T424
Test name
Test status
Simulation time 1413827988 ps
CPU time 74.81 seconds
Started Apr 18 12:58:06 PM PDT 24
Finished Apr 18 12:59:22 PM PDT 24
Peak memory 199472 kb
Host smart-19b23a0f-a46c-4614-94de-016b81a4baf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524789495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.524789495
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1448172066
Short name T214
Test name
Test status
Simulation time 3517309916 ps
CPU time 48.69 seconds
Started Apr 18 12:58:06 PM PDT 24
Finished Apr 18 12:58:55 PM PDT 24
Peak memory 199732 kb
Host smart-7dd6eeb0-45ed-4b96-8101-2c095b3a4cfb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448172066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1448172066
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1319340999
Short name T334
Test name
Test status
Simulation time 1586598301 ps
CPU time 56.53 seconds
Started Apr 18 12:58:04 PM PDT 24
Finished Apr 18 12:59:02 PM PDT 24
Peak memory 199600 kb
Host smart-381a532f-ede3-4135-9bbc-464c85c45bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319340999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1319340999
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1325357783
Short name T372
Test name
Test status
Simulation time 454050016 ps
CPU time 1.54 seconds
Started Apr 18 12:58:06 PM PDT 24
Finished Apr 18 12:58:09 PM PDT 24
Peak memory 199576 kb
Host smart-fb396037-d6d2-430b-9ed2-4cae71346a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325357783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1325357783
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2815326025
Short name T274
Test name
Test status
Simulation time 943393204 ps
CPU time 33.69 seconds
Started Apr 18 12:58:12 PM PDT 24
Finished Apr 18 12:58:47 PM PDT 24
Peak memory 207744 kb
Host smart-19637d49-0140-4df0-b62d-c3409a280077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815326025 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2815326025
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2631657364
Short name T155
Test name
Test status
Simulation time 49582172 ps
CPU time 0.98 seconds
Started Apr 18 12:58:17 PM PDT 24
Finished Apr 18 12:58:19 PM PDT 24
Peak memory 197832 kb
Host smart-9983ca2b-2e94-4e60-8370-a59472459f47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631657364 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2631657364
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1119111950
Short name T321
Test name
Test status
Simulation time 34967053782 ps
CPU time 420.57 seconds
Started Apr 18 12:58:11 PM PDT 24
Finished Apr 18 01:05:13 PM PDT 24
Peak memory 199692 kb
Host smart-7ba7ed9b-af42-4a87-a26a-f9cac8f0620f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119111950 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1119111950
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1391380727
Short name T527
Test name
Test status
Simulation time 1126235196 ps
CPU time 29.72 seconds
Started Apr 18 12:58:06 PM PDT 24
Finished Apr 18 12:58:36 PM PDT 24
Peak memory 199612 kb
Host smart-8fb9922d-ab6b-4dba-baf5-ac8cb8ecab47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391380727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1391380727
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2595391424
Short name T528
Test name
Test status
Simulation time 16998038 ps
CPU time 0.57 seconds
Started Apr 18 12:58:17 PM PDT 24
Finished Apr 18 12:58:18 PM PDT 24
Peak memory 194812 kb
Host smart-fc7a5a89-3880-402c-8080-6f944f2457e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595391424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2595391424
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.100742098
Short name T21
Test name
Test status
Simulation time 1797049668 ps
CPU time 20.66 seconds
Started Apr 18 12:58:12 PM PDT 24
Finished Apr 18 12:58:33 PM PDT 24
Peak memory 222216 kb
Host smart-225afb12-0804-4c12-b50a-de9877be667c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100742098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.100742098
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3514353922
Short name T82
Test name
Test status
Simulation time 1917283918 ps
CPU time 14.31 seconds
Started Apr 18 12:58:12 PM PDT 24
Finished Apr 18 12:58:27 PM PDT 24
Peak memory 199544 kb
Host smart-4c82eddb-3d9e-41fb-b52b-e8aac039522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514353922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3514353922
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.4245569394
Short name T440
Test name
Test status
Simulation time 4635802867 ps
CPU time 86.47 seconds
Started Apr 18 12:58:11 PM PDT 24
Finished Apr 18 12:59:38 PM PDT 24
Peak memory 199756 kb
Host smart-3465bf05-e065-4e10-9eae-050220c0f797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245569394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.4245569394
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.462355911
Short name T282
Test name
Test status
Simulation time 1600647909 ps
CPU time 86.18 seconds
Started Apr 18 12:58:11 PM PDT 24
Finished Apr 18 12:59:38 PM PDT 24
Peak memory 199604 kb
Host smart-1160205e-e467-4184-97e4-af3aaaf2374d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462355911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.462355911
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4132170246
Short name T541
Test name
Test status
Simulation time 595320587 ps
CPU time 32.37 seconds
Started Apr 18 12:58:13 PM PDT 24
Finished Apr 18 12:58:46 PM PDT 24
Peak memory 199596 kb
Host smart-2f3b6daa-f2f1-4e28-91d3-9a811ae79e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132170246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4132170246
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3102274170
Short name T332
Test name
Test status
Simulation time 370636774 ps
CPU time 1.61 seconds
Started Apr 18 12:58:11 PM PDT 24
Finished Apr 18 12:58:13 PM PDT 24
Peak memory 199548 kb
Host smart-a93a10fb-b7f4-4f5b-93d6-cee1dcc68a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102274170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3102274170
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3185540372
Short name T590
Test name
Test status
Simulation time 152622291419 ps
CPU time 263.21 seconds
Started Apr 18 12:58:13 PM PDT 24
Finished Apr 18 01:02:37 PM PDT 24
Peak memory 199648 kb
Host smart-e72fc172-5d18-4038-a8b3-17d7a068cacb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185540372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3185540372
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2284038834
Short name T337
Test name
Test status
Simulation time 32968146 ps
CPU time 1.11 seconds
Started Apr 18 12:58:12 PM PDT 24
Finished Apr 18 12:58:14 PM PDT 24
Peak memory 199556 kb
Host smart-2ab9b698-ca52-464e-80db-aa03965e02f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284038834 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2284038834
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3972471865
Short name T149
Test name
Test status
Simulation time 117921537624 ps
CPU time 521.75 seconds
Started Apr 18 12:58:16 PM PDT 24
Finished Apr 18 01:06:58 PM PDT 24
Peak memory 199668 kb
Host smart-f1e69018-ee74-4660-a6c1-b86604dbeee1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972471865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3972471865
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2315831080
Short name T385
Test name
Test status
Simulation time 219611443 ps
CPU time 3.26 seconds
Started Apr 18 12:58:16 PM PDT 24
Finished Apr 18 12:58:20 PM PDT 24
Peak memory 199596 kb
Host smart-17f07fea-3e21-4098-ba27-d8980da4a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315831080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2315831080
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2757894754
Short name T25
Test name
Test status
Simulation time 18757644 ps
CPU time 0.55 seconds
Started Apr 18 12:58:19 PM PDT 24
Finished Apr 18 12:58:20 PM PDT 24
Peak memory 194128 kb
Host smart-24166d3d-e20b-4c31-81cd-4e52b37d281a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757894754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2757894754
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.112420927
Short name T529
Test name
Test status
Simulation time 1594058180 ps
CPU time 24.75 seconds
Started Apr 18 12:58:18 PM PDT 24
Finished Apr 18 12:58:44 PM PDT 24
Peak memory 215096 kb
Host smart-b5d01800-87fe-43dc-a438-0fc67d0e76a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112420927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.112420927
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1318154846
Short name T386
Test name
Test status
Simulation time 30058919619 ps
CPU time 43.99 seconds
Started Apr 18 12:58:19 PM PDT 24
Finished Apr 18 12:59:04 PM PDT 24
Peak memory 199732 kb
Host smart-754dee39-bf33-4a1f-a840-0ca641136716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318154846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1318154846
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2420076945
Short name T77
Test name
Test status
Simulation time 1365325677 ps
CPU time 69.79 seconds
Started Apr 18 12:58:19 PM PDT 24
Finished Apr 18 12:59:29 PM PDT 24
Peak memory 199632 kb
Host smart-e61abec4-c128-4756-8f9b-ffad584ca65a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420076945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2420076945
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3096241914
Short name T258
Test name
Test status
Simulation time 5832974856 ps
CPU time 99.78 seconds
Started Apr 18 12:58:18 PM PDT 24
Finished Apr 18 12:59:59 PM PDT 24
Peak memory 199728 kb
Host smart-c0393a09-8897-4703-b001-c50d6c3180a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096241914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3096241914
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3814666692
Short name T540
Test name
Test status
Simulation time 9075180930 ps
CPU time 35.11 seconds
Started Apr 18 12:58:22 PM PDT 24
Finished Apr 18 12:58:58 PM PDT 24
Peak memory 199656 kb
Host smart-4f943769-2f7f-4b66-aace-7e0917bc3018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814666692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3814666692
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3728929469
Short name T538
Test name
Test status
Simulation time 268027988 ps
CPU time 4.13 seconds
Started Apr 18 12:58:19 PM PDT 24
Finished Apr 18 12:58:24 PM PDT 24
Peak memory 199544 kb
Host smart-4413c378-b51b-4f9c-9208-df46087f0467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728929469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3728929469
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2009316587
Short name T183
Test name
Test status
Simulation time 52339553 ps
CPU time 1.04 seconds
Started Apr 18 12:58:20 PM PDT 24
Finished Apr 18 12:58:22 PM PDT 24
Peak memory 198996 kb
Host smart-5890ea21-d321-4d9f-b59e-a5bf276be9f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009316587 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2009316587
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1963498979
Short name T251
Test name
Test status
Simulation time 376341932345 ps
CPU time 500.95 seconds
Started Apr 18 12:58:18 PM PDT 24
Finished Apr 18 01:06:39 PM PDT 24
Peak memory 199696 kb
Host smart-b45a1479-786c-48f4-962b-d476a6b08895
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963498979 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1963498979
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3254709782
Short name T333
Test name
Test status
Simulation time 4722608234 ps
CPU time 44.01 seconds
Started Apr 18 12:58:18 PM PDT 24
Finished Apr 18 12:59:03 PM PDT 24
Peak memory 199700 kb
Host smart-e19bf87f-0c83-449c-ab93-51a425c41862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254709782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3254709782
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2247375502
Short name T348
Test name
Test status
Simulation time 10689799 ps
CPU time 0.6 seconds
Started Apr 18 12:58:25 PM PDT 24
Finished Apr 18 12:58:26 PM PDT 24
Peak memory 195088 kb
Host smart-f2c2c840-c254-40f1-a8d8-7bacc33d045b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247375502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2247375502
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3445941424
Short name T589
Test name
Test status
Simulation time 8553243731 ps
CPU time 39.35 seconds
Started Apr 18 12:58:18 PM PDT 24
Finished Apr 18 12:58:59 PM PDT 24
Peak memory 205608 kb
Host smart-8e6ca0b9-7e20-44f9-afdf-f2a69cd5f8cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445941424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3445941424
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4075942858
Short name T336
Test name
Test status
Simulation time 17655883745 ps
CPU time 26.81 seconds
Started Apr 18 12:58:19 PM PDT 24
Finished Apr 18 12:58:47 PM PDT 24
Peak memory 199712 kb
Host smart-6e558e21-038d-4b1f-a081-902ae7be46b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075942858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4075942858
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.252540537
Short name T143
Test name
Test status
Simulation time 3282870204 ps
CPU time 89.55 seconds
Started Apr 18 12:58:17 PM PDT 24
Finished Apr 18 12:59:47 PM PDT 24
Peak memory 199724 kb
Host smart-13040900-8597-4e24-8e4c-8218f7c71ce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252540537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.252540537
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2443492904
Short name T378
Test name
Test status
Simulation time 17290656672 ps
CPU time 215.9 seconds
Started Apr 18 12:58:21 PM PDT 24
Finished Apr 18 01:01:58 PM PDT 24
Peak memory 199724 kb
Host smart-89f74a3f-3c5a-4856-bc0d-44a287379b29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443492904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2443492904
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.546320144
Short name T347
Test name
Test status
Simulation time 16185236966 ps
CPU time 28.29 seconds
Started Apr 18 12:58:17 PM PDT 24
Finished Apr 18 12:58:46 PM PDT 24
Peak memory 199712 kb
Host smart-e4c89423-a13a-4ae6-a8d5-cb082e0507a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546320144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.546320144
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3094672109
Short name T401
Test name
Test status
Simulation time 882374678 ps
CPU time 1.43 seconds
Started Apr 18 12:58:19 PM PDT 24
Finished Apr 18 12:58:21 PM PDT 24
Peak memory 199588 kb
Host smart-cffb9955-6391-4ad1-88df-c7abcf4e2f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094672109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3094672109
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1754251669
Short name T409
Test name
Test status
Simulation time 157698316180 ps
CPU time 1915.24 seconds
Started Apr 18 12:58:25 PM PDT 24
Finished Apr 18 01:30:21 PM PDT 24
Peak memory 199924 kb
Host smart-022469db-d0cf-4726-a29e-ea4e9dcfab75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754251669 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1754251669
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.931549753
Short name T273
Test name
Test status
Simulation time 138948932 ps
CPU time 1.24 seconds
Started Apr 18 12:58:18 PM PDT 24
Finished Apr 18 12:58:20 PM PDT 24
Peak memory 199588 kb
Host smart-143f5c14-47bb-4894-a63d-3b571566222f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931549753 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.931549753
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3027113442
Short name T169
Test name
Test status
Simulation time 110476533055 ps
CPU time 483.89 seconds
Started Apr 18 12:58:15 PM PDT 24
Finished Apr 18 01:06:20 PM PDT 24
Peak memory 199656 kb
Host smart-0b0c380a-1c1b-4a6c-8fab-a0ceeaf94641
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027113442 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3027113442
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2652156190
Short name T444
Test name
Test status
Simulation time 2237252571 ps
CPU time 85.9 seconds
Started Apr 18 12:58:18 PM PDT 24
Finished Apr 18 12:59:44 PM PDT 24
Peak memory 199620 kb
Host smart-24c3ccdc-ee9a-42c7-99ee-917764571af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652156190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2652156190
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3674195518
Short name T84
Test name
Test status
Simulation time 39144073 ps
CPU time 0.57 seconds
Started Apr 18 12:58:23 PM PDT 24
Finished Apr 18 12:58:25 PM PDT 24
Peak memory 194128 kb
Host smart-5be0e1d0-be22-4786-9a05-8a2fae51c2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674195518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3674195518
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2566043133
Short name T550
Test name
Test status
Simulation time 20902743993 ps
CPU time 39.9 seconds
Started Apr 18 12:58:24 PM PDT 24
Finished Apr 18 12:59:05 PM PDT 24
Peak memory 248328 kb
Host smart-71940b5e-f02c-49bd-892c-9030c5aff2cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566043133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2566043133
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1804253983
Short name T187
Test name
Test status
Simulation time 10191693734 ps
CPU time 18.18 seconds
Started Apr 18 12:58:24 PM PDT 24
Finished Apr 18 12:58:44 PM PDT 24
Peak memory 199604 kb
Host smart-c199543f-8de8-4300-b42d-3a2853c24fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804253983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1804253983
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1916263569
Short name T211
Test name
Test status
Simulation time 4960875828 ps
CPU time 13.86 seconds
Started Apr 18 12:58:23 PM PDT 24
Finished Apr 18 12:58:38 PM PDT 24
Peak memory 199660 kb
Host smart-d0261b20-b8c0-44d5-bc92-13c4bc5245e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916263569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1916263569
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2945407447
Short name T391
Test name
Test status
Simulation time 5617560938 ps
CPU time 203.28 seconds
Started Apr 18 12:58:25 PM PDT 24
Finished Apr 18 01:01:49 PM PDT 24
Peak memory 199728 kb
Host smart-8a9a0754-37ca-44c9-a190-38f35585eb15
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945407447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2945407447
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2316471752
Short name T516
Test name
Test status
Simulation time 15874691431 ps
CPU time 72.6 seconds
Started Apr 18 12:58:25 PM PDT 24
Finished Apr 18 12:59:38 PM PDT 24
Peak memory 199684 kb
Host smart-5a50f20e-c169-4c64-9932-0e7beff3e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316471752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2316471752
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2079275213
Short name T420
Test name
Test status
Simulation time 772582159 ps
CPU time 4.87 seconds
Started Apr 18 12:58:25 PM PDT 24
Finished Apr 18 12:58:31 PM PDT 24
Peak memory 199612 kb
Host smart-e8bfa66d-895e-4d90-a3a5-a4cb11c7cba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079275213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2079275213
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2650198022
Short name T230
Test name
Test status
Simulation time 8057598389 ps
CPU time 336.31 seconds
Started Apr 18 12:58:29 PM PDT 24
Finished Apr 18 01:04:06 PM PDT 24
Peak memory 216072 kb
Host smart-9e2cd25b-5e4f-4d24-a2bd-8283283230d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650198022 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2650198022
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1117526306
Short name T225
Test name
Test status
Simulation time 122558105 ps
CPU time 1.16 seconds
Started Apr 18 12:58:22 PM PDT 24
Finished Apr 18 12:58:24 PM PDT 24
Peak memory 199432 kb
Host smart-1801c5a0-2b95-40bb-96a2-31877b77226b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117526306 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1117526306
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3118772091
Short name T101
Test name
Test status
Simulation time 70802602569 ps
CPU time 478.59 seconds
Started Apr 18 12:58:30 PM PDT 24
Finished Apr 18 01:06:29 PM PDT 24
Peak memory 199628 kb
Host smart-730174d1-17eb-4f67-a3e6-a1028b7380a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118772091 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3118772091
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3604757194
Short name T302
Test name
Test status
Simulation time 2181944236 ps
CPU time 14.5 seconds
Started Apr 18 12:58:25 PM PDT 24
Finished Apr 18 12:58:40 PM PDT 24
Peak memory 199620 kb
Host smart-d72782c9-ec00-4a3d-b481-2f65add0de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604757194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3604757194
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2523891932
Short name T163
Test name
Test status
Simulation time 16991139 ps
CPU time 0.56 seconds
Started Apr 18 12:58:34 PM PDT 24
Finished Apr 18 12:58:35 PM PDT 24
Peak memory 194008 kb
Host smart-69a19e2a-77aa-4e77-91fc-0855f47947b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523891932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2523891932
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1872128518
Short name T489
Test name
Test status
Simulation time 1069440833 ps
CPU time 38.96 seconds
Started Apr 18 12:58:31 PM PDT 24
Finished Apr 18 12:59:11 PM PDT 24
Peak memory 230600 kb
Host smart-a1503da1-19fb-4d98-9864-98b4261e2f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872128518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1872128518
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3324462419
Short name T425
Test name
Test status
Simulation time 1070215405 ps
CPU time 21.14 seconds
Started Apr 18 12:58:29 PM PDT 24
Finished Apr 18 12:58:50 PM PDT 24
Peak memory 199480 kb
Host smart-6893642d-aeb5-486b-8b2f-669944784339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324462419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3324462419
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1966919126
Short name T568
Test name
Test status
Simulation time 191721614 ps
CPU time 10.06 seconds
Started Apr 18 12:58:28 PM PDT 24
Finished Apr 18 12:58:38 PM PDT 24
Peak memory 199552 kb
Host smart-3c439768-00cd-4502-88d6-4faeea740b64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966919126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1966919126
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.340717777
Short name T255
Test name
Test status
Simulation time 450711535 ps
CPU time 23.17 seconds
Started Apr 18 12:58:29 PM PDT 24
Finished Apr 18 12:58:53 PM PDT 24
Peak memory 199516 kb
Host smart-03f44ee5-f0fd-48af-ba4f-571b9e4d417d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340717777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.340717777
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.728508351
Short name T402
Test name
Test status
Simulation time 903984632 ps
CPU time 26.05 seconds
Started Apr 18 12:58:29 PM PDT 24
Finished Apr 18 12:58:55 PM PDT 24
Peak memory 199484 kb
Host smart-3f0537be-b9b2-4fe0-a57b-0bb73fd0a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728508351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.728508351
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1385223974
Short name T277
Test name
Test status
Simulation time 1279415697 ps
CPU time 3.81 seconds
Started Apr 18 12:58:24 PM PDT 24
Finished Apr 18 12:58:29 PM PDT 24
Peak memory 199576 kb
Host smart-8ae956f8-4f96-4b65-8247-65f4f1475440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385223974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1385223974
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.426162794
Short name T388
Test name
Test status
Simulation time 4485096001 ps
CPU time 246.18 seconds
Started Apr 18 12:58:42 PM PDT 24
Finished Apr 18 01:02:49 PM PDT 24
Peak memory 199684 kb
Host smart-3acc1c52-3131-48d9-b548-0883850b287d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426162794 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.426162794
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1513592123
Short name T202
Test name
Test status
Simulation time 27254653 ps
CPU time 1.04 seconds
Started Apr 18 12:58:28 PM PDT 24
Finished Apr 18 12:58:30 PM PDT 24
Peak memory 198996 kb
Host smart-501ddffb-80c1-4d1d-8193-cfab61ec8266
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513592123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1513592123
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3141078366
Short name T99
Test name
Test status
Simulation time 8218463646 ps
CPU time 423.98 seconds
Started Apr 18 12:58:29 PM PDT 24
Finished Apr 18 01:05:33 PM PDT 24
Peak memory 199688 kb
Host smart-2828ffcd-daa7-4067-82b0-91a4a3f4ccd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141078366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3141078366
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2528458855
Short name T204
Test name
Test status
Simulation time 2784354172 ps
CPU time 52.19 seconds
Started Apr 18 12:58:30 PM PDT 24
Finished Apr 18 12:59:23 PM PDT 24
Peak memory 199628 kb
Host smart-38d608e7-75fd-4caa-9532-bea682cefb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528458855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2528458855
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.850138405
Short name T331
Test name
Test status
Simulation time 14548888 ps
CPU time 0.61 seconds
Started Apr 18 12:58:35 PM PDT 24
Finished Apr 18 12:58:36 PM PDT 24
Peak memory 195168 kb
Host smart-497b32d0-074d-4e3b-af79-018499a3e2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850138405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.850138405
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.607769954
Short name T283
Test name
Test status
Simulation time 192870699 ps
CPU time 6.16 seconds
Started Apr 18 12:58:34 PM PDT 24
Finished Apr 18 12:58:41 PM PDT 24
Peak memory 199812 kb
Host smart-c2077510-ac51-4a31-a0ec-f22f79e5328e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607769954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.607769954
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2218840784
Short name T574
Test name
Test status
Simulation time 494809164 ps
CPU time 12.05 seconds
Started Apr 18 12:58:33 PM PDT 24
Finished Apr 18 12:58:45 PM PDT 24
Peak memory 199564 kb
Host smart-ceed3608-0ff0-427a-9616-4c3ac5270af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218840784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2218840784
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2563498783
Short name T406
Test name
Test status
Simulation time 7312698072 ps
CPU time 69.41 seconds
Started Apr 18 12:58:33 PM PDT 24
Finished Apr 18 12:59:43 PM PDT 24
Peak memory 199724 kb
Host smart-292fc50a-2444-48e6-bab5-4b6783ba96ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563498783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2563498783
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3448151858
Short name T55
Test name
Test status
Simulation time 51545562142 ps
CPU time 108.96 seconds
Started Apr 18 12:58:34 PM PDT 24
Finished Apr 18 01:00:24 PM PDT 24
Peak memory 199632 kb
Host smart-11d4e905-0de4-4b79-857b-11884ea2c03a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448151858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3448151858
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1051995796
Short name T404
Test name
Test status
Simulation time 5400144355 ps
CPU time 111.34 seconds
Started Apr 18 12:58:34 PM PDT 24
Finished Apr 18 01:00:26 PM PDT 24
Peak memory 199612 kb
Host smart-56051f29-48a2-4bd0-80b0-13ccef746266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051995796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1051995796
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.4012381786
Short name T164
Test name
Test status
Simulation time 407187432 ps
CPU time 3.01 seconds
Started Apr 18 12:58:34 PM PDT 24
Finished Apr 18 12:58:38 PM PDT 24
Peak memory 199580 kb
Host smart-2841569c-4c90-4d55-92a8-7824e81e1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012381786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4012381786
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1928903041
Short name T54
Test name
Test status
Simulation time 61458226807 ps
CPU time 290.2 seconds
Started Apr 18 12:58:35 PM PDT 24
Finished Apr 18 01:03:26 PM PDT 24
Peak memory 199704 kb
Host smart-b2c3d3b3-2557-4674-b6d5-dd275e26a737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928903041 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1928903041
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3990467635
Short name T362
Test name
Test status
Simulation time 34831996 ps
CPU time 1.19 seconds
Started Apr 18 12:58:33 PM PDT 24
Finished Apr 18 12:58:35 PM PDT 24
Peak memory 199576 kb
Host smart-5519d576-7d6e-45b8-a4c6-dcb305e1b196
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990467635 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3990467635
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1715250205
Short name T250
Test name
Test status
Simulation time 12318179446 ps
CPU time 408 seconds
Started Apr 18 12:58:33 PM PDT 24
Finished Apr 18 01:05:21 PM PDT 24
Peak memory 199736 kb
Host smart-9ef4d71a-0340-4ab4-ae53-f3e98a314551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715250205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1715250205
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.619020388
Short name T196
Test name
Test status
Simulation time 2015166461 ps
CPU time 36.46 seconds
Started Apr 18 12:58:34 PM PDT 24
Finished Apr 18 12:59:11 PM PDT 24
Peak memory 199508 kb
Host smart-c840dad6-1915-4f1d-9176-f933bdf61d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619020388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.619020388
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1471203900
Short name T439
Test name
Test status
Simulation time 38963096 ps
CPU time 0.55 seconds
Started Apr 18 12:58:44 PM PDT 24
Finished Apr 18 12:58:45 PM PDT 24
Peak memory 195024 kb
Host smart-1f680f72-4b6f-45a7-bd42-d8f66d786288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471203900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1471203900
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4152544550
Short name T330
Test name
Test status
Simulation time 5370500114 ps
CPU time 41.54 seconds
Started Apr 18 12:58:40 PM PDT 24
Finished Apr 18 12:59:23 PM PDT 24
Peak memory 224784 kb
Host smart-01421e0a-8e66-4396-9fcb-70891f3c37d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4152544550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4152544550
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.28339325
Short name T242
Test name
Test status
Simulation time 1751694019 ps
CPU time 33.44 seconds
Started Apr 18 12:58:40 PM PDT 24
Finished Apr 18 12:59:14 PM PDT 24
Peak memory 199612 kb
Host smart-4ad9af76-4b90-4928-a85f-4b0bcf5ef449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28339325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.28339325
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2263048775
Short name T510
Test name
Test status
Simulation time 2074091523 ps
CPU time 115.21 seconds
Started Apr 18 12:58:42 PM PDT 24
Finished Apr 18 01:00:38 PM PDT 24
Peak memory 199488 kb
Host smart-f61d413a-ebc9-497e-8d9c-779e30c89083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263048775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2263048775
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1067303004
Short name T438
Test name
Test status
Simulation time 6155540169 ps
CPU time 74.45 seconds
Started Apr 18 12:58:41 PM PDT 24
Finished Apr 18 12:59:56 PM PDT 24
Peak memory 199684 kb
Host smart-c4fdbeb2-e3eb-4711-81ce-70e340bb3750
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067303004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1067303004
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.294687728
Short name T150
Test name
Test status
Simulation time 8066719450 ps
CPU time 31.57 seconds
Started Apr 18 12:58:44 PM PDT 24
Finished Apr 18 12:59:16 PM PDT 24
Peak memory 199708 kb
Host smart-9da30d0d-5a18-4446-814e-cf2102d296bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294687728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.294687728
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4158795594
Short name T403
Test name
Test status
Simulation time 3297399576 ps
CPU time 5.3 seconds
Started Apr 18 12:58:44 PM PDT 24
Finished Apr 18 12:58:49 PM PDT 24
Peak memory 199680 kb
Host smart-f3b079ed-2013-4bb2-81ef-71768392d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158795594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4158795594
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2408985056
Short name T437
Test name
Test status
Simulation time 20777365834 ps
CPU time 986.48 seconds
Started Apr 18 12:58:43 PM PDT 24
Finished Apr 18 01:15:10 PM PDT 24
Peak memory 226608 kb
Host smart-779efd5e-9cf5-4de0-a1b9-ef16aa4cfa83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408985056 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2408985056
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.389027063
Short name T474
Test name
Test status
Simulation time 133689803 ps
CPU time 0.96 seconds
Started Apr 18 12:58:41 PM PDT 24
Finished Apr 18 12:58:42 PM PDT 24
Peak memory 199144 kb
Host smart-6bfdb01a-b6ae-4e7b-8fad-3233f43542d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389027063 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.389027063
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2285010513
Short name T545
Test name
Test status
Simulation time 7645770322 ps
CPU time 407.08 seconds
Started Apr 18 12:58:44 PM PDT 24
Finished Apr 18 01:05:32 PM PDT 24
Peak memory 199724 kb
Host smart-e1e81665-859d-4346-ad59-e9c96465bfa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285010513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2285010513
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3523474362
Short name T398
Test name
Test status
Simulation time 43773458 ps
CPU time 2.22 seconds
Started Apr 18 12:58:43 PM PDT 24
Finished Apr 18 12:58:46 PM PDT 24
Peak memory 199524 kb
Host smart-ffe77d3c-a52c-4345-980e-0c6d02ec133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523474362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3523474362
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3048816839
Short name T443
Test name
Test status
Simulation time 28646931 ps
CPU time 0.56 seconds
Started Apr 18 12:58:45 PM PDT 24
Finished Apr 18 12:58:46 PM PDT 24
Peak memory 195064 kb
Host smart-31423817-0106-4fef-aeb6-70611d5a9af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048816839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3048816839
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2562960663
Short name T405
Test name
Test status
Simulation time 1523438001 ps
CPU time 56.2 seconds
Started Apr 18 12:58:49 PM PDT 24
Finished Apr 18 12:59:46 PM PDT 24
Peak memory 225196 kb
Host smart-bd54c71e-3190-41ba-958a-a3aa909a07c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562960663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2562960663
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3389988628
Short name T141
Test name
Test status
Simulation time 577227866 ps
CPU time 2.14 seconds
Started Apr 18 12:58:48 PM PDT 24
Finished Apr 18 12:58:51 PM PDT 24
Peak memory 199520 kb
Host smart-32dba17d-2b65-4d4d-a7fe-37a1035254a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389988628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3389988628
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1257007664
Short name T567
Test name
Test status
Simulation time 8633271662 ps
CPU time 114.08 seconds
Started Apr 18 12:58:46 PM PDT 24
Finished Apr 18 01:00:41 PM PDT 24
Peak memory 199632 kb
Host smart-e32d0e6c-f8d1-4858-a079-050c50e9fcb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257007664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1257007664
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2033187209
Short name T449
Test name
Test status
Simulation time 3023876029 ps
CPU time 53.12 seconds
Started Apr 18 12:58:47 PM PDT 24
Finished Apr 18 12:59:41 PM PDT 24
Peak memory 199712 kb
Host smart-3293280f-5c22-4f9a-949e-2cdcf4cfecbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033187209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2033187209
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2347309016
Short name T260
Test name
Test status
Simulation time 5441697996 ps
CPU time 37.76 seconds
Started Apr 18 12:58:45 PM PDT 24
Finished Apr 18 12:59:24 PM PDT 24
Peak memory 199736 kb
Host smart-c722ba52-ccfd-484f-bf64-0646b0146a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347309016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2347309016
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3335037116
Short name T248
Test name
Test status
Simulation time 1771832498 ps
CPU time 4.34 seconds
Started Apr 18 12:58:40 PM PDT 24
Finished Apr 18 12:58:45 PM PDT 24
Peak memory 199616 kb
Host smart-2fdbced2-516e-4cd3-b0fc-917b3f68dc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335037116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3335037116
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.987482259
Short name T531
Test name
Test status
Simulation time 5528893691 ps
CPU time 155.43 seconds
Started Apr 18 12:58:46 PM PDT 24
Finished Apr 18 01:01:22 PM PDT 24
Peak memory 207844 kb
Host smart-927433c8-0e0d-4672-aa4a-61880430a354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987482259 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.987482259
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2589452079
Short name T275
Test name
Test status
Simulation time 44029275 ps
CPU time 1 seconds
Started Apr 18 12:58:47 PM PDT 24
Finished Apr 18 12:58:49 PM PDT 24
Peak memory 198976 kb
Host smart-141b1239-d9eb-46e8-bf25-d0726b433574
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589452079 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2589452079
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1377491822
Short name T563
Test name
Test status
Simulation time 143387739600 ps
CPU time 512.54 seconds
Started Apr 18 12:58:49 PM PDT 24
Finished Apr 18 01:07:22 PM PDT 24
Peak memory 199716 kb
Host smart-82aa187c-42f4-416e-beba-3a9b9b26be62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377491822 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1377491822
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1073052385
Short name T518
Test name
Test status
Simulation time 6894512640 ps
CPU time 89.24 seconds
Started Apr 18 12:58:47 PM PDT 24
Finished Apr 18 01:00:17 PM PDT 24
Peak memory 199728 kb
Host smart-9ae885d7-f76c-48ff-b276-6d1dbe3e5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073052385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1073052385
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.893529540
Short name T469
Test name
Test status
Simulation time 34611837 ps
CPU time 0.58 seconds
Started Apr 18 12:58:52 PM PDT 24
Finished Apr 18 12:58:53 PM PDT 24
Peak memory 195128 kb
Host smart-b44c37bf-883f-4fb9-9de6-4c0b860942b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893529540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.893529540
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.229961856
Short name T487
Test name
Test status
Simulation time 497953126 ps
CPU time 8.66 seconds
Started Apr 18 12:58:57 PM PDT 24
Finished Apr 18 12:59:07 PM PDT 24
Peak memory 240520 kb
Host smart-7c5508e3-0fdd-47b9-8b0d-49a9255bc6c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229961856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.229961856
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2731182462
Short name T544
Test name
Test status
Simulation time 381399230 ps
CPU time 4.8 seconds
Started Apr 18 12:58:51 PM PDT 24
Finished Apr 18 12:58:58 PM PDT 24
Peak memory 199552 kb
Host smart-4db5d5e5-6b2e-49f6-a883-f60e6fa2c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731182462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2731182462
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.444629724
Short name T539
Test name
Test status
Simulation time 1758955677 ps
CPU time 14.14 seconds
Started Apr 18 12:58:53 PM PDT 24
Finished Apr 18 12:59:08 PM PDT 24
Peak memory 199576 kb
Host smart-8c3fe804-9bc9-4dc1-b44f-efebecc3b283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444629724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.444629724
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1297080017
Short name T345
Test name
Test status
Simulation time 22254820838 ps
CPU time 146.58 seconds
Started Apr 18 12:58:51 PM PDT 24
Finished Apr 18 01:01:19 PM PDT 24
Peak memory 199748 kb
Host smart-07f51743-a187-4036-b15e-7254896c6632
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297080017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1297080017
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1449475514
Short name T174
Test name
Test status
Simulation time 3530279098 ps
CPU time 65.35 seconds
Started Apr 18 12:58:51 PM PDT 24
Finished Apr 18 12:59:57 PM PDT 24
Peak memory 199720 kb
Host smart-2abb2bf7-5da2-4559-a0df-c79d21bfbb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449475514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1449475514
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3597820230
Short name T451
Test name
Test status
Simulation time 104110338 ps
CPU time 1.06 seconds
Started Apr 18 12:58:46 PM PDT 24
Finished Apr 18 12:58:48 PM PDT 24
Peak memory 198400 kb
Host smart-9909033e-b0a3-4303-b6bd-cae533ffdbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597820230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3597820230
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.296078382
Short name T318
Test name
Test status
Simulation time 360847812419 ps
CPU time 1329.11 seconds
Started Apr 18 12:58:52 PM PDT 24
Finished Apr 18 01:21:02 PM PDT 24
Peak memory 228396 kb
Host smart-b91faa2b-e672-4957-844e-a2ce96f6fa6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296078382 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.296078382
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3318307149
Short name T151
Test name
Test status
Simulation time 331402592 ps
CPU time 1.34 seconds
Started Apr 18 12:58:52 PM PDT 24
Finished Apr 18 12:58:55 PM PDT 24
Peak memory 199524 kb
Host smart-f16c9275-a28f-4278-8a63-2821556c8917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318307149 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3318307149
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1205949225
Short name T399
Test name
Test status
Simulation time 133679213838 ps
CPU time 436.1 seconds
Started Apr 18 12:58:55 PM PDT 24
Finished Apr 18 01:06:12 PM PDT 24
Peak memory 199692 kb
Host smart-298920b6-f982-4bca-b338-8e8fcf9cfad2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205949225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1205949225
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3593446956
Short name T552
Test name
Test status
Simulation time 5046145059 ps
CPU time 14.66 seconds
Started Apr 18 12:58:54 PM PDT 24
Finished Apr 18 12:59:10 PM PDT 24
Peak memory 199716 kb
Host smart-b83f8c5f-4396-4539-8a28-4cee056e7cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593446956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3593446956
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.950593068
Short name T269
Test name
Test status
Simulation time 22344218 ps
CPU time 0.56 seconds
Started Apr 18 12:55:46 PM PDT 24
Finished Apr 18 12:55:48 PM PDT 24
Peak memory 195160 kb
Host smart-d2fd7092-d303-4d63-a66e-43e6835542e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950593068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.950593068
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3796010089
Short name T85
Test name
Test status
Simulation time 1837468755 ps
CPU time 14.17 seconds
Started Apr 18 12:55:47 PM PDT 24
Finished Apr 18 12:56:02 PM PDT 24
Peak memory 215600 kb
Host smart-6aeb12df-0162-4de7-994d-1baae5bfa7cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796010089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3796010089
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1006191258
Short name T460
Test name
Test status
Simulation time 217187957 ps
CPU time 3.56 seconds
Started Apr 18 12:55:47 PM PDT 24
Finished Apr 18 12:55:51 PM PDT 24
Peak memory 199520 kb
Host smart-62f6a584-62cb-4db1-ae8d-c6e6d209eceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006191258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1006191258
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3665685545
Short name T551
Test name
Test status
Simulation time 16967283302 ps
CPU time 147.57 seconds
Started Apr 18 12:56:02 PM PDT 24
Finished Apr 18 12:58:31 PM PDT 24
Peak memory 199640 kb
Host smart-c2e4082c-b2a4-47fc-be25-604ca916f03a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665685545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3665685545
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1999277419
Short name T229
Test name
Test status
Simulation time 28224913771 ps
CPU time 91.83 seconds
Started Apr 18 12:55:48 PM PDT 24
Finished Apr 18 12:57:21 PM PDT 24
Peak memory 199736 kb
Host smart-f355abe0-2f4e-451c-b0b3-c677650399df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999277419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1999277419
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.148347143
Short name T472
Test name
Test status
Simulation time 32609787687 ps
CPU time 68.24 seconds
Started Apr 18 12:55:48 PM PDT 24
Finished Apr 18 12:56:57 PM PDT 24
Peak memory 199684 kb
Host smart-9df4eabe-c5ce-4f34-a8c4-08b85446ec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148347143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.148347143
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1121574130
Short name T423
Test name
Test status
Simulation time 1899594318 ps
CPU time 6.08 seconds
Started Apr 18 12:55:46 PM PDT 24
Finished Apr 18 12:55:53 PM PDT 24
Peak memory 199508 kb
Host smart-216540a4-8ac8-4205-b8d0-91124f72f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121574130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1121574130
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.96363906
Short name T466
Test name
Test status
Simulation time 748527490848 ps
CPU time 1945.94 seconds
Started Apr 18 12:55:49 PM PDT 24
Finished Apr 18 01:28:16 PM PDT 24
Peak memory 238944 kb
Host smart-65a0d482-96d6-4634-8b7b-214b670d232a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96363906 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.96363906
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.4094871833
Short name T554
Test name
Test status
Simulation time 152732585 ps
CPU time 1.3 seconds
Started Apr 18 12:55:46 PM PDT 24
Finished Apr 18 12:55:48 PM PDT 24
Peak memory 199436 kb
Host smart-c2b4db09-7ce4-4338-9fc1-58fa566b01d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094871833 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.4094871833
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1237542885
Short name T168
Test name
Test status
Simulation time 98440862009 ps
CPU time 417.93 seconds
Started Apr 18 12:55:45 PM PDT 24
Finished Apr 18 01:02:44 PM PDT 24
Peak memory 199704 kb
Host smart-edefc71d-c9b6-4668-a360-21d68f506bad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237542885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1237542885
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.623319031
Short name T473
Test name
Test status
Simulation time 140276748 ps
CPU time 8.13 seconds
Started Apr 18 12:55:47 PM PDT 24
Finished Apr 18 12:55:56 PM PDT 24
Peak memory 199536 kb
Host smart-2f788148-3650-4224-834a-7ff0629ecead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623319031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.623319031
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3601574915
Short name T360
Test name
Test status
Simulation time 11809960 ps
CPU time 0.58 seconds
Started Apr 18 12:55:56 PM PDT 24
Finished Apr 18 12:55:58 PM PDT 24
Peak memory 194796 kb
Host smart-23bd4188-3b37-4e12-b4eb-4791cc4657cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601574915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3601574915
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2609028977
Short name T505
Test name
Test status
Simulation time 2086052999 ps
CPU time 60.83 seconds
Started Apr 18 12:55:54 PM PDT 24
Finished Apr 18 12:56:56 PM PDT 24
Peak memory 232428 kb
Host smart-78c51cf5-27fd-4921-9c59-be2467a53b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609028977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2609028977
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4045453497
Short name T498
Test name
Test status
Simulation time 2105734782 ps
CPU time 19.06 seconds
Started Apr 18 12:55:54 PM PDT 24
Finished Apr 18 12:56:14 PM PDT 24
Peak memory 199608 kb
Host smart-2ac65dd2-7c87-44a6-b709-0d6e4bd532d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045453497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4045453497
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.250768438
Short name T412
Test name
Test status
Simulation time 1760078794 ps
CPU time 94.73 seconds
Started Apr 18 12:55:53 PM PDT 24
Finished Apr 18 12:57:28 PM PDT 24
Peak memory 199576 kb
Host smart-5ab6b097-0203-4252-97f7-e0431c2f380c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250768438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.250768438
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1447611925
Short name T377
Test name
Test status
Simulation time 4460367593 ps
CPU time 77.9 seconds
Started Apr 18 12:55:53 PM PDT 24
Finished Apr 18 12:57:12 PM PDT 24
Peak memory 199708 kb
Host smart-21d054c3-eb30-4524-a06e-2c73c30365ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447611925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1447611925
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1326544528
Short name T357
Test name
Test status
Simulation time 5201921696 ps
CPU time 93.67 seconds
Started Apr 18 12:55:54 PM PDT 24
Finished Apr 18 12:57:29 PM PDT 24
Peak memory 199652 kb
Host smart-a8ac58d7-0ae5-4521-a25f-d8f0b4b601cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326544528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1326544528
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2125260392
Short name T166
Test name
Test status
Simulation time 1327989512 ps
CPU time 4.93 seconds
Started Apr 18 12:55:55 PM PDT 24
Finished Apr 18 12:56:00 PM PDT 24
Peak memory 199548 kb
Host smart-e410720d-7799-4cc1-858a-e602cdca31fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125260392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2125260392
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4255621674
Short name T217
Test name
Test status
Simulation time 3449564682 ps
CPU time 20.58 seconds
Started Apr 18 12:55:52 PM PDT 24
Finished Apr 18 12:56:13 PM PDT 24
Peak memory 216108 kb
Host smart-772fef4d-0f8e-4fd9-aa2b-4d1bad6a7e9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255621674 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4255621674
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1048003176
Short name T67
Test name
Test status
Simulation time 145612345 ps
CPU time 1.22 seconds
Started Apr 18 12:55:54 PM PDT 24
Finished Apr 18 12:55:56 PM PDT 24
Peak memory 199492 kb
Host smart-0edefabb-26e6-4170-868e-31cf9a1f38a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048003176 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.1048003176
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.873995084
Short name T39
Test name
Test status
Simulation time 145584177833 ps
CPU time 516.78 seconds
Started Apr 18 12:55:55 PM PDT 24
Finished Apr 18 01:04:32 PM PDT 24
Peak memory 199664 kb
Host smart-763c93c2-dbf5-4904-9dd2-5b786745f616
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873995084 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.873995084
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3843869101
Short name T244
Test name
Test status
Simulation time 10291645237 ps
CPU time 24.03 seconds
Started Apr 18 12:55:55 PM PDT 24
Finished Apr 18 12:56:20 PM PDT 24
Peak memory 199740 kb
Host smart-47a098c8-f373-426c-99b6-930e81148f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843869101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3843869101
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.917998778
Short name T480
Test name
Test status
Simulation time 52012270 ps
CPU time 0.61 seconds
Started Apr 18 12:56:02 PM PDT 24
Finished Apr 18 12:56:04 PM PDT 24
Peak memory 195228 kb
Host smart-a1d10ae0-27dd-41b2-b08e-ace938109eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917998778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.917998778
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2209638122
Short name T359
Test name
Test status
Simulation time 1495362282 ps
CPU time 25.81 seconds
Started Apr 18 12:56:00 PM PDT 24
Finished Apr 18 12:56:26 PM PDT 24
Peak memory 207672 kb
Host smart-f2a92994-5b1b-4039-831a-eca706f7478c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209638122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2209638122
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.52606739
Short name T366
Test name
Test status
Simulation time 1167566371 ps
CPU time 22.69 seconds
Started Apr 18 12:55:53 PM PDT 24
Finished Apr 18 12:56:16 PM PDT 24
Peak memory 199512 kb
Host smart-31cd47fe-921c-40de-a97a-8bd7960f16f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52606739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.52606739
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2591651903
Short name T197
Test name
Test status
Simulation time 4181165031 ps
CPU time 125.27 seconds
Started Apr 18 12:55:52 PM PDT 24
Finished Apr 18 12:57:58 PM PDT 24
Peak memory 199736 kb
Host smart-a70d86bc-c87c-4fa9-9a41-8c0deb781002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591651903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2591651903
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2825688210
Short name T565
Test name
Test status
Simulation time 2474801224 ps
CPU time 62.01 seconds
Started Apr 18 12:55:59 PM PDT 24
Finished Apr 18 12:57:02 PM PDT 24
Peak memory 199748 kb
Host smart-f59a3d38-b9c1-499d-94a8-4aec3a02b52c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825688210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2825688210
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2012583291
Short name T427
Test name
Test status
Simulation time 6145123275 ps
CPU time 68.38 seconds
Started Apr 18 12:55:53 PM PDT 24
Finished Apr 18 12:57:02 PM PDT 24
Peak memory 199664 kb
Host smart-bdec8a22-5901-4326-b1b1-88845589c567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012583291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2012583291
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.529377009
Short name T261
Test name
Test status
Simulation time 330311545 ps
CPU time 2.87 seconds
Started Apr 18 12:55:53 PM PDT 24
Finished Apr 18 12:55:56 PM PDT 24
Peak memory 199544 kb
Host smart-b3b5164b-4eb7-4a40-bd71-015f0b5ccf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529377009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.529377009
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3070645363
Short name T515
Test name
Test status
Simulation time 4088551919 ps
CPU time 50.91 seconds
Started Apr 18 12:56:04 PM PDT 24
Finished Apr 18 12:56:56 PM PDT 24
Peak memory 232712 kb
Host smart-5677c0d9-9fa0-4322-9a37-72aec5ed2db5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070645363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3070645363
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3059405924
Short name T354
Test name
Test status
Simulation time 82777599 ps
CPU time 0.94 seconds
Started Apr 18 12:55:55 PM PDT 24
Finished Apr 18 12:55:56 PM PDT 24
Peak memory 199088 kb
Host smart-5c52d0ee-e736-4391-8518-19d0fb05ecb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059405924 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3059405924
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2455898570
Short name T295
Test name
Test status
Simulation time 27284971180 ps
CPU time 372.8 seconds
Started Apr 18 12:55:54 PM PDT 24
Finished Apr 18 01:02:07 PM PDT 24
Peak memory 199708 kb
Host smart-6690264f-96d0-4de3-888e-5523ce40c348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455898570 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2455898570
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1187225852
Short name T178
Test name
Test status
Simulation time 9107366063 ps
CPU time 31.45 seconds
Started Apr 18 12:55:53 PM PDT 24
Finished Apr 18 12:56:26 PM PDT 24
Peak memory 199732 kb
Host smart-180a3651-ca33-4cd4-a99a-c41c9d272a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187225852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1187225852
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1327808153
Short name T413
Test name
Test status
Simulation time 40337576 ps
CPU time 0.6 seconds
Started Apr 18 12:56:33 PM PDT 24
Finished Apr 18 12:56:35 PM PDT 24
Peak memory 195208 kb
Host smart-466f14fe-f2db-4886-8c95-04ebf0be6243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327808153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1327808153
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.4051935035
Short name T389
Test name
Test status
Simulation time 1327218454 ps
CPU time 55.02 seconds
Started Apr 18 12:56:00 PM PDT 24
Finished Apr 18 12:56:56 PM PDT 24
Peak memory 225268 kb
Host smart-35070770-a9bc-444e-9773-0f55f5d9233b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051935035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4051935035
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4171918126
Short name T542
Test name
Test status
Simulation time 6090774763 ps
CPU time 30.2 seconds
Started Apr 18 12:56:01 PM PDT 24
Finished Apr 18 12:56:32 PM PDT 24
Peak memory 199704 kb
Host smart-4103604f-7c76-43c6-b537-7a6998594f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171918126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4171918126
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3726831409
Short name T276
Test name
Test status
Simulation time 2460960672 ps
CPU time 38.81 seconds
Started Apr 18 12:56:01 PM PDT 24
Finished Apr 18 12:56:41 PM PDT 24
Peak memory 199728 kb
Host smart-13da6701-fbc3-4762-9bdf-a404fdbc9790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726831409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3726831409
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3949584521
Short name T500
Test name
Test status
Simulation time 1831037034 ps
CPU time 48.79 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 12:56:53 PM PDT 24
Peak memory 199584 kb
Host smart-af0278b6-08ed-443c-b31f-982a890a8563
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949584521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3949584521
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.484774223
Short name T367
Test name
Test status
Simulation time 1105896074 ps
CPU time 61.05 seconds
Started Apr 18 12:56:01 PM PDT 24
Finished Apr 18 12:57:03 PM PDT 24
Peak memory 199600 kb
Host smart-b3ba93eb-02da-42a5-9655-7a46603a0db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484774223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.484774223
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1506008723
Short name T259
Test name
Test status
Simulation time 796574192 ps
CPU time 5.58 seconds
Started Apr 18 12:56:04 PM PDT 24
Finished Apr 18 12:56:10 PM PDT 24
Peak memory 199544 kb
Host smart-9445072b-122f-46a5-b648-1ef4f7f00859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506008723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1506008723
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1212518210
Short name T87
Test name
Test status
Simulation time 229612706602 ps
CPU time 3026.57 seconds
Started Apr 18 12:56:04 PM PDT 24
Finished Apr 18 01:46:32 PM PDT 24
Peak memory 215404 kb
Host smart-a5bf69d3-b718-44b9-9752-4d7562c95e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212518210 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1212518210
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2806447558
Short name T533
Test name
Test status
Simulation time 74315300 ps
CPU time 1.3 seconds
Started Apr 18 12:56:02 PM PDT 24
Finished Apr 18 12:56:04 PM PDT 24
Peak memory 199492 kb
Host smart-49a964b1-a719-4105-9f7e-97a5979e2e67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806447558 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2806447558
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.4010937004
Short name T488
Test name
Test status
Simulation time 29492538320 ps
CPU time 486.38 seconds
Started Apr 18 12:56:02 PM PDT 24
Finished Apr 18 01:04:09 PM PDT 24
Peak memory 199712 kb
Host smart-f8d4b290-487d-43f4-947b-47a4fbbf2d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010937004 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.4010937004
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.509520556
Short name T95
Test name
Test status
Simulation time 6237935738 ps
CPU time 40.25 seconds
Started Apr 18 12:56:00 PM PDT 24
Finished Apr 18 12:56:41 PM PDT 24
Peak memory 199752 kb
Host smart-b5a328a3-d1e6-4dab-ad70-ed401b33299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509520556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.509520556
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2006098349
Short name T232
Test name
Test status
Simulation time 15776985 ps
CPU time 0.63 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 12:56:05 PM PDT 24
Peak memory 195112 kb
Host smart-93836551-1d9d-4165-a8a4-a99fdd70ea96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006098349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2006098349
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1135894119
Short name T514
Test name
Test status
Simulation time 11308165655 ps
CPU time 43.29 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 12:56:47 PM PDT 24
Peak memory 240680 kb
Host smart-1892265a-efc6-4508-a563-8bb47c98ff2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135894119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1135894119
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2416392308
Short name T317
Test name
Test status
Simulation time 1350729344 ps
CPU time 68.56 seconds
Started Apr 18 12:56:01 PM PDT 24
Finished Apr 18 12:57:10 PM PDT 24
Peak memory 199528 kb
Host smart-7a528293-7774-4484-b08a-eda4011add34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416392308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2416392308
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1386895660
Short name T81
Test name
Test status
Simulation time 2327883433 ps
CPU time 61.73 seconds
Started Apr 18 12:56:04 PM PDT 24
Finished Apr 18 12:57:06 PM PDT 24
Peak memory 199676 kb
Host smart-b5a05375-b9d8-4abd-af02-e5d530af4bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386895660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1386895660
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1118558593
Short name T364
Test name
Test status
Simulation time 15497362709 ps
CPU time 99.49 seconds
Started Apr 18 12:56:02 PM PDT 24
Finished Apr 18 12:57:42 PM PDT 24
Peak memory 199680 kb
Host smart-cfe00bbb-8b25-4c3c-9675-50597f45b02b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118558593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1118558593
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1590007780
Short name T313
Test name
Test status
Simulation time 2997147490 ps
CPU time 9.46 seconds
Started Apr 18 12:56:02 PM PDT 24
Finished Apr 18 12:56:12 PM PDT 24
Peak memory 199720 kb
Host smart-b29c0921-18b9-460a-a51c-6fbb4ab98b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590007780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1590007780
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3450681012
Short name T40
Test name
Test status
Simulation time 133779889 ps
CPU time 1.22 seconds
Started Apr 18 12:56:02 PM PDT 24
Finished Apr 18 12:56:04 PM PDT 24
Peak memory 199560 kb
Host smart-e039cf9a-aa2e-43df-8b08-f9e67f71cbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450681012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3450681012
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1439087311
Short name T426
Test name
Test status
Simulation time 15315401091 ps
CPU time 259.89 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 01:00:24 PM PDT 24
Peak memory 199680 kb
Host smart-fc7e13fa-76eb-4813-9dbc-eaa753d3cc30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439087311 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1439087311
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1472789947
Short name T236
Test name
Test status
Simulation time 56727572 ps
CPU time 1.14 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 12:56:05 PM PDT 24
Peak memory 199592 kb
Host smart-f62f3bf3-a99f-484f-96d6-e6f8a5591582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472789947 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1472789947
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1222278775
Short name T159
Test name
Test status
Simulation time 42986800006 ps
CPU time 491.75 seconds
Started Apr 18 12:55:58 PM PDT 24
Finished Apr 18 01:04:10 PM PDT 24
Peak memory 199588 kb
Host smart-a102d543-363f-4a2f-83dc-233ccf9948aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222278775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1222278775
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1645437272
Short name T448
Test name
Test status
Simulation time 18659646432 ps
CPU time 64.97 seconds
Started Apr 18 12:56:03 PM PDT 24
Finished Apr 18 12:57:09 PM PDT 24
Peak memory 199692 kb
Host smart-d9953cb6-e82d-44a8-982d-9d9bf67138f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645437272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1645437272
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2075008018
Short name T75
Test name
Test status
Simulation time 67786995586 ps
CPU time 1415.97 seconds
Started Apr 18 12:59:09 PM PDT 24
Finished Apr 18 01:22:46 PM PDT 24
Peak memory 248876 kb
Host smart-9ad2cb13-8873-481b-9f51-60954337efb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075008018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.2075008018
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%