Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13056330	1			T1	29617		T2	12055		T3	344
all_values[1]	13056330	1			T1	29617		T2	12055		T3	344
all_values[2]	13056330	1			T1	29617		T2	12055		T3	344

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103316

1

T1

408

T3

9

T4

2781

auto[1]

39065674

1

T1

88443

T2

36165

T3

1023

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37063968

1

T1

77489

T2

36126

T3

981

auto[1]

2105022

1

T1

11362

T2

39

T3

51

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	43271	1			T1	408		T4	1215		T25	13
all_values[0]	auto[0]	auto[1]	517	1			T4	6		T25	2		T6	4
all_values[0]	auto[1]	auto[0]	12968452	1			T1	29192		T2	12016		T3	293
all_values[0]	auto[1]	auto[1]	44090	1			T1	17		T2	39		T3	51
all_values[1]	auto[0]	auto[0]	31558	1			T4	1549		T6	3		T13	9
all_values[1]	auto[0]	auto[1]	202	1			T4	3		T6	2		T13	4
all_values[1]	auto[1]	auto[0]	13024048	1			T1	29617		T2	12055		T3	344
all_values[1]	auto[1]	auto[1]	522	1			T6	35		T13	2		T15	3
all_values[2]	auto[0]	auto[0]	26279	1			T3	9		T4	6		T6	3
all_values[2]	auto[0]	auto[1]	1489	1			T4	2		T13	5		T15	2
all_values[2]	auto[1]	auto[0]	10970360	1			T1	18272		T2	12055		T3	335
all_values[2]	auto[1]	auto[1]	2058202	1			T1	11345		T4	22792		T6	15740