Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6354026

1

T1

5208

T2

2323

T3

3040

auto[1]

2522541

1

T1

5222

T2

9004

T3

1391

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2477237

1

T1

2965

T2

6537

T3

3577

auto[1]

6399330

1

T1

7465

T2

4790

T3

854

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5647470

1

T1

5387

T3

899

T4

11658

auto[1]

3229097

1

T1

5043

T2

11327

T3

3532

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5720198	1			T1	10185		T2	4014		T3	3806
fifo_depth[1]	404058	1			T1	183		T2	811		T3	198
fifo_depth[2]	330096	1			T1	49		T2	823		T3	177
fifo_depth[3]	272770	1			T1	10		T2	797		T3	58
fifo_depth[4]	242550	1			T1	3		T2	800		T3	133
fifo_depth[5]	217026	1			T2	851		T3	27		T4	126
fifo_depth[6]	209436	1			T2	789		T3	26		T4	157
fifo_depth[7]	183706	1			T2	720		T3	4		T4	58
fifo_depth[8]	168123	1			T2	619		T3	2		T4	138
fifo_depth[9]	115675	1			T2	471		T4	17		T24	1035
fifo_depth[10]	90914	1			T2	291		T4	19		T24	643
fifo_depth[11]	56751	1			T2	184		T4	7		T24	409
fifo_depth[12]	56655	1			T2	78		T4	3		T24	175
fifo_depth[13]	32039	1			T2	55		T24	93		T6	119
fifo_depth[14]	40390	1			T2	11		T24	32		T6	75
fifo_depth[15]	27727	1			T2	8		T24	13		T6	48
fifo_depth[16]	91613	1			T2	3		T24	4		T6	36

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3270985

1

T1

245

T2

7313

T3

625

auto[1]

5605582

1

T1

10185

T2

4014

T3

3806

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8761951

1

T1

10430

T2

11327

T3

4431

auto[1]

114616

1

T6

423

T15

6661

T16

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

248842

1

T3

108

T4

721

T5

14

auto[0]

auto[0]

auto[0]

auto[1]

197156

1

T1

19

T3

21

T4

243

auto[0]

auto[0]

auto[1]

auto[0]

889220

1

T1

102

T4

280

T25

34

auto[0]

auto[0]

auto[1]

auto[1]

233225

1

T1

14

T3

49

T4

465

auto[0]

auto[1]

auto[0]

auto[0]

420955

1

T1

3

T2

1412

T3

177

auto[0]

auto[1]

auto[0]

auto[1]

416161

1

T1

33

T2

2817

T3

166

auto[0]

auto[1]

auto[1]

auto[0]

405322

1

T1

71

T2

95

T3

56

auto[0]

auto[1]

auto[1]

auto[1]

460104

1

T1

3

T2

2989

T3

48

auto[1]

auto[0]

auto[0]

auto[0]

213469

1

T1

3

T3

293

T4

3378

auto[1]

auto[0]

auto[0]

auto[1]

212916

1

T1

971

T3

105

T4

1686

auto[1]

auto[0]

auto[1]

auto[0]

3424576

1

T1

2459

T4

1880

T25

100

auto[1]

auto[0]

auto[1]

auto[1]

228066

1

T1

1819

T3

323

T4

3005

auto[1]

auto[1]

auto[0]

auto[0]

381514

1

T1

263

T2

762

T3

2163

auto[1]

auto[1]

auto[0]

auto[1]

386224

1

T1

1673

T2

1546

T3

544

auto[1]

auto[1]

auto[1]

auto[0]

370128

1

T1

2307

T2

54

T3

243

auto[1]

auto[1]

auto[1]

auto[1]

388689

1

T1

690

T2

1652

T3

135

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

449565

1

T1

3

T3

401

T4

4099

auto[0]

auto[0]

auto[0]

auto[1]

399932

1

T1

990

T3

126

T4

1929

auto[0]

auto[0]

auto[1]

auto[0]

4299571

1

T1

2561

T4

2160

T25

134

auto[0]

auto[0]

auto[1]

auto[1]

448753

1

T1

1833

T3

372

T4

3470

auto[0]

auto[1]

auto[0]

auto[0]

783179

1

T1

266

T2

2174

T3

2340

auto[0]

auto[1]

auto[0]

auto[1]

785714

1

T1

1706

T2

4363

T3

710

auto[0]

auto[1]

auto[1]

auto[0]

764357

1

T1

2378

T2

149

T3

299

auto[0]

auto[1]

auto[1]

auto[1]

830880

1

T1

693

T2

4641

T3

183

auto[1]

auto[0]

auto[0]

auto[0]

12746

1

T6

3

T15

578

T99

539

auto[1]

auto[0]

auto[0]

auto[1]

10140

1

T6

37

T15

330

T16

1

auto[1]

auto[0]

auto[1]

auto[0]

14225

1

T6

1

T15

3237

T21

455

auto[1]

auto[0]

auto[1]

auto[1]

12538

1

T15

130

T49

1

T99

92

auto[1]

auto[1]

auto[0]

auto[0]

19290

1

T6

2

T15

518

T16

1

auto[1]

auto[1]

auto[0]

auto[1]

16671

1

T15

325

T99

64

T21

86

auto[1]

auto[1]

auto[1]

auto[0]

11093

1

T6

378

T15

738

T16

1

auto[1]

auto[1]

auto[1]

auto[1]

17913

1

T6

2

T15

805

T49

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	226215	1			T1	3		T3	293		T4	3378
fifo_depth[0]	auto[0]	auto[0]	auto[1]	223056	1			T1	971		T3	105		T4	1686
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3438801	1			T1	2459		T4	1880		T25	100
fifo_depth[0]	auto[0]	auto[1]	auto[1]	240604	1			T1	1819		T3	323		T4	3005
fifo_depth[0]	auto[1]	auto[0]	auto[0]	400804	1			T1	263		T2	762		T3	2163
fifo_depth[0]	auto[1]	auto[0]	auto[1]	402895	1			T1	1673		T2	1546		T3	544
fifo_depth[0]	auto[1]	auto[1]	auto[0]	381221	1			T1	2307		T2	54		T3	243
fifo_depth[0]	auto[1]	auto[1]	auto[1]	406602	1			T1	690		T2	1652		T3	135
fifo_depth[1]	auto[0]	auto[0]	auto[0]	17433	1			T3	5		T4	187		T5	3
fifo_depth[1]	auto[0]	auto[0]	auto[1]	16845	1			T1	15		T3	2		T4	60
fifo_depth[1]	auto[0]	auto[1]	auto[0]	186198	1			T1	69		T4	105		T25	9
fifo_depth[1]	auto[0]	auto[1]	auto[1]	17853	1			T1	14		T3	12		T4	176
fifo_depth[1]	auto[1]	auto[0]	auto[0]	42262	1			T1	3		T2	164		T3	119
fifo_depth[1]	auto[1]	auto[0]	auto[1]	40369	1			T1	21		T2	310		T3	38
fifo_depth[1]	auto[1]	auto[1]	auto[0]	39868	1			T1	58		T2	11		T3	14
fifo_depth[1]	auto[1]	auto[1]	auto[1]	43230	1			T1	3		T2	326		T3	8
fifo_depth[2]	auto[0]	auto[0]	auto[0]	14950	1			T3	46		T4	259		T5	3
fifo_depth[2]	auto[0]	auto[0]	auto[1]	14647	1			T1	3		T3	6		T4	42
fifo_depth[2]	auto[0]	auto[1]	auto[0]	138070	1			T1	26		T4	59		T25	9
fifo_depth[2]	auto[0]	auto[1]	auto[1]	15269	1			T3	11		T4	140		T5	25
fifo_depth[2]	auto[1]	auto[0]	auto[0]	37399	1			T2	147		T3	38		T4	98
fifo_depth[2]	auto[1]	auto[0]	auto[1]	35080	1			T1	9		T2	318		T3	37
fifo_depth[2]	auto[1]	auto[1]	auto[0]	35575	1			T1	11		T2	13		T3	22
fifo_depth[2]	auto[1]	auto[1]	auto[1]	39106	1			T2	345		T3	17		T4	293
fifo_depth[3]	auto[0]	auto[0]	auto[0]	12178	1			T3	6		T4	75		T5	2
fifo_depth[3]	auto[0]	auto[0]	auto[1]	11869	1			T1	1		T4	20		T25	1
fifo_depth[3]	auto[0]	auto[1]	auto[0]	105858	1			T1	5		T4	39		T25	7
fifo_depth[3]	auto[0]	auto[1]	auto[1]	12395	1			T3	4		T4	58		T25	6
fifo_depth[3]	auto[1]	auto[0]	auto[0]	33159	1			T2	149		T3	6		T4	14
fifo_depth[3]	auto[1]	auto[0]	auto[1]	31004	1			T1	3		T2	293		T3	30
fifo_depth[3]	auto[1]	auto[1]	auto[0]	31516	1			T1	1		T2	10		T3	9
fifo_depth[3]	auto[1]	auto[1]	auto[1]	34791	1			T2	345		T3	3		T4	80
fifo_depth[4]	auto[0]	auto[0]	auto[0]	11863	1			T3	32		T4	116		T5	2
fifo_depth[4]	auto[0]	auto[0]	auto[1]	11003	1			T3	8		T4	56		T25	11
fifo_depth[4]	auto[0]	auto[1]	auto[0]	80531	1			T1	2		T4	30		T25	4
fifo_depth[4]	auto[0]	auto[1]	auto[1]	12133	1			T3	15		T4	30		T5	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	32159	1			T2	154		T3	8		T4	40
fifo_depth[4]	auto[1]	auto[0]	auto[1]	29913	1			T2	310		T3	48		T4	86
fifo_depth[4]	auto[1]	auto[1]	auto[0]	30612	1			T1	1		T2	7		T3	7
fifo_depth[4]	auto[1]	auto[1]	auto[1]	34336	1			T2	329		T3	15		T4	114
fifo_depth[5]	auto[0]	auto[0]	auto[0]	10365	1			T3	4		T4	42		T5	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	9922	1			T4	12		T6	67		T57	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	66529	1			T4	11		T25	4		T6	192
fifo_depth[5]	auto[0]	auto[1]	auto[1]	10672	1			T3	4		T4	18		T25	2
fifo_depth[5]	auto[1]	auto[0]	auto[0]	30667	1			T2	168		T3	4		T4	3
fifo_depth[5]	auto[1]	auto[0]	auto[1]	27736	1			T2	342		T3	8		T4	17
fifo_depth[5]	auto[1]	auto[1]	auto[0]	28946	1			T2	10		T3	4		T4	9
fifo_depth[5]	auto[1]	auto[1]	auto[1]	32189	1			T2	331		T3	3		T4	14
fifo_depth[6]	auto[0]	auto[0]	auto[0]	10631	1			T3	12		T4	20		T5	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	9702	1			T3	5		T4	18		T25	3
fifo_depth[6]	auto[0]	auto[1]	auto[0]	59272	1			T4	17		T6	177		T55	866
fifo_depth[6]	auto[0]	auto[1]	auto[1]	10961	1			T3	2		T4	14		T25	9
fifo_depth[6]	auto[1]	auto[0]	auto[0]	29999	1			T2	156		T3	1		T4	4
fifo_depth[6]	auto[1]	auto[0]	auto[1]	27928	1			T2	288		T3	4		T4	39
fifo_depth[6]	auto[1]	auto[1]	auto[0]	28518	1			T2	8		T4	29		T24	551
fifo_depth[6]	auto[1]	auto[1]	auto[1]	32425	1			T2	337		T3	2		T4	16
fifo_depth[7]	auto[0]	auto[0]	auto[0]	9603	1			T3	2		T4	8		T5	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	8722	1			T4	7		T6	76		T15	47
fifo_depth[7]	auto[0]	auto[1]	auto[0]	47334	1			T4	7		T6	160		T55	654
fifo_depth[7]	auto[0]	auto[1]	auto[1]	9861	1			T4	11		T25	1		T6	90
fifo_depth[7]	auto[1]	auto[0]	auto[0]	27461	1			T2	142		T3	1		T4	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	25428	1			T2	280		T3	1		T4	10
fifo_depth[7]	auto[1]	auto[1]	auto[0]	26127	1			T2	10		T4	8		T24	519
fifo_depth[7]	auto[1]	auto[1]	auto[1]	29170	1			T2	288		T4	6		T24	435
fifo_depth[8]	auto[0]	auto[0]	auto[0]	10330	1			T3	1		T4	10		T26	1
fifo_depth[8]	auto[0]	auto[0]	auto[1]	9005	1			T4	25		T25	1		T6	77
fifo_depth[8]	auto[0]	auto[1]	auto[0]	37757	1			T4	6		T25	1		T6	146
fifo_depth[8]	auto[0]	auto[1]	auto[1]	10395	1			T3	1		T4	9		T6	83
fifo_depth[8]	auto[1]	auto[0]	auto[0]	25457	1			T2	122		T4	1		T24	265
fifo_depth[8]	auto[1]	auto[0]	auto[1]	23983	1			T2	243		T4	53		T24	259
fifo_depth[8]	auto[1]	auto[1]	auto[0]	24338	1			T2	7		T4	26		T24	441
fifo_depth[8]	auto[1]	auto[1]	auto[1]	26858	1			T2	247		T4	8		T24	346
fifo_depth[9]	auto[0]	auto[0]	auto[0]	6492	1			T4	1		T6	124		T20	21
fifo_depth[9]	auto[0]	auto[0]	auto[1]	6213	1			T4	1		T6	81		T15	34
fifo_depth[9]	auto[0]	auto[1]	auto[0]	24770	1			T4	4		T6	97		T55	325
fifo_depth[9]	auto[0]	auto[1]	auto[1]	6802	1			T4	2		T6	57		T20	45
fifo_depth[9]	auto[1]	auto[0]	auto[0]	17777	1			T2	91		T24	209		T6	106
fifo_depth[9]	auto[1]	auto[0]	auto[1]	17234	1			T2	178		T4	5		T24	216
fifo_depth[9]	auto[1]	auto[1]	auto[0]	17447	1			T2	9		T4	4		T24	323
fifo_depth[9]	auto[1]	auto[1]	auto[1]	18940	1			T2	193		T24	287		T6	118
fifo_depth[10]	auto[0]	auto[0]	auto[0]	6451	1			T4	3		T6	62		T20	9
fifo_depth[10]	auto[0]	auto[0]	auto[1]	4951	1			T6	26		T15	94		T44	6
fifo_depth[10]	auto[0]	auto[1]	auto[0]	17767	1			T4	1		T6	50		T55	231
fifo_depth[10]	auto[0]	auto[1]	auto[1]	6336	1			T4	6		T6	32		T20	31
fifo_depth[10]	auto[1]	auto[0]	auto[0]	13081	1			T2	54		T24	120		T6	66
fifo_depth[10]	auto[1]	auto[0]	auto[1]	13684	1			T2	120		T4	6		T24	130
fifo_depth[10]	auto[1]	auto[1]	auto[0]	13557	1			T2	5		T4	3		T24	221
fifo_depth[10]	auto[1]	auto[1]	auto[1]	15087	1			T2	112		T24	172		T6	71
fifo_depth[11]	auto[0]	auto[0]	auto[0]	4327	1			T6	63		T20	9		T15	111
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3385	1			T6	60		T15	27		T44	3
fifo_depth[11]	auto[0]	auto[1]	auto[0]	10285	1			T4	1		T6	34		T55	98
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4519	1			T4	1		T6	23		T20	13
fifo_depth[11]	auto[1]	auto[0]	auto[0]	8374	1			T2	37		T24	86		T6	36
fifo_depth[11]	auto[1]	auto[0]	auto[1]	8545	1			T2	68		T4	3		T24	90
fifo_depth[11]	auto[1]	auto[1]	auto[0]	8363	1			T2	2		T4	1		T24	137
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8953	1			T2	77		T4	1		T24	96
fifo_depth[12]	auto[0]	auto[0]	auto[0]	6738	1			T6	59		T20	5		T15	319
fifo_depth[12]	auto[0]	auto[0]	auto[1]	4328	1			T4	2		T6	17		T15	124
fifo_depth[12]	auto[0]	auto[1]	auto[0]	8880	1			T6	19		T55	61		T15	92
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5995	1			T6	14		T20	8		T15	713
fifo_depth[12]	auto[1]	auto[0]	auto[0]	7133	1			T2	15		T24	28		T6	20
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7504	1			T2	29		T24	39		T6	39
fifo_depth[12]	auto[1]	auto[1]	auto[0]	8470	1			T2	1		T4	1		T24	65
fifo_depth[12]	auto[1]	auto[1]	auto[1]	7607	1			T2	33		T24	43		T6	29
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3665	1			T6	44		T20	2		T15	99
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2459	1			T6	25		T15	60		T44	1
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4335	1			T6	5		T55	22		T15	32
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3593	1			T6	4		T20	4		T15	50
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4133	1			T2	12		T24	23		T6	7
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4902	1			T2	21		T24	19		T6	20
fifo_depth[13]	auto[1]	auto[1]	auto[0]	4477	1			T2	2		T24	25		T6	4
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4475	1			T2	20		T24	26		T6	10
fifo_depth[14]	auto[0]	auto[0]	auto[0]	5491	1			T6	42		T20	2		T15	127
fifo_depth[14]	auto[0]	auto[0]	auto[1]	3505	1			T6	8		T15	108		T21	78
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5088	1			T6	6		T55	9		T15	47
fifo_depth[14]	auto[0]	auto[1]	auto[1]	4504	1			T6	5		T20	1		T15	59
fifo_depth[14]	auto[1]	auto[0]	auto[0]	4222	1			T2	1		T24	11		T6	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	5585	1			T2	8		T24	7		T6	5
fifo_depth[14]	auto[1]	auto[1]	auto[0]	6212	1			T24	9		T6	1		T58	6
fifo_depth[14]	auto[1]	auto[1]	auto[1]	5783	1			T2	2		T24	5		T6	7
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3755	1			T6	4		T20	1		T15	81
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2496	1			T6	36		T15	53		T21	80
fifo_depth[15]	auto[0]	auto[1]	auto[0]	2976	1			T55	3		T15	43		T21	15
fifo_depth[15]	auto[0]	auto[1]	auto[1]	3531	1			T15	62		T99	126		T21	58
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3273	1			T24	5		T6	1		T58	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	4120	1			T2	4		T24	2		T6	4
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3926	1			T24	2		T15	133		T78	2
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3650	1			T2	4		T24	4		T6	3
fifo_depth[16]	auto[0]	auto[0]	auto[0]	11642	1			T6	6		T15	378		T99	113
fifo_depth[16]	auto[0]	auto[0]	auto[1]	9713	1			T6	25		T15	564		T21	43
fifo_depth[16]	auto[0]	auto[1]	auto[0]	9371	1			T55	1		T15	842		T21	287
fifo_depth[16]	auto[0]	auto[1]	auto[1]	13569	1			T15	774		T99	85		T21	42
fifo_depth[16]	auto[1]	auto[0]	auto[0]	11561	1			T24	1		T6	1		T15	194
fifo_depth[16]	auto[1]	auto[0]	auto[1]	10810	1			T2	3		T6	1		T58	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	12718	1			T24	1		T6	2		T15	924
fifo_depth[16]	auto[1]	auto[1]	auto[1]	12229	1			T24	2		T6	1		T15	444