Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13056330	1			T1	29617		T2	12055		T3	344
all_pins[1]	13056330	1			T1	29617		T2	12055		T3	344
all_pins[2]	13056330	1			T1	29617		T2	12055		T3	344

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	37064964	1			T1	77488		T2	36121		T3	978
values[0x1]	2104026	1			T1	11363		T2	44		T3	54
transitions[0x0=>0x1]	2103867	1			T1	11363		T2	44		T3	54
transitions[0x1=>0x0]	2103877	1			T1	11363		T2	44		T3	54

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13011060	1			T1	29599		T2	12011		T3	290
all_pins[0]	values[0x1]	45270	1			T1	18		T2	44		T3	54
all_pins[0]	transitions[0x0=>0x1]	45212	1			T1	18		T2	44		T3	54
all_pins[0]	transitions[0x1=>0x0]	2058154	1			T1	11345		T4	22792		T6	15739
all_pins[1]	values[0x0]	13055776	1			T1	29617		T2	12055		T3	344
all_pins[1]	values[0x1]	554	1			T6	35		T13	2		T15	3
all_pins[1]	transitions[0x0=>0x1]	509	1			T6	34		T13	2		T15	3
all_pins[1]	transitions[0x1=>0x0]	45225	1			T1	18		T2	44		T3	54
all_pins[2]	values[0x0]	10998128	1			T1	18272		T2	12055		T3	344
all_pins[2]	values[0x1]	2058202	1			T1	11345		T4	22792		T6	15740
all_pins[2]	transitions[0x0=>0x1]	2058146	1			T1	11345		T4	22792		T6	15740
all_pins[2]	transitions[0x1=>0x0]	498	1			T6	35		T13	2		T15	3