Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	933	1			T4	10		T6	10		T13	18
all_values[1]	933	1			T4	10		T6	10		T13	18
all_values[2]	933	1			T4	10		T6	10		T13	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1461

1

T4

20

T6

13

T13

36

auto[1]

1338

1

T4

10

T6

17

T13

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

982

1

T4

8

T6

11

T13

26

auto[1]

1817

1

T4

22

T6

19

T13

28

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1582

1

T4

14

T6

19

T13

38

auto[1]

1217

1

T4

16

T6

11

T13

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

179

1

T4

1

T6

1

T13

7

all_values[0]

auto[0]

auto[0]

auto[1]

93

1

T4

2

T6

3

T13

3

all_values[0]

auto[0]

auto[1]

auto[0]

163

1

T6

1

T15

2

T21

1

all_values[0]

auto[0]

auto[1]

auto[1]

96

1

T6

1

T13

2

T21

1

all_values[0]

auto[1]

auto[0]

auto[1]

218

1

T4

4

T6

3

T13

4

all_values[0]

auto[1]

auto[1]

auto[1]

184

1

T4

3

T6

1

T13

2

all_values[1]

auto[0]

auto[0]

auto[0]

150

1

T4

3

T6

2

T13

5

all_values[1]

auto[0]

auto[0]

auto[1]

123

1

T4

2

T6

1

T13

3

all_values[1]

auto[0]

auto[1]

auto[0]

136

1

T4

2

T6

2

T13

3

all_values[1]

auto[0]

auto[1]

auto[1]

113

1

T6

2

T13

1

T15

2

all_values[1]

auto[1]

auto[0]

auto[1]

214

1

T4

2

T6

1

T13

5

all_values[1]

auto[1]

auto[1]

auto[1]

197

1

T4

1

T6

2

T13

1

all_values[2]

auto[0]

auto[0]

auto[0]

185

1

T4

1

T6

1

T13

4

all_values[2]

auto[0]

auto[0]

auto[1]

96

1

T4

2

T13

2

T15

2

all_values[2]

auto[0]

auto[1]

auto[0]

169

1

T4

1

T6

4

T13

7

all_values[2]

auto[0]

auto[1]

auto[1]

79

1

T6

1

T13

1

T69

1

all_values[2]

auto[1]

auto[0]

auto[1]

203

1

T4

3

T6

1

T13

3

all_values[2]

auto[1]

auto[1]

auto[1]

201

1

T4

3

T6

3

T13

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal