Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.94 92.47 85.27 100.00 76.32 85.98 99.49 69.08


Total test records in report: 735
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T535 /workspace/coverage/default/15.hmac_test_sha_vectors.2509921201 Apr 21 01:39:57 PM PDT 24 Apr 21 01:47:38 PM PDT 24 57158457306 ps
T536 /workspace/coverage/default/32.hmac_error.1855308208 Apr 21 01:42:34 PM PDT 24 Apr 21 01:43:30 PM PDT 24 1636958731 ps
T537 /workspace/coverage/default/49.hmac_error.3875880606 Apr 21 01:45:21 PM PDT 24 Apr 21 01:47:42 PM PDT 24 36195853172 ps
T538 /workspace/coverage/default/36.hmac_datapath_stress.3959405847 Apr 21 01:43:04 PM PDT 24 Apr 21 01:45:08 PM PDT 24 4423151068 ps
T539 /workspace/coverage/default/37.hmac_datapath_stress.3097037357 Apr 21 01:43:16 PM PDT 24 Apr 21 01:43:48 PM PDT 24 562874357 ps
T540 /workspace/coverage/default/7.hmac_test_hmac_vectors.1561425364 Apr 21 01:39:13 PM PDT 24 Apr 21 01:39:15 PM PDT 24 60955370 ps
T541 /workspace/coverage/default/2.hmac_error.2794378059 Apr 21 01:38:54 PM PDT 24 Apr 21 01:39:56 PM PDT 24 98234947300 ps
T542 /workspace/coverage/default/22.hmac_alert_test.2331724963 Apr 21 01:41:05 PM PDT 24 Apr 21 01:41:06 PM PDT 24 22371584 ps
T543 /workspace/coverage/default/49.hmac_burst_wr.2178654068 Apr 21 01:45:22 PM PDT 24 Apr 21 01:45:52 PM PDT 24 6722962692 ps
T544 /workspace/coverage/default/19.hmac_wipe_secret.191841657 Apr 21 01:40:30 PM PDT 24 Apr 21 01:40:59 PM PDT 24 8838868486 ps
T545 /workspace/coverage/default/14.hmac_burst_wr.2559059223 Apr 21 01:39:52 PM PDT 24 Apr 21 01:40:45 PM PDT 24 1104507349 ps
T546 /workspace/coverage/default/25.hmac_wipe_secret.3207283315 Apr 21 01:41:23 PM PDT 24 Apr 21 01:41:42 PM PDT 24 3332656318 ps
T547 /workspace/coverage/default/22.hmac_error.1787197611 Apr 21 01:40:56 PM PDT 24 Apr 21 01:42:01 PM PDT 24 3843639759 ps
T548 /workspace/coverage/default/35.hmac_long_msg.3666771942 Apr 21 01:42:49 PM PDT 24 Apr 21 01:43:20 PM PDT 24 7467645316 ps
T549 /workspace/coverage/default/17.hmac_long_msg.1172525709 Apr 21 01:40:13 PM PDT 24 Apr 21 01:41:32 PM PDT 24 4835582516 ps
T550 /workspace/coverage/default/29.hmac_error.2079989229 Apr 21 01:42:02 PM PDT 24 Apr 21 01:42:47 PM PDT 24 852018351 ps
T551 /workspace/coverage/default/21.hmac_test_hmac_vectors.187225833 Apr 21 01:40:48 PM PDT 24 Apr 21 01:40:50 PM PDT 24 238318157 ps
T552 /workspace/coverage/default/47.hmac_test_hmac_vectors.2975799214 Apr 21 01:44:59 PM PDT 24 Apr 21 01:45:01 PM PDT 24 61673542 ps
T553 /workspace/coverage/default/15.hmac_datapath_stress.1706978571 Apr 21 01:39:55 PM PDT 24 Apr 21 01:41:01 PM PDT 24 12357157204 ps
T554 /workspace/coverage/default/15.hmac_long_msg.1865902918 Apr 21 01:39:54 PM PDT 24 Apr 21 01:40:11 PM PDT 24 2811696128 ps
T555 /workspace/coverage/default/29.hmac_test_hmac_vectors.651835135 Apr 21 01:42:05 PM PDT 24 Apr 21 01:42:07 PM PDT 24 42422440 ps
T556 /workspace/coverage/default/45.hmac_burst_wr.2945879379 Apr 21 01:44:43 PM PDT 24 Apr 21 01:44:54 PM PDT 24 1111574839 ps
T557 /workspace/coverage/default/19.hmac_stress_all.710113546 Apr 21 01:40:30 PM PDT 24 Apr 21 01:54:54 PM PDT 24 246039458655 ps
T558 /workspace/coverage/default/15.hmac_wipe_secret.3122843917 Apr 21 01:39:58 PM PDT 24 Apr 21 01:41:29 PM PDT 24 92297215414 ps
T559 /workspace/coverage/default/23.hmac_test_sha_vectors.2666618552 Apr 21 01:41:06 PM PDT 24 Apr 21 01:49:14 PM PDT 24 81562065205 ps
T560 /workspace/coverage/default/7.hmac_test_sha_vectors.3800878172 Apr 21 01:39:11 PM PDT 24 Apr 21 01:46:40 PM PDT 24 112123312288 ps
T561 /workspace/coverage/default/38.hmac_datapath_stress.2553183160 Apr 21 01:43:23 PM PDT 24 Apr 21 01:45:15 PM PDT 24 1961360770 ps
T562 /workspace/coverage/default/38.hmac_stress_all.1378812353 Apr 21 01:43:24 PM PDT 24 Apr 21 01:44:29 PM PDT 24 2438008953 ps
T563 /workspace/coverage/default/41.hmac_test_sha_vectors.179192325 Apr 21 01:43:58 PM PDT 24 Apr 21 01:50:55 PM PDT 24 9540464658 ps
T564 /workspace/coverage/default/46.hmac_long_msg.287061269 Apr 21 01:44:43 PM PDT 24 Apr 21 01:45:11 PM PDT 24 1999211731 ps
T11 /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4238452145 Apr 21 01:39:13 PM PDT 24 Apr 21 01:58:58 PM PDT 24 68422811624 ps
T565 /workspace/coverage/default/33.hmac_stress_all.198482414 Apr 21 01:42:45 PM PDT 24 Apr 21 01:44:03 PM PDT 24 27278863810 ps
T566 /workspace/coverage/default/42.hmac_error.1506421921 Apr 21 01:44:05 PM PDT 24 Apr 21 01:44:26 PM PDT 24 402864041 ps
T567 /workspace/coverage/default/41.hmac_back_pressure.2379367216 Apr 21 01:43:58 PM PDT 24 Apr 21 01:44:12 PM PDT 24 411240925 ps
T568 /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.3554864385 Apr 21 01:45:36 PM PDT 24 Apr 21 02:07:23 PM PDT 24 145772434495 ps
T569 /workspace/coverage/default/10.hmac_error.2587386513 Apr 21 01:39:23 PM PDT 24 Apr 21 01:40:49 PM PDT 24 10621024044 ps
T570 /workspace/coverage/default/43.hmac_stress_all.2527788525 Apr 21 01:44:26 PM PDT 24 Apr 21 01:59:25 PM PDT 24 66169735876 ps
T571 /workspace/coverage/default/24.hmac_stress_all.775955271 Apr 21 01:41:21 PM PDT 24 Apr 21 01:46:16 PM PDT 24 252145149163 ps
T572 /workspace/coverage/default/11.hmac_back_pressure.3656852164 Apr 21 01:39:32 PM PDT 24 Apr 21 01:40:15 PM PDT 24 1330683442 ps
T573 /workspace/coverage/default/49.hmac_wipe_secret.3571001169 Apr 21 01:45:22 PM PDT 24 Apr 21 01:45:37 PM PDT 24 3889459933 ps
T574 /workspace/coverage/default/35.hmac_test_hmac_vectors.1611823841 Apr 21 01:43:00 PM PDT 24 Apr 21 01:43:02 PM PDT 24 38531670 ps
T575 /workspace/coverage/default/26.hmac_stress_all.668131151 Apr 21 01:41:33 PM PDT 24 Apr 21 01:51:38 PM PDT 24 98143452522 ps
T576 /workspace/coverage/default/5.hmac_datapath_stress.1022410967 Apr 21 01:39:07 PM PDT 24 Apr 21 01:40:48 PM PDT 24 7046597914 ps
T577 /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.454902630 Apr 21 01:46:08 PM PDT 24 Apr 21 02:04:21 PM PDT 24 81473402238 ps
T578 /workspace/coverage/default/18.hmac_datapath_stress.2829825073 Apr 21 01:40:17 PM PDT 24 Apr 21 01:40:23 PM PDT 24 185512646 ps
T579 /workspace/coverage/default/34.hmac_alert_test.138144857 Apr 21 01:42:48 PM PDT 24 Apr 21 01:42:49 PM PDT 24 17950969 ps
T580 /workspace/coverage/default/40.hmac_long_msg.3778620237 Apr 21 01:43:45 PM PDT 24 Apr 21 01:43:55 PM PDT 24 2071633462 ps
T581 /workspace/coverage/default/36.hmac_test_sha_vectors.3798074835 Apr 21 01:43:12 PM PDT 24 Apr 21 01:51:13 PM PDT 24 115875507240 ps
T582 /workspace/coverage/default/17.hmac_smoke.1321878782 Apr 21 01:40:10 PM PDT 24 Apr 21 01:40:12 PM PDT 24 1173971603 ps
T583 /workspace/coverage/default/38.hmac_test_sha_vectors.3334437619 Apr 21 01:43:26 PM PDT 24 Apr 21 01:51:42 PM PDT 24 82009170547 ps
T584 /workspace/coverage/default/14.hmac_test_hmac_vectors.3689467439 Apr 21 01:39:48 PM PDT 24 Apr 21 01:39:50 PM PDT 24 141800085 ps
T585 /workspace/coverage/default/23.hmac_test_hmac_vectors.3521404475 Apr 21 01:41:05 PM PDT 24 Apr 21 01:41:06 PM PDT 24 34901520 ps
T586 /workspace/coverage/default/4.hmac_back_pressure.1340575152 Apr 21 01:39:00 PM PDT 24 Apr 21 01:39:26 PM PDT 24 1767179061 ps
T587 /workspace/coverage/default/38.hmac_error.182587866 Apr 21 01:43:25 PM PDT 24 Apr 21 01:45:09 PM PDT 24 23707734798 ps
T588 /workspace/coverage/default/0.hmac_datapath_stress.1587510252 Apr 21 01:38:55 PM PDT 24 Apr 21 01:38:57 PM PDT 24 16900540 ps
T589 /workspace/coverage/default/16.hmac_burst_wr.3678582506 Apr 21 01:40:00 PM PDT 24 Apr 21 01:40:14 PM PDT 24 742386578 ps
T590 /workspace/coverage/default/13.hmac_back_pressure.3135571998 Apr 21 01:39:40 PM PDT 24 Apr 21 01:40:21 PM PDT 24 2281115644 ps
T591 /workspace/coverage/default/20.hmac_long_msg.205620799 Apr 21 01:40:36 PM PDT 24 Apr 21 01:41:00 PM PDT 24 439176404 ps
T592 /workspace/coverage/default/16.hmac_back_pressure.1730476586 Apr 21 01:40:00 PM PDT 24 Apr 21 01:40:57 PM PDT 24 5891155554 ps
T593 /workspace/coverage/default/39.hmac_back_pressure.3872139134 Apr 21 01:43:30 PM PDT 24 Apr 21 01:43:52 PM PDT 24 2027166393 ps
T594 /workspace/coverage/default/4.hmac_burst_wr.1152935392 Apr 21 01:39:01 PM PDT 24 Apr 21 01:39:11 PM PDT 24 193374631 ps
T595 /workspace/coverage/default/3.hmac_smoke.476921161 Apr 21 01:38:56 PM PDT 24 Apr 21 01:38:58 PM PDT 24 97619665 ps
T596 /workspace/coverage/default/48.hmac_test_hmac_vectors.1975693392 Apr 21 01:45:13 PM PDT 24 Apr 21 01:45:14 PM PDT 24 85868231 ps
T597 /workspace/coverage/default/39.hmac_wipe_secret.2413320560 Apr 21 01:43:34 PM PDT 24 Apr 21 01:44:57 PM PDT 24 4338064577 ps
T598 /workspace/coverage/default/25.hmac_back_pressure.4119846518 Apr 21 01:41:25 PM PDT 24 Apr 21 01:41:56 PM PDT 24 4221677473 ps
T599 /workspace/coverage/default/18.hmac_back_pressure.3400010808 Apr 21 01:40:17 PM PDT 24 Apr 21 01:40:48 PM PDT 24 3468179867 ps
T600 /workspace/coverage/default/13.hmac_test_hmac_vectors.1667376994 Apr 21 01:39:41 PM PDT 24 Apr 21 01:39:42 PM PDT 24 49643540 ps
T601 /workspace/coverage/default/2.hmac_alert_test.1523928281 Apr 21 01:38:58 PM PDT 24 Apr 21 01:38:58 PM PDT 24 13395052 ps
T602 /workspace/coverage/default/14.hmac_test_sha_vectors.2213754192 Apr 21 01:39:48 PM PDT 24 Apr 21 01:47:45 PM PDT 24 166565248552 ps
T603 /workspace/coverage/default/49.hmac_stress_all.422530517 Apr 21 01:45:25 PM PDT 24 Apr 21 01:45:32 PM PDT 24 319271547 ps
T60 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2436411101 Apr 21 12:53:45 PM PDT 24 Apr 21 12:53:49 PM PDT 24 503977924 ps
T63 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1815899939 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:53 PM PDT 24 88167337 ps
T64 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4248833686 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:39 PM PDT 24 180238806 ps
T604 /workspace/coverage/cover_reg_top/32.hmac_intr_test.137681363 Apr 21 12:53:52 PM PDT 24 Apr 21 12:53:54 PM PDT 24 37170222 ps
T605 /workspace/coverage/cover_reg_top/35.hmac_intr_test.369964505 Apr 21 12:53:50 PM PDT 24 Apr 21 12:53:51 PM PDT 24 20958253 ps
T606 /workspace/coverage/cover_reg_top/17.hmac_intr_test.284046896 Apr 21 12:53:47 PM PDT 24 Apr 21 12:53:48 PM PDT 24 17155316 ps
T83 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3652365675 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:42 PM PDT 24 630550393 ps
T607 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3090896843 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:48 PM PDT 24 67150291 ps
T608 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2929517055 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:53 PM PDT 24 26906812 ps
T609 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1681070670 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:53 PM PDT 24 26380701 ps
T610 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3710908383 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:48 PM PDT 24 11383549 ps
T611 /workspace/coverage/cover_reg_top/34.hmac_intr_test.358155846 Apr 21 12:53:52 PM PDT 24 Apr 21 12:53:53 PM PDT 24 41372068 ps
T84 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.212496866 Apr 21 12:53:29 PM PDT 24 Apr 21 12:53:38 PM PDT 24 2632009452 ps
T612 /workspace/coverage/cover_reg_top/8.hmac_intr_test.4141096325 Apr 21 12:53:41 PM PDT 24 Apr 21 12:53:42 PM PDT 24 67090595 ps
T613 /workspace/coverage/cover_reg_top/23.hmac_intr_test.295104606 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:53 PM PDT 24 12265799 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.938293887 Apr 21 12:53:45 PM PDT 24 Apr 21 12:53:46 PM PDT 24 89943652 ps
T85 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2598657255 Apr 21 12:53:31 PM PDT 24 Apr 21 12:53:33 PM PDT 24 19485455 ps
T61 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1715065744 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:53 PM PDT 24 756508103 ps
T615 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3394866509 Apr 21 12:53:54 PM PDT 24 Apr 21 12:53:56 PM PDT 24 15278152 ps
T616 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.227555783 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:52 PM PDT 24 154747350 ps
T617 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2102186290 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:46 PM PDT 24 13497600 ps
T62 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2372655632 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:49 PM PDT 24 82429314 ps
T86 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.960159036 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:47 PM PDT 24 53569445 ps
T618 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2674226814 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:44 PM PDT 24 38661333 ps
T619 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1778241325 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:50 PM PDT 24 21608402 ps
T620 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1636917710 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:51 PM PDT 24 19375416 ps
T621 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.36677123 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:50 PM PDT 24 180092229 ps
T622 /workspace/coverage/cover_reg_top/45.hmac_intr_test.936054340 Apr 21 12:53:52 PM PDT 24 Apr 21 12:53:54 PM PDT 24 24442954 ps
T623 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2311533526 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:48 PM PDT 24 32230809 ps
T87 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3405397978 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:53 PM PDT 24 40199741 ps
T100 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1252794692 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:45 PM PDT 24 1753427965 ps
T624 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1889853409 Apr 21 12:53:37 PM PDT 24 Apr 21 12:53:38 PM PDT 24 18418061 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3712695768 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:37 PM PDT 24 35138703 ps
T626 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2517024634 Apr 21 12:53:40 PM PDT 24 Apr 21 12:53:42 PM PDT 24 97150486 ps
T627 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1584766225 Apr 21 12:53:32 PM PDT 24 Apr 21 12:53:37 PM PDT 24 304823035 ps
T628 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3509235094 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:39 PM PDT 24 1027251134 ps
T629 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1736033570 Apr 21 12:53:31 PM PDT 24 Apr 21 12:53:35 PM PDT 24 295453141 ps
T630 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1276540557 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:47 PM PDT 24 69714873 ps
T631 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.201145654 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:52 PM PDT 24 45701595 ps
T632 /workspace/coverage/cover_reg_top/13.hmac_intr_test.832887582 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:46 PM PDT 24 29272875 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3733367486 Apr 21 12:53:31 PM PDT 24 Apr 21 12:53:31 PM PDT 24 127046144 ps
T104 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3541670909 Apr 21 12:54:02 PM PDT 24 Apr 21 12:54:05 PM PDT 24 195848767 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4225291447 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:42 PM PDT 24 1038299376 ps
T88 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2083535595 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:39 PM PDT 24 83641043 ps
T635 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1045524491 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:46 PM PDT 24 25796997 ps
T636 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3815927785 Apr 21 12:53:47 PM PDT 24 Apr 21 12:53:50 PM PDT 24 34337866 ps
T637 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2583015256 Apr 21 12:54:01 PM PDT 24 Apr 21 12:54:02 PM PDT 24 50727108 ps
T638 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2888308452 Apr 21 12:53:44 PM PDT 24 Apr 21 01:00:22 PM PDT 24 153064749684 ps
T639 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4115951721 Apr 21 12:53:41 PM PDT 24 Apr 21 12:53:44 PM PDT 24 91173291 ps
T640 /workspace/coverage/cover_reg_top/31.hmac_intr_test.838813689 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:50 PM PDT 24 21476844 ps
T65 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3688263143 Apr 21 12:53:32 PM PDT 24 Apr 21 12:53:37 PM PDT 24 253466648 ps
T641 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2035015097 Apr 21 12:53:43 PM PDT 24 Apr 21 12:53:45 PM PDT 24 24879658 ps
T642 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3448284550 Apr 21 12:53:45 PM PDT 24 Apr 21 12:53:48 PM PDT 24 111190846 ps
T643 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3532258849 Apr 21 12:53:47 PM PDT 24 Apr 21 12:53:49 PM PDT 24 38009221 ps
T644 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1510232700 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:43 PM PDT 24 24749077 ps
T645 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1271688260 Apr 21 12:53:36 PM PDT 24 Apr 21 12:53:37 PM PDT 24 37270120 ps
T89 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4171999259 Apr 21 12:53:31 PM PDT 24 Apr 21 12:53:35 PM PDT 24 160175820 ps
T90 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3402143369 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:56 PM PDT 24 6257294759 ps
T646 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4271723179 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:50 PM PDT 24 20653920 ps
T647 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1410848860 Apr 21 12:53:45 PM PDT 24 Apr 21 12:53:46 PM PDT 24 29304868 ps
T648 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3701238324 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:52 PM PDT 24 158033417 ps
T105 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1273006865 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:52 PM PDT 24 187642492 ps
T649 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3328802285 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:36 PM PDT 24 213582096 ps
T650 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2418868002 Apr 21 12:53:47 PM PDT 24 Apr 21 12:53:49 PM PDT 24 269702922 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1838356895 Apr 21 12:53:33 PM PDT 24 Apr 21 12:53:34 PM PDT 24 25056049 ps
T651 /workspace/coverage/cover_reg_top/37.hmac_intr_test.685927602 Apr 21 12:53:50 PM PDT 24 Apr 21 12:53:51 PM PDT 24 31647425 ps
T652 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2046856 Apr 21 12:53:41 PM PDT 24 Apr 21 12:53:43 PM PDT 24 243709579 ps
T92 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3685874860 Apr 21 12:53:39 PM PDT 24 Apr 21 12:53:41 PM PDT 24 133931837 ps
T653 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.623122174 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:53 PM PDT 24 164956860 ps
T654 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1799887941 Apr 21 12:53:40 PM PDT 24 Apr 21 12:53:41 PM PDT 24 22070531 ps
T655 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.816779887 Apr 21 12:53:45 PM PDT 24 Apr 21 12:53:49 PM PDT 24 407703596 ps
T656 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.975114827 Apr 21 12:53:41 PM PDT 24 Apr 21 12:53:47 PM PDT 24 135197493 ps
T657 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.191297712 Apr 21 12:53:43 PM PDT 24 Apr 21 12:53:44 PM PDT 24 225933198 ps
T93 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.121321926 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:47 PM PDT 24 47113696 ps
T658 /workspace/coverage/cover_reg_top/11.hmac_intr_test.4075160941 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:45 PM PDT 24 129219721 ps
T659 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.532759550 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:36 PM PDT 24 30981661 ps
T660 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2845665710 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:40 PM PDT 24 123050973 ps
T661 /workspace/coverage/cover_reg_top/6.hmac_intr_test.282806984 Apr 21 12:53:41 PM PDT 24 Apr 21 12:53:42 PM PDT 24 30262682 ps
T109 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.405211844 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:50 PM PDT 24 104376283 ps
T662 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3686899619 Apr 21 12:53:37 PM PDT 24 Apr 21 12:53:39 PM PDT 24 232164892 ps
T663 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1214223641 Apr 21 12:53:37 PM PDT 24 Apr 21 12:53:40 PM PDT 24 41335914 ps
T664 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2052949047 Apr 21 12:53:33 PM PDT 24 Apr 21 12:53:34 PM PDT 24 15032952 ps
T665 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1031828689 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:48 PM PDT 24 70204886 ps
T666 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1482290136 Apr 21 12:53:32 PM PDT 24 Apr 21 12:53:35 PM PDT 24 69655627 ps
T667 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3675843788 Apr 21 12:53:41 PM PDT 24 Apr 21 12:53:43 PM PDT 24 16381346 ps
T668 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3333545000 Apr 21 12:53:50 PM PDT 24 Apr 21 12:53:52 PM PDT 24 78962036 ps
T669 /workspace/coverage/cover_reg_top/33.hmac_intr_test.783378881 Apr 21 12:53:50 PM PDT 24 Apr 21 12:53:51 PM PDT 24 14738400 ps
T670 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.214512022 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:51 PM PDT 24 80125676 ps
T106 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1674191725 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:48 PM PDT 24 590973822 ps
T671 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3843360604 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:47 PM PDT 24 24175775 ps
T672 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3122761422 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:47 PM PDT 24 404978880 ps
T673 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3258994357 Apr 21 12:53:52 PM PDT 24 Apr 21 12:53:53 PM PDT 24 77429644 ps
T101 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.352541970 Apr 21 12:53:32 PM PDT 24 Apr 21 12:53:36 PM PDT 24 426216217 ps
T94 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4101890669 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:46 PM PDT 24 380947925 ps
T674 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2161398124 Apr 21 12:53:31 PM PDT 24 Apr 21 12:53:32 PM PDT 24 35660974 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.501934477 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:36 PM PDT 24 26246530 ps
T675 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1697381968 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:52 PM PDT 24 91467734 ps
T676 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2384897331 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:50 PM PDT 24 607505456 ps
T677 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2358998351 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:47 PM PDT 24 2303830716 ps
T678 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.473413522 Apr 21 12:53:40 PM PDT 24 Apr 21 12:53:43 PM PDT 24 449666387 ps
T679 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3022891451 Apr 21 12:53:40 PM PDT 24 Apr 21 12:53:47 PM PDT 24 792568940 ps
T680 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2010333752 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:40 PM PDT 24 366197863 ps
T681 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3788536199 Apr 21 12:53:55 PM PDT 24 Apr 21 12:53:56 PM PDT 24 37445054 ps
T682 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1480311675 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:37 PM PDT 24 93429731 ps
T683 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2727079930 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:45 PM PDT 24 195607632 ps
T684 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3005784529 Apr 21 12:53:30 PM PDT 24 Apr 21 12:53:40 PM PDT 24 221531847 ps
T685 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3312769639 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:44 PM PDT 24 145542786 ps
T686 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1507033395 Apr 21 12:53:47 PM PDT 24 Apr 21 12:53:48 PM PDT 24 28149472 ps
T687 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2516290493 Apr 21 12:53:55 PM PDT 24 Apr 21 12:53:56 PM PDT 24 53552267 ps
T688 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.769555011 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:50 PM PDT 24 52009874 ps
T689 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2608208458 Apr 21 12:53:46 PM PDT 24 Apr 21 12:53:49 PM PDT 24 199298722 ps
T96 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.762188712 Apr 21 12:53:57 PM PDT 24 Apr 21 12:53:59 PM PDT 24 32741071 ps
T102 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.787013639 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:38 PM PDT 24 90354486 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1946256499 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:39 PM PDT 24 232500525 ps
T690 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.517597043 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:48 PM PDT 24 237028480 ps
T691 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2040501599 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:36 PM PDT 24 140433421 ps
T692 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3380965144 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:55 PM PDT 24 50266900 ps
T107 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2026114526 Apr 21 12:53:39 PM PDT 24 Apr 21 12:53:44 PM PDT 24 963085550 ps
T693 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3802108649 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:49 PM PDT 24 14831301 ps
T694 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1592627550 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:35 PM PDT 24 20329353 ps
T695 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.96029048 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:37 PM PDT 24 81774241 ps
T696 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3654680835 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:50 PM PDT 24 25231186 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2418505825 Apr 21 12:53:35 PM PDT 24 Apr 21 12:53:38 PM PDT 24 1108717391 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2979128864 Apr 21 12:53:33 PM PDT 24 Apr 21 12:53:34 PM PDT 24 57717557 ps
T697 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2963192856 Apr 21 12:53:36 PM PDT 24 Apr 21 12:53:37 PM PDT 24 18642518 ps
T698 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.75781286 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:55 PM PDT 24 1851054662 ps
T699 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2427556432 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:51 PM PDT 24 64554334 ps
T700 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2282916679 Apr 21 12:53:57 PM PDT 24 Apr 21 12:53:57 PM PDT 24 42051090 ps
T701 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3730938897 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:42 PM PDT 24 349152158 ps
T702 /workspace/coverage/cover_reg_top/16.hmac_intr_test.872339284 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:52 PM PDT 24 28019112 ps
T703 /workspace/coverage/cover_reg_top/9.hmac_intr_test.223992360 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:51 PM PDT 24 88322513 ps
T704 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1505570321 Apr 21 12:53:50 PM PDT 24 Apr 21 12:53:51 PM PDT 24 54385623 ps
T705 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1056601058 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:46 PM PDT 24 43831145 ps
T98 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3986428724 Apr 21 12:53:45 PM PDT 24 Apr 21 12:53:47 PM PDT 24 19309808 ps
T706 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4069680525 Apr 21 12:53:59 PM PDT 24 Apr 21 12:54:02 PM PDT 24 418146207 ps
T707 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3327602499 Apr 21 12:53:37 PM PDT 24 Apr 21 12:53:39 PM PDT 24 99257677 ps
T708 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2346313831 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:44 PM PDT 24 176128044 ps
T709 /workspace/coverage/cover_reg_top/47.hmac_intr_test.119872416 Apr 21 12:53:57 PM PDT 24 Apr 21 12:53:58 PM PDT 24 45263190 ps
T710 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1185924370 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:50 PM PDT 24 28300599 ps
T711 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1278185326 Apr 21 12:53:33 PM PDT 24 Apr 21 12:53:35 PM PDT 24 95168730 ps
T712 /workspace/coverage/cover_reg_top/5.hmac_intr_test.4150659571 Apr 21 12:53:39 PM PDT 24 Apr 21 12:53:40 PM PDT 24 13260093 ps
T713 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2135678153 Apr 21 12:53:40 PM PDT 24 Apr 21 12:53:42 PM PDT 24 169754383 ps
T714 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1814523434 Apr 21 12:53:43 PM PDT 24 Apr 21 12:53:45 PM PDT 24 85382687 ps
T715 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3794705092 Apr 21 12:53:55 PM PDT 24 Apr 21 12:53:56 PM PDT 24 50513964 ps
T716 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3263103473 Apr 21 12:53:32 PM PDT 24 Apr 21 12:53:33 PM PDT 24 33327745 ps
T717 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4164364607 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:45 PM PDT 24 179656826 ps
T718 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1203100129 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:43 PM PDT 24 46074105 ps
T719 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3922447364 Apr 21 12:53:39 PM PDT 24 Apr 21 12:53:43 PM PDT 24 68970351 ps
T720 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1841755760 Apr 21 12:54:06 PM PDT 24 Apr 21 12:54:08 PM PDT 24 681925899 ps
T721 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3290061427 Apr 21 12:53:34 PM PDT 24 Apr 21 12:53:44 PM PDT 24 215028239 ps
T722 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3068520618 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:39 PM PDT 24 13361914 ps
T723 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.79229259 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:44 PM PDT 24 115324923 ps
T110 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.517793249 Apr 21 12:53:45 PM PDT 24 Apr 21 12:53:48 PM PDT 24 152281801 ps
T724 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.496009394 Apr 21 12:53:42 PM PDT 24 Apr 21 12:53:44 PM PDT 24 48235180 ps
T725 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3242651537 Apr 21 12:53:41 PM PDT 24 Apr 21 12:53:45 PM PDT 24 300899714 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_intr_test.40672055 Apr 21 12:53:31 PM PDT 24 Apr 21 12:53:32 PM PDT 24 45053468 ps
T727 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2856253637 Apr 21 12:53:59 PM PDT 24 Apr 21 12:54:00 PM PDT 24 88830874 ps
T728 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.462203403 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:46 PM PDT 24 165423734 ps
T729 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1651935439 Apr 21 12:53:38 PM PDT 24 Apr 21 12:53:43 PM PDT 24 136002399 ps
T730 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1693549422 Apr 21 12:53:44 PM PDT 24 Apr 21 12:53:48 PM PDT 24 386128397 ps
T731 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1732767651 Apr 21 12:54:00 PM PDT 24 Apr 21 12:54:01 PM PDT 24 14969291 ps
T732 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.664190756 Apr 21 12:54:02 PM PDT 24 Apr 21 12:54:04 PM PDT 24 55467432 ps
T733 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4155462181 Apr 21 12:53:49 PM PDT 24 Apr 21 12:53:50 PM PDT 24 57348762 ps
T734 /workspace/coverage/cover_reg_top/48.hmac_intr_test.694575177 Apr 21 12:53:48 PM PDT 24 Apr 21 12:53:50 PM PDT 24 56540971 ps
T735 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.768576969 Apr 21 12:53:51 PM PDT 24 Apr 21 12:53:56 PM PDT 24 236903456 ps

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.1827510625
Short name T6
Test name
Test status
Simulation time 9753787452 ps
CPU time 524.61 seconds
Started Apr 21 01:46:04 PM PDT 24
Finished Apr 21 01:54:49 PM PDT 24
Peak memory 245424 kb
Host smart-3d63e4bc-2fc8-4824-a9af-85b30d44fdb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827510625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.1827510625
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2136924395
Short name T13
Test name
Test status
Simulation time 83228193767 ps
CPU time 821.15 seconds
Started Apr 21 01:43:00 PM PDT 24
Finished Apr 21 01:56:41 PM PDT 24
Peak memory 207900 kb
Host smart-0e459f79-e954-436c-bfbd-8cc353c57e33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136924395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2136924395
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2727571061
Short name T27
Test name
Test status
Simulation time 99980187 ps
CPU time 0.95 seconds
Started Apr 21 01:38:50 PM PDT 24
Finished Apr 21 01:38:51 PM PDT 24
Peak memory 219268 kb
Host smart-1444a039-e94a-48c8-95b5-d36bd8782074
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727571061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2727571061
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2436411101
Short name T60
Test name
Test status
Simulation time 503977924 ps
CPU time 2.87 seconds
Started Apr 21 12:53:45 PM PDT 24
Finished Apr 21 12:53:49 PM PDT 24
Peak memory 199144 kb
Host smart-a61ce7b9-619f-46a1-9fc9-7034afc715d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436411101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2436411101
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.2975417461
Short name T8
Test name
Test status
Simulation time 29552463956 ps
CPU time 604.59 seconds
Started Apr 21 01:45:24 PM PDT 24
Finished Apr 21 01:55:29 PM PDT 24
Peak memory 237708 kb
Host smart-36ddda2b-d68d-431b-8a83-c89bad2578d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975417461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.2975417461
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_error.2642973014
Short name T1
Test name
Test status
Simulation time 15665501041 ps
CPU time 195.24 seconds
Started Apr 21 01:40:11 PM PDT 24
Finished Apr 21 01:43:27 PM PDT 24
Peak memory 199688 kb
Host smart-f6c9963f-b6ce-4902-946a-face794f5fc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642973014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2642973014
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.212496866
Short name T84
Test name
Test status
Simulation time 2632009452 ps
CPU time 8.67 seconds
Started Apr 21 12:53:29 PM PDT 24
Finished Apr 21 12:53:38 PM PDT 24
Peak memory 199252 kb
Host smart-b014ce93-a376-4610-9800-317a6a5c74d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212496866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.212496866
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.415322131
Short name T21
Test name
Test status
Simulation time 196111721987 ps
CPU time 1764.31 seconds
Started Apr 21 01:46:36 PM PDT 24
Finished Apr 21 02:16:00 PM PDT 24
Peak memory 248004 kb
Host smart-3a0bcfe2-319b-4113-9c00-615ea85e318e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415322131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.415322131
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3688263143
Short name T65
Test name
Test status
Simulation time 253466648 ps
CPU time 4.45 seconds
Started Apr 21 12:53:32 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 199224 kb
Host smart-6235851e-d735-44d1-84fe-e9a8cef8b233
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688263143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3688263143
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1070712354
Short name T147
Test name
Test status
Simulation time 21774033 ps
CPU time 0.58 seconds
Started Apr 21 01:39:27 PM PDT 24
Finished Apr 21 01:39:28 PM PDT 24
Peak memory 195296 kb
Host smart-98781216-2234-4c0d-8dc4-588f35d20f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070712354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1070712354
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_error.1747807407
Short name T202
Test name
Test status
Simulation time 2821599368 ps
CPU time 152.83 seconds
Started Apr 21 01:38:46 PM PDT 24
Finished Apr 21 01:41:19 PM PDT 24
Peak memory 199704 kb
Host smart-2202cb92-5f31-4cb4-9ee5-dd74cd3c72c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747807407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1747807407
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1715065744
Short name T61
Test name
Test status
Simulation time 756508103 ps
CPU time 1.74 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 199252 kb
Host smart-ff618800-5d99-4cb6-a2fd-ec46127c3f78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715065744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1715065744
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/6.hmac_error.4266604531
Short name T47
Test name
Test status
Simulation time 5563950634 ps
CPU time 94.5 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:40:48 PM PDT 24
Peak memory 199716 kb
Host smart-c86107fa-6052-4f01-a670-42e13d3a9dce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266604531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4266604531
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.3901524775
Short name T43
Test name
Test status
Simulation time 13984280797 ps
CPU time 208.43 seconds
Started Apr 21 01:46:16 PM PDT 24
Finished Apr 21 01:49:44 PM PDT 24
Peak memory 207964 kb
Host smart-78f7d6f5-7076-4171-9cf7-3054d73067d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901524775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.3901524775
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3005784529
Short name T684
Test name
Test status
Simulation time 221531847 ps
CPU time 10 seconds
Started Apr 21 12:53:30 PM PDT 24
Finished Apr 21 12:53:40 PM PDT 24
Peak memory 198288 kb
Host smart-34eac016-cf90-489b-8ce7-175200923497
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005784529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3005784529
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2598657255
Short name T85
Test name
Test status
Simulation time 19485455 ps
CPU time 0.87 seconds
Started Apr 21 12:53:31 PM PDT 24
Finished Apr 21 12:53:33 PM PDT 24
Peak memory 198388 kb
Host smart-83829164-af98-4004-a05b-ff9a1fcccdb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598657255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2598657255
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.532759550
Short name T659
Test name
Test status
Simulation time 30981661 ps
CPU time 1.69 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:36 PM PDT 24
Peak memory 199260 kb
Host smart-8de247ca-474b-4f75-b7f3-12e08b7fe2b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532759550 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.532759550
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2161398124
Short name T674
Test name
Test status
Simulation time 35660974 ps
CPU time 0.75 seconds
Started Apr 21 12:53:31 PM PDT 24
Finished Apr 21 12:53:32 PM PDT 24
Peak memory 196500 kb
Host smart-be3ef546-8be5-40c4-997a-f246ee4db408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161398124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2161398124
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.40672055
Short name T726
Test name
Test status
Simulation time 45053468 ps
CPU time 0.57 seconds
Started Apr 21 12:53:31 PM PDT 24
Finished Apr 21 12:53:32 PM PDT 24
Peak memory 193836 kb
Host smart-31aa5f33-ffee-4cb8-8ee7-0b2cf9953f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.40672055
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3263103473
Short name T716
Test name
Test status
Simulation time 33327745 ps
CPU time 1.59 seconds
Started Apr 21 12:53:32 PM PDT 24
Finished Apr 21 12:53:33 PM PDT 24
Peak memory 199144 kb
Host smart-cae7a404-9c33-4cac-bc54-8bb20deaf3f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263103473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3263103473
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2040501599
Short name T691
Test name
Test status
Simulation time 140433421 ps
CPU time 1.63 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:36 PM PDT 24
Peak memory 199240 kb
Host smart-a5302830-b2a5-4c03-a0eb-a75e3dda4315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040501599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2040501599
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4171999259
Short name T89
Test name
Test status
Simulation time 160175820 ps
CPU time 3.4 seconds
Started Apr 21 12:53:31 PM PDT 24
Finished Apr 21 12:53:35 PM PDT 24
Peak memory 198016 kb
Host smart-3a02d831-7486-4717-bf91-79da0fff148f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171999259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4171999259
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3290061427
Short name T721
Test name
Test status
Simulation time 215028239 ps
CPU time 9.41 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 198096 kb
Host smart-177e97ce-1400-4ffb-aad2-a08177a20eb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290061427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3290061427
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1838356895
Short name T91
Test name
Test status
Simulation time 25056049 ps
CPU time 0.72 seconds
Started Apr 21 12:53:33 PM PDT 24
Finished Apr 21 12:53:34 PM PDT 24
Peak memory 197064 kb
Host smart-130e6e2e-96b3-4843-b040-e5d3912252ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838356895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1838356895
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1482290136
Short name T666
Test name
Test status
Simulation time 69655627 ps
CPU time 2.53 seconds
Started Apr 21 12:53:32 PM PDT 24
Finished Apr 21 12:53:35 PM PDT 24
Peak memory 199268 kb
Host smart-a6a0be4e-a08d-421f-ad6f-5339e31f0008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482290136 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1482290136
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2979128864
Short name T97
Test name
Test status
Simulation time 57717557 ps
CPU time 0.7 seconds
Started Apr 21 12:53:33 PM PDT 24
Finished Apr 21 12:53:34 PM PDT 24
Peak memory 196580 kb
Host smart-54e311e4-5b33-4442-9cae-17d1559af0fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979128864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2979128864
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3733367486
Short name T633
Test name
Test status
Simulation time 127046144 ps
CPU time 0.6 seconds
Started Apr 21 12:53:31 PM PDT 24
Finished Apr 21 12:53:31 PM PDT 24
Peak memory 193904 kb
Host smart-802557d3-0775-4155-8699-57893cecfe68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733367486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3733367486
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1278185326
Short name T711
Test name
Test status
Simulation time 95168730 ps
CPU time 1.75 seconds
Started Apr 21 12:53:33 PM PDT 24
Finished Apr 21 12:53:35 PM PDT 24
Peak memory 198904 kb
Host smart-aca4ec38-4c13-4628-9491-688404e121b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278185326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1278185326
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1584766225
Short name T627
Test name
Test status
Simulation time 304823035 ps
CPU time 4.05 seconds
Started Apr 21 12:53:32 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 199204 kb
Host smart-217d23a4-c022-4c35-b8d3-1d26fbe30786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584766225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1584766225
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.787013639
Short name T102
Test name
Test status
Simulation time 90354486 ps
CPU time 2.97 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:38 PM PDT 24
Peak memory 199216 kb
Host smart-2a1a23ce-a358-443c-ac7f-a8ed802e0dda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787013639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.787013639
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3701238324
Short name T648
Test name
Test status
Simulation time 158033417 ps
CPU time 1.92 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:52 PM PDT 24
Peak memory 199124 kb
Host smart-9e34d0ee-54fd-459b-81bd-8d1e5d6c0a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701238324 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3701238324
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1185924370
Short name T710
Test name
Test status
Simulation time 28300599 ps
CPU time 0.77 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 198140 kb
Host smart-2efdb5ab-710b-4e71-9957-f747a2acc27e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185924370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1185924370
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3675843788
Short name T667
Test name
Test status
Simulation time 16381346 ps
CPU time 0.65 seconds
Started Apr 21 12:53:41 PM PDT 24
Finished Apr 21 12:53:43 PM PDT 24
Peak memory 193924 kb
Host smart-c94c9caa-0ab8-439b-a994-4313366aa8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675843788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3675843788
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4164364607
Short name T717
Test name
Test status
Simulation time 179656826 ps
CPU time 2.12 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 199256 kb
Host smart-587c2bfe-4d71-4976-a2f2-4d00eca41d01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164364607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4164364607
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.768576969
Short name T735
Test name
Test status
Simulation time 236903456 ps
CPU time 4.35 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:56 PM PDT 24
Peak memory 199312 kb
Host smart-574e756a-f3da-4c47-870d-c8112703d858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768576969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.768576969
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2372655632
Short name T62
Test name
Test status
Simulation time 82429314 ps
CPU time 1.88 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:49 PM PDT 24
Peak memory 199216 kb
Host smart-c3201c2b-ebb9-41a1-8201-bf0f177c48f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372655632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2372655632
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3090896843
Short name T607
Test name
Test status
Simulation time 67150291 ps
CPU time 3.52 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 199292 kb
Host smart-e901a468-32b7-427e-a880-b1be1739d24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090896843 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3090896843
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4101890669
Short name T94
Test name
Test status
Simulation time 380947925 ps
CPU time 0.97 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 199024 kb
Host smart-61c712fc-1eb9-49d7-b293-f868c96e057e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101890669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4101890669
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.4075160941
Short name T658
Test name
Test status
Simulation time 129219721 ps
CPU time 0.6 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 194072 kb
Host smart-ca3e93af-c72c-403b-ba8f-a04d282428d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075160941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.4075160941
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1510232700
Short name T644
Test name
Test status
Simulation time 24749077 ps
CPU time 1.09 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:43 PM PDT 24
Peak memory 199136 kb
Host smart-0a63583c-c186-4624-a7b6-9687d7ae5e19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510232700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1510232700
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.517597043
Short name T690
Test name
Test status
Simulation time 237028480 ps
CPU time 3.13 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 199256 kb
Host smart-f576b053-9286-49e2-865c-6e27e0750680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517597043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.517597043
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.405211844
Short name T109
Test name
Test status
Simulation time 104376283 ps
CPU time 1.94 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 199224 kb
Host smart-011d2a6e-0993-4ba1-aecf-5274dfa915c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405211844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.405211844
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1276540557
Short name T630
Test name
Test status
Simulation time 69714873 ps
CPU time 2.29 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 199272 kb
Host smart-44cb2932-be5d-4797-90f5-817a58fe62d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276540557 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1276540557
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3986428724
Short name T98
Test name
Test status
Simulation time 19309808 ps
CPU time 0.92 seconds
Started Apr 21 12:53:45 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 198684 kb
Host smart-fa08eb30-7c74-4b1f-a94d-ae05d7e21c4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986428724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3986428724
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2929517055
Short name T608
Test name
Test status
Simulation time 26906812 ps
CPU time 0.57 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 194192 kb
Host smart-761e1cea-2b5b-41f2-a270-50fcc69ffb8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929517055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2929517055
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1841755760
Short name T720
Test name
Test status
Simulation time 681925899 ps
CPU time 1.76 seconds
Started Apr 21 12:54:06 PM PDT 24
Finished Apr 21 12:54:08 PM PDT 24
Peak memory 199140 kb
Host smart-dd54f8db-d8ef-4e19-94a9-d66ed4025f30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841755760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1841755760
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.496009394
Short name T724
Test name
Test status
Simulation time 48235180 ps
CPU time 1.18 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199172 kb
Host smart-ff2ee167-cb72-46c3-beb3-375e9338502c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496009394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.496009394
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.517793249
Short name T110
Test name
Test status
Simulation time 152281801 ps
CPU time 1.81 seconds
Started Apr 21 12:53:45 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 199176 kb
Host smart-30a7e716-ce3e-4c20-ad7b-02defd43e74c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517793249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.517793249
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2674226814
Short name T618
Test name
Test status
Simulation time 38661333 ps
CPU time 1.22 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199244 kb
Host smart-e50c5517-2216-443e-a2b7-990540746538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674226814 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2674226814
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1056601058
Short name T705
Test name
Test status
Simulation time 43831145 ps
CPU time 0.83 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 198132 kb
Host smart-4eb49f7a-66df-428c-afbd-4cda756df991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056601058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1056601058
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.832887582
Short name T632
Test name
Test status
Simulation time 29272875 ps
CPU time 0.61 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 193912 kb
Host smart-bc95820b-0bca-4397-be08-3a54eb523d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832887582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.832887582
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.79229259
Short name T723
Test name
Test status
Simulation time 115324923 ps
CPU time 1.7 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199184 kb
Host smart-63f68f9d-ce28-4614-a258-441e3270ee83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79229259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_
outstanding.79229259
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3380965144
Short name T692
Test name
Test status
Simulation time 50266900 ps
CPU time 2.52 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:55 PM PDT 24
Peak memory 199340 kb
Host smart-a626ca0d-258a-4a76-8157-74693205e5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380965144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3380965144
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2888308452
Short name T638
Test name
Test status
Simulation time 153064749684 ps
CPU time 396.97 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 01:00:22 PM PDT 24
Peak memory 214888 kb
Host smart-23cec2ae-825a-49de-b2b0-658508493f2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888308452 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2888308452
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.664190756
Short name T732
Test name
Test status
Simulation time 55467432 ps
CPU time 0.91 seconds
Started Apr 21 12:54:02 PM PDT 24
Finished Apr 21 12:54:04 PM PDT 24
Peak memory 198868 kb
Host smart-115cb280-6c62-460c-8cdf-e3b0f566d8be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664190756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.664190756
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1203100129
Short name T718
Test name
Test status
Simulation time 46074105 ps
CPU time 0.57 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:43 PM PDT 24
Peak memory 193908 kb
Host smart-c5053326-1f79-4907-8c4b-42abeb3814f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203100129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1203100129
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.191297712
Short name T657
Test name
Test status
Simulation time 225933198 ps
CPU time 1.2 seconds
Started Apr 21 12:53:43 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199100 kb
Host smart-c39e4c04-4562-456d-9d43-eeaa0f095783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191297712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.191297712
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.816779887
Short name T655
Test name
Test status
Simulation time 407703596 ps
CPU time 3.36 seconds
Started Apr 21 12:53:45 PM PDT 24
Finished Apr 21 12:53:49 PM PDT 24
Peak memory 199232 kb
Host smart-8dd879dc-d11c-46d4-8288-2593948bcdce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816779887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.816779887
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.462203403
Short name T728
Test name
Test status
Simulation time 165423734 ps
CPU time 1.36 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 199280 kb
Host smart-37cddd8a-432c-422f-af8e-cbb3e880c46a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462203403 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.462203403
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.938293887
Short name T614
Test name
Test status
Simulation time 89943652 ps
CPU time 0.82 seconds
Started Apr 21 12:53:45 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 198152 kb
Host smart-ee71fbb4-8836-48f7-8b95-7350139fa12d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938293887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.938293887
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1732767651
Short name T731
Test name
Test status
Simulation time 14969291 ps
CPU time 0.57 seconds
Started Apr 21 12:54:00 PM PDT 24
Finished Apr 21 12:54:01 PM PDT 24
Peak memory 193712 kb
Host smart-a9ec108e-4e18-4226-b4ec-8f114700ad12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732767651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1732767651
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1045524491
Short name T635
Test name
Test status
Simulation time 25796997 ps
CPU time 1.11 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 198196 kb
Host smart-e499b1bc-9175-488e-b19d-bb82c7435c48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045524491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1045524491
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.227555783
Short name T616
Test name
Test status
Simulation time 154747350 ps
CPU time 3.36 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:52 PM PDT 24
Peak memory 199208 kb
Host smart-0838b529-7f91-4935-8d1b-339f26809628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227555783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.227555783
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3541670909
Short name T104
Test name
Test status
Simulation time 195848767 ps
CPU time 1.86 seconds
Started Apr 21 12:54:02 PM PDT 24
Finished Apr 21 12:54:05 PM PDT 24
Peak memory 199036 kb
Host smart-556d6ee1-3005-4f3d-97b6-e4025efef572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541670909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3541670909
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.36677123
Short name T621
Test name
Test status
Simulation time 180092229 ps
CPU time 3.44 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 207588 kb
Host smart-28f890f8-1605-4c8c-94df-3f66055758bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36677123 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.36677123
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3405397978
Short name T87
Test name
Test status
Simulation time 40199741 ps
CPU time 0.66 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 196660 kb
Host smart-6e1629b2-9b3d-47d2-a362-533df4c6d7de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405397978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3405397978
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.872339284
Short name T702
Test name
Test status
Simulation time 28019112 ps
CPU time 0.6 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:52 PM PDT 24
Peak memory 193948 kb
Host smart-e20b4553-ec63-4ec2-8a0a-1d010a34d8ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872339284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.872339284
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4069680525
Short name T706
Test name
Test status
Simulation time 418146207 ps
CPU time 1.72 seconds
Started Apr 21 12:53:59 PM PDT 24
Finished Apr 21 12:54:02 PM PDT 24
Peak memory 198988 kb
Host smart-2869cd1f-fff7-4891-af2e-ee4c29d6cfe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069680525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.4069680525
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3122761422
Short name T672
Test name
Test status
Simulation time 404978880 ps
CPU time 1.7 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 199300 kb
Host smart-5498515c-822d-46c9-91e2-5341afcc9ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122761422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3122761422
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1252794692
Short name T100
Test name
Test status
Simulation time 1753427965 ps
CPU time 1.87 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 199284 kb
Host smart-23f7f127-6e3e-4044-8f40-ba75ccca05cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252794692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1252794692
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1815899939
Short name T63
Test name
Test status
Simulation time 88167337 ps
CPU time 3.02 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 199436 kb
Host smart-e0fb4304-9376-496c-bebf-908210d8119e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815899939 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1815899939
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.960159036
Short name T86
Test name
Test status
Simulation time 53569445 ps
CPU time 0.72 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 196752 kb
Host smart-120f852c-309d-4ce8-9d09-34c0bcdc02dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960159036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.960159036
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.284046896
Short name T606
Test name
Test status
Simulation time 17155316 ps
CPU time 0.57 seconds
Started Apr 21 12:53:47 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 193780 kb
Host smart-56c7eb97-9741-4331-9335-b1eb66a18ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284046896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.284046896
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3333545000
Short name T668
Test name
Test status
Simulation time 78962036 ps
CPU time 1.81 seconds
Started Apr 21 12:53:50 PM PDT 24
Finished Apr 21 12:53:52 PM PDT 24
Peak memory 198868 kb
Host smart-92bd724d-625a-4296-80a2-173d28b97695
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333545000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3333545000
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2384897331
Short name T676
Test name
Test status
Simulation time 607505456 ps
CPU time 3.06 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 199260 kb
Host smart-43831d1f-be78-46e7-9fd7-6fc732975b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384897331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2384897331
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1674191725
Short name T106
Test name
Test status
Simulation time 590973822 ps
CPU time 3.07 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 199220 kb
Host smart-99a18ae2-1c58-4f50-a1be-d25838bcd281
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674191725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1674191725
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3815927785
Short name T636
Test name
Test status
Simulation time 34337866 ps
CPU time 2.07 seconds
Started Apr 21 12:53:47 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 199312 kb
Host smart-b89e67aa-5412-476b-bc71-7dde62d0a5f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815927785 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3815927785
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3258994357
Short name T673
Test name
Test status
Simulation time 77429644 ps
CPU time 0.79 seconds
Started Apr 21 12:53:52 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 198356 kb
Host smart-8027dc45-e04e-4b71-af22-bc16145b5a8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258994357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3258994357
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3710908383
Short name T610
Test name
Test status
Simulation time 11383549 ps
CPU time 0.61 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 194172 kb
Host smart-35bdb4da-f36a-4e6f-8c9a-75f34deb9a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710908383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3710908383
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3448284550
Short name T642
Test name
Test status
Simulation time 111190846 ps
CPU time 2.37 seconds
Started Apr 21 12:53:45 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 199232 kb
Host smart-12effa72-65c6-4eaf-ba64-57bcd281b8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448284550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3448284550
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2418868002
Short name T650
Test name
Test status
Simulation time 269702922 ps
CPU time 2 seconds
Started Apr 21 12:53:47 PM PDT 24
Finished Apr 21 12:53:49 PM PDT 24
Peak memory 199320 kb
Host smart-fd1650c7-f061-4e76-a4a8-24dfbc05803e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418868002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2418868002
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2608208458
Short name T689
Test name
Test status
Simulation time 199298722 ps
CPU time 1.9 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:49 PM PDT 24
Peak memory 199168 kb
Host smart-ae2f6a41-d0f4-4068-ac6f-f9e62eb1b1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608208458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2608208458
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3532258849
Short name T643
Test name
Test status
Simulation time 38009221 ps
CPU time 1.24 seconds
Started Apr 21 12:53:47 PM PDT 24
Finished Apr 21 12:53:49 PM PDT 24
Peak memory 199104 kb
Host smart-af317f07-5f2f-4c55-bd29-009a537b6475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532258849 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3532258849
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.121321926
Short name T93
Test name
Test status
Simulation time 47113696 ps
CPU time 0.76 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 197844 kb
Host smart-ea0dc244-b8d1-44cf-ae39-411ccae13319
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121321926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.121321926
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3843360604
Short name T671
Test name
Test status
Simulation time 24175775 ps
CPU time 0.6 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 193892 kb
Host smart-24fa3da8-4b42-470a-9328-ac6d665531de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843360604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3843360604
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.769555011
Short name T688
Test name
Test status
Simulation time 52009874 ps
CPU time 1.13 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 198948 kb
Host smart-fcc5a030-70b6-43ea-aed9-1a33a9f30ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769555011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.769555011
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.623122174
Short name T653
Test name
Test status
Simulation time 164956860 ps
CPU time 3.53 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 199252 kb
Host smart-1f5d2854-8b53-42d0-b31b-ca30f8f500a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623122174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.623122174
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1273006865
Short name T105
Test name
Test status
Simulation time 187642492 ps
CPU time 2.87 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:52 PM PDT 24
Peak memory 199180 kb
Host smart-79891ce3-2585-49ba-815f-8dae910627c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273006865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1273006865
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4225291447
Short name T634
Test name
Test status
Simulation time 1038299376 ps
CPU time 6.48 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:42 PM PDT 24
Peak memory 198052 kb
Host smart-09085744-8495-4112-ab8b-797e401a9b68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225291447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4225291447
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3402143369
Short name T90
Test name
Test status
Simulation time 6257294759 ps
CPU time 17.05 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:56 PM PDT 24
Peak memory 198304 kb
Host smart-0aec0081-3be4-4003-a9fb-b294e7f8320b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402143369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3402143369
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1592627550
Short name T694
Test name
Test status
Simulation time 20329353 ps
CPU time 0.83 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:35 PM PDT 24
Peak memory 196788 kb
Host smart-1becf934-5f7e-410f-b9b7-9a1a80efc016
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592627550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1592627550
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1214223641
Short name T663
Test name
Test status
Simulation time 41335914 ps
CPU time 2.58 seconds
Started Apr 21 12:53:37 PM PDT 24
Finished Apr 21 12:53:40 PM PDT 24
Peak memory 199464 kb
Host smart-fd862b3c-4e0c-4a0c-826e-b5ffca6971fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214223641 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1214223641
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.501934477
Short name T95
Test name
Test status
Simulation time 26246530 ps
CPU time 0.78 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:36 PM PDT 24
Peak memory 198512 kb
Host smart-a5ad2537-579b-4699-a3e4-8007b6d3b642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501934477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.501934477
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2963192856
Short name T697
Test name
Test status
Simulation time 18642518 ps
CPU time 0.64 seconds
Started Apr 21 12:53:36 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 193860 kb
Host smart-b77bf5d9-db67-4979-afc4-429d8d971790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963192856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2963192856
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1480311675
Short name T682
Test name
Test status
Simulation time 93429731 ps
CPU time 1.21 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 197180 kb
Host smart-c215b5a6-9257-4376-9108-56a66fefc528
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480311675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1480311675
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1736033570
Short name T629
Test name
Test status
Simulation time 295453141 ps
CPU time 3.96 seconds
Started Apr 21 12:53:31 PM PDT 24
Finished Apr 21 12:53:35 PM PDT 24
Peak memory 199248 kb
Host smart-d5d881b0-6f69-4a73-8151-d1ebcedc58ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736033570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1736033570
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.352541970
Short name T101
Test name
Test status
Simulation time 426216217 ps
CPU time 3.82 seconds
Started Apr 21 12:53:32 PM PDT 24
Finished Apr 21 12:53:36 PM PDT 24
Peak memory 199204 kb
Host smart-142e1fb3-8e68-4ee5-b09f-1db9764ce916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352541970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.352541970
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1636917710
Short name T620
Test name
Test status
Simulation time 19375416 ps
CPU time 0.65 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 193940 kb
Host smart-f4af1499-4483-42a3-af74-09b92a41701a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636917710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1636917710
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1697381968
Short name T675
Test name
Test status
Simulation time 91467734 ps
CPU time 0.58 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:52 PM PDT 24
Peak memory 193884 kb
Host smart-ae0b3314-f400-41c6-88f0-3241138741cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697381968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1697381968
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1507033395
Short name T686
Test name
Test status
Simulation time 28149472 ps
CPU time 0.59 seconds
Started Apr 21 12:53:47 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 193952 kb
Host smart-1ffd72bc-3c06-49b8-bd20-e35793b57397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507033395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1507033395
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.295104606
Short name T613
Test name
Test status
Simulation time 12265799 ps
CPU time 0.63 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 193956 kb
Host smart-cc4c172f-97ab-4191-98d2-86f542fc945c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295104606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.295104606
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1410848860
Short name T647
Test name
Test status
Simulation time 29304868 ps
CPU time 0.62 seconds
Started Apr 21 12:53:45 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 193824 kb
Host smart-6476bdba-690f-4591-9a4d-421f5b9eacdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410848860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1410848860
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2856253637
Short name T727
Test name
Test status
Simulation time 88830874 ps
CPU time 0.57 seconds
Started Apr 21 12:53:59 PM PDT 24
Finished Apr 21 12:54:00 PM PDT 24
Peak memory 193828 kb
Host smart-917b950b-2f97-434b-8164-3d29de37486b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856253637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2856253637
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3802108649
Short name T693
Test name
Test status
Simulation time 14831301 ps
CPU time 0.59 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:49 PM PDT 24
Peak memory 193948 kb
Host smart-ce6ce768-0200-4c88-9156-14e679f164c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802108649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3802108649
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4155462181
Short name T733
Test name
Test status
Simulation time 57348762 ps
CPU time 0.65 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 193928 kb
Host smart-e1462930-4be0-494c-a1a5-85c8b34c7277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155462181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4155462181
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2311533526
Short name T623
Test name
Test status
Simulation time 32230809 ps
CPU time 0.57 seconds
Started Apr 21 12:53:46 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 194044 kb
Host smart-3ea8c466-b667-4cf0-bdb1-33725d0120e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311533526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2311533526
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2102186290
Short name T617
Test name
Test status
Simulation time 13497600 ps
CPU time 0.62 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:46 PM PDT 24
Peak memory 194136 kb
Host smart-bc5c34df-a4a7-468c-8e3f-1f5d52c01bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102186290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2102186290
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2010333752
Short name T680
Test name
Test status
Simulation time 366197863 ps
CPU time 6.06 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:40 PM PDT 24
Peak memory 199188 kb
Host smart-903f09b6-9378-4715-9d94-44356c8b925a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010333752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2010333752
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.75781286
Short name T698
Test name
Test status
Simulation time 1851054662 ps
CPU time 15.87 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:55 PM PDT 24
Peak memory 199184 kb
Host smart-dbf55e4d-a86d-4f18-939e-fc49c7f64a2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75781286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.75781286
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2052949047
Short name T664
Test name
Test status
Simulation time 15032952 ps
CPU time 0.71 seconds
Started Apr 21 12:53:33 PM PDT 24
Finished Apr 21 12:53:34 PM PDT 24
Peak memory 197200 kb
Host smart-9f5af5f9-c173-43b5-88ae-e8570bb1c3bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052949047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2052949047
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3686899619
Short name T662
Test name
Test status
Simulation time 232164892 ps
CPU time 1.8 seconds
Started Apr 21 12:53:37 PM PDT 24
Finished Apr 21 12:53:39 PM PDT 24
Peak memory 199360 kb
Host smart-d40c6643-5b4c-441f-a2c7-08105c8018b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686899619 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3686899619
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3327602499
Short name T707
Test name
Test status
Simulation time 99257677 ps
CPU time 0.93 seconds
Started Apr 21 12:53:37 PM PDT 24
Finished Apr 21 12:53:39 PM PDT 24
Peak memory 199024 kb
Host smart-bfa8f468-97bc-4d92-aa6c-c4cb0526ad61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327602499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3327602499
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1271688260
Short name T645
Test name
Test status
Simulation time 37270120 ps
CPU time 0.57 seconds
Started Apr 21 12:53:36 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 193868 kb
Host smart-ce0c5f9c-446f-4e1e-8ec3-37c4a806f54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271688260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1271688260
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.96029048
Short name T695
Test name
Test status
Simulation time 81774241 ps
CPU time 1.76 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 199228 kb
Host smart-7b76474c-3da8-4d3d-a0bc-e9348271f927
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96029048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_o
utstanding.96029048
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3509235094
Short name T628
Test name
Test status
Simulation time 1027251134 ps
CPU time 4.78 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:39 PM PDT 24
Peak memory 199264 kb
Host smart-c6552cad-5673-4d3f-a9a8-5c9c3fcd9e12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509235094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3509235094
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1946256499
Short name T103
Test name
Test status
Simulation time 232500525 ps
CPU time 4.34 seconds
Started Apr 21 12:53:34 PM PDT 24
Finished Apr 21 12:53:39 PM PDT 24
Peak memory 199236 kb
Host smart-537ed2e3-03da-4dc6-a997-4387bda65d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946256499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1946256499
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4271723179
Short name T646
Test name
Test status
Simulation time 20653920 ps
CPU time 0.62 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 193976 kb
Host smart-9639808c-ab00-40bf-bf46-f93875df0539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271723179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4271723179
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.838813689
Short name T640
Test name
Test status
Simulation time 21476844 ps
CPU time 0.6 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 193820 kb
Host smart-e5e1c5e8-494a-4a52-a62e-fd0affc53d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838813689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.838813689
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.137681363
Short name T604
Test name
Test status
Simulation time 37170222 ps
CPU time 0.61 seconds
Started Apr 21 12:53:52 PM PDT 24
Finished Apr 21 12:53:54 PM PDT 24
Peak memory 194100 kb
Host smart-f696db95-7d5d-4cce-9631-db6cfedc8a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137681363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.137681363
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.783378881
Short name T669
Test name
Test status
Simulation time 14738400 ps
CPU time 0.61 seconds
Started Apr 21 12:53:50 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 194140 kb
Host smart-eeb2b322-baf2-4203-834e-8f336be09f34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783378881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.783378881
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.358155846
Short name T611
Test name
Test status
Simulation time 41372068 ps
CPU time 0.6 seconds
Started Apr 21 12:53:52 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 193956 kb
Host smart-934418f9-d7a8-4700-a109-d08a8ceb863f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358155846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.358155846
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.369964505
Short name T605
Test name
Test status
Simulation time 20958253 ps
CPU time 0.58 seconds
Started Apr 21 12:53:50 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 194120 kb
Host smart-ce029824-199e-4f51-aa7d-84411fa6ad1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369964505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.369964505
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1505570321
Short name T704
Test name
Test status
Simulation time 54385623 ps
CPU time 0.62 seconds
Started Apr 21 12:53:50 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 193964 kb
Host smart-2f951d6c-3c52-4507-95ba-76122fce67f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505570321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1505570321
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.685927602
Short name T651
Test name
Test status
Simulation time 31647425 ps
CPU time 0.66 seconds
Started Apr 21 12:53:50 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 193832 kb
Host smart-902b3cdb-f159-4466-bc22-31518a1a4791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685927602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.685927602
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1681070670
Short name T609
Test name
Test status
Simulation time 26380701 ps
CPU time 0.6 seconds
Started Apr 21 12:53:51 PM PDT 24
Finished Apr 21 12:53:53 PM PDT 24
Peak memory 194284 kb
Host smart-8505e1e7-c496-40ff-9a5d-007bd7546fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681070670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1681070670
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3794705092
Short name T715
Test name
Test status
Simulation time 50513964 ps
CPU time 0.57 seconds
Started Apr 21 12:53:55 PM PDT 24
Finished Apr 21 12:53:56 PM PDT 24
Peak memory 193912 kb
Host smart-3e383747-8289-4c79-bb8f-b5241afbc1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794705092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3794705092
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3022891451
Short name T679
Test name
Test status
Simulation time 792568940 ps
CPU time 6.18 seconds
Started Apr 21 12:53:40 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 199160 kb
Host smart-9756ce04-4de4-4585-8980-2db38d1935f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022891451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3022891451
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3652365675
Short name T83
Test name
Test status
Simulation time 630550393 ps
CPU time 6.06 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:42 PM PDT 24
Peak memory 197840 kb
Host smart-845fa9d9-f04d-4ba8-b735-b1154f34d448
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652365675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3652365675
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3712695768
Short name T625
Test name
Test status
Simulation time 35138703 ps
CPU time 1 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:37 PM PDT 24
Peak memory 199024 kb
Host smart-9d992e83-2fda-4771-92be-df05b8efcd21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712695768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3712695768
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2046856
Short name T652
Test name
Test status
Simulation time 243709579 ps
CPU time 1.28 seconds
Started Apr 21 12:53:41 PM PDT 24
Finished Apr 21 12:53:43 PM PDT 24
Peak memory 199328 kb
Host smart-931d6c05-5e0e-477c-81a5-af9bc1be9f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046856 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2046856
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3328802285
Short name T649
Test name
Test status
Simulation time 213582096 ps
CPU time 0.85 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:36 PM PDT 24
Peak memory 198204 kb
Host smart-8efd612b-1d22-40fb-a30c-d62ad3584c16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328802285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3328802285
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3068520618
Short name T722
Test name
Test status
Simulation time 13361914 ps
CPU time 0.64 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:39 PM PDT 24
Peak memory 193948 kb
Host smart-1704e478-07c0-44a7-8107-67669a40a2df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068520618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3068520618
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2135678153
Short name T713
Test name
Test status
Simulation time 169754383 ps
CPU time 2.01 seconds
Started Apr 21 12:53:40 PM PDT 24
Finished Apr 21 12:53:42 PM PDT 24
Peak memory 199024 kb
Host smart-efc1f851-a807-4326-b283-6fcea222aefc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135678153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2135678153
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3730938897
Short name T701
Test name
Test status
Simulation time 349152158 ps
CPU time 3.21 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:42 PM PDT 24
Peak memory 199216 kb
Host smart-fc81e7d2-ffd4-47ed-8536-82f037a12d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730938897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3730938897
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2418505825
Short name T108
Test name
Test status
Simulation time 1108717391 ps
CPU time 2.83 seconds
Started Apr 21 12:53:35 PM PDT 24
Finished Apr 21 12:53:38 PM PDT 24
Peak memory 199244 kb
Host smart-4ba0137a-79a4-4cd0-8678-7a4db3b11cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418505825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2418505825
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3394866509
Short name T615
Test name
Test status
Simulation time 15278152 ps
CPU time 0.61 seconds
Started Apr 21 12:53:54 PM PDT 24
Finished Apr 21 12:53:56 PM PDT 24
Peak memory 193864 kb
Host smart-1ec18f30-6ef8-4835-a5b8-7aa2a54a44ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394866509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3394866509
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2282916679
Short name T700
Test name
Test status
Simulation time 42051090 ps
CPU time 0.58 seconds
Started Apr 21 12:53:57 PM PDT 24
Finished Apr 21 12:53:57 PM PDT 24
Peak memory 194104 kb
Host smart-2f007cc8-370b-4134-a13d-e94146d30923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282916679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2282916679
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2583015256
Short name T637
Test name
Test status
Simulation time 50727108 ps
CPU time 0.58 seconds
Started Apr 21 12:54:01 PM PDT 24
Finished Apr 21 12:54:02 PM PDT 24
Peak memory 193916 kb
Host smart-fd457b08-18d6-43e4-88e3-824cddb3c41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583015256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2583015256
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3788536199
Short name T681
Test name
Test status
Simulation time 37445054 ps
CPU time 0.57 seconds
Started Apr 21 12:53:55 PM PDT 24
Finished Apr 21 12:53:56 PM PDT 24
Peak memory 193952 kb
Host smart-b8f21711-e506-412f-bc09-6a02f0f1d7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788536199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3788536199
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2516290493
Short name T687
Test name
Test status
Simulation time 53552267 ps
CPU time 0.6 seconds
Started Apr 21 12:53:55 PM PDT 24
Finished Apr 21 12:53:56 PM PDT 24
Peak memory 193944 kb
Host smart-57040296-cab6-49ed-be1b-284074b6a118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516290493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2516290493
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.936054340
Short name T622
Test name
Test status
Simulation time 24442954 ps
CPU time 0.58 seconds
Started Apr 21 12:53:52 PM PDT 24
Finished Apr 21 12:53:54 PM PDT 24
Peak memory 194112 kb
Host smart-b9f5dafb-dadc-41fa-9b8b-ba5cb9ab8812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936054340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.936054340
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3654680835
Short name T696
Test name
Test status
Simulation time 25231186 ps
CPU time 0.59 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 193924 kb
Host smart-aa7f7d6e-62aa-4421-b3c9-38916ac182d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654680835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3654680835
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.119872416
Short name T709
Test name
Test status
Simulation time 45263190 ps
CPU time 0.62 seconds
Started Apr 21 12:53:57 PM PDT 24
Finished Apr 21 12:53:58 PM PDT 24
Peak memory 194068 kb
Host smart-db0d1ff2-3028-4466-af91-dfbc217cfccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119872416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.119872416
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.694575177
Short name T734
Test name
Test status
Simulation time 56540971 ps
CPU time 0.57 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 194104 kb
Host smart-a8b2468a-d628-4914-a500-cb086859c6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694575177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.694575177
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1778241325
Short name T619
Test name
Test status
Simulation time 21608402 ps
CPU time 0.64 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:50 PM PDT 24
Peak memory 193928 kb
Host smart-6126ba69-8f12-4e56-adc1-9aedfffefd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778241325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1778241325
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4115951721
Short name T639
Test name
Test status
Simulation time 91173291 ps
CPU time 2.3 seconds
Started Apr 21 12:53:41 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199272 kb
Host smart-31927caa-02bb-4197-a2df-ae03b8cb2d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115951721 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4115951721
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2083535595
Short name T88
Test name
Test status
Simulation time 83641043 ps
CPU time 0.9 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:39 PM PDT 24
Peak memory 198208 kb
Host smart-83353bb0-20fd-4fa1-91db-08c5f41c8493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083535595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2083535595
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.4150659571
Short name T712
Test name
Test status
Simulation time 13260093 ps
CPU time 0.67 seconds
Started Apr 21 12:53:39 PM PDT 24
Finished Apr 21 12:53:40 PM PDT 24
Peak memory 193876 kb
Host smart-817ff129-e5ff-4165-b865-b621adca1125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150659571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.4150659571
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.975114827
Short name T656
Test name
Test status
Simulation time 135197493 ps
CPU time 1.06 seconds
Started Apr 21 12:53:41 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 199204 kb
Host smart-daa63852-a826-426b-a587-1257ecd08bac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975114827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.975114827
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2427556432
Short name T699
Test name
Test status
Simulation time 64554334 ps
CPU time 1.27 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 199068 kb
Host smart-b1a67357-9517-4419-bfb6-f11682b29a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427556432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2427556432
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1651935439
Short name T729
Test name
Test status
Simulation time 136002399 ps
CPU time 3.9 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:43 PM PDT 24
Peak memory 199284 kb
Host smart-58f492b5-47f6-44b5-a50f-9633aa2ce990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651935439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1651935439
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1693549422
Short name T730
Test name
Test status
Simulation time 386128397 ps
CPU time 3.43 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 199368 kb
Host smart-bbb59463-1b11-48c6-977d-85ab12ed3697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693549422 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1693549422
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4248833686
Short name T64
Test name
Test status
Simulation time 180238806 ps
CPU time 0.79 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:39 PM PDT 24
Peak memory 198488 kb
Host smart-13219950-abb9-44a5-b829-480904a8f0fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248833686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4248833686
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.282806984
Short name T661
Test name
Test status
Simulation time 30262682 ps
CPU time 0.55 seconds
Started Apr 21 12:53:41 PM PDT 24
Finished Apr 21 12:53:42 PM PDT 24
Peak memory 193824 kb
Host smart-bdf50af8-8a8f-4eeb-9a6d-5106ec33c893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282806984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.282806984
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2517024634
Short name T626
Test name
Test status
Simulation time 97150486 ps
CPU time 1.67 seconds
Started Apr 21 12:53:40 PM PDT 24
Finished Apr 21 12:53:42 PM PDT 24
Peak memory 199224 kb
Host smart-50ce9e54-b535-4daf-a926-23eee3d640ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517024634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2517024634
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2358998351
Short name T677
Test name
Test status
Simulation time 2303830716 ps
CPU time 4.03 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:47 PM PDT 24
Peak memory 199444 kb
Host smart-ccd080b9-2e10-4d57-a95f-2115c032b65c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358998351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2358998351
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2026114526
Short name T107
Test name
Test status
Simulation time 963085550 ps
CPU time 4.3 seconds
Started Apr 21 12:53:39 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199236 kb
Host smart-1f15a872-c31d-40ec-8543-f501a84a2003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026114526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2026114526
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3242651537
Short name T725
Test name
Test status
Simulation time 300899714 ps
CPU time 2.65 seconds
Started Apr 21 12:53:41 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 199256 kb
Host smart-175a5bf9-28e3-462d-94f3-64d3558f1ae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242651537 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3242651537
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.762188712
Short name T96
Test name
Test status
Simulation time 32741071 ps
CPU time 0.67 seconds
Started Apr 21 12:53:57 PM PDT 24
Finished Apr 21 12:53:59 PM PDT 24
Peak memory 196612 kb
Host smart-2e632481-f1bb-4ecc-90c9-17dac3b5cda8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762188712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.762188712
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1889853409
Short name T624
Test name
Test status
Simulation time 18418061 ps
CPU time 0.6 seconds
Started Apr 21 12:53:37 PM PDT 24
Finished Apr 21 12:53:38 PM PDT 24
Peak memory 193824 kb
Host smart-0c48a064-ca7b-441f-9c5e-551b4d05dbae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889853409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1889853409
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1799887941
Short name T654
Test name
Test status
Simulation time 22070531 ps
CPU time 1.11 seconds
Started Apr 21 12:53:40 PM PDT 24
Finished Apr 21 12:53:41 PM PDT 24
Peak memory 198628 kb
Host smart-ec4329af-b059-48a4-840a-fa4f55549431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799887941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1799887941
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3922447364
Short name T719
Test name
Test status
Simulation time 68970351 ps
CPU time 3.45 seconds
Started Apr 21 12:53:39 PM PDT 24
Finished Apr 21 12:53:43 PM PDT 24
Peak memory 199216 kb
Host smart-f95f7bd3-d8a2-4d73-bbdc-4906a7f41cec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922447364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3922447364
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.473413522
Short name T678
Test name
Test status
Simulation time 449666387 ps
CPU time 2.92 seconds
Started Apr 21 12:53:40 PM PDT 24
Finished Apr 21 12:53:43 PM PDT 24
Peak memory 199160 kb
Host smart-926eecd9-8d8a-48c4-8c3d-ceb75ae78431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473413522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.473413522
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3312769639
Short name T685
Test name
Test status
Simulation time 145542786 ps
CPU time 1.2 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199204 kb
Host smart-35b00e2e-312f-4a04-887e-74c2fccdd2e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312769639 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3312769639
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3685874860
Short name T92
Test name
Test status
Simulation time 133931837 ps
CPU time 0.96 seconds
Started Apr 21 12:53:39 PM PDT 24
Finished Apr 21 12:53:41 PM PDT 24
Peak memory 198636 kb
Host smart-0fed494b-416f-4471-8c46-a4b75125fdef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685874860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3685874860
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.4141096325
Short name T612
Test name
Test status
Simulation time 67090595 ps
CPU time 0.57 seconds
Started Apr 21 12:53:41 PM PDT 24
Finished Apr 21 12:53:42 PM PDT 24
Peak memory 193920 kb
Host smart-aafc3a64-50c4-4520-b625-d434db3b331c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141096325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4141096325
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.201145654
Short name T631
Test name
Test status
Simulation time 45701595 ps
CPU time 2.11 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:52 PM PDT 24
Peak memory 198860 kb
Host smart-eb549b74-92da-4f69-a964-e6e388a2f482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201145654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.201145654
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2845665710
Short name T660
Test name
Test status
Simulation time 123050973 ps
CPU time 1.6 seconds
Started Apr 21 12:53:38 PM PDT 24
Finished Apr 21 12:53:40 PM PDT 24
Peak memory 199236 kb
Host smart-85e99dd3-78ef-4600-b888-28b3aa365544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845665710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2845665710
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2346313831
Short name T708
Test name
Test status
Simulation time 176128044 ps
CPU time 1.74 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 199232 kb
Host smart-cc5d6a9f-767c-413c-91b8-fd2875eee0be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346313831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2346313831
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1814523434
Short name T714
Test name
Test status
Simulation time 85382687 ps
CPU time 2.19 seconds
Started Apr 21 12:53:43 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 199328 kb
Host smart-caf3dcaa-67cd-4701-9a0b-3fa2bed8c07c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814523434 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1814523434
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2035015097
Short name T641
Test name
Test status
Simulation time 24879658 ps
CPU time 0.71 seconds
Started Apr 21 12:53:43 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 197188 kb
Host smart-15732919-1a34-4aa3-a36d-dbb03adfad16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035015097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2035015097
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.223992360
Short name T703
Test name
Test status
Simulation time 88322513 ps
CPU time 0.61 seconds
Started Apr 21 12:53:49 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 193748 kb
Host smart-1bf8c5e9-288d-464d-80c6-4844641d285d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223992360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.223992360
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2727079930
Short name T683
Test name
Test status
Simulation time 195607632 ps
CPU time 1.74 seconds
Started Apr 21 12:53:42 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 199276 kb
Host smart-1db6d8f1-5dd0-4074-a4db-1d010fed3fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727079930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2727079930
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1031828689
Short name T665
Test name
Test status
Simulation time 70204886 ps
CPU time 3.52 seconds
Started Apr 21 12:53:44 PM PDT 24
Finished Apr 21 12:53:48 PM PDT 24
Peak memory 199352 kb
Host smart-697afeb3-ecb7-4910-8108-0d9ece20a50d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031828689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1031828689
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.214512022
Short name T670
Test name
Test status
Simulation time 80125676 ps
CPU time 1.98 seconds
Started Apr 21 12:53:48 PM PDT 24
Finished Apr 21 12:53:51 PM PDT 24
Peak memory 199188 kb
Host smart-051d41d9-a66e-4f6b-a3cb-53a21e77a66e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214512022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.214512022
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4192012858
Short name T472
Test name
Test status
Simulation time 17137478 ps
CPU time 0.59 seconds
Started Apr 21 01:38:50 PM PDT 24
Finished Apr 21 01:38:51 PM PDT 24
Peak memory 195292 kb
Host smart-8ba92d1d-e5b0-42d9-91bf-46a3b5347d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192012858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4192012858
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3942875621
Short name T500
Test name
Test status
Simulation time 832435100 ps
CPU time 32.25 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:39:23 PM PDT 24
Peak memory 245720 kb
Host smart-2e22f26a-4d72-4b7a-add2-48bfe5400f6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942875621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3942875621
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3581232434
Short name T180
Test name
Test status
Simulation time 2864328791 ps
CPU time 22.49 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:39:18 PM PDT 24
Peak memory 199360 kb
Host smart-8c54d162-51af-4743-a209-7f7cd9b70f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581232434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3581232434
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1587510252
Short name T588
Test name
Test status
Simulation time 16900540 ps
CPU time 0.7 seconds
Started Apr 21 01:38:55 PM PDT 24
Finished Apr 21 01:38:57 PM PDT 24
Peak memory 196528 kb
Host smart-3ddf9c52-47c0-4d37-8c96-4c95d660ac14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587510252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1587510252
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1504377080
Short name T351
Test name
Test status
Simulation time 3448682387 ps
CPU time 64.84 seconds
Started Apr 21 01:38:46 PM PDT 24
Finished Apr 21 01:39:51 PM PDT 24
Peak memory 199688 kb
Host smart-f20a6b4d-c155-4bb9-a643-e81f90a9a62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504377080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1504377080
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1873051117
Short name T310
Test name
Test status
Simulation time 1978565045 ps
CPU time 5.96 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:38:57 PM PDT 24
Peak memory 199640 kb
Host smart-a904655b-b9ce-4ded-8e13-2c902d130462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873051117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1873051117
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1918605105
Short name T270
Test name
Test status
Simulation time 106114850907 ps
CPU time 1439.42 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 02:02:51 PM PDT 24
Peak memory 232380 kb
Host smart-6c45333b-0e56-46f9-bea1-02c0a0262044
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918605105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1918605105
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.486589059
Short name T201
Test name
Test status
Simulation time 78450102 ps
CPU time 1.03 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:38:53 PM PDT 24
Peak memory 198820 kb
Host smart-646418a8-c84e-4472-9098-f185dce9bad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486589059 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.486589059
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2144549030
Short name T293
Test name
Test status
Simulation time 31547869527 ps
CPU time 405.38 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:45:37 PM PDT 24
Peak memory 199712 kb
Host smart-bd4ed0d5-4cfa-43ca-a057-0a2747bc24ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144549030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2144549030
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2315439724
Short name T533
Test name
Test status
Simulation time 1290320851 ps
CPU time 17.44 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:39:09 PM PDT 24
Peak memory 199612 kb
Host smart-8cb626a0-1318-4d5f-85c0-9a250af4a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315439724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2315439724
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2584183306
Short name T220
Test name
Test status
Simulation time 16709991 ps
CPU time 0.61 seconds
Started Apr 21 01:38:53 PM PDT 24
Finished Apr 21 01:38:54 PM PDT 24
Peak memory 195240 kb
Host smart-9ded9158-b661-4beb-8a79-2a1a1e3c587d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584183306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2584183306
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2037409624
Short name T528
Test name
Test status
Simulation time 789366687 ps
CPU time 28.23 seconds
Started Apr 21 01:38:50 PM PDT 24
Finished Apr 21 01:39:19 PM PDT 24
Peak memory 209812 kb
Host smart-9c06f1f6-6963-4da3-bde0-2907d8b108d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037409624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2037409624
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1731429640
Short name T488
Test name
Test status
Simulation time 2019178390 ps
CPU time 19.65 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:39:12 PM PDT 24
Peak memory 199624 kb
Host smart-75daf914-a0ea-4087-8c72-e2f2b07aecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731429640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1731429640
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.571520087
Short name T221
Test name
Test status
Simulation time 1153973449 ps
CPU time 64.19 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:39:55 PM PDT 24
Peak memory 199572 kb
Host smart-b9a3c04f-970f-43be-a3bc-8f72e403f779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571520087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.571520087
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1086899235
Short name T282
Test name
Test status
Simulation time 108155459391 ps
CPU time 171.25 seconds
Started Apr 21 01:38:53 PM PDT 24
Finished Apr 21 01:41:45 PM PDT 24
Peak memory 199780 kb
Host smart-e9cd5a56-2a4f-4748-b29a-43a0d3137fac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086899235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1086899235
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3019960758
Short name T303
Test name
Test status
Simulation time 7897909769 ps
CPU time 110.06 seconds
Started Apr 21 01:38:50 PM PDT 24
Finished Apr 21 01:40:40 PM PDT 24
Peak memory 199708 kb
Host smart-1e183867-c078-4ffc-8c8b-0c23b0bec1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019960758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3019960758
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4000788992
Short name T31
Test name
Test status
Simulation time 226687221 ps
CPU time 0.83 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:38:52 PM PDT 24
Peak memory 218240 kb
Host smart-2f95b3be-da9a-405a-b954-3a8ca8de17c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000788992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4000788992
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3379017311
Short name T375
Test name
Test status
Simulation time 1604684179 ps
CPU time 5.79 seconds
Started Apr 21 01:38:49 PM PDT 24
Finished Apr 21 01:38:55 PM PDT 24
Peak memory 199652 kb
Host smart-0cfadf1f-890b-46ed-b439-2497343f02f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379017311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3379017311
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3396964228
Short name T464
Test name
Test status
Simulation time 397263746 ps
CPU time 4.69 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:38:57 PM PDT 24
Peak memory 199608 kb
Host smart-89ba7c61-4e91-4678-bfbf-23ad4491f96a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396964228 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3396964228
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.432012276
Short name T442
Test name
Test status
Simulation time 240698834 ps
CPU time 1.27 seconds
Started Apr 21 01:38:53 PM PDT 24
Finished Apr 21 01:38:54 PM PDT 24
Peak memory 199572 kb
Host smart-8e448cf5-00d0-4676-a20d-2fd18a840f1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432012276 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.432012276
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.518305602
Short name T355
Test name
Test status
Simulation time 39967973750 ps
CPU time 512.04 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:47:25 PM PDT 24
Peak memory 199712 kb
Host smart-1729a8a3-1229-4567-bd52-a0c1c857ec23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518305602 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.518305602
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2149308283
Short name T471
Test name
Test status
Simulation time 1480799910 ps
CPU time 6.28 seconds
Started Apr 21 01:38:52 PM PDT 24
Finished Apr 21 01:38:58 PM PDT 24
Peak memory 199588 kb
Host smart-78597e7f-1f34-4201-9c6a-52721e620370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149308283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2149308283
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1974492698
Short name T53
Test name
Test status
Simulation time 4049848041 ps
CPU time 37.4 seconds
Started Apr 21 01:39:24 PM PDT 24
Finished Apr 21 01:40:01 PM PDT 24
Peak memory 232340 kb
Host smart-63e784d8-766d-46d5-bcf0-9afc86b1807c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974492698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1974492698
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.154238900
Short name T426
Test name
Test status
Simulation time 2086891044 ps
CPU time 26.4 seconds
Started Apr 21 01:39:26 PM PDT 24
Finished Apr 21 01:39:52 PM PDT 24
Peak memory 199540 kb
Host smart-bb72b0e6-f8fc-4436-85e5-bf43bcf7b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154238900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.154238900
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3512717775
Short name T383
Test name
Test status
Simulation time 3784312327 ps
CPU time 55.58 seconds
Started Apr 21 01:39:26 PM PDT 24
Finished Apr 21 01:40:22 PM PDT 24
Peak memory 199740 kb
Host smart-f33f6810-affe-4575-a0b7-783df1b72b70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512717775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3512717775
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2587386513
Short name T569
Test name
Test status
Simulation time 10621024044 ps
CPU time 85.69 seconds
Started Apr 21 01:39:23 PM PDT 24
Finished Apr 21 01:40:49 PM PDT 24
Peak memory 199736 kb
Host smart-48c206b1-6abf-41d7-aac1-8b3f0d588dbe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587386513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2587386513
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2253165737
Short name T495
Test name
Test status
Simulation time 2203742811 ps
CPU time 31.09 seconds
Started Apr 21 01:39:23 PM PDT 24
Finished Apr 21 01:39:54 PM PDT 24
Peak memory 199664 kb
Host smart-2abebf5e-4061-4041-9654-3373150db181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253165737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2253165737
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.300071389
Short name T158
Test name
Test status
Simulation time 377930314 ps
CPU time 5.75 seconds
Started Apr 21 01:39:23 PM PDT 24
Finished Apr 21 01:39:29 PM PDT 24
Peak memory 199664 kb
Host smart-d743b982-3e44-4081-b2af-37de04e07849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300071389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.300071389
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.4215784187
Short name T272
Test name
Test status
Simulation time 14304434758 ps
CPU time 125.33 seconds
Started Apr 21 01:39:28 PM PDT 24
Finished Apr 21 01:41:34 PM PDT 24
Peak memory 227408 kb
Host smart-e437a899-0e63-4279-9995-6683d17d03c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215784187 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.4215784187
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3609942666
Short name T253
Test name
Test status
Simulation time 93657189 ps
CPU time 1 seconds
Started Apr 21 01:39:28 PM PDT 24
Finished Apr 21 01:39:29 PM PDT 24
Peak memory 199272 kb
Host smart-73e2da32-1a67-4c2e-8539-118586563ac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609942666 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3609942666
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3408772687
Short name T449
Test name
Test status
Simulation time 159696205715 ps
CPU time 451.89 seconds
Started Apr 21 01:39:28 PM PDT 24
Finished Apr 21 01:47:00 PM PDT 24
Peak memory 199740 kb
Host smart-4fa721ed-0a86-427a-9e10-34cc35eeeced
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408772687 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3408772687
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.154400000
Short name T137
Test name
Test status
Simulation time 21666097146 ps
CPU time 90.17 seconds
Started Apr 21 01:39:23 PM PDT 24
Finished Apr 21 01:40:54 PM PDT 24
Peak memory 199720 kb
Host smart-cc3c2e87-ed64-4b74-bdef-c0d8a2c6b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154400000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.154400000
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3902621320
Short name T127
Test name
Test status
Simulation time 41898683 ps
CPU time 0.56 seconds
Started Apr 21 01:39:30 PM PDT 24
Finished Apr 21 01:39:30 PM PDT 24
Peak memory 195248 kb
Host smart-a2e3874e-f509-4796-b246-4c97c9196af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902621320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3902621320
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3656852164
Short name T572
Test name
Test status
Simulation time 1330683442 ps
CPU time 42.32 seconds
Started Apr 21 01:39:32 PM PDT 24
Finished Apr 21 01:40:15 PM PDT 24
Peak memory 207832 kb
Host smart-fcbce3ea-0a41-443f-b45b-f20d98639057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656852164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3656852164
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1900980409
Short name T277
Test name
Test status
Simulation time 8668144142 ps
CPU time 32.38 seconds
Started Apr 21 01:39:28 PM PDT 24
Finished Apr 21 01:40:01 PM PDT 24
Peak memory 199744 kb
Host smart-3b76cee5-50d9-4e7d-a1b4-37c8f6aa6fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900980409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1900980409
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1844669780
Short name T334
Test name
Test status
Simulation time 5202872153 ps
CPU time 47.06 seconds
Started Apr 21 01:39:29 PM PDT 24
Finished Apr 21 01:40:16 PM PDT 24
Peak memory 199780 kb
Host smart-f44452ec-5d56-44e2-9294-92ffb9d541cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844669780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1844669780
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2941118760
Short name T506
Test name
Test status
Simulation time 13443929921 ps
CPU time 160.99 seconds
Started Apr 21 01:39:32 PM PDT 24
Finished Apr 21 01:42:13 PM PDT 24
Peak memory 199764 kb
Host smart-58325e34-eb3b-411c-b490-09c063826423
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941118760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2941118760
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3784674248
Short name T320
Test name
Test status
Simulation time 1723581524 ps
CPU time 52.49 seconds
Started Apr 21 01:39:31 PM PDT 24
Finished Apr 21 01:40:24 PM PDT 24
Peak memory 199628 kb
Host smart-4e734d0c-1768-439a-a071-9f90dc8f8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784674248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3784674248
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1268455540
Short name T118
Test name
Test status
Simulation time 105268343 ps
CPU time 3.23 seconds
Started Apr 21 01:39:31 PM PDT 24
Finished Apr 21 01:39:34 PM PDT 24
Peak memory 199636 kb
Host smart-ecdff73e-eb8c-462f-8ef6-12a5ebfc6cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268455540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1268455540
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2146955813
Short name T74
Test name
Test status
Simulation time 58459306471 ps
CPU time 764.22 seconds
Started Apr 21 01:39:33 PM PDT 24
Finished Apr 21 01:52:17 PM PDT 24
Peak memory 240708 kb
Host smart-508d5b02-9687-4f23-80d2-b15c083dec4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146955813 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2146955813
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2744309979
Short name T249
Test name
Test status
Simulation time 153790126 ps
CPU time 1.36 seconds
Started Apr 21 01:39:32 PM PDT 24
Finished Apr 21 01:39:34 PM PDT 24
Peak memory 199632 kb
Host smart-d3048de9-4791-43c2-8f9b-b055ec3b28f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744309979 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2744309979
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3531418705
Short name T414
Test name
Test status
Simulation time 39637518800 ps
CPU time 494.56 seconds
Started Apr 21 01:39:32 PM PDT 24
Finished Apr 21 01:47:47 PM PDT 24
Peak memory 199744 kb
Host smart-ff66031f-015b-486a-9321-c8fed0d5339f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531418705 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3531418705
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2211324185
Short name T520
Test name
Test status
Simulation time 4058363757 ps
CPU time 45.24 seconds
Started Apr 21 01:39:32 PM PDT 24
Finished Apr 21 01:40:18 PM PDT 24
Peak memory 199752 kb
Host smart-99de6a78-64be-4c25-a08c-464186abd5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211324185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2211324185
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.139583044
Short name T477
Test name
Test status
Simulation time 15087928 ps
CPU time 0.58 seconds
Started Apr 21 01:39:39 PM PDT 24
Finished Apr 21 01:39:40 PM PDT 24
Peak memory 195108 kb
Host smart-3ecf516a-dc07-4a99-90ef-fb428860915e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139583044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.139583044
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2646495029
Short name T335
Test name
Test status
Simulation time 678550318 ps
CPU time 11.62 seconds
Started Apr 21 01:39:34 PM PDT 24
Finished Apr 21 01:39:45 PM PDT 24
Peak memory 215012 kb
Host smart-53c91d76-6ad2-4614-b3a5-9e90cad82bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646495029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2646495029
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2144965172
Short name T99
Test name
Test status
Simulation time 449501653 ps
CPU time 19.97 seconds
Started Apr 21 01:39:35 PM PDT 24
Finished Apr 21 01:39:55 PM PDT 24
Peak memory 199568 kb
Host smart-f6d9acdc-9090-469c-ba28-48fd0ec38565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144965172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2144965172
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3577007004
Short name T436
Test name
Test status
Simulation time 477125941 ps
CPU time 6.52 seconds
Started Apr 21 01:39:33 PM PDT 24
Finished Apr 21 01:39:39 PM PDT 24
Peak memory 199576 kb
Host smart-0836d82d-4b66-4b96-9304-c7643119d34e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577007004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3577007004
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1579686846
Short name T534
Test name
Test status
Simulation time 14831441169 ps
CPU time 89.33 seconds
Started Apr 21 01:39:34 PM PDT 24
Finished Apr 21 01:41:04 PM PDT 24
Peak memory 199760 kb
Host smart-189abc1a-266a-4b34-a540-f5ae103e526a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579686846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1579686846
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4199704085
Short name T447
Test name
Test status
Simulation time 5491990653 ps
CPU time 105.06 seconds
Started Apr 21 01:39:33 PM PDT 24
Finished Apr 21 01:41:19 PM PDT 24
Peak memory 199760 kb
Host smart-69ef4f67-7b75-4652-bfa8-ddf6a63cc1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199704085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4199704085
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3684332743
Short name T81
Test name
Test status
Simulation time 124667513 ps
CPU time 3.86 seconds
Started Apr 21 01:39:32 PM PDT 24
Finished Apr 21 01:39:36 PM PDT 24
Peak memory 199596 kb
Host smart-6134868e-33b5-4710-918c-a9f202002e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684332743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3684332743
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3621497027
Short name T73
Test name
Test status
Simulation time 68476592154 ps
CPU time 837.1 seconds
Started Apr 21 01:39:36 PM PDT 24
Finished Apr 21 01:53:34 PM PDT 24
Peak memory 207956 kb
Host smart-3bfe569f-9302-422d-bca9-fc60bad19fd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621497027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3621497027
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.114751677
Short name T527
Test name
Test status
Simulation time 27910307 ps
CPU time 1.05 seconds
Started Apr 21 01:39:37 PM PDT 24
Finished Apr 21 01:39:38 PM PDT 24
Peak memory 198512 kb
Host smart-e446b4f7-fb19-4e00-8ab8-e8528d6a7a97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114751677 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.114751677
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.429271740
Short name T503
Test name
Test status
Simulation time 38620367943 ps
CPU time 471.9 seconds
Started Apr 21 01:39:35 PM PDT 24
Finished Apr 21 01:47:27 PM PDT 24
Peak memory 199688 kb
Host smart-148352ab-1a87-458f-a546-18adab479490
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429271740 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.429271740
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2208704430
Short name T372
Test name
Test status
Simulation time 4727991952 ps
CPU time 55.47 seconds
Started Apr 21 01:39:34 PM PDT 24
Finished Apr 21 01:40:30 PM PDT 24
Peak memory 199756 kb
Host smart-a3e426ba-00a4-4238-b40b-f3f1937c66a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208704430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2208704430
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3584435872
Short name T467
Test name
Test status
Simulation time 23091474 ps
CPU time 0.57 seconds
Started Apr 21 01:39:46 PM PDT 24
Finished Apr 21 01:39:47 PM PDT 24
Peak memory 195204 kb
Host smart-eefc6940-9168-4a24-9b84-ec55e97654da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584435872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3584435872
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3135571998
Short name T590
Test name
Test status
Simulation time 2281115644 ps
CPU time 40.87 seconds
Started Apr 21 01:39:40 PM PDT 24
Finished Apr 21 01:40:21 PM PDT 24
Peak memory 231572 kb
Host smart-e39153dc-0490-4006-af1d-3dd9bc122163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135571998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3135571998
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2578612280
Short name T225
Test name
Test status
Simulation time 2798686786 ps
CPU time 19.19 seconds
Started Apr 21 01:39:42 PM PDT 24
Finished Apr 21 01:40:01 PM PDT 24
Peak memory 199784 kb
Host smart-22babef5-d279-44b1-bb51-7be272bada74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578612280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2578612280
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.574265272
Short name T353
Test name
Test status
Simulation time 1559174795 ps
CPU time 47.57 seconds
Started Apr 21 01:39:41 PM PDT 24
Finished Apr 21 01:40:29 PM PDT 24
Peak memory 199620 kb
Host smart-5be7b799-7dcd-481c-b868-6c1da33495b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574265272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.574265272
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3613777066
Short name T440
Test name
Test status
Simulation time 238630052 ps
CPU time 13.1 seconds
Started Apr 21 01:39:42 PM PDT 24
Finished Apr 21 01:39:56 PM PDT 24
Peak memory 199592 kb
Host smart-38720c5d-0c00-4601-ae7b-872bdb5c1aa5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613777066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3613777066
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3058993320
Short name T233
Test name
Test status
Simulation time 798459643 ps
CPU time 14.33 seconds
Started Apr 21 01:39:40 PM PDT 24
Finished Apr 21 01:39:54 PM PDT 24
Peak memory 199596 kb
Host smart-fd074c10-a684-46cb-b5fd-a089fe4d7a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058993320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3058993320
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2478422054
Short name T315
Test name
Test status
Simulation time 319874691 ps
CPU time 3.21 seconds
Started Apr 21 01:39:39 PM PDT 24
Finished Apr 21 01:39:43 PM PDT 24
Peak memory 199640 kb
Host smart-77cff433-fa65-4dfa-8f43-4e4055fb9c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478422054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2478422054
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1348651035
Short name T69
Test name
Test status
Simulation time 481757729002 ps
CPU time 1742.41 seconds
Started Apr 21 01:39:43 PM PDT 24
Finished Apr 21 02:08:46 PM PDT 24
Peak memory 199672 kb
Host smart-5ad0e346-bace-4fca-b9f0-f0faf6c989e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348651035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1348651035
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1667376994
Short name T600
Test name
Test status
Simulation time 49643540 ps
CPU time 0.95 seconds
Started Apr 21 01:39:41 PM PDT 24
Finished Apr 21 01:39:42 PM PDT 24
Peak memory 197896 kb
Host smart-071d7328-c6f4-4f87-8925-41f81ef6663e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667376994 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1667376994
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.955837169
Short name T265
Test name
Test status
Simulation time 28568159308 ps
CPU time 389.92 seconds
Started Apr 21 01:39:42 PM PDT 24
Finished Apr 21 01:46:12 PM PDT 24
Peak memory 199732 kb
Host smart-c08e5813-5cce-42ad-b5ab-5cb0a59302a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955837169 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.955837169
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1414516452
Short name T473
Test name
Test status
Simulation time 8895578814 ps
CPU time 102.78 seconds
Started Apr 21 01:39:44 PM PDT 24
Finished Apr 21 01:41:27 PM PDT 24
Peak memory 199704 kb
Host smart-33a4523a-4b26-4c63-b018-134a24a54a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414516452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1414516452
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.3828683833
Short name T66
Test name
Test status
Simulation time 48920656968 ps
CPU time 1636.5 seconds
Started Apr 21 01:47:30 PM PDT 24
Finished Apr 21 02:14:46 PM PDT 24
Peak memory 226432 kb
Host smart-8150ac9e-4376-434e-a38a-c38da82f7fdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828683833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.3828683833
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1826887331
Short name T330
Test name
Test status
Simulation time 13946229 ps
CPU time 0.57 seconds
Started Apr 21 01:39:51 PM PDT 24
Finished Apr 21 01:39:52 PM PDT 24
Peak memory 194164 kb
Host smart-ff67960f-578e-4606-8f5e-368dd1fe84e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826887331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1826887331
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2928818387
Short name T480
Test name
Test status
Simulation time 6076744998 ps
CPU time 39.33 seconds
Started Apr 21 01:39:46 PM PDT 24
Finished Apr 21 01:40:26 PM PDT 24
Peak memory 216096 kb
Host smart-d52e0b47-06e3-4a40-b565-cf287bd9378f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928818387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2928818387
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2559059223
Short name T545
Test name
Test status
Simulation time 1104507349 ps
CPU time 53.5 seconds
Started Apr 21 01:39:52 PM PDT 24
Finished Apr 21 01:40:45 PM PDT 24
Peak memory 199628 kb
Host smart-bc23f6f7-8ec5-463b-a207-5a0928b09402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559059223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2559059223
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2600117584
Short name T468
Test name
Test status
Simulation time 1148714802 ps
CPU time 65.44 seconds
Started Apr 21 01:39:48 PM PDT 24
Finished Apr 21 01:40:53 PM PDT 24
Peak memory 199632 kb
Host smart-bdb8256b-fc01-4fc2-bb7e-cf39f2646c79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600117584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2600117584
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.392511503
Short name T502
Test name
Test status
Simulation time 1338424071 ps
CPU time 70.04 seconds
Started Apr 21 01:39:48 PM PDT 24
Finished Apr 21 01:40:58 PM PDT 24
Peak memory 199564 kb
Host smart-fe591f75-bbcb-49f7-bc71-980090391f99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392511503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.392511503
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1352103624
Short name T512
Test name
Test status
Simulation time 3148377753 ps
CPU time 34.79 seconds
Started Apr 21 01:39:44 PM PDT 24
Finished Apr 21 01:40:19 PM PDT 24
Peak memory 199736 kb
Host smart-c8d08af5-4a5a-4f32-badf-85df0a664fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352103624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1352103624
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1326962433
Short name T141
Test name
Test status
Simulation time 63437070 ps
CPU time 0.8 seconds
Started Apr 21 01:39:46 PM PDT 24
Finished Apr 21 01:39:47 PM PDT 24
Peak memory 198472 kb
Host smart-5f61e26b-a492-44ca-bd7b-2a2a44a12bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326962433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1326962433
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.112881631
Short name T71
Test name
Test status
Simulation time 487784329844 ps
CPU time 1268.76 seconds
Started Apr 21 01:39:48 PM PDT 24
Finished Apr 21 02:00:58 PM PDT 24
Peak memory 199712 kb
Host smart-1122c056-ff24-442a-87d2-449bdf3c4237
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112881631 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.112881631
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3689467439
Short name T584
Test name
Test status
Simulation time 141800085 ps
CPU time 1.14 seconds
Started Apr 21 01:39:48 PM PDT 24
Finished Apr 21 01:39:50 PM PDT 24
Peak memory 199620 kb
Host smart-e984a4e5-2bcb-4147-a590-9fce5b8cc2b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689467439 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3689467439
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2213754192
Short name T602
Test name
Test status
Simulation time 166565248552 ps
CPU time 476.1 seconds
Started Apr 21 01:39:48 PM PDT 24
Finished Apr 21 01:47:45 PM PDT 24
Peak memory 199716 kb
Host smart-26243f34-b9d4-4315-b5b4-4ddcb121696b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213754192 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2213754192
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3087938458
Short name T452
Test name
Test status
Simulation time 2655932541 ps
CPU time 19.62 seconds
Started Apr 21 01:39:50 PM PDT 24
Finished Apr 21 01:40:10 PM PDT 24
Peak memory 199748 kb
Host smart-a08691dd-a5ea-4d0a-92f4-6ecf0818b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087938458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3087938458
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1186796125
Short name T283
Test name
Test status
Simulation time 24837037 ps
CPU time 0.56 seconds
Started Apr 21 01:39:56 PM PDT 24
Finished Apr 21 01:39:57 PM PDT 24
Peak memory 195180 kb
Host smart-a5fdfe81-1c23-411b-8bd1-2824e342431c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186796125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1186796125
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.379943434
Short name T169
Test name
Test status
Simulation time 1200016561 ps
CPU time 19.57 seconds
Started Apr 21 01:39:54 PM PDT 24
Finished Apr 21 01:40:14 PM PDT 24
Peak memory 199492 kb
Host smart-6f5c540b-a54a-4580-988b-88c6b044bb28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379943434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.379943434
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.854851620
Short name T296
Test name
Test status
Simulation time 2382416267 ps
CPU time 28.08 seconds
Started Apr 21 01:39:53 PM PDT 24
Finished Apr 21 01:40:21 PM PDT 24
Peak memory 199692 kb
Host smart-8e8f79e7-5778-4127-969c-2666f7836cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854851620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.854851620
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1706978571
Short name T553
Test name
Test status
Simulation time 12357157204 ps
CPU time 65.87 seconds
Started Apr 21 01:39:55 PM PDT 24
Finished Apr 21 01:41:01 PM PDT 24
Peak memory 199680 kb
Host smart-a688f429-ac8a-4f61-8964-fcc194964fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706978571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1706978571
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4131220406
Short name T190
Test name
Test status
Simulation time 54861402152 ps
CPU time 67.08 seconds
Started Apr 21 01:39:55 PM PDT 24
Finished Apr 21 01:41:03 PM PDT 24
Peak memory 199712 kb
Host smart-053eff92-aee7-40e0-a8de-62174ab963c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131220406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4131220406
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1865902918
Short name T554
Test name
Test status
Simulation time 2811696128 ps
CPU time 16.5 seconds
Started Apr 21 01:39:54 PM PDT 24
Finished Apr 21 01:40:11 PM PDT 24
Peak memory 199744 kb
Host smart-d1529ad6-1825-4ab1-a6a0-62f48ce83b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865902918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1865902918
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2012033804
Short name T530
Test name
Test status
Simulation time 1896910656 ps
CPU time 5.63 seconds
Started Apr 21 01:39:53 PM PDT 24
Finished Apr 21 01:39:59 PM PDT 24
Peak memory 199636 kb
Host smart-d0a6754d-f2ab-49ab-a8a4-979b732569f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012033804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2012033804
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2125714998
Short name T248
Test name
Test status
Simulation time 804933134790 ps
CPU time 1048.59 seconds
Started Apr 21 01:39:57 PM PDT 24
Finished Apr 21 01:57:26 PM PDT 24
Peak memory 243988 kb
Host smart-f1d29bad-3008-4148-a9e5-02ad96f44342
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125714998 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2125714998
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3709762921
Short name T399
Test name
Test status
Simulation time 659124881 ps
CPU time 1.02 seconds
Started Apr 21 01:39:56 PM PDT 24
Finished Apr 21 01:39:58 PM PDT 24
Peak memory 199004 kb
Host smart-a356d879-0beb-4ee8-a6ae-61f50bba64b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709762921 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3709762921
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2509921201
Short name T535
Test name
Test status
Simulation time 57158457306 ps
CPU time 461.14 seconds
Started Apr 21 01:39:57 PM PDT 24
Finished Apr 21 01:47:38 PM PDT 24
Peak memory 199676 kb
Host smart-4fadbbec-1218-4e8d-8ffd-5993886459df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509921201 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2509921201
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3122843917
Short name T558
Test name
Test status
Simulation time 92297215414 ps
CPU time 90.65 seconds
Started Apr 21 01:39:58 PM PDT 24
Finished Apr 21 01:41:29 PM PDT 24
Peak memory 199724 kb
Host smart-fe493fdf-50ed-43bf-8fb4-b196ff5eb183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122843917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3122843917
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.278724754
Short name T42
Test name
Test status
Simulation time 287828315742 ps
CPU time 1636.36 seconds
Started Apr 21 01:47:53 PM PDT 24
Finished Apr 21 02:15:09 PM PDT 24
Peak memory 246324 kb
Host smart-93b07808-76a0-435c-b85d-cb5ca935385f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278724754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.278724754
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4088932664
Short name T389
Test name
Test status
Simulation time 14612252 ps
CPU time 0.58 seconds
Started Apr 21 01:40:07 PM PDT 24
Finished Apr 21 01:40:08 PM PDT 24
Peak memory 195220 kb
Host smart-aff94c2f-9500-4488-ac0c-14ffc4f3d269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088932664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4088932664
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1730476586
Short name T592
Test name
Test status
Simulation time 5891155554 ps
CPU time 57.44 seconds
Started Apr 21 01:40:00 PM PDT 24
Finished Apr 21 01:40:57 PM PDT 24
Peak memory 226284 kb
Host smart-c385e718-e41e-43ae-b066-4d516107e2ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730476586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1730476586
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3678582506
Short name T589
Test name
Test status
Simulation time 742386578 ps
CPU time 13.7 seconds
Started Apr 21 01:40:00 PM PDT 24
Finished Apr 21 01:40:14 PM PDT 24
Peak memory 199616 kb
Host smart-1ab849f2-7d6e-45de-a006-838ba3ed6742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678582506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3678582506
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4050311137
Short name T152
Test name
Test status
Simulation time 4557666691 ps
CPU time 130.78 seconds
Started Apr 21 01:40:01 PM PDT 24
Finished Apr 21 01:42:12 PM PDT 24
Peak memory 199732 kb
Host smart-28786d67-3da2-4b7b-9ce1-76edba0505e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050311137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4050311137
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2961429739
Short name T23
Test name
Test status
Simulation time 13826396721 ps
CPU time 187.17 seconds
Started Apr 21 01:40:08 PM PDT 24
Finished Apr 21 01:43:15 PM PDT 24
Peak memory 199724 kb
Host smart-4918da89-1416-4d72-b640-f3bc7178ba7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961429739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2961429739
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1917643811
Short name T273
Test name
Test status
Simulation time 2139503277 ps
CPU time 42.21 seconds
Started Apr 21 01:40:00 PM PDT 24
Finished Apr 21 01:40:43 PM PDT 24
Peak memory 199636 kb
Host smart-2bafb7c1-7c81-4ddd-b991-36698f2d4040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917643811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1917643811
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1310522501
Short name T116
Test name
Test status
Simulation time 155314092 ps
CPU time 2.24 seconds
Started Apr 21 01:40:02 PM PDT 24
Finished Apr 21 01:40:04 PM PDT 24
Peak memory 199552 kb
Host smart-9386aa46-3f97-48e2-9335-720e0c7d8599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310522501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1310522501
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1384610789
Short name T415
Test name
Test status
Simulation time 43599175433 ps
CPU time 676.95 seconds
Started Apr 21 01:40:07 PM PDT 24
Finished Apr 21 01:51:24 PM PDT 24
Peak memory 235052 kb
Host smart-bccdfb86-b963-4c41-a591-4a8ad0818b92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384610789 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1384610789
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3757796630
Short name T326
Test name
Test status
Simulation time 52942410 ps
CPU time 0.96 seconds
Started Apr 21 01:40:06 PM PDT 24
Finished Apr 21 01:40:07 PM PDT 24
Peak memory 198480 kb
Host smart-7b1ce651-f3b1-4ff7-8116-f68af52579e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757796630 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3757796630
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.687213404
Short name T174
Test name
Test status
Simulation time 31275886434 ps
CPU time 420.19 seconds
Started Apr 21 01:40:06 PM PDT 24
Finished Apr 21 01:47:06 PM PDT 24
Peak memory 199712 kb
Host smart-131a5152-1762-4611-8b69-62bce69d9dbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687213404 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.687213404
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.592001671
Short name T496
Test name
Test status
Simulation time 14519259595 ps
CPU time 88.91 seconds
Started Apr 21 01:40:07 PM PDT 24
Finished Apr 21 01:41:36 PM PDT 24
Peak memory 199692 kb
Host smart-eb365d25-7d08-4755-bf39-97832342d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592001671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.592001671
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.1797576596
Short name T9
Test name
Test status
Simulation time 618812697955 ps
CPU time 3757.82 seconds
Started Apr 21 01:48:01 PM PDT 24
Finished Apr 21 02:50:40 PM PDT 24
Peak memory 261860 kb
Host smart-498b2532-0495-462c-8863-d55704a928a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797576596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.1797576596
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2657748597
Short name T229
Test name
Test status
Simulation time 44554260 ps
CPU time 0.59 seconds
Started Apr 21 01:40:16 PM PDT 24
Finished Apr 21 01:40:16 PM PDT 24
Peak memory 195124 kb
Host smart-4341154f-2bf0-4d26-a4b1-522dda70bd73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657748597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2657748597
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2481725330
Short name T52
Test name
Test status
Simulation time 2840363570 ps
CPU time 54.62 seconds
Started Apr 21 01:40:09 PM PDT 24
Finished Apr 21 01:41:04 PM PDT 24
Peak memory 232192 kb
Host smart-693bdc94-661e-4697-bc32-b7aabe5ec260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481725330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2481725330
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.927234089
Short name T25
Test name
Test status
Simulation time 6382609304 ps
CPU time 46.65 seconds
Started Apr 21 01:40:09 PM PDT 24
Finished Apr 21 01:40:56 PM PDT 24
Peak memory 199712 kb
Host smart-6a1b3fe6-77dc-4305-aed6-6ba203bb1ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927234089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.927234089
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2304894792
Short name T465
Test name
Test status
Simulation time 8653287715 ps
CPU time 125 seconds
Started Apr 21 01:40:11 PM PDT 24
Finished Apr 21 01:42:16 PM PDT 24
Peak memory 199772 kb
Host smart-41ab6a46-5633-45f6-adfa-81d00677aa39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304894792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2304894792
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1172525709
Short name T549
Test name
Test status
Simulation time 4835582516 ps
CPU time 79.26 seconds
Started Apr 21 01:40:13 PM PDT 24
Finished Apr 21 01:41:32 PM PDT 24
Peak memory 199728 kb
Host smart-fe27da47-5de8-4f8e-af76-c623b816155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172525709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1172525709
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1321878782
Short name T582
Test name
Test status
Simulation time 1173971603 ps
CPU time 2.24 seconds
Started Apr 21 01:40:10 PM PDT 24
Finished Apr 21 01:40:12 PM PDT 24
Peak memory 199636 kb
Host smart-edd73753-9ee4-41fb-9717-b3ea8105d4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321878782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1321878782
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3684793692
Short name T318
Test name
Test status
Simulation time 61435651433 ps
CPU time 183.46 seconds
Started Apr 21 01:40:13 PM PDT 24
Finished Apr 21 01:43:16 PM PDT 24
Peak memory 199764 kb
Host smart-3a2c7d1a-e425-4535-9c89-cde5dcb89792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684793692 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3684793692
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.2087286879
Short name T68
Test name
Test status
Simulation time 170133342329 ps
CPU time 2801.98 seconds
Started Apr 21 01:40:15 PM PDT 24
Finished Apr 21 02:26:57 PM PDT 24
Peak memory 260312 kb
Host smart-6eb64c16-f405-49ab-90d4-8e6a5940745d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087286879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.2087286879
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1114189665
Short name T410
Test name
Test status
Simulation time 48699252 ps
CPU time 0.96 seconds
Started Apr 21 01:40:14 PM PDT 24
Finished Apr 21 01:40:15 PM PDT 24
Peak memory 198892 kb
Host smart-98ea9737-885a-4db4-8ba3-cbbe20966ba5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114189665 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1114189665
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.4281893626
Short name T232
Test name
Test status
Simulation time 144673683248 ps
CPU time 487.29 seconds
Started Apr 21 01:40:14 PM PDT 24
Finished Apr 21 01:48:22 PM PDT 24
Peak memory 199708 kb
Host smart-1eabd0a9-b82d-4ef7-bc18-2f688df0cae5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281893626 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.4281893626
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1005844631
Short name T458
Test name
Test status
Simulation time 4907632453 ps
CPU time 35.23 seconds
Started Apr 21 01:40:13 PM PDT 24
Finished Apr 21 01:40:49 PM PDT 24
Peak memory 199788 kb
Host smart-c0ec8bc6-1ab6-4125-8933-7912db238860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005844631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1005844631
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.3781252504
Short name T7
Test name
Test status
Simulation time 40953596660 ps
CPU time 1300.34 seconds
Started Apr 21 01:48:27 PM PDT 24
Finished Apr 21 02:10:08 PM PDT 24
Peak memory 246216 kb
Host smart-a2eee728-c0ef-4423-8863-c47fe48e1dc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781252504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.3781252504
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.4141474076
Short name T333
Test name
Test status
Simulation time 42186759 ps
CPU time 0.53 seconds
Started Apr 21 01:40:25 PM PDT 24
Finished Apr 21 01:40:26 PM PDT 24
Peak memory 194832 kb
Host smart-435ee94f-af9e-498f-b20f-16405d2129ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141474076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.4141474076
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3400010808
Short name T599
Test name
Test status
Simulation time 3468179867 ps
CPU time 30.98 seconds
Started Apr 21 01:40:17 PM PDT 24
Finished Apr 21 01:40:48 PM PDT 24
Peak memory 215996 kb
Host smart-b4c69078-f5ad-4a54-aba0-aed2b3fa3e36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400010808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3400010808
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.422209467
Short name T425
Test name
Test status
Simulation time 3081678341 ps
CPU time 11.59 seconds
Started Apr 21 01:40:22 PM PDT 24
Finished Apr 21 01:40:34 PM PDT 24
Peak memory 199704 kb
Host smart-d41921df-8698-43b0-9509-11983f5058a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422209467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.422209467
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2829825073
Short name T578
Test name
Test status
Simulation time 185512646 ps
CPU time 5.7 seconds
Started Apr 21 01:40:17 PM PDT 24
Finished Apr 21 01:40:23 PM PDT 24
Peak memory 199620 kb
Host smart-50df8804-e334-42c3-bac8-75c66a04b7ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829825073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2829825073
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3401043131
Short name T44
Test name
Test status
Simulation time 7723688472 ps
CPU time 210.37 seconds
Started Apr 21 01:40:22 PM PDT 24
Finished Apr 21 01:43:53 PM PDT 24
Peak memory 199756 kb
Host smart-c2764e4c-d2b5-4fe6-b230-6a9af8487b7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401043131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3401043131
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3851365687
Short name T384
Test name
Test status
Simulation time 7949773644 ps
CPU time 107.09 seconds
Started Apr 21 01:40:17 PM PDT 24
Finished Apr 21 01:42:04 PM PDT 24
Peak memory 199748 kb
Host smart-3959a95e-e775-43e8-847c-0e2ee059641f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851365687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3851365687
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2323417964
Short name T149
Test name
Test status
Simulation time 86217930 ps
CPU time 0.93 seconds
Started Apr 21 01:40:15 PM PDT 24
Finished Apr 21 01:40:16 PM PDT 24
Peak memory 199036 kb
Host smart-9ad8db56-34a8-4ad6-b0d2-84ca9a96a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323417964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2323417964
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3200719430
Short name T420
Test name
Test status
Simulation time 118140395235 ps
CPU time 1427.22 seconds
Started Apr 21 01:40:21 PM PDT 24
Finished Apr 21 02:04:09 PM PDT 24
Peak memory 199756 kb
Host smart-a171eb7e-38be-435a-be91-cecbbc14de6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200719430 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3200719430
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1859521300
Short name T135
Test name
Test status
Simulation time 177261407 ps
CPU time 0.99 seconds
Started Apr 21 01:40:22 PM PDT 24
Finished Apr 21 01:40:24 PM PDT 24
Peak memory 198732 kb
Host smart-cd3bcfc5-603f-4a52-9e72-d1a87065a192
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859521300 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1859521300
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2803168415
Short name T284
Test name
Test status
Simulation time 164878623431 ps
CPU time 511.45 seconds
Started Apr 21 01:40:22 PM PDT 24
Finished Apr 21 01:48:54 PM PDT 24
Peak memory 199732 kb
Host smart-473a3961-0b0a-4e78-a0e9-facca4600fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803168415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2803168415
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3273864550
Short name T369
Test name
Test status
Simulation time 456566331 ps
CPU time 3.31 seconds
Started Apr 21 01:40:22 PM PDT 24
Finished Apr 21 01:40:25 PM PDT 24
Peak memory 199660 kb
Host smart-c28bbcc8-a571-445b-8296-ef2f5acc54fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273864550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3273864550
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2600883
Short name T134
Test name
Test status
Simulation time 32743177 ps
CPU time 0.58 seconds
Started Apr 21 01:40:31 PM PDT 24
Finished Apr 21 01:40:32 PM PDT 24
Peak memory 194876 kb
Host smart-43f8c446-1e5d-4318-b99e-fbc3fbb33f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2600883
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3568163803
Short name T51
Test name
Test status
Simulation time 39461357 ps
CPU time 1.29 seconds
Started Apr 21 01:40:26 PM PDT 24
Finished Apr 21 01:40:27 PM PDT 24
Peak memory 199584 kb
Host smart-9b61ef0e-84a8-4ad1-891b-70fec9c5b8f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568163803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3568163803
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1801443568
Short name T305
Test name
Test status
Simulation time 4537148799 ps
CPU time 32.25 seconds
Started Apr 21 01:40:28 PM PDT 24
Finished Apr 21 01:41:00 PM PDT 24
Peak memory 199720 kb
Host smart-794ff891-d904-44bb-9725-f2ee6d62187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801443568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1801443568
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2430561389
Short name T433
Test name
Test status
Simulation time 1024287778 ps
CPU time 58.15 seconds
Started Apr 21 01:40:26 PM PDT 24
Finished Apr 21 01:41:25 PM PDT 24
Peak memory 199648 kb
Host smart-a452e809-3c78-41eb-95f9-60e618edf798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430561389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2430561389
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3345288081
Short name T478
Test name
Test status
Simulation time 68648671673 ps
CPU time 104.96 seconds
Started Apr 21 01:40:31 PM PDT 24
Finished Apr 21 01:42:16 PM PDT 24
Peak memory 199712 kb
Host smart-8b52f1cb-4854-4760-ad8b-c479a28104d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345288081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3345288081
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.291536613
Short name T514
Test name
Test status
Simulation time 1307341698 ps
CPU time 16.43 seconds
Started Apr 21 01:40:25 PM PDT 24
Finished Apr 21 01:40:42 PM PDT 24
Peak memory 199588 kb
Host smart-7142eae8-df20-45d9-94ea-950956706a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291536613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.291536613
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3874955550
Short name T401
Test name
Test status
Simulation time 1900140893 ps
CPU time 6.7 seconds
Started Apr 21 01:40:27 PM PDT 24
Finished Apr 21 01:40:34 PM PDT 24
Peak memory 199596 kb
Host smart-b624c2ce-7399-41c8-b401-a6def7bb156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874955550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3874955550
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.710113546
Short name T557
Test name
Test status
Simulation time 246039458655 ps
CPU time 863.83 seconds
Started Apr 21 01:40:30 PM PDT 24
Finished Apr 21 01:54:54 PM PDT 24
Peak memory 231632 kb
Host smart-c5fcf0fe-8de3-47be-8912-c133ab2e0e4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710113546 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.710113546
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.156426330
Short name T200
Test name
Test status
Simulation time 70159664 ps
CPU time 1.19 seconds
Started Apr 21 01:40:31 PM PDT 24
Finished Apr 21 01:40:32 PM PDT 24
Peak memory 199248 kb
Host smart-89778595-d98b-444a-91e8-6e453814159c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156426330 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.156426330
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3898883340
Short name T356
Test name
Test status
Simulation time 16328716253 ps
CPU time 455.21 seconds
Started Apr 21 01:40:27 PM PDT 24
Finished Apr 21 01:48:03 PM PDT 24
Peak memory 199696 kb
Host smart-7d6b63e8-f196-40cf-960c-f3509ca1761f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898883340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3898883340
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.191841657
Short name T544
Test name
Test status
Simulation time 8838868486 ps
CPU time 28.21 seconds
Started Apr 21 01:40:30 PM PDT 24
Finished Apr 21 01:40:59 PM PDT 24
Peak memory 199712 kb
Host smart-67f67135-d447-4919-ba5d-f5c233579168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191841657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.191841657
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.2384417844
Short name T10
Test name
Test status
Simulation time 8979722307 ps
CPU time 473.06 seconds
Started Apr 21 01:49:09 PM PDT 24
Finished Apr 21 01:57:02 PM PDT 24
Peak memory 199944 kb
Host smart-57a07a49-8739-4163-890d-f88ea132cbb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384417844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.2384417844
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1523928281
Short name T601
Test name
Test status
Simulation time 13395052 ps
CPU time 0.56 seconds
Started Apr 21 01:38:58 PM PDT 24
Finished Apr 21 01:38:58 PM PDT 24
Peak memory 195088 kb
Host smart-8334bd18-4d2a-4433-825e-67b6a5246c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523928281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1523928281
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1663595979
Short name T243
Test name
Test status
Simulation time 859452592 ps
CPU time 31.92 seconds
Started Apr 21 01:38:54 PM PDT 24
Finished Apr 21 01:39:26 PM PDT 24
Peak memory 230672 kb
Host smart-d5b01aff-a8a0-4fcd-a17c-b6a505680367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663595979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1663595979
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.982511346
Short name T206
Test name
Test status
Simulation time 1610854407 ps
CPU time 22.19 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:39:18 PM PDT 24
Peak memory 199568 kb
Host smart-7146129e-551c-439f-9d95-88a455cbc1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982511346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.982511346
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3448976068
Short name T178
Test name
Test status
Simulation time 165647348 ps
CPU time 8.75 seconds
Started Apr 21 01:38:54 PM PDT 24
Finished Apr 21 01:39:03 PM PDT 24
Peak memory 199640 kb
Host smart-d1fc3c05-6927-4415-aa43-e1286ec345a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448976068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3448976068
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2794378059
Short name T541
Test name
Test status
Simulation time 98234947300 ps
CPU time 61.64 seconds
Started Apr 21 01:38:54 PM PDT 24
Finished Apr 21 01:39:56 PM PDT 24
Peak memory 199756 kb
Host smart-d5c9f6a8-bb26-49e4-860a-4aeab2325a47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794378059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2794378059
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.797469512
Short name T360
Test name
Test status
Simulation time 3088344944 ps
CPU time 88.85 seconds
Started Apr 21 01:38:58 PM PDT 24
Finished Apr 21 01:40:27 PM PDT 24
Peak memory 199716 kb
Host smart-d7998ea3-c1b0-412a-9474-547b2429f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797469512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.797469512
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.962337702
Short name T28
Test name
Test status
Simulation time 106492875 ps
CPU time 0.88 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:38:57 PM PDT 24
Peak memory 218196 kb
Host smart-1de6a4a3-94cb-49f1-9c14-d0730db5af5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962337702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.962337702
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.570619198
Short name T234
Test name
Test status
Simulation time 6311932172 ps
CPU time 7.06 seconds
Started Apr 21 01:38:51 PM PDT 24
Finished Apr 21 01:38:58 PM PDT 24
Peak memory 199704 kb
Host smart-54533d62-52dc-455e-b19e-12eb2e7cc329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570619198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.570619198
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3207827480
Short name T387
Test name
Test status
Simulation time 132644409140 ps
CPU time 473.46 seconds
Started Apr 21 01:38:53 PM PDT 24
Finished Apr 21 01:46:46 PM PDT 24
Peak memory 233644 kb
Host smart-b0ba8c58-70ac-4726-adbf-9068b85367df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207827480 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3207827480
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1434476247
Short name T197
Test name
Test status
Simulation time 69997940 ps
CPU time 1.05 seconds
Started Apr 21 01:38:54 PM PDT 24
Finished Apr 21 01:38:56 PM PDT 24
Peak memory 198936 kb
Host smart-fa9b3c9b-799d-4a5f-987f-23211f1ac800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434476247 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1434476247
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.844204721
Short name T498
Test name
Test status
Simulation time 110508430367 ps
CPU time 473.9 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:46:50 PM PDT 24
Peak memory 199708 kb
Host smart-567f1871-21cf-463b-b02f-aa1ccde3e5f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844204721 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.844204721
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2339161110
Short name T476
Test name
Test status
Simulation time 16925753438 ps
CPU time 37.54 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:39:34 PM PDT 24
Peak memory 199760 kb
Host smart-77ab4f63-6b5e-4d2b-95e0-1e954226a6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339161110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2339161110
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.20418564
Short name T34
Test name
Test status
Simulation time 10744876 ps
CPU time 0.55 seconds
Started Apr 21 01:40:41 PM PDT 24
Finished Apr 21 01:40:42 PM PDT 24
Peak memory 194168 kb
Host smart-89d6bdef-752e-47bf-9ee8-23189f1638f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20418564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.20418564
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2371646936
Short name T255
Test name
Test status
Simulation time 563086140 ps
CPU time 20.75 seconds
Started Apr 21 01:40:37 PM PDT 24
Finished Apr 21 01:40:58 PM PDT 24
Peak memory 213272 kb
Host smart-5b902645-d9c9-4a6c-8bd2-f44fd0ae75fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371646936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2371646936
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.816121300
Short name T417
Test name
Test status
Simulation time 7208419850 ps
CPU time 53.03 seconds
Started Apr 21 01:40:37 PM PDT 24
Finished Apr 21 01:41:31 PM PDT 24
Peak memory 199712 kb
Host smart-35ae00ed-6a37-4789-bfbe-d559d24b24f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816121300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.816121300
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2021390425
Short name T194
Test name
Test status
Simulation time 5780930429 ps
CPU time 75.97 seconds
Started Apr 21 01:40:36 PM PDT 24
Finished Apr 21 01:41:53 PM PDT 24
Peak memory 199744 kb
Host smart-f09bcd7f-628b-4d68-91dd-8312b9650c6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021390425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2021390425
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3263210331
Short name T46
Test name
Test status
Simulation time 5127118814 ps
CPU time 66.46 seconds
Started Apr 21 01:40:39 PM PDT 24
Finished Apr 21 01:41:45 PM PDT 24
Peak memory 199708 kb
Host smart-051d8887-773e-48d3-bd0e-c3a5744a5035
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263210331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3263210331
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.205620799
Short name T591
Test name
Test status
Simulation time 439176404 ps
CPU time 24.11 seconds
Started Apr 21 01:40:36 PM PDT 24
Finished Apr 21 01:41:00 PM PDT 24
Peak memory 199640 kb
Host smart-e48ee02a-2059-458b-b0fb-854f398b3b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205620799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.205620799
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1430984881
Short name T456
Test name
Test status
Simulation time 294189865 ps
CPU time 2.21 seconds
Started Apr 21 01:40:38 PM PDT 24
Finished Apr 21 01:40:40 PM PDT 24
Peak memory 199612 kb
Host smart-d02a4344-e7f1-44d6-8ff7-fc6d9e7c0ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430984881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1430984881
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2888108083
Short name T411
Test name
Test status
Simulation time 42403322435 ps
CPU time 104.04 seconds
Started Apr 21 01:40:42 PM PDT 24
Finished Apr 21 01:42:26 PM PDT 24
Peak memory 224304 kb
Host smart-b673e6eb-86e7-4afd-9289-719dd8d35338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888108083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2888108083
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3415377653
Short name T332
Test name
Test status
Simulation time 28037375 ps
CPU time 0.98 seconds
Started Apr 21 01:40:41 PM PDT 24
Finished Apr 21 01:40:42 PM PDT 24
Peak memory 199456 kb
Host smart-06387fb2-3c49-4b02-957e-f9e3eb088b9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415377653 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3415377653
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2663598944
Short name T112
Test name
Test status
Simulation time 36448366514 ps
CPU time 475.3 seconds
Started Apr 21 01:40:41 PM PDT 24
Finished Apr 21 01:48:36 PM PDT 24
Peak memory 199688 kb
Host smart-31802769-174b-4313-b153-582ac1404e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663598944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2663598944
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3198519704
Short name T216
Test name
Test status
Simulation time 873358194 ps
CPU time 13.89 seconds
Started Apr 21 01:40:40 PM PDT 24
Finished Apr 21 01:40:54 PM PDT 24
Peak memory 199592 kb
Host smart-518c76d8-f584-413b-bdf6-1481fcb23bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198519704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3198519704
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.84478327
Short name T364
Test name
Test status
Simulation time 23592122 ps
CPU time 0.55 seconds
Started Apr 21 01:40:52 PM PDT 24
Finished Apr 21 01:40:52 PM PDT 24
Peak memory 194908 kb
Host smart-b0703ccd-e517-490e-9637-281531d30b0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84478327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.84478327
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.97006866
Short name T455
Test name
Test status
Simulation time 2803447062 ps
CPU time 27.87 seconds
Started Apr 21 01:40:45 PM PDT 24
Finished Apr 21 01:41:13 PM PDT 24
Peak memory 232560 kb
Host smart-ecf13772-b583-46aa-bcab-f78fc6f6aa77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97006866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.97006866
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2168446304
Short name T358
Test name
Test status
Simulation time 424773765 ps
CPU time 9.07 seconds
Started Apr 21 01:40:45 PM PDT 24
Finished Apr 21 01:40:54 PM PDT 24
Peak memory 199616 kb
Host smart-ebf743a3-5dbf-4fd1-b5fa-cd274902a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168446304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2168446304
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3492979855
Short name T263
Test name
Test status
Simulation time 1010889738 ps
CPU time 55.14 seconds
Started Apr 21 01:40:44 PM PDT 24
Finished Apr 21 01:41:40 PM PDT 24
Peak memory 199656 kb
Host smart-c727d98c-35d4-42e2-8003-c00b5f64fab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492979855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3492979855
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1882237927
Short name T423
Test name
Test status
Simulation time 29410525025 ps
CPU time 176.69 seconds
Started Apr 21 01:40:48 PM PDT 24
Finished Apr 21 01:43:45 PM PDT 24
Peak memory 199792 kb
Host smart-df59e899-725f-4176-a240-817cae36dbb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882237927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1882237927
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1253095505
Short name T382
Test name
Test status
Simulation time 2219589774 ps
CPU time 17.56 seconds
Started Apr 21 01:40:47 PM PDT 24
Finished Apr 21 01:41:05 PM PDT 24
Peak memory 199692 kb
Host smart-0893a33c-3109-43e3-96ba-cfec0d263eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253095505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1253095505
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1687167590
Short name T241
Test name
Test status
Simulation time 63617148 ps
CPU time 1.1 seconds
Started Apr 21 01:40:46 PM PDT 24
Finished Apr 21 01:40:48 PM PDT 24
Peak memory 199224 kb
Host smart-1f5d5788-e824-45da-93fc-eb5aeac55b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687167590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1687167590
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1026971960
Short name T72
Test name
Test status
Simulation time 94314233893 ps
CPU time 1133.21 seconds
Started Apr 21 01:40:48 PM PDT 24
Finished Apr 21 01:59:42 PM PDT 24
Peak memory 199708 kb
Host smart-bc313eba-a90f-4ff5-b4ef-f357f1014ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026971960 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1026971960
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.187225833
Short name T551
Test name
Test status
Simulation time 238318157 ps
CPU time 1.17 seconds
Started Apr 21 01:40:48 PM PDT 24
Finished Apr 21 01:40:50 PM PDT 24
Peak memory 199652 kb
Host smart-cbbf5c68-5442-46b3-bb64-242606083049
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187225833 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.187225833
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.71360726
Short name T205
Test name
Test status
Simulation time 129701749678 ps
CPU time 432.69 seconds
Started Apr 21 01:40:49 PM PDT 24
Finished Apr 21 01:48:02 PM PDT 24
Peak memory 199776 kb
Host smart-7cf4bd14-219f-4821-ab69-36240d968175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71360726 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.71360726
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2664633878
Short name T338
Test name
Test status
Simulation time 3870482105 ps
CPU time 55.32 seconds
Started Apr 21 01:40:50 PM PDT 24
Finished Apr 21 01:41:45 PM PDT 24
Peak memory 199780 kb
Host smart-0667238c-48c4-4442-ae3e-8f376cb96272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664633878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2664633878
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2331724963
Short name T542
Test name
Test status
Simulation time 22371584 ps
CPU time 0.57 seconds
Started Apr 21 01:41:05 PM PDT 24
Finished Apr 21 01:41:06 PM PDT 24
Peak memory 195300 kb
Host smart-c00ae474-6b9e-4850-ba7b-4cc09cc05871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331724963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2331724963
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.216048645
Short name T361
Test name
Test status
Simulation time 4033783044 ps
CPU time 33.18 seconds
Started Apr 21 01:40:54 PM PDT 24
Finished Apr 21 01:41:27 PM PDT 24
Peak memory 207968 kb
Host smart-da6ff973-a493-4510-a27a-5725f597f96c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216048645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.216048645
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2025047788
Short name T39
Test name
Test status
Simulation time 4764336805 ps
CPU time 45.96 seconds
Started Apr 21 01:40:53 PM PDT 24
Finished Apr 21 01:41:39 PM PDT 24
Peak memory 199748 kb
Host smart-be5066f4-66eb-45c5-ba05-086d3aa107dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025047788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2025047788
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3620574277
Short name T213
Test name
Test status
Simulation time 23069981308 ps
CPU time 109.7 seconds
Started Apr 21 01:40:54 PM PDT 24
Finished Apr 21 01:42:44 PM PDT 24
Peak memory 199680 kb
Host smart-433fa937-7ca5-48dd-9ec9-4f3e574015f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620574277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3620574277
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1787197611
Short name T547
Test name
Test status
Simulation time 3843639759 ps
CPU time 64.43 seconds
Started Apr 21 01:40:56 PM PDT 24
Finished Apr 21 01:42:01 PM PDT 24
Peak memory 199636 kb
Host smart-dae840bb-f364-4d0f-a816-a5ea18229403
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787197611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1787197611
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1497757665
Short name T346
Test name
Test status
Simulation time 5493891635 ps
CPU time 88.67 seconds
Started Apr 21 01:40:54 PM PDT 24
Finished Apr 21 01:42:23 PM PDT 24
Peak memory 199716 kb
Host smart-888e9e6e-f77b-4344-8d54-7ce562cb71eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497757665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1497757665
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2473083845
Short name T445
Test name
Test status
Simulation time 26270316 ps
CPU time 1.05 seconds
Started Apr 21 01:40:52 PM PDT 24
Finished Apr 21 01:40:53 PM PDT 24
Peak memory 199624 kb
Host smart-cd68f5cf-72c7-4bc4-9e6c-1b286fa9859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473083845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2473083845
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4051823116
Short name T139
Test name
Test status
Simulation time 46677952 ps
CPU time 1.08 seconds
Started Apr 21 01:40:59 PM PDT 24
Finished Apr 21 01:41:01 PM PDT 24
Peak memory 199524 kb
Host smart-43edbba3-1d49-45ff-acde-e3ad8cb88721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051823116 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4051823116
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.329753058
Short name T67
Test name
Test status
Simulation time 49389053214 ps
CPU time 588.08 seconds
Started Apr 21 01:41:01 PM PDT 24
Finished Apr 21 01:50:49 PM PDT 24
Peak memory 216248 kb
Host smart-65bec6ae-2329-4040-a2a9-f4b84a4204c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329753058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.329753058
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3006090658
Short name T236
Test name
Test status
Simulation time 49535198 ps
CPU time 0.97 seconds
Started Apr 21 01:41:01 PM PDT 24
Finished Apr 21 01:41:02 PM PDT 24
Peak memory 198124 kb
Host smart-77c52971-0087-4e85-bda4-fc02766dd527
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006090658 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3006090658
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.288237037
Short name T485
Test name
Test status
Simulation time 178670560624 ps
CPU time 525.57 seconds
Started Apr 21 01:41:00 PM PDT 24
Finished Apr 21 01:49:46 PM PDT 24
Peak memory 199724 kb
Host smart-5d1f12a5-7043-4183-82f0-e2e050f43b79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288237037 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.288237037
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1730690629
Short name T459
Test name
Test status
Simulation time 2450167107 ps
CPU time 44.16 seconds
Started Apr 21 01:40:55 PM PDT 24
Finished Apr 21 01:41:39 PM PDT 24
Peak memory 199704 kb
Host smart-11d5eca0-d2a4-4a1d-ab25-ef90727cc94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730690629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1730690629
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.464893190
Short name T313
Test name
Test status
Simulation time 40269386 ps
CPU time 0.58 seconds
Started Apr 21 01:41:20 PM PDT 24
Finished Apr 21 01:41:20 PM PDT 24
Peak memory 195228 kb
Host smart-89c567b4-c6ee-421b-b764-3d14480ff33e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464893190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.464893190
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2669604072
Short name T224
Test name
Test status
Simulation time 1186412475 ps
CPU time 37.62 seconds
Started Apr 21 01:41:02 PM PDT 24
Finished Apr 21 01:41:40 PM PDT 24
Peak memory 225180 kb
Host smart-d6c4f8b0-6c92-45a1-9dc4-6985e463002a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669604072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2669604072
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.173290922
Short name T130
Test name
Test status
Simulation time 3514811665 ps
CPU time 15.4 seconds
Started Apr 21 01:41:04 PM PDT 24
Finished Apr 21 01:41:20 PM PDT 24
Peak memory 199732 kb
Host smart-1b43b873-f430-44f3-98a0-c721db003ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173290922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.173290922
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3928858288
Short name T325
Test name
Test status
Simulation time 1649314043 ps
CPU time 24.99 seconds
Started Apr 21 01:41:02 PM PDT 24
Finished Apr 21 01:41:27 PM PDT 24
Peak memory 199624 kb
Host smart-76e395d8-b1df-44da-800d-d2228dfedc05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928858288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3928858288
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1978256071
Short name T531
Test name
Test status
Simulation time 24403474976 ps
CPU time 83.65 seconds
Started Apr 21 01:41:07 PM PDT 24
Finished Apr 21 01:42:30 PM PDT 24
Peak memory 199768 kb
Host smart-e9f24775-0fdb-4080-988c-26082aff4ba6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978256071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1978256071
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3580703053
Short name T306
Test name
Test status
Simulation time 5555884298 ps
CPU time 98.14 seconds
Started Apr 21 01:41:02 PM PDT 24
Finished Apr 21 01:42:41 PM PDT 24
Peak memory 199744 kb
Host smart-104027aa-c5ec-4dd8-9645-ce59b6b34470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580703053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3580703053
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1256691780
Short name T143
Test name
Test status
Simulation time 382737067 ps
CPU time 4.32 seconds
Started Apr 21 01:40:59 PM PDT 24
Finished Apr 21 01:41:04 PM PDT 24
Peak memory 199660 kb
Host smart-e504c4f7-d3b7-4aa9-a73e-cc2833b42367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256691780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1256691780
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3079091775
Short name T36
Test name
Test status
Simulation time 125858512870 ps
CPU time 1724.72 seconds
Started Apr 21 01:41:09 PM PDT 24
Finished Apr 21 02:09:54 PM PDT 24
Peak memory 213388 kb
Host smart-593858d8-acce-415c-858d-573a23c0ac13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079091775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3079091775
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.3521404475
Short name T585
Test name
Test status
Simulation time 34901520 ps
CPU time 1.29 seconds
Started Apr 21 01:41:05 PM PDT 24
Finished Apr 21 01:41:06 PM PDT 24
Peak memory 199624 kb
Host smart-81c915f5-8dba-456d-adee-f57fe011c934
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521404475 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.3521404475
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2666618552
Short name T559
Test name
Test status
Simulation time 81562065205 ps
CPU time 487.8 seconds
Started Apr 21 01:41:06 PM PDT 24
Finished Apr 21 01:49:14 PM PDT 24
Peak memory 199744 kb
Host smart-e94ab416-ebcb-4c29-8494-69b0a59ccd88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666618552 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.2666618552
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2326328292
Short name T510
Test name
Test status
Simulation time 12301381661 ps
CPU time 52.63 seconds
Started Apr 21 01:41:05 PM PDT 24
Finished Apr 21 01:41:58 PM PDT 24
Peak memory 199720 kb
Host smart-78efd678-0b99-4898-b937-6d80c0677155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326328292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2326328292
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3770256900
Short name T271
Test name
Test status
Simulation time 16327651 ps
CPU time 0.67 seconds
Started Apr 21 01:41:25 PM PDT 24
Finished Apr 21 01:41:27 PM PDT 24
Peak memory 195248 kb
Host smart-d537fadd-eb73-4429-8729-ead375f24ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770256900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3770256900
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3288110777
Short name T182
Test name
Test status
Simulation time 805919016 ps
CPU time 32.38 seconds
Started Apr 21 01:41:20 PM PDT 24
Finished Apr 21 01:41:53 PM PDT 24
Peak memory 232368 kb
Host smart-f89a5e3b-b294-4ea4-8ba7-5c88f430381d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288110777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3288110777
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3850166118
Short name T32
Test name
Test status
Simulation time 12940434684 ps
CPU time 47.16 seconds
Started Apr 21 01:41:19 PM PDT 24
Finished Apr 21 01:42:07 PM PDT 24
Peak memory 199704 kb
Host smart-ebd63099-9683-4a45-bb75-dfcbb3555338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850166118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3850166118
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1217637662
Short name T24
Test name
Test status
Simulation time 5325769859 ps
CPU time 151.6 seconds
Started Apr 21 01:41:21 PM PDT 24
Finished Apr 21 01:43:53 PM PDT 24
Peak memory 199772 kb
Host smart-ef319b43-7181-4893-b50d-6de7413c0c2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217637662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1217637662
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1169235904
Short name T188
Test name
Test status
Simulation time 22855277228 ps
CPU time 154.14 seconds
Started Apr 21 01:41:21 PM PDT 24
Finished Apr 21 01:43:55 PM PDT 24
Peak memory 199756 kb
Host smart-5c2f56d5-de4a-42e5-ac5e-5342f5e099d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169235904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1169235904
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.721287881
Short name T124
Test name
Test status
Simulation time 2250994675 ps
CPU time 30.16 seconds
Started Apr 21 01:41:21 PM PDT 24
Finished Apr 21 01:41:51 PM PDT 24
Peak memory 199724 kb
Host smart-69622bb4-7c83-4fa8-ae2e-3bcdb7709e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721287881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.721287881
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3124512479
Short name T184
Test name
Test status
Simulation time 508618950 ps
CPU time 3.93 seconds
Started Apr 21 01:41:10 PM PDT 24
Finished Apr 21 01:41:14 PM PDT 24
Peak memory 199628 kb
Host smart-a90665ee-a804-4e2a-812d-212303a12a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124512479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3124512479
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.775955271
Short name T571
Test name
Test status
Simulation time 252145149163 ps
CPU time 295.08 seconds
Started Apr 21 01:41:21 PM PDT 24
Finished Apr 21 01:46:16 PM PDT 24
Peak memory 207940 kb
Host smart-a3a2f962-8aa3-4823-b7d9-2023552d7208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775955271 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.775955271
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3353986270
Short name T475
Test name
Test status
Simulation time 55839671 ps
CPU time 0.95 seconds
Started Apr 21 01:41:19 PM PDT 24
Finished Apr 21 01:41:21 PM PDT 24
Peak memory 198104 kb
Host smart-f14a533d-44b5-4763-9d28-7c840d2a55fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353986270 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3353986270
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3991472430
Short name T198
Test name
Test status
Simulation time 28888253841 ps
CPU time 478.73 seconds
Started Apr 21 01:41:19 PM PDT 24
Finished Apr 21 01:49:18 PM PDT 24
Peak memory 199716 kb
Host smart-9d41cad1-7f8a-4f2a-abbb-bcf55af588e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991472430 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3991472430
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2139619050
Short name T33
Test name
Test status
Simulation time 8729240020 ps
CPU time 52.49 seconds
Started Apr 21 01:41:22 PM PDT 24
Finished Apr 21 01:42:15 PM PDT 24
Peak memory 199772 kb
Host smart-4d333f7e-c639-416e-ab1b-09821ebaae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139619050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2139619050
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.517030813
Short name T260
Test name
Test status
Simulation time 14738470 ps
CPU time 0.58 seconds
Started Apr 21 01:41:26 PM PDT 24
Finished Apr 21 01:41:27 PM PDT 24
Peak memory 195248 kb
Host smart-9eeda6e7-e6a9-4b66-88a2-399de6d61d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517030813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.517030813
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4119846518
Short name T598
Test name
Test status
Simulation time 4221677473 ps
CPU time 30.31 seconds
Started Apr 21 01:41:25 PM PDT 24
Finished Apr 21 01:41:56 PM PDT 24
Peak memory 215836 kb
Host smart-79e2ce4e-fcdc-4659-9835-6dd917c02587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119846518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4119846518
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2458162230
Short name T279
Test name
Test status
Simulation time 10236197898 ps
CPU time 36.45 seconds
Started Apr 21 01:41:21 PM PDT 24
Finished Apr 21 01:41:57 PM PDT 24
Peak memory 199740 kb
Host smart-dd89696e-91c1-47b5-9519-4627933fd16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458162230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2458162230
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2161993392
Short name T227
Test name
Test status
Simulation time 1283980791 ps
CPU time 75.39 seconds
Started Apr 21 01:41:23 PM PDT 24
Finished Apr 21 01:42:39 PM PDT 24
Peak memory 199596 kb
Host smart-77ad5af7-3c31-42d9-9c70-2cf378287f05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161993392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2161993392
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.301095066
Short name T341
Test name
Test status
Simulation time 5122722296 ps
CPU time 17.7 seconds
Started Apr 21 01:41:23 PM PDT 24
Finished Apr 21 01:41:41 PM PDT 24
Peak memory 199744 kb
Host smart-c96149e2-8f86-4997-aa81-661b06fa29d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301095066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.301095066
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1081575326
Short name T339
Test name
Test status
Simulation time 4306842729 ps
CPU time 81.88 seconds
Started Apr 21 01:41:20 PM PDT 24
Finished Apr 21 01:42:42 PM PDT 24
Peak memory 199788 kb
Host smart-22dbf793-efc3-4ff7-bf83-52af6ddb45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081575326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1081575326
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3292007398
Short name T164
Test name
Test status
Simulation time 455020556 ps
CPU time 3.58 seconds
Started Apr 21 01:41:21 PM PDT 24
Finished Apr 21 01:41:25 PM PDT 24
Peak memory 199616 kb
Host smart-02b42eb5-6166-4327-bc8b-f5b925fca85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292007398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3292007398
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2847941904
Short name T75
Test name
Test status
Simulation time 147464443610 ps
CPU time 928.72 seconds
Started Apr 21 01:41:25 PM PDT 24
Finished Apr 21 01:56:55 PM PDT 24
Peak memory 199760 kb
Host smart-f5258126-96d8-4665-9ca3-a74b5de3d346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847941904 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2847941904
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1320519008
Short name T322
Test name
Test status
Simulation time 42567389 ps
CPU time 0.96 seconds
Started Apr 21 01:41:27 PM PDT 24
Finished Apr 21 01:41:28 PM PDT 24
Peak memory 198352 kb
Host smart-43c194c4-904b-4273-9c6d-33022494f021
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320519008 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1320519008
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2312878580
Short name T187
Test name
Test status
Simulation time 132604760537 ps
CPU time 421.21 seconds
Started Apr 21 01:41:27 PM PDT 24
Finished Apr 21 01:48:28 PM PDT 24
Peak memory 199744 kb
Host smart-b5dd5fb8-9837-47c1-b651-78c4f673f607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312878580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2312878580
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3207283315
Short name T546
Test name
Test status
Simulation time 3332656318 ps
CPU time 17.87 seconds
Started Apr 21 01:41:23 PM PDT 24
Finished Apr 21 01:41:42 PM PDT 24
Peak memory 199784 kb
Host smart-ccf0ed22-9733-4398-9bc4-a7c3e58fba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207283315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3207283315
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1873323236
Short name T366
Test name
Test status
Simulation time 18348333 ps
CPU time 0.56 seconds
Started Apr 21 01:41:33 PM PDT 24
Finished Apr 21 01:41:34 PM PDT 24
Peak memory 195332 kb
Host smart-a9589fe4-ec8c-480f-ae69-2972532d8b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873323236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1873323236
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.690151651
Short name T195
Test name
Test status
Simulation time 4974320755 ps
CPU time 45.38 seconds
Started Apr 21 01:41:27 PM PDT 24
Finished Apr 21 01:42:13 PM PDT 24
Peak memory 212312 kb
Host smart-00eea36f-bbfb-4907-b64e-25d907d88720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690151651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.690151651
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1955957120
Short name T402
Test name
Test status
Simulation time 1189133573 ps
CPU time 29.34 seconds
Started Apr 21 01:41:34 PM PDT 24
Finished Apr 21 01:42:04 PM PDT 24
Peak memory 199556 kb
Host smart-62b6c888-6977-45bc-9f81-e24baeb1da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955957120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1955957120
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3583462531
Short name T2
Test name
Test status
Simulation time 10691784082 ps
CPU time 72.97 seconds
Started Apr 21 01:41:31 PM PDT 24
Finished Apr 21 01:42:44 PM PDT 24
Peak memory 199720 kb
Host smart-b0318fef-c05a-4e0c-aad7-09466ec981b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583462531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3583462531
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1357606807
Short name T35
Test name
Test status
Simulation time 664739938 ps
CPU time 33.61 seconds
Started Apr 21 01:41:30 PM PDT 24
Finished Apr 21 01:42:04 PM PDT 24
Peak memory 199636 kb
Host smart-0ea4dc46-ab9e-415c-aa63-ce6dc0001de2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357606807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1357606807
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1366150486
Short name T288
Test name
Test status
Simulation time 167767017356 ps
CPU time 117.49 seconds
Started Apr 21 01:41:28 PM PDT 24
Finished Apr 21 01:43:25 PM PDT 24
Peak memory 199756 kb
Host smart-cec8f356-223e-4da9-872a-dc1d4899404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366150486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1366150486
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1097302095
Short name T175
Test name
Test status
Simulation time 572652936 ps
CPU time 6.3 seconds
Started Apr 21 01:41:27 PM PDT 24
Finished Apr 21 01:41:33 PM PDT 24
Peak memory 199516 kb
Host smart-92b798ad-339e-485b-a7db-869437bc7f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097302095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1097302095
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.668131151
Short name T575
Test name
Test status
Simulation time 98143452522 ps
CPU time 605.15 seconds
Started Apr 21 01:41:33 PM PDT 24
Finished Apr 21 01:51:38 PM PDT 24
Peak memory 207940 kb
Host smart-2def5711-5f98-4359-aba5-8b239fc4c730
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668131151 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.668131151
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.798157784
Short name T254
Test name
Test status
Simulation time 49296526 ps
CPU time 0.94 seconds
Started Apr 21 01:41:32 PM PDT 24
Finished Apr 21 01:41:33 PM PDT 24
Peak memory 198064 kb
Host smart-8ee5b11f-30de-4487-8e9f-330465d0e69b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798157784 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.798157784
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3778722916
Short name T171
Test name
Test status
Simulation time 14236716343 ps
CPU time 382.12 seconds
Started Apr 21 01:41:29 PM PDT 24
Finished Apr 21 01:47:52 PM PDT 24
Peak memory 199748 kb
Host smart-13ca1be2-7b27-4cf0-9755-49a7bf2054e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778722916 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3778722916
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2209807526
Short name T357
Test name
Test status
Simulation time 11303774693 ps
CPU time 107.13 seconds
Started Apr 21 01:41:31 PM PDT 24
Finished Apr 21 01:43:19 PM PDT 24
Peak memory 199680 kb
Host smart-0a19c203-0033-464d-88b7-065998a4105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209807526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2209807526
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1443312849
Short name T177
Test name
Test status
Simulation time 13162573 ps
CPU time 0.55 seconds
Started Apr 21 01:41:48 PM PDT 24
Finished Apr 21 01:41:49 PM PDT 24
Peak memory 195296 kb
Host smart-a1c62d1c-b8d7-4091-930a-c447421941a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443312849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1443312849
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3703907112
Short name T54
Test name
Test status
Simulation time 20695079640 ps
CPU time 40.29 seconds
Started Apr 21 01:41:35 PM PDT 24
Finished Apr 21 01:42:16 PM PDT 24
Peak memory 227380 kb
Host smart-524b0037-c7a7-40cc-a9f9-1f0daac522c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703907112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3703907112
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3999915381
Short name T394
Test name
Test status
Simulation time 12009862722 ps
CPU time 42.2 seconds
Started Apr 21 01:41:33 PM PDT 24
Finished Apr 21 01:42:16 PM PDT 24
Peak memory 199676 kb
Host smart-d42ddaea-1c59-4e0f-8413-995ffe470c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999915381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3999915381
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.15457811
Short name T516
Test name
Test status
Simulation time 621223802 ps
CPU time 31.68 seconds
Started Apr 21 01:41:34 PM PDT 24
Finished Apr 21 01:42:06 PM PDT 24
Peak memory 199612 kb
Host smart-e789270d-a3ad-4678-8d33-100eaa8a8b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15457811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.15457811
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2593212554
Short name T507
Test name
Test status
Simulation time 9241621589 ps
CPU time 160.77 seconds
Started Apr 21 01:41:37 PM PDT 24
Finished Apr 21 01:44:18 PM PDT 24
Peak memory 199744 kb
Host smart-fc457eeb-a260-492d-b9d6-4597d13d8a8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593212554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2593212554
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.175950549
Short name T385
Test name
Test status
Simulation time 3836298681 ps
CPU time 111.94 seconds
Started Apr 21 01:41:35 PM PDT 24
Finished Apr 21 01:43:27 PM PDT 24
Peak memory 199736 kb
Host smart-e2914c86-96ff-40d3-8922-46733fba0c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175950549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.175950549
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.417891731
Short name T388
Test name
Test status
Simulation time 1557674062 ps
CPU time 4.43 seconds
Started Apr 21 01:41:34 PM PDT 24
Finished Apr 21 01:41:39 PM PDT 24
Peak memory 199592 kb
Host smart-67e3af2a-b19d-4de0-8ce3-814108bc191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417891731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.417891731
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3293894839
Short name T373
Test name
Test status
Simulation time 72565021427 ps
CPU time 161.36 seconds
Started Apr 21 01:41:45 PM PDT 24
Finished Apr 21 01:44:26 PM PDT 24
Peak memory 199736 kb
Host smart-1102c1b5-686b-4da0-aeee-ea0cee09cf98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293894839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3293894839
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3117897215
Short name T14
Test name
Test status
Simulation time 43882106 ps
CPU time 0.98 seconds
Started Apr 21 01:41:42 PM PDT 24
Finished Apr 21 01:41:43 PM PDT 24
Peak memory 198900 kb
Host smart-d079b48b-a783-4233-a271-8d96b1c24dd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117897215 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3117897215
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1686699797
Short name T497
Test name
Test status
Simulation time 31878094244 ps
CPU time 403.14 seconds
Started Apr 21 01:41:37 PM PDT 24
Finished Apr 21 01:48:21 PM PDT 24
Peak memory 199720 kb
Host smart-b9293569-740b-4f94-91f0-43a4bed07ba3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686699797 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1686699797
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4072682872
Short name T20
Test name
Test status
Simulation time 487475433 ps
CPU time 19.18 seconds
Started Apr 21 01:41:38 PM PDT 24
Finished Apr 21 01:41:57 PM PDT 24
Peak memory 199584 kb
Host smart-35d6fe09-2dd0-4c45-b0bc-2574666ef2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072682872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4072682872
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1439586170
Short name T298
Test name
Test status
Simulation time 22549661 ps
CPU time 0.54 seconds
Started Apr 21 01:42:00 PM PDT 24
Finished Apr 21 01:42:01 PM PDT 24
Peak memory 194192 kb
Host smart-84de92af-7254-4d40-9409-9669c02be314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439586170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1439586170
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2156000743
Short name T437
Test name
Test status
Simulation time 473980679 ps
CPU time 16.63 seconds
Started Apr 21 01:41:54 PM PDT 24
Finished Apr 21 01:42:11 PM PDT 24
Peak memory 199676 kb
Host smart-c38baa22-614b-4320-b0ca-6f9710b63b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156000743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2156000743
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2606341510
Short name T235
Test name
Test status
Simulation time 1427631406 ps
CPU time 21.2 seconds
Started Apr 21 01:41:52 PM PDT 24
Finished Apr 21 01:42:13 PM PDT 24
Peak memory 199576 kb
Host smart-9d7ace04-0d7e-4065-ad93-733c54da2b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606341510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2606341510
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2830249816
Short name T82
Test name
Test status
Simulation time 2316598482 ps
CPU time 129.63 seconds
Started Apr 21 01:41:51 PM PDT 24
Finished Apr 21 01:44:01 PM PDT 24
Peak memory 199740 kb
Host smart-5ee4187f-8580-417c-81a0-5c92a1bb7fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830249816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2830249816
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1530890893
Short name T523
Test name
Test status
Simulation time 13443714552 ps
CPU time 93.13 seconds
Started Apr 21 01:41:53 PM PDT 24
Finished Apr 21 01:43:27 PM PDT 24
Peak memory 199772 kb
Host smart-f858a995-229c-4a6a-bff3-879a082ae80d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530890893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1530890893
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2327198805
Short name T344
Test name
Test status
Simulation time 6235261083 ps
CPU time 55.85 seconds
Started Apr 21 01:41:52 PM PDT 24
Finished Apr 21 01:42:48 PM PDT 24
Peak memory 199744 kb
Host smart-54602fac-808b-400a-a0d8-eb3bfca18a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327198805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2327198805
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1048520774
Short name T376
Test name
Test status
Simulation time 402584546 ps
CPU time 2.04 seconds
Started Apr 21 01:41:49 PM PDT 24
Finished Apr 21 01:41:52 PM PDT 24
Peak memory 199564 kb
Host smart-ec26d6d7-67c1-42c5-af2c-b2666e4bbea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048520774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1048520774
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1859563672
Short name T48
Test name
Test status
Simulation time 468946886913 ps
CPU time 2019.58 seconds
Started Apr 21 01:42:00 PM PDT 24
Finished Apr 21 02:15:40 PM PDT 24
Peak memory 199776 kb
Host smart-b3a7ba0c-0143-4cb6-b4f2-ba1a82e6fbea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859563672 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1859563672
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2104142936
Short name T150
Test name
Test status
Simulation time 212666429 ps
CPU time 1.23 seconds
Started Apr 21 01:41:56 PM PDT 24
Finished Apr 21 01:41:57 PM PDT 24
Peak memory 199408 kb
Host smart-19794457-7af4-4391-befe-3ed2eb085652
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104142936 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2104142936
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3419552722
Short name T365
Test name
Test status
Simulation time 33155984449 ps
CPU time 437.23 seconds
Started Apr 21 01:41:56 PM PDT 24
Finished Apr 21 01:49:14 PM PDT 24
Peak memory 199764 kb
Host smart-8a84ce40-cf95-407e-a6fc-bbf24511c1cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419552722 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3419552722
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3425637737
Short name T299
Test name
Test status
Simulation time 3788119132 ps
CPU time 48.15 seconds
Started Apr 21 01:41:55 PM PDT 24
Finished Apr 21 01:42:43 PM PDT 24
Peak memory 199744 kb
Host smart-f5ae9c0d-7d74-4995-a487-f8f7a42c96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425637737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3425637737
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3502868667
Short name T367
Test name
Test status
Simulation time 30822585 ps
CPU time 0.59 seconds
Started Apr 21 01:42:07 PM PDT 24
Finished Apr 21 01:42:08 PM PDT 24
Peak memory 195204 kb
Host smart-222e5b0f-65d7-4d33-adfa-e0bc92f7cd58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502868667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3502868667
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.190800574
Short name T50
Test name
Test status
Simulation time 34636240 ps
CPU time 1.31 seconds
Started Apr 21 01:41:57 PM PDT 24
Finished Apr 21 01:41:59 PM PDT 24
Peak memory 199584 kb
Host smart-4f0375c1-11c2-4ac5-857c-900e5506e4fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190800574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.190800574
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.73401697
Short name T439
Test name
Test status
Simulation time 131010170 ps
CPU time 2.89 seconds
Started Apr 21 01:42:03 PM PDT 24
Finished Apr 21 01:42:07 PM PDT 24
Peak memory 199656 kb
Host smart-185d49b3-983a-42f7-bc73-fa322c14326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73401697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.73401697
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1258962135
Short name T311
Test name
Test status
Simulation time 980018922 ps
CPU time 57.46 seconds
Started Apr 21 01:42:02 PM PDT 24
Finished Apr 21 01:43:00 PM PDT 24
Peak memory 199592 kb
Host smart-faa34efa-db63-4328-9815-c5183c934ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258962135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1258962135
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2079989229
Short name T550
Test name
Test status
Simulation time 852018351 ps
CPU time 44.41 seconds
Started Apr 21 01:42:02 PM PDT 24
Finished Apr 21 01:42:47 PM PDT 24
Peak memory 199640 kb
Host smart-5b4b8d60-8a7f-4ad7-ae38-910af9c0a07e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079989229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2079989229
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1644805643
Short name T176
Test name
Test status
Simulation time 765740912 ps
CPU time 15.18 seconds
Started Apr 21 01:41:59 PM PDT 24
Finished Apr 21 01:42:14 PM PDT 24
Peak memory 199604 kb
Host smart-2b990be8-e482-4a41-a674-b89b28d3393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644805643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1644805643
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3870445324
Short name T393
Test name
Test status
Simulation time 20640681 ps
CPU time 0.78 seconds
Started Apr 21 01:41:57 PM PDT 24
Finished Apr 21 01:41:59 PM PDT 24
Peak memory 197672 kb
Host smart-3da917b6-1f71-48a4-bee8-336c281f814a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870445324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3870445324
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2034714916
Short name T251
Test name
Test status
Simulation time 555337537 ps
CPU time 6.86 seconds
Started Apr 21 01:42:03 PM PDT 24
Finished Apr 21 01:42:10 PM PDT 24
Peak memory 210468 kb
Host smart-14239b20-cb7a-4f66-b0c1-efe0c85a2ed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034714916 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2034714916
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.651835135
Short name T555
Test name
Test status
Simulation time 42422440 ps
CPU time 0.92 seconds
Started Apr 21 01:42:05 PM PDT 24
Finished Apr 21 01:42:07 PM PDT 24
Peak memory 197924 kb
Host smart-ca46ed96-06d6-49a9-84a7-139e882ee483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651835135 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.651835135
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.242756811
Short name T460
Test name
Test status
Simulation time 375981230109 ps
CPU time 529.9 seconds
Started Apr 21 01:42:04 PM PDT 24
Finished Apr 21 01:50:54 PM PDT 24
Peak memory 199724 kb
Host smart-656549fe-bc50-4251-a731-0cfabca545d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242756811 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.242756811
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1656801873
Short name T499
Test name
Test status
Simulation time 6675248807 ps
CPU time 17.84 seconds
Started Apr 21 01:42:02 PM PDT 24
Finished Apr 21 01:42:21 PM PDT 24
Peak memory 199748 kb
Host smart-d611361c-feb5-4dc1-bbb7-2281ad89481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656801873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1656801873
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.300267614
Short name T419
Test name
Test status
Simulation time 55064307 ps
CPU time 0.56 seconds
Started Apr 21 01:38:59 PM PDT 24
Finished Apr 21 01:39:00 PM PDT 24
Peak memory 195212 kb
Host smart-df1fc55f-f60d-4be8-adfe-0181541a9196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300267614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.300267614
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1197279867
Short name T396
Test name
Test status
Simulation time 1015501582 ps
CPU time 9.88 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:39:06 PM PDT 24
Peak memory 216008 kb
Host smart-d1f6812f-188f-45fb-8b69-53fd35f1b7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197279867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1197279867
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2498532807
Short name T122
Test name
Test status
Simulation time 306892053 ps
CPU time 13.92 seconds
Started Apr 21 01:38:58 PM PDT 24
Finished Apr 21 01:39:12 PM PDT 24
Peak memory 199644 kb
Host smart-271a4a98-4da8-45af-b6ad-608544b88a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498532807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2498532807
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1290298074
Short name T337
Test name
Test status
Simulation time 2107176265 ps
CPU time 115.72 seconds
Started Apr 21 01:39:00 PM PDT 24
Finished Apr 21 01:40:56 PM PDT 24
Peak memory 199576 kb
Host smart-a44f2570-86e7-4ab4-9d0d-00c99b7e8839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290298074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1290298074
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3064978263
Short name T185
Test name
Test status
Simulation time 57312397017 ps
CPU time 161.39 seconds
Started Apr 21 01:38:58 PM PDT 24
Finished Apr 21 01:41:39 PM PDT 24
Peak memory 199708 kb
Host smart-505392c2-96e6-41db-9687-2a3a2815cd91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064978263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3064978263
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3248878040
Short name T120
Test name
Test status
Simulation time 790831843 ps
CPU time 4.23 seconds
Started Apr 21 01:38:59 PM PDT 24
Finished Apr 21 01:39:04 PM PDT 24
Peak memory 199536 kb
Host smart-b99f4000-d042-4208-8081-61ad981f8f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248878040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3248878040
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3452910400
Short name T30
Test name
Test status
Simulation time 111939018 ps
CPU time 0.9 seconds
Started Apr 21 01:39:01 PM PDT 24
Finished Apr 21 01:39:02 PM PDT 24
Peak memory 218192 kb
Host smart-6ec5ecf3-2e12-49eb-91a7-506b65d9167e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452910400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3452910400
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.476921161
Short name T595
Test name
Test status
Simulation time 97619665 ps
CPU time 1.49 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:38:58 PM PDT 24
Peak memory 199584 kb
Host smart-3409591c-0285-499f-9765-f97419313e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476921161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.476921161
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.141277073
Short name T461
Test name
Test status
Simulation time 7007613870 ps
CPU time 72.87 seconds
Started Apr 21 01:38:58 PM PDT 24
Finished Apr 21 01:40:11 PM PDT 24
Peak memory 215240 kb
Host smart-c9a159e4-d2e9-44d1-b77c-f3848676f67f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141277073 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.141277073
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3955496167
Short name T168
Test name
Test status
Simulation time 86628899 ps
CPU time 1.01 seconds
Started Apr 21 01:38:59 PM PDT 24
Finished Apr 21 01:39:00 PM PDT 24
Peak memory 198804 kb
Host smart-afe7e83d-f0e7-4643-9785-73ebefd6950a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955496167 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3955496167
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2765943847
Short name T404
Test name
Test status
Simulation time 27290355993 ps
CPU time 467.71 seconds
Started Apr 21 01:38:56 PM PDT 24
Finished Apr 21 01:46:44 PM PDT 24
Peak memory 199712 kb
Host smart-97c2ade3-53e1-4772-a193-eb4cd27e86ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765943847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2765943847
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2239488978
Short name T77
Test name
Test status
Simulation time 2299266605 ps
CPU time 42.3 seconds
Started Apr 21 01:38:58 PM PDT 24
Finished Apr 21 01:39:41 PM PDT 24
Peak memory 199728 kb
Host smart-b13faa95-2bd0-4764-b1df-0bf5a0b759a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239488978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2239488978
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1651655339
Short name T173
Test name
Test status
Simulation time 32333417 ps
CPU time 0.55 seconds
Started Apr 21 01:42:16 PM PDT 24
Finished Apr 21 01:42:17 PM PDT 24
Peak memory 195260 kb
Host smart-a2b4c25f-aa75-4e90-b3a0-7766aaf14b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651655339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1651655339
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.774852417
Short name T408
Test name
Test status
Simulation time 709552732 ps
CPU time 23.5 seconds
Started Apr 21 01:42:10 PM PDT 24
Finished Apr 21 01:42:34 PM PDT 24
Peak memory 207820 kb
Host smart-c14fa398-68a1-494d-8d83-e577a132d916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774852417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.774852417
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1524768950
Short name T191
Test name
Test status
Simulation time 264229882 ps
CPU time 2.65 seconds
Started Apr 21 01:42:13 PM PDT 24
Finished Apr 21 01:42:16 PM PDT 24
Peak memory 199624 kb
Host smart-9a2ff5bd-5ad6-4b24-a2aa-98191ba3d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524768950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1524768950
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3070629488
Short name T136
Test name
Test status
Simulation time 1647572672 ps
CPU time 94.53 seconds
Started Apr 21 01:42:10 PM PDT 24
Finished Apr 21 01:43:45 PM PDT 24
Peak memory 199620 kb
Host smart-af553383-3f87-4867-978c-d836e57c765e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070629488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3070629488
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.287307137
Short name T132
Test name
Test status
Simulation time 2416419622 ps
CPU time 42.37 seconds
Started Apr 21 01:42:13 PM PDT 24
Finished Apr 21 01:42:55 PM PDT 24
Peak memory 199764 kb
Host smart-7a382423-7914-4600-8921-ab22b94e5d40
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287307137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.287307137
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3662103078
Short name T199
Test name
Test status
Simulation time 728993826 ps
CPU time 21.3 seconds
Started Apr 21 01:42:11 PM PDT 24
Finished Apr 21 01:42:32 PM PDT 24
Peak memory 199628 kb
Host smart-df9b8756-7fc6-4b51-ad32-0f8322ca7475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662103078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3662103078
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1371884510
Short name T301
Test name
Test status
Simulation time 140330362 ps
CPU time 1.46 seconds
Started Apr 21 01:42:10 PM PDT 24
Finished Apr 21 01:42:12 PM PDT 24
Peak memory 199520 kb
Host smart-b218d4fb-f497-4271-bd52-5061d0a23521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371884510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1371884510
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2854102281
Short name T501
Test name
Test status
Simulation time 29010146549 ps
CPU time 1540.64 seconds
Started Apr 21 01:42:14 PM PDT 24
Finished Apr 21 02:07:55 PM PDT 24
Peak memory 240132 kb
Host smart-beea6819-b594-474c-8dcf-9970153bc7cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854102281 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2854102281
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1715005529
Short name T522
Test name
Test status
Simulation time 56048448 ps
CPU time 1.27 seconds
Started Apr 21 01:42:12 PM PDT 24
Finished Apr 21 01:42:14 PM PDT 24
Peak memory 199644 kb
Host smart-4ee4683d-0ef8-412a-9ebc-6311022ad963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715005529 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1715005529
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.286027607
Short name T352
Test name
Test status
Simulation time 112530965377 ps
CPU time 455.46 seconds
Started Apr 21 01:42:20 PM PDT 24
Finished Apr 21 01:49:56 PM PDT 24
Peak memory 199692 kb
Host smart-451de5a3-7f6d-4ce9-912e-e4c0d0d18cc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286027607 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.286027607
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.374914221
Short name T218
Test name
Test status
Simulation time 4481732508 ps
CPU time 36.03 seconds
Started Apr 21 01:42:12 PM PDT 24
Finished Apr 21 01:42:48 PM PDT 24
Peak memory 199756 kb
Host smart-e7775854-548f-4112-a277-f7eca8217c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374914221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.374914221
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2211681632
Short name T281
Test name
Test status
Simulation time 25618490 ps
CPU time 0.56 seconds
Started Apr 21 01:42:29 PM PDT 24
Finished Apr 21 01:42:30 PM PDT 24
Peak memory 195248 kb
Host smart-c73206df-326c-4131-9353-fa749a39fa03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211681632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2211681632
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.859917269
Short name T466
Test name
Test status
Simulation time 1157473859 ps
CPU time 42.25 seconds
Started Apr 21 01:42:22 PM PDT 24
Finished Apr 21 01:43:05 PM PDT 24
Peak memory 209668 kb
Host smart-e309f6f5-c629-4447-86c3-a3eff66340c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859917269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.859917269
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1734409733
Short name T481
Test name
Test status
Simulation time 238423590 ps
CPU time 3.97 seconds
Started Apr 21 01:42:23 PM PDT 24
Finished Apr 21 01:42:27 PM PDT 24
Peak memory 199524 kb
Host smart-8a6e797d-d26c-485c-87e0-d5a751b72c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734409733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1734409733
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3828526801
Short name T491
Test name
Test status
Simulation time 6836610763 ps
CPU time 89.56 seconds
Started Apr 21 01:42:24 PM PDT 24
Finished Apr 21 01:43:54 PM PDT 24
Peak memory 199756 kb
Host smart-3acfa22c-5172-44e7-b74c-c4788ce77206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828526801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3828526801
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2137139635
Short name T317
Test name
Test status
Simulation time 34568481624 ps
CPU time 208.35 seconds
Started Apr 21 01:42:24 PM PDT 24
Finished Apr 21 01:45:52 PM PDT 24
Peak memory 199768 kb
Host smart-08c5b5d8-b7d6-49f3-a4ac-f456d18a80cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137139635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2137139635
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.850374245
Short name T125
Test name
Test status
Simulation time 44105601007 ps
CPU time 102.29 seconds
Started Apr 21 01:42:16 PM PDT 24
Finished Apr 21 01:43:59 PM PDT 24
Peak memory 199784 kb
Host smart-f8bfd9fb-e0d9-47b2-a373-16b277a8667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850374245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.850374245
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1306330781
Short name T59
Test name
Test status
Simulation time 2139599741 ps
CPU time 6.67 seconds
Started Apr 21 01:42:15 PM PDT 24
Finished Apr 21 01:42:22 PM PDT 24
Peak memory 199632 kb
Host smart-f7cb303a-7b34-4527-9461-d519cabd712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306330781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1306330781
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.603533064
Short name T321
Test name
Test status
Simulation time 6393058297 ps
CPU time 80.93 seconds
Started Apr 21 01:42:27 PM PDT 24
Finished Apr 21 01:43:48 PM PDT 24
Peak memory 199740 kb
Host smart-a3d88ad6-ae1d-4e81-9b10-5203345b3d47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603533064 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.603533064
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3147405142
Short name T193
Test name
Test status
Simulation time 31539763 ps
CPU time 1.19 seconds
Started Apr 21 01:42:30 PM PDT 24
Finished Apr 21 01:42:31 PM PDT 24
Peak memory 198708 kb
Host smart-e162b1da-92b1-465f-9434-e444d88d2170
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147405142 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3147405142
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1835595795
Short name T469
Test name
Test status
Simulation time 42559540228 ps
CPU time 518.83 seconds
Started Apr 21 01:42:26 PM PDT 24
Finished Apr 21 01:51:05 PM PDT 24
Peak memory 199760 kb
Host smart-0a5e97d9-c15d-4f58-88d5-a6ae67d178c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835595795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1835595795
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3892148983
Short name T486
Test name
Test status
Simulation time 1768420348 ps
CPU time 30.39 seconds
Started Apr 21 01:42:26 PM PDT 24
Finished Apr 21 01:42:57 PM PDT 24
Peak memory 199612 kb
Host smart-76d8bbc0-08f2-4ce5-a832-dfbdb5c97a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892148983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3892148983
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3726934367
Short name T532
Test name
Test status
Simulation time 47239373 ps
CPU time 0.59 seconds
Started Apr 21 01:42:37 PM PDT 24
Finished Apr 21 01:42:38 PM PDT 24
Peak memory 195208 kb
Host smart-983c3faa-14ab-40f5-ab25-6e22566fb581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726934367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3726934367
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3198256280
Short name T451
Test name
Test status
Simulation time 218049792 ps
CPU time 8.56 seconds
Started Apr 21 01:42:31 PM PDT 24
Finished Apr 21 01:42:40 PM PDT 24
Peak memory 211792 kb
Host smart-0c00b6fd-ebdd-4bd3-8c75-317910ce70e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198256280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3198256280
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.317207027
Short name T519
Test name
Test status
Simulation time 1279021498 ps
CPU time 6.22 seconds
Started Apr 21 01:42:34 PM PDT 24
Finished Apr 21 01:42:41 PM PDT 24
Peak memory 199564 kb
Host smart-2173753c-ef27-4144-bf3a-c4f5b2a8b76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317207027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.317207027
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3872960872
Short name T259
Test name
Test status
Simulation time 4126733150 ps
CPU time 54.3 seconds
Started Apr 21 01:42:32 PM PDT 24
Finished Apr 21 01:43:26 PM PDT 24
Peak memory 199764 kb
Host smart-9425c6db-c939-4120-a629-392cedb7ecb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872960872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3872960872
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1855308208
Short name T536
Test name
Test status
Simulation time 1636958731 ps
CPU time 55.26 seconds
Started Apr 21 01:42:34 PM PDT 24
Finished Apr 21 01:43:30 PM PDT 24
Peak memory 199548 kb
Host smart-75f76f1f-301f-4652-a939-dcb177c34995
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855308208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1855308208
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3394475945
Short name T113
Test name
Test status
Simulation time 14079169785 ps
CPU time 51.89 seconds
Started Apr 21 01:42:30 PM PDT 24
Finished Apr 21 01:43:22 PM PDT 24
Peak memory 199788 kb
Host smart-527a97c0-1e43-4d42-a846-e1c531453ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394475945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3394475945
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1894859876
Short name T518
Test name
Test status
Simulation time 681515490 ps
CPU time 4.16 seconds
Started Apr 21 01:42:28 PM PDT 24
Finished Apr 21 01:42:32 PM PDT 24
Peak memory 199604 kb
Host smart-dd750e6e-5983-4cba-8219-2f95be3627f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894859876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1894859876
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2819684892
Short name T214
Test name
Test status
Simulation time 1449916238 ps
CPU time 53.7 seconds
Started Apr 21 01:42:34 PM PDT 24
Finished Apr 21 01:43:27 PM PDT 24
Peak memory 211916 kb
Host smart-f5112889-9ac9-4e43-810b-7d3ae52721f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819684892 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2819684892
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.4089314778
Short name T508
Test name
Test status
Simulation time 100954724 ps
CPU time 0.93 seconds
Started Apr 21 01:42:33 PM PDT 24
Finished Apr 21 01:42:34 PM PDT 24
Peak memory 198212 kb
Host smart-3e44b711-4ff6-49b7-b652-3bc4eadcd9eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089314778 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.4089314778
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2643522284
Short name T463
Test name
Test status
Simulation time 169684005146 ps
CPU time 495.43 seconds
Started Apr 21 01:42:36 PM PDT 24
Finished Apr 21 01:50:52 PM PDT 24
Peak memory 199700 kb
Host smart-c0f55dc3-509f-44af-aefd-dc416df75a52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643522284 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2643522284
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1419575010
Short name T424
Test name
Test status
Simulation time 1003901957 ps
CPU time 18.81 seconds
Started Apr 21 01:42:34 PM PDT 24
Finished Apr 21 01:42:53 PM PDT 24
Peak memory 199572 kb
Host smart-011b89e9-7670-4189-b5e4-8bf74773f579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419575010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1419575010
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3211868926
Short name T237
Test name
Test status
Simulation time 19167912 ps
CPU time 0.57 seconds
Started Apr 21 01:42:43 PM PDT 24
Finished Apr 21 01:42:43 PM PDT 24
Peak memory 194144 kb
Host smart-4c4e6513-cfe0-4fc6-a1c2-aa0d225e1f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211868926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3211868926
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2113672384
Short name T154
Test name
Test status
Simulation time 13420219262 ps
CPU time 42.76 seconds
Started Apr 21 01:42:40 PM PDT 24
Finished Apr 21 01:43:23 PM PDT 24
Peak memory 207836 kb
Host smart-5fee7331-8800-4809-9def-28e1b48ab421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113672384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2113672384
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.340123554
Short name T343
Test name
Test status
Simulation time 1369911378 ps
CPU time 18.6 seconds
Started Apr 21 01:42:41 PM PDT 24
Finished Apr 21 01:43:00 PM PDT 24
Peak memory 199612 kb
Host smart-932f77f1-7705-4322-b29f-2b75984555fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340123554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.340123554
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3471166101
Short name T230
Test name
Test status
Simulation time 9581167873 ps
CPU time 139.2 seconds
Started Apr 21 01:42:40 PM PDT 24
Finished Apr 21 01:44:59 PM PDT 24
Peak memory 199744 kb
Host smart-c57f2796-ee82-42c0-b857-3074e2fb97ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471166101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3471166101
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.460675064
Short name T362
Test name
Test status
Simulation time 14411355302 ps
CPU time 190.94 seconds
Started Apr 21 01:42:42 PM PDT 24
Finished Apr 21 01:45:53 PM PDT 24
Peak memory 199700 kb
Host smart-f1231996-3b67-45c4-ad9d-af2bf1dfc77b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460675064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.460675064
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3670959235
Short name T80
Test name
Test status
Simulation time 2810299397 ps
CPU time 22.14 seconds
Started Apr 21 01:42:36 PM PDT 24
Finished Apr 21 01:42:58 PM PDT 24
Peak memory 199772 kb
Host smart-2c6dd06d-db24-4fe8-8f56-6361ee9bbb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670959235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3670959235
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.96293983
Short name T153
Test name
Test status
Simulation time 416419691 ps
CPU time 5.91 seconds
Started Apr 21 01:42:36 PM PDT 24
Finished Apr 21 01:42:42 PM PDT 24
Peak memory 199592 kb
Host smart-5cdf27ad-987d-4dd1-a4e8-7079c1541efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96293983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.96293983
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.198482414
Short name T565
Test name
Test status
Simulation time 27278863810 ps
CPU time 78.22 seconds
Started Apr 21 01:42:45 PM PDT 24
Finished Apr 21 01:44:03 PM PDT 24
Peak memory 199760 kb
Host smart-c40ec9ab-3401-4272-bad0-797719f653aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198482414 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.198482414
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1214850300
Short name T435
Test name
Test status
Simulation time 59156227 ps
CPU time 1.14 seconds
Started Apr 21 01:42:44 PM PDT 24
Finished Apr 21 01:42:46 PM PDT 24
Peak memory 199548 kb
Host smart-1064bff1-9e48-4351-8fbd-bd5c7c6f1e54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214850300 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1214850300
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.4189266744
Short name T140
Test name
Test status
Simulation time 52100342827 ps
CPU time 484.45 seconds
Started Apr 21 01:42:44 PM PDT 24
Finished Apr 21 01:50:48 PM PDT 24
Peak memory 199688 kb
Host smart-468b9802-dbf6-4fd7-8060-fba5c82e77f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189266744 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.4189266744
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3581883880
Short name T438
Test name
Test status
Simulation time 6924791157 ps
CPU time 64.23 seconds
Started Apr 21 01:42:44 PM PDT 24
Finished Apr 21 01:43:49 PM PDT 24
Peak memory 199704 kb
Host smart-caa686bb-d899-4b2a-b088-082ae58fb10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581883880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3581883880
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.138144857
Short name T579
Test name
Test status
Simulation time 17950969 ps
CPU time 0.64 seconds
Started Apr 21 01:42:48 PM PDT 24
Finished Apr 21 01:42:49 PM PDT 24
Peak memory 195192 kb
Host smart-4716bd3f-8f5f-40e6-bdcf-09333854d5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138144857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.138144857
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3537944100
Short name T348
Test name
Test status
Simulation time 3966303561 ps
CPU time 35.08 seconds
Started Apr 21 01:42:45 PM PDT 24
Finished Apr 21 01:43:20 PM PDT 24
Peak memory 207960 kb
Host smart-d5d83913-8836-4bbf-a0a8-4fcebab53a43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537944100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3537944100
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2826203043
Short name T257
Test name
Test status
Simulation time 4393077158 ps
CPU time 48.65 seconds
Started Apr 21 01:42:46 PM PDT 24
Finished Apr 21 01:43:34 PM PDT 24
Peak memory 199740 kb
Host smart-6ad22d82-d931-4a3a-ba8a-977de08326a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826203043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2826203043
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.474999481
Short name T58
Test name
Test status
Simulation time 3609669187 ps
CPU time 99.98 seconds
Started Apr 21 01:42:44 PM PDT 24
Finished Apr 21 01:44:25 PM PDT 24
Peak memory 199744 kb
Host smart-f9eec64e-9515-466d-a0a4-c88b45ae9f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474999481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.474999481
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2326762352
Short name T115
Test name
Test status
Simulation time 11587099194 ps
CPU time 35.13 seconds
Started Apr 21 01:42:47 PM PDT 24
Finished Apr 21 01:43:22 PM PDT 24
Peak memory 199728 kb
Host smart-28dcd4e4-b1bf-44b9-83d6-3ce7e87d5271
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326762352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2326762352
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1584554339
Short name T327
Test name
Test status
Simulation time 9880064046 ps
CPU time 33.02 seconds
Started Apr 21 01:42:47 PM PDT 24
Finished Apr 21 01:43:20 PM PDT 24
Peak memory 199744 kb
Host smart-2113ef8f-d3b1-4bc9-9bc3-aaa4e24f6a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584554339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1584554339
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.710465438
Short name T342
Test name
Test status
Simulation time 213722311 ps
CPU time 3.27 seconds
Started Apr 21 01:42:43 PM PDT 24
Finished Apr 21 01:42:47 PM PDT 24
Peak memory 199536 kb
Host smart-142aaae4-b5fc-42d2-a9ec-c38d1d973c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710465438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.710465438
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2945377181
Short name T381
Test name
Test status
Simulation time 9910216407 ps
CPU time 483.57 seconds
Started Apr 21 01:42:46 PM PDT 24
Finished Apr 21 01:50:50 PM PDT 24
Peak memory 199700 kb
Host smart-fd3c20bd-8808-4132-9721-750b9f7e096c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945377181 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2945377181
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2206209566
Short name T211
Test name
Test status
Simulation time 31663951 ps
CPU time 0.98 seconds
Started Apr 21 01:42:47 PM PDT 24
Finished Apr 21 01:42:48 PM PDT 24
Peak memory 198824 kb
Host smart-508a5140-48b0-4964-b4f5-5fb36a916175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206209566 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2206209566
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2928699454
Short name T129
Test name
Test status
Simulation time 22812832516 ps
CPU time 400.64 seconds
Started Apr 21 01:42:45 PM PDT 24
Finished Apr 21 01:49:26 PM PDT 24
Peak memory 199736 kb
Host smart-0ed982af-5a5d-44ce-8e58-f6586b42cc19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928699454 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2928699454
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2392907848
Short name T300
Test name
Test status
Simulation time 1614213014 ps
CPU time 17.79 seconds
Started Apr 21 01:42:45 PM PDT 24
Finished Apr 21 01:43:03 PM PDT 24
Peak memory 199584 kb
Host smart-165d1099-4d4a-4ea7-975e-c88cbe3d0489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392907848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2392907848
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3902257914
Short name T526
Test name
Test status
Simulation time 14482124 ps
CPU time 0.56 seconds
Started Apr 21 01:43:03 PM PDT 24
Finished Apr 21 01:43:04 PM PDT 24
Peak memory 194192 kb
Host smart-05faf7f2-8e44-4dcd-a9aa-c3a050475344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902257914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3902257914
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.828115060
Short name T484
Test name
Test status
Simulation time 1408005123 ps
CPU time 56.58 seconds
Started Apr 21 01:42:53 PM PDT 24
Finished Apr 21 01:43:50 PM PDT 24
Peak memory 236592 kb
Host smart-761bde19-5140-4fc6-a8e4-981d865acc7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828115060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.828115060
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3067809974
Short name T308
Test name
Test status
Simulation time 698005270 ps
CPU time 17.39 seconds
Started Apr 21 01:42:57 PM PDT 24
Finished Apr 21 01:43:14 PM PDT 24
Peak memory 199604 kb
Host smart-d364514d-d2e3-4faf-851c-fbe2e255a7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067809974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3067809974
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.936456110
Short name T489
Test name
Test status
Simulation time 2473480773 ps
CPU time 133.18 seconds
Started Apr 21 01:42:53 PM PDT 24
Finished Apr 21 01:45:06 PM PDT 24
Peak memory 199628 kb
Host smart-beef8a95-ee12-4fd2-a909-0cf00dcef1bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936456110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.936456110
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.4010593016
Short name T41
Test name
Test status
Simulation time 20612587464 ps
CPU time 102.17 seconds
Started Apr 21 01:42:55 PM PDT 24
Finished Apr 21 01:44:38 PM PDT 24
Peak memory 199780 kb
Host smart-b496a5d2-8ada-4ba4-a3fe-ccef14935177
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010593016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.4010593016
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3666771942
Short name T548
Test name
Test status
Simulation time 7467645316 ps
CPU time 30.63 seconds
Started Apr 21 01:42:49 PM PDT 24
Finished Apr 21 01:43:20 PM PDT 24
Peak memory 199748 kb
Host smart-f9d7a6ff-7ad9-4494-aa04-da5965c539a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666771942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3666771942
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2045667935
Short name T208
Test name
Test status
Simulation time 836649822 ps
CPU time 2.93 seconds
Started Apr 21 01:42:49 PM PDT 24
Finished Apr 21 01:42:52 PM PDT 24
Peak memory 199580 kb
Host smart-c0263135-920e-4e6a-8236-5ec19197a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045667935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2045667935
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1611823841
Short name T574
Test name
Test status
Simulation time 38531670 ps
CPU time 1.24 seconds
Started Apr 21 01:43:00 PM PDT 24
Finished Apr 21 01:43:02 PM PDT 24
Peak memory 199624 kb
Host smart-978a7f64-5d4d-49c9-84f7-4160c1b57305
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611823841 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1611823841
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3339329395
Short name T421
Test name
Test status
Simulation time 170174333286 ps
CPU time 526.37 seconds
Started Apr 21 01:42:59 PM PDT 24
Finished Apr 21 01:51:46 PM PDT 24
Peak memory 199708 kb
Host smart-506eb48a-ec39-4e12-833b-92bcb58e20e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339329395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3339329395
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3479053718
Short name T397
Test name
Test status
Simulation time 3882853527 ps
CPU time 69.1 seconds
Started Apr 21 01:42:59 PM PDT 24
Finished Apr 21 01:44:08 PM PDT 24
Peak memory 199756 kb
Host smart-bedbeaa8-abf3-4e71-a074-1961ec904e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479053718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3479053718
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3239457659
Short name T209
Test name
Test status
Simulation time 34433881 ps
CPU time 0.53 seconds
Started Apr 21 01:43:11 PM PDT 24
Finished Apr 21 01:43:11 PM PDT 24
Peak memory 194176 kb
Host smart-bb035cf8-fa13-4be8-897e-0173787c8ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239457659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3239457659
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3593423868
Short name T258
Test name
Test status
Simulation time 1169350581 ps
CPU time 19.47 seconds
Started Apr 21 01:43:06 PM PDT 24
Finished Apr 21 01:43:25 PM PDT 24
Peak memory 207848 kb
Host smart-42644c7c-3286-4a7b-9b94-8540d3bae924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593423868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3593423868
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1696397283
Short name T192
Test name
Test status
Simulation time 1577153515 ps
CPU time 15.84 seconds
Started Apr 21 01:43:09 PM PDT 24
Finished Apr 21 01:43:25 PM PDT 24
Peak memory 199608 kb
Host smart-71ce8c0c-3b40-4694-9caf-4420344adcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696397283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1696397283
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3959405847
Short name T538
Test name
Test status
Simulation time 4423151068 ps
CPU time 124.28 seconds
Started Apr 21 01:43:04 PM PDT 24
Finished Apr 21 01:45:08 PM PDT 24
Peak memory 199688 kb
Host smart-f7d0f22d-2e70-4cf1-b92f-5bccce66f371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959405847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3959405847
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2522033177
Short name T278
Test name
Test status
Simulation time 2368699655 ps
CPU time 139.79 seconds
Started Apr 21 01:43:10 PM PDT 24
Finished Apr 21 01:45:30 PM PDT 24
Peak memory 199768 kb
Host smart-30c4f566-247d-4301-8cd5-0bf24a291bbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522033177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2522033177
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3603305985
Short name T345
Test name
Test status
Simulation time 4243835073 ps
CPU time 120.37 seconds
Started Apr 21 01:43:02 PM PDT 24
Finished Apr 21 01:45:03 PM PDT 24
Peak memory 199704 kb
Host smart-c447cbe2-8745-46cb-9fa4-36c95328f244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603305985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3603305985
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2134400990
Short name T443
Test name
Test status
Simulation time 330318323 ps
CPU time 5.28 seconds
Started Apr 21 01:43:01 PM PDT 24
Finished Apr 21 01:43:07 PM PDT 24
Peak memory 199560 kb
Host smart-2a68fcc8-4fcc-4c04-8ad7-79149b0a183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134400990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2134400990
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1030047984
Short name T416
Test name
Test status
Simulation time 24906002165 ps
CPU time 1287.89 seconds
Started Apr 21 01:43:13 PM PDT 24
Finished Apr 21 02:04:42 PM PDT 24
Peak memory 248636 kb
Host smart-bde78ed7-274a-4525-a616-66a227fec8ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030047984 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1030047984
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2905752494
Short name T160
Test name
Test status
Simulation time 256825153 ps
CPU time 1.21 seconds
Started Apr 21 01:43:11 PM PDT 24
Finished Apr 21 01:43:13 PM PDT 24
Peak memory 199576 kb
Host smart-b5535eb6-a5c2-42df-b94d-e033fa66baf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905752494 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2905752494
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3798074835
Short name T581
Test name
Test status
Simulation time 115875507240 ps
CPU time 481.17 seconds
Started Apr 21 01:43:12 PM PDT 24
Finished Apr 21 01:51:13 PM PDT 24
Peak memory 199748 kb
Host smart-73126a89-a58d-4380-84d5-de6ad7a6c4ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798074835 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3798074835
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2142843859
Short name T359
Test name
Test status
Simulation time 1829714124 ps
CPU time 50.75 seconds
Started Apr 21 01:43:10 PM PDT 24
Finished Apr 21 01:44:01 PM PDT 24
Peak memory 199632 kb
Host smart-c52a74ab-9600-4baf-a378-4ad70f193e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142843859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2142843859
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2305850997
Short name T19
Test name
Test status
Simulation time 16459053 ps
CPU time 0.56 seconds
Started Apr 21 01:43:17 PM PDT 24
Finished Apr 21 01:43:18 PM PDT 24
Peak memory 195280 kb
Host smart-6fd0174f-d680-4eec-84e6-8c7929ca294c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305850997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2305850997
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1754334469
Short name T505
Test name
Test status
Simulation time 5647890414 ps
CPU time 49.68 seconds
Started Apr 21 01:43:15 PM PDT 24
Finished Apr 21 01:44:05 PM PDT 24
Peak memory 224328 kb
Host smart-0ebe1a65-d33d-4cd2-9264-e577f71ae4ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754334469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1754334469
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.702083991
Short name T5
Test name
Test status
Simulation time 683597330 ps
CPU time 10.81 seconds
Started Apr 21 01:43:15 PM PDT 24
Finished Apr 21 01:43:26 PM PDT 24
Peak memory 199584 kb
Host smart-01879c19-8f0f-46f0-97a1-90a7a71ecc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702083991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.702083991
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3097037357
Short name T539
Test name
Test status
Simulation time 562874357 ps
CPU time 31.48 seconds
Started Apr 21 01:43:16 PM PDT 24
Finished Apr 21 01:43:48 PM PDT 24
Peak memory 199588 kb
Host smart-7c4820d5-0f70-4058-b5c9-e1d3bb4a21bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097037357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3097037357
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.567551117
Short name T12
Test name
Test status
Simulation time 47343877928 ps
CPU time 190.92 seconds
Started Apr 21 01:43:17 PM PDT 24
Finished Apr 21 01:46:29 PM PDT 24
Peak memory 199708 kb
Host smart-ae50ec3a-053b-4b7e-8860-77d79e93002f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567551117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.567551117
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2424674703
Short name T292
Test name
Test status
Simulation time 4045299539 ps
CPU time 57.95 seconds
Started Apr 21 01:43:14 PM PDT 24
Finished Apr 21 01:44:13 PM PDT 24
Peak memory 199748 kb
Host smart-a2e7e22c-3a77-4bbc-8e21-60c96b194dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424674703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2424674703
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.179324010
Short name T441
Test name
Test status
Simulation time 173050055 ps
CPU time 4.89 seconds
Started Apr 21 01:43:15 PM PDT 24
Finished Apr 21 01:43:20 PM PDT 24
Peak memory 199636 kb
Host smart-3f3243e0-fc90-47bb-bc91-64dcac063dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179324010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.179324010
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3567515818
Short name T76
Test name
Test status
Simulation time 94089900506 ps
CPU time 850.96 seconds
Started Apr 21 01:43:17 PM PDT 24
Finished Apr 21 01:57:28 PM PDT 24
Peak memory 199740 kb
Host smart-26ebf815-eb33-418f-8f60-b6b9b45d31bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567515818 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3567515818
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3033328894
Short name T239
Test name
Test status
Simulation time 159328070 ps
CPU time 1.18 seconds
Started Apr 21 01:43:17 PM PDT 24
Finished Apr 21 01:43:19 PM PDT 24
Peak memory 199604 kb
Host smart-a0eb95ea-1f32-41e7-b89d-0834f89038e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033328894 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3033328894
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1693903076
Short name T276
Test name
Test status
Simulation time 27643027960 ps
CPU time 402.32 seconds
Started Apr 21 01:43:18 PM PDT 24
Finished Apr 21 01:50:01 PM PDT 24
Peak memory 199756 kb
Host smart-562648eb-87bc-43ed-adeb-dd2469aa79ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693903076 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1693903076
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2414983733
Short name T242
Test name
Test status
Simulation time 2396531872 ps
CPU time 12.45 seconds
Started Apr 21 01:43:17 PM PDT 24
Finished Apr 21 01:43:29 PM PDT 24
Peak memory 199736 kb
Host smart-c8840ab4-3d1c-44dc-96ac-b7e80d7e418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414983733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2414983733
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2382395277
Short name T40
Test name
Test status
Simulation time 11197352 ps
CPU time 0.55 seconds
Started Apr 21 01:43:27 PM PDT 24
Finished Apr 21 01:43:28 PM PDT 24
Peak memory 194152 kb
Host smart-d6d04418-55c3-474c-b7d6-d43d82c63bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382395277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2382395277
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3298127663
Short name T16
Test name
Test status
Simulation time 1322116879 ps
CPU time 55.06 seconds
Started Apr 21 01:43:21 PM PDT 24
Finished Apr 21 01:44:17 PM PDT 24
Peak memory 231432 kb
Host smart-223df140-1cc0-4fb4-9558-ae6512cc3fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298127663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3298127663
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2778047198
Short name T3
Test name
Test status
Simulation time 6213726465 ps
CPU time 48.41 seconds
Started Apr 21 01:43:19 PM PDT 24
Finished Apr 21 01:44:08 PM PDT 24
Peak memory 199724 kb
Host smart-fc317134-fc1a-42b1-ad6b-f1f99712d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778047198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2778047198
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2553183160
Short name T561
Test name
Test status
Simulation time 1961360770 ps
CPU time 111.99 seconds
Started Apr 21 01:43:23 PM PDT 24
Finished Apr 21 01:45:15 PM PDT 24
Peak memory 199624 kb
Host smart-2c6a4ad9-5b3c-47e7-878c-88a0b6fa4f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553183160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2553183160
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.182587866
Short name T587
Test name
Test status
Simulation time 23707734798 ps
CPU time 103.12 seconds
Started Apr 21 01:43:25 PM PDT 24
Finished Apr 21 01:45:09 PM PDT 24
Peak memory 199760 kb
Host smart-cca8d23c-5d49-429d-9629-2faa8a75cacd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182587866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.182587866
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1279769881
Short name T395
Test name
Test status
Simulation time 9923402248 ps
CPU time 88.28 seconds
Started Apr 21 01:43:21 PM PDT 24
Finished Apr 21 01:44:50 PM PDT 24
Peak memory 199684 kb
Host smart-b269e69e-426d-4ca7-957c-23519bd93cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279769881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1279769881
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.127541540
Short name T231
Test name
Test status
Simulation time 434134168 ps
CPU time 2.74 seconds
Started Apr 21 01:43:19 PM PDT 24
Finished Apr 21 01:43:22 PM PDT 24
Peak memory 199644 kb
Host smart-d5baece8-6f72-422c-8beb-19bf431485ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127541540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.127541540
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1378812353
Short name T562
Test name
Test status
Simulation time 2438008953 ps
CPU time 64.28 seconds
Started Apr 21 01:43:24 PM PDT 24
Finished Apr 21 01:44:29 PM PDT 24
Peak memory 199700 kb
Host smart-5314f616-1521-4519-80e5-2d12fdd54253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378812353 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1378812353
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.4020831348
Short name T406
Test name
Test status
Simulation time 27225246 ps
CPU time 1.02 seconds
Started Apr 21 01:43:31 PM PDT 24
Finished Apr 21 01:43:32 PM PDT 24
Peak memory 199484 kb
Host smart-08eab861-6c4c-43a7-b79b-64c5d7475569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020831348 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.4020831348
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3334437619
Short name T583
Test name
Test status
Simulation time 82009170547 ps
CPU time 495.73 seconds
Started Apr 21 01:43:26 PM PDT 24
Finished Apr 21 01:51:42 PM PDT 24
Peak memory 199668 kb
Host smart-fb72c7d6-939d-4c24-b37c-1025ab797bd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334437619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3334437619
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.126190929
Short name T462
Test name
Test status
Simulation time 3586415627 ps
CPU time 47.61 seconds
Started Apr 21 01:43:24 PM PDT 24
Finished Apr 21 01:44:11 PM PDT 24
Peak memory 199756 kb
Host smart-74db86b4-1f7d-4a80-9401-22023558ce85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126190929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.126190929
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1723652894
Short name T446
Test name
Test status
Simulation time 36517502 ps
CPU time 0.56 seconds
Started Apr 21 01:43:41 PM PDT 24
Finished Apr 21 01:43:42 PM PDT 24
Peak memory 195192 kb
Host smart-db8771c1-21d3-4ac9-8d75-025d96075c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723652894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1723652894
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3872139134
Short name T593
Test name
Test status
Simulation time 2027166393 ps
CPU time 21.57 seconds
Started Apr 21 01:43:30 PM PDT 24
Finished Apr 21 01:43:52 PM PDT 24
Peak memory 225048 kb
Host smart-ef080a10-16e3-46a4-8050-645e748e5e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872139134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3872139134
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2446110660
Short name T228
Test name
Test status
Simulation time 3082762877 ps
CPU time 28.53 seconds
Started Apr 21 01:43:32 PM PDT 24
Finished Apr 21 01:44:00 PM PDT 24
Peak memory 199716 kb
Host smart-935bddf1-5687-4032-9a81-2525ad1efbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446110660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2446110660
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1199249150
Short name T309
Test name
Test status
Simulation time 4574225080 ps
CPU time 125.46 seconds
Started Apr 21 01:43:28 PM PDT 24
Finished Apr 21 01:45:34 PM PDT 24
Peak memory 199788 kb
Host smart-f58cec05-980f-41f8-a803-5497ea44a4d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199249150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1199249150
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2838579192
Short name T431
Test name
Test status
Simulation time 686242118 ps
CPU time 6.53 seconds
Started Apr 21 01:43:29 PM PDT 24
Finished Apr 21 01:43:36 PM PDT 24
Peak memory 199508 kb
Host smart-ecd6dad9-98f4-4a50-8795-671c5923c243
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838579192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2838579192
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2246103255
Short name T479
Test name
Test status
Simulation time 16454908537 ps
CPU time 78.98 seconds
Started Apr 21 01:43:28 PM PDT 24
Finished Apr 21 01:44:47 PM PDT 24
Peak memory 199696 kb
Host smart-fcd3c25d-9c6f-47a6-a538-83ba15998016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246103255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2246103255
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1403136612
Short name T267
Test name
Test status
Simulation time 1351762318 ps
CPU time 4.26 seconds
Started Apr 21 01:43:30 PM PDT 24
Finished Apr 21 01:43:35 PM PDT 24
Peak memory 199616 kb
Host smart-97f51677-57fa-4efc-97aa-37730622715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403136612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1403136612
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1021026622
Short name T492
Test name
Test status
Simulation time 53820681965 ps
CPU time 723.2 seconds
Started Apr 21 01:43:36 PM PDT 24
Finished Apr 21 01:55:39 PM PDT 24
Peak memory 216080 kb
Host smart-b131db1d-e65d-4135-a25b-0107bd92277d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021026622 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1021026622
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2973449177
Short name T319
Test name
Test status
Simulation time 52834598 ps
CPU time 1.01 seconds
Started Apr 21 01:43:37 PM PDT 24
Finished Apr 21 01:43:38 PM PDT 24
Peak memory 198976 kb
Host smart-7d09ea5e-08c0-4f1b-b7dc-65c11c7c7f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973449177 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2973449177
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2686515383
Short name T252
Test name
Test status
Simulation time 85198730179 ps
CPU time 525.56 seconds
Started Apr 21 01:43:34 PM PDT 24
Finished Apr 21 01:52:20 PM PDT 24
Peak memory 199736 kb
Host smart-d3f76388-7a6b-40f6-a3e1-8fcf4b803713
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686515383 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2686515383
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2413320560
Short name T597
Test name
Test status
Simulation time 4338064577 ps
CPU time 83.05 seconds
Started Apr 21 01:43:34 PM PDT 24
Finished Apr 21 01:44:57 PM PDT 24
Peak memory 199708 kb
Host smart-224a5a47-1b03-44a9-9558-15d1dc44b154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413320560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2413320560
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2171386753
Short name T302
Test name
Test status
Simulation time 21733419 ps
CPU time 0.55 seconds
Started Apr 21 01:39:02 PM PDT 24
Finished Apr 21 01:39:03 PM PDT 24
Peak memory 195264 kb
Host smart-00371790-5439-469b-a7bb-8140129a4a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171386753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2171386753
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1340575152
Short name T586
Test name
Test status
Simulation time 1767179061 ps
CPU time 25.1 seconds
Started Apr 21 01:39:00 PM PDT 24
Finished Apr 21 01:39:26 PM PDT 24
Peak memory 232320 kb
Host smart-1e482ffb-09f1-494e-9c82-6ef140bfd3a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1340575152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1340575152
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1152935392
Short name T594
Test name
Test status
Simulation time 193374631 ps
CPU time 9.7 seconds
Started Apr 21 01:39:01 PM PDT 24
Finished Apr 21 01:39:11 PM PDT 24
Peak memory 199588 kb
Host smart-ddd77fb6-7b2f-421e-b710-9db658fa84d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152935392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1152935392
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1942504136
Short name T275
Test name
Test status
Simulation time 896582678 ps
CPU time 3.97 seconds
Started Apr 21 01:38:58 PM PDT 24
Finished Apr 21 01:39:03 PM PDT 24
Peak memory 199648 kb
Host smart-591e7882-e6b5-4167-b830-cd49894b9449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942504136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1942504136
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.4058604698
Short name T181
Test name
Test status
Simulation time 2821585130 ps
CPU time 149.71 seconds
Started Apr 21 01:39:01 PM PDT 24
Finished Apr 21 01:41:31 PM PDT 24
Peak memory 199776 kb
Host smart-0ed4db65-005c-4ac9-8352-23426682479d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058604698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4058604698
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2761867408
Short name T379
Test name
Test status
Simulation time 1187138229 ps
CPU time 11.48 seconds
Started Apr 21 01:39:01 PM PDT 24
Finished Apr 21 01:39:12 PM PDT 24
Peak memory 199572 kb
Host smart-1cdcc1d0-30a8-4491-b230-7e0b40f03be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761867408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2761867408
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2015362912
Short name T29
Test name
Test status
Simulation time 312429779 ps
CPU time 0.98 seconds
Started Apr 21 01:39:01 PM PDT 24
Finished Apr 21 01:39:02 PM PDT 24
Peak memory 219260 kb
Host smart-b5249b24-c69a-4d05-af9a-171594ee74ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015362912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2015362912
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2015233047
Short name T457
Test name
Test status
Simulation time 950175969 ps
CPU time 6.78 seconds
Started Apr 21 01:39:01 PM PDT 24
Finished Apr 21 01:39:08 PM PDT 24
Peak memory 199552 kb
Host smart-da2ae29b-9b9f-46e0-ad42-930107cae3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015233047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2015233047
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1292937158
Short name T517
Test name
Test status
Simulation time 45182886591 ps
CPU time 607.97 seconds
Started Apr 21 01:39:03 PM PDT 24
Finished Apr 21 01:49:11 PM PDT 24
Peak memory 233544 kb
Host smart-3e9f15dc-efb5-4da3-8f86-0134babcbf72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292937158 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1292937158
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3995946583
Short name T428
Test name
Test status
Simulation time 100319557 ps
CPU time 0.92 seconds
Started Apr 21 01:39:03 PM PDT 24
Finished Apr 21 01:39:05 PM PDT 24
Peak memory 197736 kb
Host smart-5019dd87-4bd6-47ee-8366-7abb94f6f7b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995946583 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3995946583
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.573299925
Short name T240
Test name
Test status
Simulation time 30946364290 ps
CPU time 532.23 seconds
Started Apr 21 01:39:02 PM PDT 24
Finished Apr 21 01:47:55 PM PDT 24
Peak memory 199748 kb
Host smart-59bea12d-2182-4f7f-9f4f-d7bf6d8b1c69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573299925 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.573299925
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3585529677
Short name T391
Test name
Test status
Simulation time 28076740448 ps
CPU time 91.64 seconds
Started Apr 21 01:39:04 PM PDT 24
Finished Apr 21 01:40:36 PM PDT 24
Peak memory 199680 kb
Host smart-ffa0d5ca-fdc2-4bfc-977b-fa8ceff5fbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585529677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3585529677
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3556976552
Short name T374
Test name
Test status
Simulation time 12546066 ps
CPU time 0.53 seconds
Started Apr 21 01:43:58 PM PDT 24
Finished Apr 21 01:43:59 PM PDT 24
Peak memory 194868 kb
Host smart-e8506167-66dc-4c39-88ac-b298f1664750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556976552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3556976552
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1671660336
Short name T434
Test name
Test status
Simulation time 1003745362 ps
CPU time 38.65 seconds
Started Apr 21 01:43:45 PM PDT 24
Finished Apr 21 01:44:24 PM PDT 24
Peak memory 231368 kb
Host smart-b652686b-e80c-4e6a-940a-9e881d891de5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671660336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1671660336
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3289214965
Short name T274
Test name
Test status
Simulation time 1325159540 ps
CPU time 64.36 seconds
Started Apr 21 01:43:47 PM PDT 24
Finished Apr 21 01:44:52 PM PDT 24
Peak memory 199592 kb
Host smart-9bc7088f-2c88-4846-b4ee-8526cd9f3733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289214965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3289214965
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3773696876
Short name T166
Test name
Test status
Simulation time 2527666969 ps
CPU time 137.68 seconds
Started Apr 21 01:43:47 PM PDT 24
Finished Apr 21 01:46:05 PM PDT 24
Peak memory 199752 kb
Host smart-438cbe7c-c3e4-447f-abbf-569b884ff262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773696876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3773696876
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3937420933
Short name T347
Test name
Test status
Simulation time 20983243300 ps
CPU time 131.39 seconds
Started Apr 21 01:43:48 PM PDT 24
Finished Apr 21 01:46:00 PM PDT 24
Peak memory 199752 kb
Host smart-becf556e-b7ae-47c2-a8a5-984aaebdef76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937420933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3937420933
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3778620237
Short name T580
Test name
Test status
Simulation time 2071633462 ps
CPU time 10.1 seconds
Started Apr 21 01:43:45 PM PDT 24
Finished Apr 21 01:43:55 PM PDT 24
Peak memory 199592 kb
Host smart-5ac48b6d-f02e-4d01-a28a-9fbb983322ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778620237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3778620237
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2739117793
Short name T79
Test name
Test status
Simulation time 28038891 ps
CPU time 0.87 seconds
Started Apr 21 01:43:43 PM PDT 24
Finished Apr 21 01:43:44 PM PDT 24
Peak memory 196884 kb
Host smart-58a1ef26-f0fc-4bf8-803d-6eec77a10051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739117793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2739117793
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3033400521
Short name T331
Test name
Test status
Simulation time 20846037147 ps
CPU time 1013.39 seconds
Started Apr 21 01:43:57 PM PDT 24
Finished Apr 21 02:00:51 PM PDT 24
Peak memory 199716 kb
Host smart-12ef1ead-1b95-4930-8002-61317c0ee09e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033400521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3033400521
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3202090765
Short name T316
Test name
Test status
Simulation time 84780691 ps
CPU time 0.97 seconds
Started Apr 21 01:43:56 PM PDT 24
Finished Apr 21 01:43:57 PM PDT 24
Peak memory 199156 kb
Host smart-63f7986a-f061-4c5b-81bd-c89dacc8eddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202090765 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3202090765
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3517288531
Short name T524
Test name
Test status
Simulation time 115767860300 ps
CPU time 475.32 seconds
Started Apr 21 01:43:56 PM PDT 24
Finished Apr 21 01:51:52 PM PDT 24
Peak memory 199596 kb
Host smart-ef6e13dd-5923-45cf-bacc-cbea012b5c32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517288531 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3517288531
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2449810440
Short name T37
Test name
Test status
Simulation time 949201517 ps
CPU time 18.68 seconds
Started Apr 21 01:43:48 PM PDT 24
Finished Apr 21 01:44:07 PM PDT 24
Peak memory 199620 kb
Host smart-f518ae4c-576b-417a-b3dc-3de0524ae2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449810440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2449810440
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3079355275
Short name T324
Test name
Test status
Simulation time 48107524 ps
CPU time 0.6 seconds
Started Apr 21 01:44:02 PM PDT 24
Finished Apr 21 01:44:03 PM PDT 24
Peak memory 194176 kb
Host smart-37d66dc0-49f1-4e13-8648-f05e7e53d327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079355275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3079355275
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2379367216
Short name T567
Test name
Test status
Simulation time 411240925 ps
CPU time 13.21 seconds
Started Apr 21 01:43:58 PM PDT 24
Finished Apr 21 01:44:12 PM PDT 24
Peak memory 207836 kb
Host smart-c6281ea5-483a-459b-b890-468b599f178e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379367216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2379367216
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1412331222
Short name T403
Test name
Test status
Simulation time 1001777461 ps
CPU time 19.48 seconds
Started Apr 21 01:43:56 PM PDT 24
Finished Apr 21 01:44:16 PM PDT 24
Peak memory 199648 kb
Host smart-3e9ccd61-9221-407e-a65c-587b29d92cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412331222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1412331222
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1808773282
Short name T328
Test name
Test status
Simulation time 8410249829 ps
CPU time 116.38 seconds
Started Apr 21 01:43:58 PM PDT 24
Finished Apr 21 01:45:54 PM PDT 24
Peak memory 199744 kb
Host smart-0e59b005-c162-4763-b9a4-5796922e2e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808773282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1808773282
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.236504269
Short name T219
Test name
Test status
Simulation time 4441256725 ps
CPU time 40.89 seconds
Started Apr 21 01:43:57 PM PDT 24
Finished Apr 21 01:44:38 PM PDT 24
Peak memory 199780 kb
Host smart-5fc6e5bd-5f27-4a9a-b03d-ac1e8cd93b9c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236504269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.236504269
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3123555641
Short name T390
Test name
Test status
Simulation time 2124084277 ps
CPU time 20.26 seconds
Started Apr 21 01:43:57 PM PDT 24
Finished Apr 21 01:44:18 PM PDT 24
Peak memory 199584 kb
Host smart-f42594ec-1f7e-4f1f-afc0-09f933f8ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123555641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3123555641
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2982014128
Short name T430
Test name
Test status
Simulation time 615926024 ps
CPU time 4.88 seconds
Started Apr 21 01:43:50 PM PDT 24
Finished Apr 21 01:43:55 PM PDT 24
Peak memory 199588 kb
Host smart-213d3804-f422-4ff6-8b68-9541fdea3f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982014128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2982014128
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2379043941
Short name T70
Test name
Test status
Simulation time 81963172354 ps
CPU time 1030.16 seconds
Started Apr 21 01:44:04 PM PDT 24
Finished Apr 21 02:01:14 PM PDT 24
Peak memory 216144 kb
Host smart-64688919-1f46-483f-8054-814614db4acc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379043941 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2379043941
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3651437744
Short name T159
Test name
Test status
Simulation time 34773388 ps
CPU time 1.26 seconds
Started Apr 21 01:44:00 PM PDT 24
Finished Apr 21 01:44:02 PM PDT 24
Peak memory 199568 kb
Host smart-0a1de09a-3721-41d9-b200-b597471d4615
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651437744 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3651437744
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.179192325
Short name T563
Test name
Test status
Simulation time 9540464658 ps
CPU time 416.63 seconds
Started Apr 21 01:43:58 PM PDT 24
Finished Apr 21 01:50:55 PM PDT 24
Peak memory 199724 kb
Host smart-0a13a943-8f20-45e6-8e54-efb8786d4610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179192325 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.179192325
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3783389655
Short name T504
Test name
Test status
Simulation time 1901021599 ps
CPU time 34.56 seconds
Started Apr 21 01:43:59 PM PDT 24
Finished Apr 21 01:44:33 PM PDT 24
Peak memory 199556 kb
Host smart-39dfe43f-e447-4a62-898b-619824b408ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783389655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3783389655
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2288435804
Short name T371
Test name
Test status
Simulation time 46881670 ps
CPU time 0.57 seconds
Started Apr 21 01:44:12 PM PDT 24
Finished Apr 21 01:44:13 PM PDT 24
Peak memory 194212 kb
Host smart-803ec24c-daff-4eca-aff6-a0d196856f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288435804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2288435804
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3148605878
Short name T244
Test name
Test status
Simulation time 531080339 ps
CPU time 20.68 seconds
Started Apr 21 01:43:58 PM PDT 24
Finished Apr 21 01:44:19 PM PDT 24
Peak memory 223692 kb
Host smart-f715069b-f97d-47c1-858c-a6d5e978a2ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148605878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3148605878
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3994759378
Short name T123
Test name
Test status
Simulation time 10457251962 ps
CPU time 52.77 seconds
Started Apr 21 01:44:02 PM PDT 24
Finished Apr 21 01:44:55 PM PDT 24
Peak memory 199700 kb
Host smart-de9f3b2b-67dd-4b88-9f6e-2ec282adccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994759378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3994759378
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.154778602
Short name T78
Test name
Test status
Simulation time 2720795901 ps
CPU time 75.56 seconds
Started Apr 21 01:43:59 PM PDT 24
Finished Apr 21 01:45:15 PM PDT 24
Peak memory 199752 kb
Host smart-f9512d3b-7886-4388-b0df-d21d12c26538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154778602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.154778602
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1506421921
Short name T566
Test name
Test status
Simulation time 402864041 ps
CPU time 20.98 seconds
Started Apr 21 01:44:05 PM PDT 24
Finished Apr 21 01:44:26 PM PDT 24
Peak memory 199616 kb
Host smart-d9d27175-1119-4b20-8747-8812cdd5b3b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506421921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1506421921
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.948711912
Short name T215
Test name
Test status
Simulation time 2609853874 ps
CPU time 37.27 seconds
Started Apr 21 01:43:58 PM PDT 24
Finished Apr 21 01:44:36 PM PDT 24
Peak memory 199748 kb
Host smart-f44ec66a-d3ba-4cad-83e8-3159173d5cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948711912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.948711912
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1733701156
Short name T494
Test name
Test status
Simulation time 206329543 ps
CPU time 6.08 seconds
Started Apr 21 01:44:03 PM PDT 24
Finished Apr 21 01:44:09 PM PDT 24
Peak memory 199628 kb
Host smart-c5714914-f1f0-41b3-bc8b-0353b1f23924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733701156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1733701156
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.192048299
Short name T250
Test name
Test status
Simulation time 15398531162 ps
CPU time 446.37 seconds
Started Apr 21 01:44:07 PM PDT 24
Finished Apr 21 01:51:34 PM PDT 24
Peak memory 199680 kb
Host smart-0eb376e0-3923-4769-b503-019078293561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192048299 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.192048299
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1205615866
Short name T450
Test name
Test status
Simulation time 54684218 ps
CPU time 1.15 seconds
Started Apr 21 01:44:09 PM PDT 24
Finished Apr 21 01:44:11 PM PDT 24
Peak memory 199612 kb
Host smart-92dda523-0b5c-417f-96e6-1a4d1e2670ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205615866 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1205615866
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.879369457
Short name T157
Test name
Test status
Simulation time 24925186168 ps
CPU time 422.12 seconds
Started Apr 21 01:44:03 PM PDT 24
Finished Apr 21 01:51:06 PM PDT 24
Peak memory 199744 kb
Host smart-bcd3376a-553e-443d-b4d9-4c05776ae2ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879369457 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.879369457
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1118616042
Short name T179
Test name
Test status
Simulation time 21123959531 ps
CPU time 21.01 seconds
Started Apr 21 01:44:04 PM PDT 24
Finished Apr 21 01:44:25 PM PDT 24
Peak memory 199736 kb
Host smart-c4833d32-7a3b-4430-9fab-ebcd9bcac92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118616042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1118616042
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.4130732794
Short name T18
Test name
Test status
Simulation time 36215356 ps
CPU time 0.55 seconds
Started Apr 21 01:44:26 PM PDT 24
Finished Apr 21 01:44:26 PM PDT 24
Peak memory 195220 kb
Host smart-b2f9213f-0d32-472d-961f-ced806a05549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130732794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.4130732794
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2693039736
Short name T156
Test name
Test status
Simulation time 1864192872 ps
CPU time 65.07 seconds
Started Apr 21 01:44:14 PM PDT 24
Finished Apr 21 01:45:20 PM PDT 24
Peak memory 215960 kb
Host smart-51a8cf7e-3be0-494b-85fb-45273e6a9b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693039736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2693039736
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1054917921
Short name T453
Test name
Test status
Simulation time 11365712222 ps
CPU time 35.67 seconds
Started Apr 21 01:44:20 PM PDT 24
Finished Apr 21 01:44:55 PM PDT 24
Peak memory 199740 kb
Host smart-458d3680-de23-4fa5-b861-0702b4a7da32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054917921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1054917921
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4290184668
Short name T454
Test name
Test status
Simulation time 3214818316 ps
CPU time 146.44 seconds
Started Apr 21 01:44:19 PM PDT 24
Finished Apr 21 01:46:46 PM PDT 24
Peak memory 199740 kb
Host smart-d4e50917-4927-4c94-8081-0f8781375da2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290184668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4290184668
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3828538135
Short name T400
Test name
Test status
Simulation time 10788885456 ps
CPU time 104.61 seconds
Started Apr 21 01:44:17 PM PDT 24
Finished Apr 21 01:46:01 PM PDT 24
Peak memory 199732 kb
Host smart-31d88cfa-487a-4e52-9d83-b24f993943a5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828538135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3828538135
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3187422612
Short name T57
Test name
Test status
Simulation time 26504632905 ps
CPU time 101.84 seconds
Started Apr 21 01:44:17 PM PDT 24
Finished Apr 21 01:45:59 PM PDT 24
Peak memory 199752 kb
Host smart-d3b72798-8ee5-4a6a-a96e-5d306b20977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187422612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3187422612
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3938426352
Short name T444
Test name
Test status
Simulation time 2096571705 ps
CPU time 6.59 seconds
Started Apr 21 01:44:15 PM PDT 24
Finished Apr 21 01:44:22 PM PDT 24
Peak memory 199576 kb
Host smart-816325d6-bc04-4d4d-9f08-4921556a93d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938426352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3938426352
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2527788525
Short name T570
Test name
Test status
Simulation time 66169735876 ps
CPU time 898.58 seconds
Started Apr 21 01:44:26 PM PDT 24
Finished Apr 21 01:59:25 PM PDT 24
Peak memory 199728 kb
Host smart-a8ee203e-1576-479f-bf6c-0f73fdfc8f4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527788525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2527788525
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2889690788
Short name T427
Test name
Test status
Simulation time 32201000 ps
CPU time 1.23 seconds
Started Apr 21 01:44:23 PM PDT 24
Finished Apr 21 01:44:24 PM PDT 24
Peak memory 199356 kb
Host smart-3560a1ae-2fbd-4822-bafb-180d0448ff5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889690788 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2889690788
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.4291817667
Short name T167
Test name
Test status
Simulation time 125204101904 ps
CPU time 561.53 seconds
Started Apr 21 01:44:22 PM PDT 24
Finished Apr 21 01:53:44 PM PDT 24
Peak memory 199704 kb
Host smart-38bf3a72-3dd3-420c-a4c5-c92ac70ba7d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291817667 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.4291817667
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1888725561
Short name T285
Test name
Test status
Simulation time 183418174 ps
CPU time 2.12 seconds
Started Apr 21 01:44:21 PM PDT 24
Finished Apr 21 01:44:23 PM PDT 24
Peak memory 199648 kb
Host smart-c96770fd-55e3-4666-8231-6d00f078431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888725561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1888725561
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.778998280
Short name T349
Test name
Test status
Simulation time 38414642 ps
CPU time 0.53 seconds
Started Apr 21 01:44:34 PM PDT 24
Finished Apr 21 01:44:35 PM PDT 24
Peak memory 194132 kb
Host smart-13db4862-5c1e-43a4-a08c-3d262d0ca9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778998280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.778998280
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.795934106
Short name T217
Test name
Test status
Simulation time 5156642427 ps
CPU time 43.1 seconds
Started Apr 21 01:44:25 PM PDT 24
Finished Apr 21 01:45:08 PM PDT 24
Peak memory 224348 kb
Host smart-47987f6b-0316-4dae-9156-ea2e25e34059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795934106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.795934106
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2015283908
Short name T148
Test name
Test status
Simulation time 74503150 ps
CPU time 0.64 seconds
Started Apr 21 01:44:26 PM PDT 24
Finished Apr 21 01:44:27 PM PDT 24
Peak memory 196928 kb
Host smart-bee18f4d-0d76-44a1-8493-792e28d28108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015283908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2015283908
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1072812971
Short name T380
Test name
Test status
Simulation time 688140769 ps
CPU time 37.03 seconds
Started Apr 21 01:44:27 PM PDT 24
Finished Apr 21 01:45:04 PM PDT 24
Peak memory 199660 kb
Host smart-f3e5677a-80a0-4427-8c77-18981f8ca5f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072812971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1072812971
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3585442249
Short name T163
Test name
Test status
Simulation time 10821849941 ps
CPU time 57.56 seconds
Started Apr 21 01:44:31 PM PDT 24
Finished Apr 21 01:45:29 PM PDT 24
Peak memory 199700 kb
Host smart-076f43fb-2341-465b-b8a4-faee35400889
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585442249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3585442249
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3139884886
Short name T286
Test name
Test status
Simulation time 7395898631 ps
CPU time 34.26 seconds
Started Apr 21 01:44:25 PM PDT 24
Finished Apr 21 01:44:59 PM PDT 24
Peak memory 199748 kb
Host smart-4f386d2a-14f5-49ab-8d38-1b3f252f760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139884886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3139884886
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2463842446
Short name T398
Test name
Test status
Simulation time 470676751 ps
CPU time 5.16 seconds
Started Apr 21 01:44:26 PM PDT 24
Finished Apr 21 01:44:32 PM PDT 24
Peak memory 199616 kb
Host smart-dc298a84-47c3-4c8f-9c32-de04b6a3881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463842446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2463842446
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.4221584355
Short name T155
Test name
Test status
Simulation time 6134072928 ps
CPU time 294.53 seconds
Started Apr 21 01:44:32 PM PDT 24
Finished Apr 21 01:49:27 PM PDT 24
Peak memory 199764 kb
Host smart-e49c7c96-a866-47b1-a996-9c28b0ceaae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221584355 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.4221584355
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2690518622
Short name T226
Test name
Test status
Simulation time 29908399 ps
CPU time 1.18 seconds
Started Apr 21 01:44:32 PM PDT 24
Finished Apr 21 01:44:34 PM PDT 24
Peak memory 199644 kb
Host smart-b551d8bf-3a64-450e-ad87-8c5dc172c2b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690518622 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2690518622
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2168285029
Short name T55
Test name
Test status
Simulation time 17545511754 ps
CPU time 436.98 seconds
Started Apr 21 01:44:31 PM PDT 24
Finished Apr 21 01:51:48 PM PDT 24
Peak memory 199688 kb
Host smart-afc903d2-0a1b-464a-b410-0b44af85be5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168285029 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2168285029
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2907437846
Short name T138
Test name
Test status
Simulation time 14325175924 ps
CPU time 35.63 seconds
Started Apr 21 01:44:31 PM PDT 24
Finished Apr 21 01:45:07 PM PDT 24
Peak memory 199704 kb
Host smart-341c6ed3-0169-4581-9e49-d305bbb99864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907437846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2907437846
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.106946524
Short name T474
Test name
Test status
Simulation time 16828565 ps
CPU time 0.58 seconds
Started Apr 21 01:44:44 PM PDT 24
Finished Apr 21 01:44:44 PM PDT 24
Peak memory 194868 kb
Host smart-12f9c0b5-d02b-43d3-8e90-23828b90d2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106946524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.106946524
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1340721772
Short name T354
Test name
Test status
Simulation time 795009747 ps
CPU time 13.94 seconds
Started Apr 21 01:44:39 PM PDT 24
Finished Apr 21 01:44:53 PM PDT 24
Peak memory 207832 kb
Host smart-23419f38-061c-41ff-bbbc-6b6d81251263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1340721772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1340721772
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2945879379
Short name T556
Test name
Test status
Simulation time 1111574839 ps
CPU time 11.04 seconds
Started Apr 21 01:44:43 PM PDT 24
Finished Apr 21 01:44:54 PM PDT 24
Peak memory 199636 kb
Host smart-9cd5bf3a-baff-4256-9308-cef6f9876eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945879379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2945879379
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.233045483
Short name T119
Test name
Test status
Simulation time 1032474071 ps
CPU time 55.66 seconds
Started Apr 21 01:44:40 PM PDT 24
Finished Apr 21 01:45:36 PM PDT 24
Peak memory 199648 kb
Host smart-b18ce88b-315c-494a-b216-d529b445fc1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233045483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.233045483
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3767543171
Short name T145
Test name
Test status
Simulation time 188418407282 ps
CPU time 149.78 seconds
Started Apr 21 01:44:39 PM PDT 24
Finished Apr 21 01:47:09 PM PDT 24
Peak memory 199724 kb
Host smart-1b5b3429-9385-40cd-aacb-82d736998208
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767543171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3767543171
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.35066598
Short name T162
Test name
Test status
Simulation time 3982595509 ps
CPU time 66.35 seconds
Started Apr 21 01:44:38 PM PDT 24
Finished Apr 21 01:45:44 PM PDT 24
Peak memory 199748 kb
Host smart-42a1398e-b197-4e60-a0f8-6c87e1c58ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35066598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.35066598
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1906986191
Short name T189
Test name
Test status
Simulation time 1299056505 ps
CPU time 6.91 seconds
Started Apr 21 01:44:36 PM PDT 24
Finished Apr 21 01:44:43 PM PDT 24
Peak memory 199620 kb
Host smart-539dcf0e-21ec-4f28-92df-24b462c075e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906986191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1906986191
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3350387320
Short name T340
Test name
Test status
Simulation time 113951848948 ps
CPU time 1456.97 seconds
Started Apr 21 01:44:43 PM PDT 24
Finished Apr 21 02:09:00 PM PDT 24
Peak memory 215236 kb
Host smart-3d620eb3-1ff4-425f-ba0d-80e56a456a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350387320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3350387320
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.734270712
Short name T121
Test name
Test status
Simulation time 200311578 ps
CPU time 1.11 seconds
Started Apr 21 01:44:42 PM PDT 24
Finished Apr 21 01:44:44 PM PDT 24
Peak memory 199552 kb
Host smart-a02cc8e3-2f51-4825-a23f-c70e787ff9de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734270712 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.734270712
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.972317043
Short name T222
Test name
Test status
Simulation time 69961480327 ps
CPU time 441.43 seconds
Started Apr 21 01:44:40 PM PDT 24
Finished Apr 21 01:52:02 PM PDT 24
Peak memory 199704 kb
Host smart-998d2a69-ea5a-4e0e-8462-2ceed5292784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972317043 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.972317043
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.502107588
Short name T304
Test name
Test status
Simulation time 1441988454 ps
CPU time 26.13 seconds
Started Apr 21 01:44:41 PM PDT 24
Finished Apr 21 01:45:07 PM PDT 24
Peak memory 199636 kb
Host smart-77f891bf-1ba5-4b75-95e3-ee68fbccac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502107588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.502107588
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3588813361
Short name T291
Test name
Test status
Simulation time 126601551 ps
CPU time 0.55 seconds
Started Apr 21 01:44:56 PM PDT 24
Finished Apr 21 01:44:57 PM PDT 24
Peak memory 195316 kb
Host smart-52824769-7edf-451d-b09d-5be0fc21ee0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588813361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3588813361
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2774784020
Short name T422
Test name
Test status
Simulation time 5125196933 ps
CPU time 48.91 seconds
Started Apr 21 01:44:46 PM PDT 24
Finished Apr 21 01:45:35 PM PDT 24
Peak memory 240636 kb
Host smart-4ed6a678-b3da-4145-a219-45b7c63632ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774784020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2774784020
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1802100673
Short name T246
Test name
Test status
Simulation time 663780842 ps
CPU time 11.91 seconds
Started Apr 21 01:44:48 PM PDT 24
Finished Apr 21 01:45:00 PM PDT 24
Peak memory 199640 kb
Host smart-98bffd14-1980-4310-87d6-55515b35688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802100673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1802100673
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.661668380
Short name T170
Test name
Test status
Simulation time 5297957068 ps
CPU time 78.71 seconds
Started Apr 21 01:44:46 PM PDT 24
Finished Apr 21 01:46:05 PM PDT 24
Peak memory 199752 kb
Host smart-1ae9c856-29d7-4ac3-b80f-29d6a0cd1711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661668380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.661668380
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2865044729
Short name T45
Test name
Test status
Simulation time 23045817646 ps
CPU time 204.62 seconds
Started Apr 21 01:44:50 PM PDT 24
Finished Apr 21 01:48:15 PM PDT 24
Peak memory 199760 kb
Host smart-f7784606-b7b0-4409-855d-1b007d6c5575
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865044729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2865044729
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.287061269
Short name T564
Test name
Test status
Simulation time 1999211731 ps
CPU time 27.49 seconds
Started Apr 21 01:44:43 PM PDT 24
Finished Apr 21 01:45:11 PM PDT 24
Peak memory 199624 kb
Host smart-5c4ea388-ccdc-4e36-b839-44df2f23defa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287061269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.287061269
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2415802836
Short name T312
Test name
Test status
Simulation time 171360619 ps
CPU time 1.69 seconds
Started Apr 21 01:44:43 PM PDT 24
Finished Apr 21 01:44:44 PM PDT 24
Peak memory 199636 kb
Host smart-a791576a-d387-48ef-8622-a1846855232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415802836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2415802836
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.642431542
Short name T280
Test name
Test status
Simulation time 77760668749 ps
CPU time 964.39 seconds
Started Apr 21 01:44:52 PM PDT 24
Finished Apr 21 02:00:56 PM PDT 24
Peak memory 240716 kb
Host smart-deab7917-7a9f-4083-8eee-c92b716591cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642431542 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.642431542
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2882669727
Short name T266
Test name
Test status
Simulation time 47748285 ps
CPU time 1.03 seconds
Started Apr 21 01:44:52 PM PDT 24
Finished Apr 21 01:44:53 PM PDT 24
Peak memory 199304 kb
Host smart-6fe51a6e-15b6-4e38-a385-c3b9287c64d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882669727 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2882669727
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.265147119
Short name T142
Test name
Test status
Simulation time 52557932920 ps
CPU time 509.64 seconds
Started Apr 21 01:44:49 PM PDT 24
Finished Apr 21 01:53:19 PM PDT 24
Peak memory 199712 kb
Host smart-4c501999-4ad8-43ee-b04c-1999d0694e3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265147119 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.265147119
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2389711186
Short name T186
Test name
Test status
Simulation time 10386311258 ps
CPU time 68.71 seconds
Started Apr 21 01:44:50 PM PDT 24
Finished Apr 21 01:45:59 PM PDT 24
Peak memory 199752 kb
Host smart-29971b60-77c8-48c3-ac7a-44b731da2716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389711186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2389711186
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2520331766
Short name T297
Test name
Test status
Simulation time 114559030 ps
CPU time 0.62 seconds
Started Apr 21 01:45:03 PM PDT 24
Finished Apr 21 01:45:04 PM PDT 24
Peak memory 195240 kb
Host smart-82aed675-0b1f-44dd-a674-9681b03c5cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520331766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2520331766
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4035403482
Short name T247
Test name
Test status
Simulation time 5861409494 ps
CPU time 46.57 seconds
Started Apr 21 01:44:53 PM PDT 24
Finished Apr 21 01:45:40 PM PDT 24
Peak memory 223960 kb
Host smart-191b001b-a7a5-466b-89de-ae70500337f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035403482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4035403482
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1948617280
Short name T165
Test name
Test status
Simulation time 1390407986 ps
CPU time 20.98 seconds
Started Apr 21 01:44:59 PM PDT 24
Finished Apr 21 01:45:20 PM PDT 24
Peak memory 199592 kb
Host smart-5313d8b6-33bf-44f4-857b-1b9fcd507332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948617280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1948617280
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2756719974
Short name T525
Test name
Test status
Simulation time 1325354134 ps
CPU time 76.57 seconds
Started Apr 21 01:44:56 PM PDT 24
Finished Apr 21 01:46:12 PM PDT 24
Peak memory 199624 kb
Host smart-d7c06173-add0-4b05-80b4-55208fe732eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756719974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2756719974
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2044901758
Short name T196
Test name
Test status
Simulation time 92701231752 ps
CPU time 94.9 seconds
Started Apr 21 01:44:58 PM PDT 24
Finished Apr 21 01:46:33 PM PDT 24
Peak memory 199732 kb
Host smart-db75cc9e-e2f3-425b-a688-e75eb4c0b349
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044901758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2044901758
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2087308214
Short name T289
Test name
Test status
Simulation time 18017089253 ps
CPU time 64.48 seconds
Started Apr 21 01:44:54 PM PDT 24
Finished Apr 21 01:45:59 PM PDT 24
Peak memory 199732 kb
Host smart-d05625bd-690c-4dbf-8a9a-96617d7a6599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087308214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2087308214
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3654813335
Short name T144
Test name
Test status
Simulation time 472791038 ps
CPU time 3.57 seconds
Started Apr 21 01:44:53 PM PDT 24
Finished Apr 21 01:44:57 PM PDT 24
Peak memory 199628 kb
Host smart-6895dc4a-40a7-4885-97aa-cecd9486ee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654813335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3654813335
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3421795787
Short name T407
Test name
Test status
Simulation time 126028259466 ps
CPU time 1860.77 seconds
Started Apr 21 01:45:01 PM PDT 24
Finished Apr 21 02:16:02 PM PDT 24
Peak memory 207908 kb
Host smart-fb631a58-09d2-441f-9a7a-2946e5bdf602
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421795787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3421795787
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2975799214
Short name T552
Test name
Test status
Simulation time 61673542 ps
CPU time 1.21 seconds
Started Apr 21 01:44:59 PM PDT 24
Finished Apr 21 01:45:01 PM PDT 24
Peak memory 199632 kb
Host smart-50b6bb20-5430-48ba-92d2-fe31e295b1ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975799214 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2975799214
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2255939035
Short name T261
Test name
Test status
Simulation time 50748762690 ps
CPU time 487.64 seconds
Started Apr 21 01:44:59 PM PDT 24
Finished Apr 21 01:53:07 PM PDT 24
Peak memory 199764 kb
Host smart-b608cfce-f63a-4138-b385-3eb477709303
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255939035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2255939035
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1452798954
Short name T262
Test name
Test status
Simulation time 340100643 ps
CPU time 3.22 seconds
Started Apr 21 01:45:00 PM PDT 24
Finished Apr 21 01:45:04 PM PDT 24
Peak memory 199604 kb
Host smart-05a329dd-bb9c-4557-a707-60da4a0d862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452798954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1452798954
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2731982567
Short name T17
Test name
Test status
Simulation time 11420917 ps
CPU time 0.56 seconds
Started Apr 21 01:45:16 PM PDT 24
Finished Apr 21 01:45:17 PM PDT 24
Peak memory 195212 kb
Host smart-0660685e-2290-4eda-bc5a-1473b084282b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731982567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2731982567
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1741652856
Short name T448
Test name
Test status
Simulation time 3002941855 ps
CPU time 26.76 seconds
Started Apr 21 01:45:06 PM PDT 24
Finished Apr 21 01:45:33 PM PDT 24
Peak memory 224344 kb
Host smart-ec55f967-d883-42a7-a8c7-719afd09af16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741652856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1741652856
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3082372634
Short name T203
Test name
Test status
Simulation time 2389072347 ps
CPU time 49.14 seconds
Started Apr 21 01:45:08 PM PDT 24
Finished Apr 21 01:45:57 PM PDT 24
Peak memory 199728 kb
Host smart-501e91c3-b614-488d-82ed-693d34c9985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082372634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3082372634
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3169598444
Short name T146
Test name
Test status
Simulation time 4454623650 ps
CPU time 118.79 seconds
Started Apr 21 01:45:08 PM PDT 24
Finished Apr 21 01:47:07 PM PDT 24
Peak memory 199744 kb
Host smart-8a19a037-01bd-4461-b362-ee212f55704a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169598444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3169598444
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.4115763440
Short name T126
Test name
Test status
Simulation time 15631414 ps
CPU time 0.63 seconds
Started Apr 21 01:45:10 PM PDT 24
Finished Apr 21 01:45:10 PM PDT 24
Peak memory 196176 kb
Host smart-f3612ad9-aa08-46bc-9975-28b058574753
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115763440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.4115763440
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.4079529971
Short name T307
Test name
Test status
Simulation time 23654329006 ps
CPU time 100.81 seconds
Started Apr 21 01:45:04 PM PDT 24
Finished Apr 21 01:46:45 PM PDT 24
Peak memory 199744 kb
Host smart-a9d336b3-f8ff-4b7d-8fae-d9c519ab7e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079529971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4079529971
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2252835894
Short name T207
Test name
Test status
Simulation time 175987253 ps
CPU time 5.25 seconds
Started Apr 21 01:45:06 PM PDT 24
Finished Apr 21 01:45:11 PM PDT 24
Peak memory 199612 kb
Host smart-1b59ae58-b2a7-457b-80d2-640d4b0c1b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252835894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2252835894
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4219773939
Short name T4
Test name
Test status
Simulation time 114429598303 ps
CPU time 365.74 seconds
Started Apr 21 01:45:18 PM PDT 24
Finished Apr 21 01:51:25 PM PDT 24
Peak memory 199724 kb
Host smart-9e812145-0aa3-4571-aff9-cea679cd04f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219773939 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4219773939
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1975693392
Short name T596
Test name
Test status
Simulation time 85868231 ps
CPU time 1.18 seconds
Started Apr 21 01:45:13 PM PDT 24
Finished Apr 21 01:45:14 PM PDT 24
Peak memory 199628 kb
Host smart-e1935d70-e690-4fab-ba09-d7d58cad3b28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975693392 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1975693392
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2355016425
Short name T264
Test name
Test status
Simulation time 114628862375 ps
CPU time 512.4 seconds
Started Apr 21 01:45:12 PM PDT 24
Finished Apr 21 01:53:45 PM PDT 24
Peak memory 199728 kb
Host smart-4c987c80-f0f8-45aa-b581-eab281425b92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355016425 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2355016425
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1135451494
Short name T287
Test name
Test status
Simulation time 1794733857 ps
CPU time 52.05 seconds
Started Apr 21 01:45:08 PM PDT 24
Finished Apr 21 01:46:01 PM PDT 24
Peak memory 199584 kb
Host smart-b0ad3fd2-bd04-483b-80f0-8c6441bc5363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135451494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1135451494
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.374815196
Short name T114
Test name
Test status
Simulation time 19309581 ps
CPU time 0.57 seconds
Started Apr 21 01:45:32 PM PDT 24
Finished Apr 21 01:45:33 PM PDT 24
Peak memory 194864 kb
Host smart-2ea90812-cda0-4295-a220-80a58dc80fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374815196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.374815196
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2988756260
Short name T370
Test name
Test status
Simulation time 1812115508 ps
CPU time 14.68 seconds
Started Apr 21 01:45:14 PM PDT 24
Finished Apr 21 01:45:29 PM PDT 24
Peak memory 199660 kb
Host smart-7890aee3-d170-4d29-bda3-3551e98719cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988756260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2988756260
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2178654068
Short name T543
Test name
Test status
Simulation time 6722962692 ps
CPU time 30.21 seconds
Started Apr 21 01:45:22 PM PDT 24
Finished Apr 21 01:45:52 PM PDT 24
Peak memory 199752 kb
Host smart-58c693b6-d97a-41a7-8a74-51ad012d9d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178654068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2178654068
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3679789059
Short name T161
Test name
Test status
Simulation time 1730666768 ps
CPU time 101.37 seconds
Started Apr 21 01:45:18 PM PDT 24
Finished Apr 21 01:47:00 PM PDT 24
Peak memory 199588 kb
Host smart-812cacbd-dd74-4f29-b845-caaebc5bd994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679789059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3679789059
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3875880606
Short name T537
Test name
Test status
Simulation time 36195853172 ps
CPU time 141.35 seconds
Started Apr 21 01:45:21 PM PDT 24
Finished Apr 21 01:47:42 PM PDT 24
Peak memory 199756 kb
Host smart-ea30c120-85c6-4b43-8f6b-7827b5c0b38e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875880606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3875880606
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4208113861
Short name T256
Test name
Test status
Simulation time 210977972 ps
CPU time 11.93 seconds
Started Apr 21 01:45:18 PM PDT 24
Finished Apr 21 01:45:31 PM PDT 24
Peak memory 199564 kb
Host smart-4b7c8757-b2c8-4a9b-919a-484e42179d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208113861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4208113861
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1962017475
Short name T386
Test name
Test status
Simulation time 97653938 ps
CPU time 1.83 seconds
Started Apr 21 01:45:14 PM PDT 24
Finished Apr 21 01:45:16 PM PDT 24
Peak memory 199628 kb
Host smart-e7d7bae5-aae7-47b0-a38f-dc1c541d6051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962017475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1962017475
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.422530517
Short name T603
Test name
Test status
Simulation time 319271547 ps
CPU time 6.91 seconds
Started Apr 21 01:45:25 PM PDT 24
Finished Apr 21 01:45:32 PM PDT 24
Peak memory 199592 kb
Host smart-f78f7ece-57c4-4b5a-86e3-70f2ed3402a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422530517 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.422530517
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3479552274
Short name T483
Test name
Test status
Simulation time 32130317 ps
CPU time 1.15 seconds
Started Apr 21 01:45:26 PM PDT 24
Finished Apr 21 01:45:27 PM PDT 24
Peak memory 198848 kb
Host smart-9c799da2-f790-4df7-b0a9-9053a36e688b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479552274 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3479552274
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.390002902
Short name T368
Test name
Test status
Simulation time 7530618407 ps
CPU time 420.81 seconds
Started Apr 21 01:45:26 PM PDT 24
Finished Apr 21 01:52:27 PM PDT 24
Peak memory 199716 kb
Host smart-3373d6ea-d405-44a2-8a7b-d5ff5a29ac48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390002902 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.390002902
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3571001169
Short name T573
Test name
Test status
Simulation time 3889459933 ps
CPU time 14.84 seconds
Started Apr 21 01:45:22 PM PDT 24
Finished Apr 21 01:45:37 PM PDT 24
Peak memory 199700 kb
Host smart-158fb3a8-b9e5-40d8-ade6-72657316d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571001169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3571001169
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2624895016
Short name T529
Test name
Test status
Simulation time 22963605 ps
CPU time 0.58 seconds
Started Apr 21 01:39:09 PM PDT 24
Finished Apr 21 01:39:10 PM PDT 24
Peak memory 195232 kb
Host smart-eff2008d-150d-4419-8db2-b82ea96d68e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624895016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2624895016
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2925739296
Short name T429
Test name
Test status
Simulation time 565902581 ps
CPU time 16.29 seconds
Started Apr 21 01:39:05 PM PDT 24
Finished Apr 21 01:39:22 PM PDT 24
Peak memory 199616 kb
Host smart-76314d08-aa53-4036-8796-6b837964dec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925739296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2925739296
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.184781615
Short name T392
Test name
Test status
Simulation time 2218687492 ps
CPU time 21.58 seconds
Started Apr 21 01:39:03 PM PDT 24
Finished Apr 21 01:39:25 PM PDT 24
Peak memory 199644 kb
Host smart-553c561a-0e45-48e9-9db9-bdab3624e994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184781615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.184781615
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1022410967
Short name T576
Test name
Test status
Simulation time 7046597914 ps
CPU time 101.02 seconds
Started Apr 21 01:39:07 PM PDT 24
Finished Apr 21 01:40:48 PM PDT 24
Peak memory 199748 kb
Host smart-9e6d7f48-49bf-4515-a0b4-a382b4c71926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022410967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1022410967
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2615912218
Short name T323
Test name
Test status
Simulation time 226383393 ps
CPU time 7.09 seconds
Started Apr 21 01:39:15 PM PDT 24
Finished Apr 21 01:39:23 PM PDT 24
Peak memory 199576 kb
Host smart-6153f1c7-2d5a-4098-8c95-734c2e80a34c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615912218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2615912218
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1363962039
Short name T223
Test name
Test status
Simulation time 371647430 ps
CPU time 22.1 seconds
Started Apr 21 01:39:07 PM PDT 24
Finished Apr 21 01:39:29 PM PDT 24
Peak memory 199612 kb
Host smart-f8644fb7-9cd5-492b-8467-54138f708331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363962039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1363962039
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2484338973
Short name T470
Test name
Test status
Simulation time 525402019 ps
CPU time 2.21 seconds
Started Apr 21 01:39:03 PM PDT 24
Finished Apr 21 01:39:05 PM PDT 24
Peak memory 199656 kb
Host smart-1c747ca2-b789-4be3-ae97-203f26023c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484338973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2484338973
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.366384358
Short name T15
Test name
Test status
Simulation time 35368949687 ps
CPU time 416.22 seconds
Started Apr 21 01:39:06 PM PDT 24
Finished Apr 21 01:46:02 PM PDT 24
Peak memory 215736 kb
Host smart-1c38faf3-6833-4571-80b7-dd3ab453a2ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366384358 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.366384358
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2341229028
Short name T111
Test name
Test status
Simulation time 29892634 ps
CPU time 0.9 seconds
Started Apr 21 01:39:05 PM PDT 24
Finished Apr 21 01:39:07 PM PDT 24
Peak memory 198304 kb
Host smart-1b90351a-cc70-4460-8f9d-aa3e6ea8be0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341229028 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2341229028
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3926665870
Short name T183
Test name
Test status
Simulation time 85137272573 ps
CPU time 505.49 seconds
Started Apr 21 01:39:07 PM PDT 24
Finished Apr 21 01:47:32 PM PDT 24
Peak memory 199708 kb
Host smart-4ed74b46-c49c-41f2-a592-4499d442eec8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926665870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3926665870
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3865750408
Short name T412
Test name
Test status
Simulation time 4658601132 ps
CPU time 83.23 seconds
Started Apr 21 01:39:20 PM PDT 24
Finished Apr 21 01:40:44 PM PDT 24
Peak memory 199776 kb
Host smart-9a0483b6-c4ed-4f15-bf65-e2e4ca62703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865750408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3865750408
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.572320843
Short name T487
Test name
Test status
Simulation time 12832328 ps
CPU time 0.54 seconds
Started Apr 21 01:39:10 PM PDT 24
Finished Apr 21 01:39:11 PM PDT 24
Peak memory 194152 kb
Host smart-070d904f-bb92-43be-8c55-0ba299823d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572320843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.572320843
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.502584185
Short name T295
Test name
Test status
Simulation time 1739406334 ps
CPU time 11.25 seconds
Started Apr 21 01:39:10 PM PDT 24
Finished Apr 21 01:39:21 PM PDT 24
Peak memory 207808 kb
Host smart-659694dc-b720-47ab-997e-f1dfbf274261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502584185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.502584185
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.137592857
Short name T378
Test name
Test status
Simulation time 12757830417 ps
CPU time 27.15 seconds
Started Apr 21 01:39:11 PM PDT 24
Finished Apr 21 01:39:39 PM PDT 24
Peak memory 199720 kb
Host smart-bba0fbb6-c873-4b4e-99ae-c83ca1edb1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137592857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.137592857
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2318158055
Short name T172
Test name
Test status
Simulation time 2089813179 ps
CPU time 77.15 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:40:32 PM PDT 24
Peak memory 199612 kb
Host smart-d184fb1e-fcda-4ce0-8c00-18ea694b5da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318158055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2318158055
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.189115251
Short name T133
Test name
Test status
Simulation time 7540631634 ps
CPU time 55.27 seconds
Started Apr 21 01:39:10 PM PDT 24
Finished Apr 21 01:40:05 PM PDT 24
Peak memory 199712 kb
Host smart-d8831bfe-da8b-408f-a4c4-272551b084af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189115251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.189115251
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4106564741
Short name T336
Test name
Test status
Simulation time 379937331 ps
CPU time 3.24 seconds
Started Apr 21 01:39:09 PM PDT 24
Finished Apr 21 01:39:13 PM PDT 24
Peak memory 199644 kb
Host smart-bb32f18e-4a2c-4747-9f0e-2ec355b65a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106564741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4106564741
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1959367272
Short name T413
Test name
Test status
Simulation time 7135565087 ps
CPU time 97.84 seconds
Started Apr 21 01:39:09 PM PDT 24
Finished Apr 21 01:40:47 PM PDT 24
Peak memory 199712 kb
Host smart-17e8e75d-b640-449a-90ae-275529feec6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959367272 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1959367272
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.923309156
Short name T117
Test name
Test status
Simulation time 309329573 ps
CPU time 1.26 seconds
Started Apr 21 01:39:11 PM PDT 24
Finished Apr 21 01:39:13 PM PDT 24
Peak memory 199512 kb
Host smart-676bbe09-975e-4722-9e97-43f906c190d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923309156 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.923309156
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2855257996
Short name T212
Test name
Test status
Simulation time 26194619412 ps
CPU time 489.94 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:47:23 PM PDT 24
Peak memory 199756 kb
Host smart-fea797de-3eb4-421c-bd61-927737d8a24d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855257996 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2855257996
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.113651265
Short name T128
Test name
Test status
Simulation time 18905868762 ps
CPU time 65.37 seconds
Started Apr 21 01:39:10 PM PDT 24
Finished Apr 21 01:40:16 PM PDT 24
Peak memory 199708 kb
Host smart-a7a9ba99-cce6-4e94-bc0e-7e73f3c2964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113651265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.113651265
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.3554864385
Short name T568
Test name
Test status
Simulation time 145772434495 ps
CPU time 1306.03 seconds
Started Apr 21 01:45:36 PM PDT 24
Finished Apr 21 02:07:23 PM PDT 24
Peak memory 240788 kb
Host smart-a900408e-f37b-497e-86be-7b514ce2558a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554864385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.3554864385
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.2147925593
Short name T511
Test name
Test status
Simulation time 131054611021 ps
CPU time 1364.8 seconds
Started Apr 21 01:45:41 PM PDT 24
Finished Apr 21 02:08:26 PM PDT 24
Peak memory 248924 kb
Host smart-9913c95d-7e64-43f0-8ddd-42158b5c85cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2147925593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.2147925593
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2776860951
Short name T269
Test name
Test status
Simulation time 43330596 ps
CPU time 0.56 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:39:14 PM PDT 24
Peak memory 195256 kb
Host smart-2ba74245-45d6-49fa-8baa-b435ccd7cf10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776860951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2776860951
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2407266992
Short name T151
Test name
Test status
Simulation time 451245061 ps
CPU time 3.85 seconds
Started Apr 21 01:39:10 PM PDT 24
Finished Apr 21 01:39:14 PM PDT 24
Peak memory 199612 kb
Host smart-c84756f0-4ff8-47a1-8530-7bda77476e59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407266992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2407266992
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.195301630
Short name T405
Test name
Test status
Simulation time 935242528 ps
CPU time 43.79 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:39:57 PM PDT 24
Peak memory 199620 kb
Host smart-aeb7126f-5ffc-4dc7-9bf9-dd8855874a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195301630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.195301630
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2838244326
Short name T363
Test name
Test status
Simulation time 484574603 ps
CPU time 25.6 seconds
Started Apr 21 01:39:12 PM PDT 24
Finished Apr 21 01:39:38 PM PDT 24
Peak memory 199648 kb
Host smart-4d5ddd7b-f31b-48fa-8504-97473c071bcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838244326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2838244326
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3575048164
Short name T493
Test name
Test status
Simulation time 2252810465 ps
CPU time 118.92 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:41:12 PM PDT 24
Peak memory 199628 kb
Host smart-a54f2ad8-4652-420d-a10f-888b8e6590e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575048164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3575048164
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2088784045
Short name T204
Test name
Test status
Simulation time 1731520618 ps
CPU time 33.99 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:39:49 PM PDT 24
Peak memory 199604 kb
Host smart-bf0f5bb8-de6f-481c-9a22-59b8a51a5b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088784045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2088784045
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1295320692
Short name T521
Test name
Test status
Simulation time 323449128 ps
CPU time 1.33 seconds
Started Apr 21 01:39:07 PM PDT 24
Finished Apr 21 01:39:08 PM PDT 24
Peak memory 199588 kb
Host smart-226e9851-fd50-4d3c-8202-cf73f60cea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295320692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1295320692
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.275378303
Short name T22
Test name
Test status
Simulation time 289575252581 ps
CPU time 1245.77 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:59:59 PM PDT 24
Peak memory 216104 kb
Host smart-c893e754-9fb1-41a2-ab5b-a03af1c353d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275378303 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.275378303
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1561425364
Short name T540
Test name
Test status
Simulation time 60955370 ps
CPU time 1.4 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:39:15 PM PDT 24
Peak memory 199608 kb
Host smart-012869f1-ac07-4e33-9db7-4c53ec819373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561425364 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1561425364
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3800878172
Short name T560
Test name
Test status
Simulation time 112123312288 ps
CPU time 448.52 seconds
Started Apr 21 01:39:11 PM PDT 24
Finished Apr 21 01:46:40 PM PDT 24
Peak memory 199752 kb
Host smart-f479304e-9e24-4b9e-b1c3-ecacf4745472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800878172 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.3800878172
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1954034386
Short name T482
Test name
Test status
Simulation time 455801263 ps
CPU time 7.3 seconds
Started Apr 21 01:39:12 PM PDT 24
Finished Apr 21 01:39:19 PM PDT 24
Peak memory 199584 kb
Host smart-9979b5c5-7c32-47c9-9904-e1b0de42129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954034386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1954034386
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1667378706
Short name T294
Test name
Test status
Simulation time 13687850 ps
CPU time 0.56 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:39:14 PM PDT 24
Peak memory 195080 kb
Host smart-4bdf126c-fea7-4542-a2ea-26a882ce3926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667378706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1667378706
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1429090402
Short name T49
Test name
Test status
Simulation time 6202209769 ps
CPU time 54.67 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:40:09 PM PDT 24
Peak memory 225176 kb
Host smart-71c332d3-07d0-4443-bc75-639c59f990f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429090402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1429090402
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1955285744
Short name T26
Test name
Test status
Simulation time 58154335 ps
CPU time 1.51 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:39:16 PM PDT 24
Peak memory 199428 kb
Host smart-00f26c0a-9337-468a-967a-c84ccc65f6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955285744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1955285744
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3546920549
Short name T290
Test name
Test status
Simulation time 3205230905 ps
CPU time 100.35 seconds
Started Apr 21 01:39:19 PM PDT 24
Finished Apr 21 01:41:00 PM PDT 24
Peak memory 199768 kb
Host smart-6eb04c4c-dcd0-48e2-b73c-95fb076912b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546920549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3546920549
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.847958597
Short name T245
Test name
Test status
Simulation time 28117198528 ps
CPU time 72.18 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:40:27 PM PDT 24
Peak memory 199764 kb
Host smart-7ad2a85b-4c87-4f0c-8aec-06f57275c6f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847958597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.847958597
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.253188143
Short name T432
Test name
Test status
Simulation time 2088951663 ps
CPU time 20.2 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:39:35 PM PDT 24
Peak memory 199632 kb
Host smart-1abbcb21-1a54-4219-8aa2-79c92e10a3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253188143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.253188143
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.770560909
Short name T490
Test name
Test status
Simulation time 348636174 ps
CPU time 4.69 seconds
Started Apr 21 01:39:12 PM PDT 24
Finished Apr 21 01:39:17 PM PDT 24
Peak memory 199640 kb
Host smart-4f0a3de8-69cc-4e13-8136-2a74a9073d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770560909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.770560909
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.227597445
Short name T418
Test name
Test status
Simulation time 189778626835 ps
CPU time 183.41 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:42:18 PM PDT 24
Peak memory 199708 kb
Host smart-52b54580-b9b8-4ea6-aa2d-498dc4182e85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227597445 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.227597445
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4238452145
Short name T11
Test name
Test status
Simulation time 68422811624 ps
CPU time 1184.12 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:58:58 PM PDT 24
Peak memory 224388 kb
Host smart-bdf2bd8f-6525-4e8d-b9fb-40a8155c9645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238452145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.4238452145
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1942302677
Short name T38
Test name
Test status
Simulation time 29156753 ps
CPU time 0.95 seconds
Started Apr 21 01:39:13 PM PDT 24
Finished Apr 21 01:39:14 PM PDT 24
Peak memory 199008 kb
Host smart-16146d8e-7ce3-4f4b-92f9-b6a092c9b33e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942302677 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1942302677
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2681135571
Short name T350
Test name
Test status
Simulation time 142738057866 ps
CPU time 483.55 seconds
Started Apr 21 01:39:14 PM PDT 24
Finished Apr 21 01:47:18 PM PDT 24
Peak memory 199712 kb
Host smart-ae82b912-8b45-4a2e-b44b-265ea6fb37b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681135571 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2681135571
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2639932119
Short name T131
Test name
Test status
Simulation time 6530605852 ps
CPU time 63.06 seconds
Started Apr 21 01:39:15 PM PDT 24
Finished Apr 21 01:40:19 PM PDT 24
Peak memory 199768 kb
Host smart-0cb1eac3-f3ae-45b0-b8cf-94097f1ffd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639932119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2639932119
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1925423300
Short name T238
Test name
Test status
Simulation time 29419171 ps
CPU time 0.57 seconds
Started Apr 21 01:39:25 PM PDT 24
Finished Apr 21 01:39:26 PM PDT 24
Peak memory 194884 kb
Host smart-d265ffeb-4d1c-4bc6-809e-b2a86e9698a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925423300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1925423300
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2133607244
Short name T509
Test name
Test status
Simulation time 1981036013 ps
CPU time 36.05 seconds
Started Apr 21 01:39:17 PM PDT 24
Finished Apr 21 01:39:54 PM PDT 24
Peak memory 226220 kb
Host smart-1fd03cad-6b4f-48f9-8130-83fdc3e9a27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133607244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2133607244
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2708906870
Short name T329
Test name
Test status
Simulation time 1922678725 ps
CPU time 11.73 seconds
Started Apr 21 01:39:23 PM PDT 24
Finished Apr 21 01:39:35 PM PDT 24
Peak memory 199656 kb
Host smart-4c83e09a-1575-407b-bc8c-0c45ca82fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708906870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2708906870
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1933615017
Short name T314
Test name
Test status
Simulation time 24577483045 ps
CPU time 89.31 seconds
Started Apr 21 01:39:19 PM PDT 24
Finished Apr 21 01:40:49 PM PDT 24
Peak memory 199752 kb
Host smart-d6f861d9-2072-47d6-8e23-476ca42d5489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933615017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1933615017
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3062960402
Short name T210
Test name
Test status
Simulation time 2712698463 ps
CPU time 145.66 seconds
Started Apr 21 01:39:18 PM PDT 24
Finished Apr 21 01:41:44 PM PDT 24
Peak memory 199716 kb
Host smart-08aa4771-5d0f-4d6d-b049-1c89399b6764
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062960402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3062960402
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3310986018
Short name T268
Test name
Test status
Simulation time 2200275610 ps
CPU time 20.61 seconds
Started Apr 21 01:39:16 PM PDT 24
Finished Apr 21 01:39:37 PM PDT 24
Peak memory 199700 kb
Host smart-92df1e04-25c1-4665-9b44-0b2bac74eaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310986018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3310986018
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1046944140
Short name T56
Test name
Test status
Simulation time 1239668099 ps
CPU time 6.42 seconds
Started Apr 21 01:39:15 PM PDT 24
Finished Apr 21 01:39:22 PM PDT 24
Peak memory 199628 kb
Host smart-98488a60-2e0f-4e0a-bb14-768a0bbc51b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046944140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1046944140
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2544498481
Short name T409
Test name
Test status
Simulation time 146988011 ps
CPU time 1.44 seconds
Started Apr 21 01:39:22 PM PDT 24
Finished Apr 21 01:39:24 PM PDT 24
Peak memory 199596 kb
Host smart-97451991-87a3-45f8-b209-163b54f0067c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544498481 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2544498481
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2625281146
Short name T515
Test name
Test status
Simulation time 206058277 ps
CPU time 1.19 seconds
Started Apr 21 01:39:21 PM PDT 24
Finished Apr 21 01:39:23 PM PDT 24
Peak memory 199400 kb
Host smart-330e2d19-ebdf-402d-90f8-d6448c864dca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625281146 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2625281146
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.276355736
Short name T513
Test name
Test status
Simulation time 270500098548 ps
CPU time 543.75 seconds
Started Apr 21 01:39:23 PM PDT 24
Finished Apr 21 01:48:27 PM PDT 24
Peak memory 199768 kb
Host smart-8e9a7dca-cb58-4565-a4d8-ac85095fc699
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276355736 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.276355736
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.416195570
Short name T377
Test name
Test status
Simulation time 6932328820 ps
CPU time 77.12 seconds
Started Apr 21 01:39:19 PM PDT 24
Finished Apr 21 01:40:37 PM PDT 24
Peak memory 199776 kb
Host smart-deb77c27-50cd-4cf2-87a5-147c86c0be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416195570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.416195570
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.454902630
Short name T577
Test name
Test status
Simulation time 81473402238 ps
CPU time 1092.07 seconds
Started Apr 21 01:46:08 PM PDT 24
Finished Apr 21 02:04:21 PM PDT 24
Peak memory 230340 kb
Host smart-62b5d2b8-9571-4abd-9624-e985052ece02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454902630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.454902630
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest
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