Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15433958	1			T1	8		T2	134472		T3	347
all_values[1]	15433958	1			T1	8		T2	134472		T3	347
all_values[2]	15433958	1			T1	8		T2	134472		T3	347

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97889

1

T1

3

T2

48

T3

7

auto[1]

46203985

1

T1

21

T2

403368

T3

1034

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43784258

1

T1

21

T2

372536

T3

1015

auto[1]

2517616

1

T1

3

T2

30880

T3

26

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	43896	1			T2	12		T4	214		T24	253
all_values[0]	auto[0]	auto[1]	469	1			T2	4		T4	2		T24	2
all_values[0]	auto[1]	auto[0]	15337253	1			T1	5		T2	134031		T3	324
all_values[0]	auto[1]	auto[1]	52340	1			T1	3		T2	425		T3	23
all_values[1]	auto[0]	auto[0]	28671	1			T1	3		T2	14		T21	8
all_values[1]	auto[0]	auto[1]	194	1			T2	6		T21	8		T28	2
all_values[1]	auto[1]	auto[0]	15404550	1			T1	5		T2	134448		T3	344
all_values[1]	auto[1]	auto[1]	543	1			T2	4		T3	3		T21	3
all_values[2]	auto[0]	auto[0]	20933	1			T2	6		T3	7		T5	1658
all_values[2]	auto[0]	auto[1]	3726	1			T2	6		T21	2		T28	5
all_values[2]	auto[1]	auto[0]	12948955	1			T1	8		T2	104025		T3	340
all_values[2]	auto[1]	auto[1]	2460344	1			T2	30435		T14	7782		T21	9794