Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7541320

1

T1

15

T2

59914

T3

7489

auto[1]

2931737

1

T1

513

T2

22910

T3

1740

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2896148

1

T1

528

T2

21562

T3

4193

auto[1]

7576909

1

T2

61262

T3

5036

T4

5205

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6677133

1

T1

528

T2

52389

T3

5408

auto[1]

3795924

1

T2

30435

T3

3821

T4

4282

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6550780	1			T1	463		T2	78331		T3	629
fifo_depth[1]	522771	1			T1	4		T2	2849		T3	6
fifo_depth[2]	444948	1			T1	50		T2	1116		T3	6
fifo_depth[3]	367957	1			T2	343		T3	11		T4	100
fifo_depth[4]	319487	1			T1	11		T2	145		T3	10
fifo_depth[5]	286504	1			T2	29		T3	12		T4	2
fifo_depth[6]	271334	1			T2	8		T3	9		T4	1
fifo_depth[7]	238692	1			T2	3		T3	15		T24	1
fifo_depth[8]	212284	1			T3	116		T5	530		T23	98
fifo_depth[9]	149048	1			T3	53		T5	404		T16	1
fifo_depth[10]	112082	1			T3	185		T5	249		T23	65
fifo_depth[11]	69738	1			T3	154		T5	138		T23	32
fifo_depth[12]	63746	1			T3	335		T5	70		T23	8
fifo_depth[13]	36001	1			T3	216		T5	33		T23	8
fifo_depth[14]	43269	1			T3	267		T5	7		T23	3
fifo_depth[15]	29357	1			T3	230		T5	3		T42	12
fifo_depth[16]	110973	1			T3	523		T23	1		T42	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4054117

1

T1

65

T2

4493

T3

9172

auto[1]

6418940

1

T1

463

T2

78331

T3

57

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10341217

1

T1

528

T2

82824

T3

8657

auto[1]

131840

1

T3

572

T12

5744

T6

2019

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

265186

1

T2

143

T3

3051

T4

76

auto[0]

auto[0]

auto[0]

auto[1]

261962

1

T1

65

T2

64

T4

412

auto[0]

auto[0]

auto[1]

auto[0]

1246535

1

T2

1805

T3

925

T4

28

auto[0]

auto[0]

auto[1]

auto[1]

293965

1

T2

308

T3

1386

T4

272

auto[0]

auto[1]

auto[0]

auto[0]

502856

1

T2

588

T3

1111

T4

82

auto[0]

auto[1]

auto[0]

auto[1]

468097

1

T2

722

T3

21

T4

177

auto[0]

auto[1]

auto[1]

auto[0]

504822

1

T2

291

T3

2360

T4

34

auto[0]

auto[1]

auto[1]

auto[1]

510694

1

T2

572

T3

318

T4

27

auto[1]

auto[0]

auto[0]

auto[0]

244581

1

T1

15

T2

1641

T3

8

auto[1]

auto[0]

auto[0]

auto[1]

251505

1

T1

448

T2

1293

T4

4543

auto[1]

auto[0]

auto[1]

auto[0]

3845123

1

T2

42669

T3

27

T4

386

auto[1]

auto[0]

auto[1]

auto[1]

268276

1

T2

4466

T3

11

T4

3635

auto[1]

auto[1]

auto[0]

auto[0]

474815

1

T2

8434

T3

1

T4

985

auto[1]

auto[1]

auto[0]

auto[1]

427146

1

T2

8677

T3

1

T4

2154

auto[1]

auto[1]

auto[1]

auto[0]

457402

1

T2

4343

T3

6

T4

461

auto[1]

auto[1]

auto[1]

auto[1]

450092

1

T2

6808

T3

3

T4

362

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

493720

1

T1

15

T2

1784

T3

2848

auto[0]

auto[0]

auto[0]

auto[1]

497214

1

T1

513

T2

1357

T4

4955

auto[0]

auto[0]

auto[1]

auto[0]

5076184

1

T2

44474

T3

846

T4

414

auto[0]

auto[0]

auto[1]

auto[1]

544049

1

T2

4774

T3

1319

T4

3907

auto[0]

auto[1]

auto[0]

auto[0]

956882

1

T2

9022

T3

1094

T4

1067

auto[0]

auto[1]

auto[0]

auto[1]

878310

1

T2

9399

T3

22

T4

2331

auto[0]

auto[1]

auto[1]

auto[0]

948067

1

T2

4634

T3

2207

T4

495

auto[0]

auto[1]

auto[1]

auto[1]

946791

1

T2

7380

T3

321

T4

389

auto[1]

auto[0]

auto[0]

auto[0]

16047

1

T3

211

T12

1225

T6

523

auto[1]

auto[0]

auto[0]

auto[1]

16253

1

T12

240

T6

51

T52

1

auto[1]

auto[0]

auto[1]

auto[0]

15474

1

T3

106

T12

680

T6

226

auto[1]

auto[0]

auto[1]

auto[1]

18192

1

T3

78

T12

331

T6

168

auto[1]

auto[1]

auto[0]

auto[0]

20789

1

T3

18

T12

983

T6

651

auto[1]

auto[1]

auto[0]

auto[1]

16933

1

T12

243

T6

144

T109

7

auto[1]

auto[1]

auto[1]

auto[0]

14157

1

T3

159

T12

1660

T6

169

auto[1]

auto[1]

auto[1]

auto[1]

13995

1

T12

382

T6

87

T7

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	260628	1			T1	15		T2	1641		T3	219
fifo_depth[0]	auto[0]	auto[0]	auto[1]	267758	1			T1	448		T2	1293		T4	4543
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3860597	1			T2	42669		T3	133		T4	386
fifo_depth[0]	auto[0]	auto[1]	auto[1]	286468	1			T2	4466		T3	89		T4	3635
fifo_depth[0]	auto[1]	auto[0]	auto[0]	495604	1			T2	8434		T3	19		T4	985
fifo_depth[0]	auto[1]	auto[0]	auto[1]	444079	1			T2	8677		T3	1		T4	2154
fifo_depth[0]	auto[1]	auto[1]	auto[0]	471559	1			T2	4343		T3	165		T4	461
fifo_depth[0]	auto[1]	auto[1]	auto[1]	464087	1			T2	6808		T3	3		T4	362
fifo_depth[1]	auto[0]	auto[0]	auto[0]	20796	1			T2	65		T3	2		T4	51
fifo_depth[1]	auto[0]	auto[0]	auto[1]	21522	1			T1	4		T2	48		T4	251
fifo_depth[1]	auto[0]	auto[1]	auto[0]	253486	1			T2	1247		T4	21		T24	51
fifo_depth[1]	auto[0]	auto[1]	auto[1]	23280	1			T2	202		T3	2		T4	177
fifo_depth[1]	auto[1]	auto[0]	auto[0]	51735	1			T2	380		T3	1		T4	46
fifo_depth[1]	auto[1]	auto[0]	auto[1]	48129	1			T2	398		T4	108		T24	15
fifo_depth[1]	auto[1]	auto[1]	auto[0]	52091	1			T2	163		T4	25		T24	7
fifo_depth[1]	auto[1]	auto[1]	auto[1]	51732	1			T2	346		T3	1		T4	14
fifo_depth[2]	auto[0]	auto[0]	auto[0]	18396	1			T2	41		T3	1		T4	22
fifo_depth[2]	auto[0]	auto[0]	auto[1]	18430	1			T1	50		T2	10		T4	111
fifo_depth[2]	auto[0]	auto[1]	auto[0]	202784	1			T2	400		T4	4		T24	36
fifo_depth[2]	auto[0]	auto[1]	auto[1]	20135	1			T2	75		T3	5		T4	71
fifo_depth[2]	auto[1]	auto[0]	auto[0]	46433	1			T2	149		T4	22		T24	15
fifo_depth[2]	auto[1]	auto[0]	auto[1]	43769	1			T2	205		T4	44		T24	8
fifo_depth[2]	auto[1]	auto[1]	auto[0]	47534	1			T2	81		T4	6		T24	4
fifo_depth[2]	auto[1]	auto[1]	auto[1]	47467	1			T2	155		T4	10		T24	5
fifo_depth[3]	auto[0]	auto[0]	auto[0]	15197	1			T2	21		T3	6		T4	2
fifo_depth[3]	auto[0]	auto[0]	auto[1]	15064	1			T2	4		T4	37		T24	10
fifo_depth[3]	auto[0]	auto[1]	auto[0]	156896	1			T2	113		T4	2		T24	21
fifo_depth[3]	auto[0]	auto[1]	auto[1]	17016	1			T2	23		T3	2		T4	22
fifo_depth[3]	auto[1]	auto[0]	auto[0]	40901	1			T2	41		T3	2		T4	11
fifo_depth[3]	auto[1]	auto[0]	auto[1]	38388	1			T2	76		T4	21		T24	6
fifo_depth[3]	auto[1]	auto[1]	auto[0]	42215	1			T2	23		T4	2		T24	2
fifo_depth[3]	auto[1]	auto[1]	auto[1]	42280	1			T2	42		T3	1		T4	3
fifo_depth[4]	auto[0]	auto[0]	auto[0]	14434	1			T2	8		T3	4		T4	1
fifo_depth[4]	auto[0]	auto[0]	auto[1]	14156	1			T1	11		T2	2		T4	10
fifo_depth[4]	auto[0]	auto[1]	auto[0]	117583	1			T2	39		T3	1		T4	1
fifo_depth[4]	auto[0]	auto[1]	auto[1]	16497	1			T2	6		T3	2		T4	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	38586	1			T2	8		T4	3		T24	2
fifo_depth[4]	auto[1]	auto[0]	auto[1]	36821	1			T2	35		T4	4		T24	3
fifo_depth[4]	auto[1]	auto[1]	auto[0]	40827	1			T2	24		T3	1		T4	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	40583	1			T2	23		T3	2		T24	3
fifo_depth[5]	auto[0]	auto[0]	auto[0]	13374	1			T2	6		T3	7		T23	65
fifo_depth[5]	auto[0]	auto[0]	auto[1]	12831	1			T4	2		T23	26		T110	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	97786	1			T2	5		T24	2		T23	16
fifo_depth[5]	auto[0]	auto[1]	auto[1]	14953	1			T2	2		T3	3		T24	3
fifo_depth[5]	auto[1]	auto[0]	auto[0]	36246	1			T2	7		T3	1		T24	2
fifo_depth[5]	auto[1]	auto[0]	auto[1]	34432	1			T2	6		T5	273		T42	250
fifo_depth[5]	auto[1]	auto[1]	auto[0]	38617	1			T5	239		T16	3		T23	38
fifo_depth[5]	auto[1]	auto[1]	auto[1]	38265	1			T2	3		T3	1		T24	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	13396	1			T2	1		T3	3		T24	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	12527	1			T4	1		T23	25		T21	50
fifo_depth[6]	auto[0]	auto[1]	auto[0]	85053	1			T23	12		T21	936		T35	279
fifo_depth[6]	auto[0]	auto[1]	auto[1]	15094	1			T3	1		T21	105		T35	120
fifo_depth[6]	auto[1]	auto[0]	auto[0]	35337	1			T2	3		T3	3		T5	83
fifo_depth[6]	auto[1]	auto[0]	auto[1]	33818	1			T2	1		T5	274		T42	251
fifo_depth[6]	auto[1]	auto[1]	auto[0]	38111	1			T5	225		T16	4		T23	27
fifo_depth[6]	auto[1]	auto[1]	auto[1]	37998	1			T2	3		T3	2		T5	114
fifo_depth[7]	auto[0]	auto[0]	auto[0]	12379	1			T2	1		T3	7		T23	51
fifo_depth[7]	auto[0]	auto[0]	auto[1]	11352	1			T23	26		T21	40		T35	77
fifo_depth[7]	auto[0]	auto[1]	auto[0]	68370	1			T2	1		T24	1		T23	21
fifo_depth[7]	auto[0]	auto[1]	auto[1]	13698	1			T3	3		T21	101		T35	117
fifo_depth[7]	auto[1]	auto[0]	auto[0]	32271	1			T5	65		T42	363		T21	937
fifo_depth[7]	auto[1]	auto[0]	auto[1]	31105	1			T2	1		T5	245		T42	231
fifo_depth[7]	auto[1]	auto[1]	auto[0]	34791	1			T3	4		T5	179		T16	3
fifo_depth[7]	auto[1]	auto[1]	auto[1]	34726	1			T3	1		T5	105		T42	600
fifo_depth[8]	auto[0]	auto[0]	auto[0]	12339	1			T3	70		T23	41		T21	40
fifo_depth[8]	auto[0]	auto[0]	auto[1]	11984	1			T23	17		T21	42		T35	64
fifo_depth[8]	auto[0]	auto[1]	auto[0]	53290	1			T23	12		T21	523		T35	216
fifo_depth[8]	auto[0]	auto[1]	auto[1]	13410	1			T3	16		T21	85		T35	94
fifo_depth[8]	auto[1]	auto[0]	auto[0]	29704	1			T3	16		T5	74		T42	290
fifo_depth[8]	auto[1]	auto[0]	auto[1]	28780	1			T5	208		T42	196		T21	719
fifo_depth[8]	auto[1]	auto[1]	auto[0]	31376	1			T3	13		T5	158		T23	28
fifo_depth[8]	auto[1]	auto[1]	auto[1]	31401	1			T3	1		T5	90		T42	510
fifo_depth[9]	auto[0]	auto[0]	auto[0]	8743	1			T3	9		T23	35		T21	21
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7453	1			T23	16		T21	43		T35	47
fifo_depth[9]	auto[0]	auto[1]	auto[0]	36135	1			T23	5		T21	305		T35	157
fifo_depth[9]	auto[0]	auto[1]	auto[1]	9719	1			T3	19		T21	64		T35	71
fifo_depth[9]	auto[1]	auto[0]	auto[0]	21157	1			T3	18		T5	55		T42	222
fifo_depth[9]	auto[1]	auto[0]	auto[1]	20524	1			T5	150		T42	141		T21	542
fifo_depth[9]	auto[1]	auto[1]	auto[0]	22772	1			T3	7		T5	124		T16	1
fifo_depth[9]	auto[1]	auto[1]	auto[1]	22545	1			T5	75		T42	376		T21	412
fifo_depth[10]	auto[0]	auto[0]	auto[0]	7660	1			T23	30		T21	16		T35	53
fifo_depth[10]	auto[0]	auto[0]	auto[1]	7008	1			T23	10		T21	20		T35	36
fifo_depth[10]	auto[0]	auto[1]	auto[0]	24356	1			T3	1		T23	3		T21	199
fifo_depth[10]	auto[0]	auto[1]	auto[1]	8263	1			T3	89		T21	35		T35	56
fifo_depth[10]	auto[1]	auto[0]	auto[0]	15710	1			T3	81		T5	38		T42	139
fifo_depth[10]	auto[1]	auto[0]	auto[1]	15189	1			T3	1		T5	84		T42	100
fifo_depth[10]	auto[1]	auto[1]	auto[0]	17104	1			T3	8		T5	93		T23	22
fifo_depth[10]	auto[1]	auto[1]	auto[1]	16792	1			T3	5		T5	34		T42	248
fifo_depth[11]	auto[0]	auto[0]	auto[0]	5304	1			T3	9		T23	14		T21	17
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4274	1			T23	5		T21	11		T35	16
fifo_depth[11]	auto[0]	auto[1]	auto[0]	14393	1			T23	2		T21	119		T35	49
fifo_depth[11]	auto[0]	auto[1]	auto[1]	5472	1			T3	49		T21	19		T35	36
fifo_depth[11]	auto[1]	auto[0]	auto[0]	9924	1			T3	81		T5	24		T42	81
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9510	1			T3	2		T5	50		T42	56
fifo_depth[11]	auto[1]	auto[1]	auto[0]	10741	1			T3	7		T5	49		T23	11
fifo_depth[11]	auto[1]	auto[1]	auto[1]	10120	1			T3	6		T5	15		T42	127
fifo_depth[12]	auto[0]	auto[0]	auto[0]	5599	1			T3	88		T23	2		T21	5
fifo_depth[12]	auto[0]	auto[0]	auto[1]	5869	1			T21	6		T35	8		T12	163
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10837	1			T23	1		T21	58		T35	34
fifo_depth[12]	auto[0]	auto[1]	auto[1]	6563	1			T3	152		T21	8		T35	11
fifo_depth[12]	auto[1]	auto[0]	auto[0]	8652	1			T3	81		T5	11		T42	32
fifo_depth[12]	auto[1]	auto[0]	auto[1]	8508	1			T5	24		T42	34		T21	108
fifo_depth[12]	auto[1]	auto[1]	auto[0]	8125	1			T3	8		T5	28		T23	5
fifo_depth[12]	auto[1]	auto[1]	auto[1]	9593	1			T3	6		T5	7		T42	79
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3822	1			T3	7		T23	3		T21	3
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2994	1			T23	1		T21	2		T35	5
fifo_depth[13]	auto[0]	auto[1]	auto[0]	6028	1			T23	2		T21	23		T35	11
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3608	1			T3	82		T21	3		T35	6
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4813	1			T3	81		T5	8		T42	24
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4730	1			T3	1		T5	5		T42	13
fifo_depth[13]	auto[1]	auto[1]	auto[0]	5209	1			T3	6		T5	16		T23	2
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4797	1			T3	39		T5	4		T42	39
fifo_depth[14]	auto[0]	auto[0]	auto[0]	4806	1			T3	18		T21	2		T35	3
fifo_depth[14]	auto[0]	auto[0]	auto[1]	4543	1			T23	1		T21	3		T35	1
fifo_depth[14]	auto[0]	auto[1]	auto[0]	6788	1			T3	2		T21	6		T35	3
fifo_depth[14]	auto[0]	auto[1]	auto[1]	5881	1			T3	118		T21	3		T35	2
fifo_depth[14]	auto[1]	auto[0]	auto[0]	5386	1			T3	81		T5	4		T42	8
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4673	1			T3	1		T42	6		T21	18
fifo_depth[14]	auto[1]	auto[1]	auto[0]	5036	1			T3	10		T5	3		T23	2
fifo_depth[14]	auto[1]	auto[1]	auto[1]	6156	1			T3	37		T42	11		T21	11
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3484	1			T3	20		T21	1		T35	2
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2818	1			T21	2		T35	1		T12	59
fifo_depth[15]	auto[0]	auto[1]	auto[0]	4602	1			T3	2		T35	2		T12	19
fifo_depth[15]	auto[0]	auto[1]	auto[1]	3669	1			T3	83		T12	455		T6	115
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3874	1			T3	81		T5	2		T42	4
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3367	1			T42	6		T21	13		T12	244
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3982	1			T3	6		T5	1		T21	2
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3561	1			T3	38		T42	2		T21	4
fifo_depth[16]	auto[0]	auto[0]	auto[0]	14055	1			T3	114		T23	1		T12	487
fifo_depth[16]	auto[0]	auto[0]	auto[1]	12777	1			T12	92		T6	133		T109	139
fifo_depth[16]	auto[0]	auto[1]	auto[0]	13543	1			T3	1		T12	82		T6	9
fifo_depth[16]	auto[0]	auto[1]	auto[1]	16721	1			T3	85		T12	3491		T6	91
fifo_depth[16]	auto[1]	auto[0]	auto[0]	12681	1			T3	81		T42	1		T21	4
fifo_depth[16]	auto[1]	auto[0]	auto[1]	13672	1			T21	2		T12	505		T6	201
fifo_depth[16]	auto[1]	auto[1]	auto[0]	12881	1			T3	238		T21	2		T12	402
fifo_depth[16]	auto[1]	auto[1]	auto[1]	14643	1			T3	4		T42	1		T21	3