Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15433958	1			T1	8		T2	134472		T3	347
all_pins[1]	15433958	1			T1	8		T2	134472		T3	347
all_pins[2]	15433958	1			T1	8		T2	134472		T3	347

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43787209	1			T1	21		T2	372543		T3	1012
values[0x1]	2514665	1			T1	3		T2	30873		T3	29
transitions[0x0=>0x1]	2514492	1			T1	3		T2	30871		T3	29
transitions[0x1=>0x0]	2514505	1			T1	3		T2	30871		T3	29

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15380211	1			T1	5		T2	134038		T3	322
all_pins[0]	values[0x1]	53747	1			T1	3		T2	434		T3	25
all_pins[0]	transitions[0x0=>0x1]	53683	1			T1	3		T2	434		T3	25
all_pins[0]	transitions[0x1=>0x0]	2460293	1			T2	30435		T14	7782		T21	9793
all_pins[1]	values[0x0]	15433384	1			T1	8		T2	134468		T3	343
all_pins[1]	values[0x1]	574	1			T2	4		T3	4		T21	3
all_pins[1]	transitions[0x0=>0x1]	524	1			T2	3		T3	4		T21	2
all_pins[1]	transitions[0x1=>0x0]	53697	1			T1	3		T2	433		T3	25
all_pins[2]	values[0x0]	12973614	1			T1	8		T2	104037		T3	347
all_pins[2]	values[0x1]	2460344	1			T2	30435		T14	7782		T21	9794
all_pins[2]	transitions[0x0=>0x1]	2460285	1			T2	30434		T14	7782		T21	9793
all_pins[2]	transitions[0x1=>0x0]	515	1			T2	3		T3	4		T21	2