Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 908 1 T2 21 T21 18 T28 10
all_values[1] 908 1 T2 21 T21 18 T28 10
all_values[2] 908 1 T2 21 T21 18 T28 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1349 1 T2 39 T21 29 T28 16
auto[1] 1375 1 T2 24 T21 25 T28 14


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 985 1 T2 21 T21 13 T28 2
auto[1] 1739 1 T2 42 T21 41 T28 28


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1567 1 T2 34 T21 26 T28 13
auto[1] 1157 1 T2 29 T21 28 T28 17


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 183 1 T2 7 T21 5 T72 1
all_values[0] auto[0] auto[0] auto[1] 78 1 T2 2 T21 2 T28 2
all_values[0] auto[0] auto[1] auto[0] 162 1 T2 2 T21 2 T72 4
all_values[0] auto[0] auto[1] auto[1] 95 1 T28 1 T73 1 T47 3
all_values[0] auto[1] auto[0] auto[1] 200 1 T2 5 T21 6 T28 2
all_values[0] auto[1] auto[1] auto[1] 190 1 T2 5 T21 3 T28 5
all_values[1] auto[0] auto[0] auto[0] 146 1 T2 5 T21 1 T28 1
all_values[1] auto[0] auto[0] auto[1] 115 1 T2 3 T21 5 T28 2
all_values[1] auto[0] auto[1] auto[0] 141 1 T2 1 T28 1 T73 1
all_values[1] auto[0] auto[1] auto[1] 117 1 T2 2 T21 1 T28 1
all_values[1] auto[1] auto[0] auto[1] 194 1 T2 6 T21 7 T28 2
all_values[1] auto[1] auto[1] auto[1] 195 1 T2 4 T21 4 T28 3
all_values[2] auto[0] auto[0] auto[0] 186 1 T2 2 T21 2 T73 2
all_values[2] auto[0] auto[0] auto[1] 79 1 T2 5 T28 3 T72 1
all_values[2] auto[0] auto[1] auto[0] 167 1 T2 4 T21 3 T72 3
all_values[2] auto[0] auto[1] auto[1] 98 1 T2 1 T21 5 T28 2
all_values[2] auto[1] auto[0] auto[1] 168 1 T2 4 T21 1 T28 4
all_values[2] auto[1] auto[1] auto[1] 210 1 T2 5 T21 7 T28 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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