Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.94 92.47 85.22 100.00 76.32 85.98 99.49 69.08


Total test records in report: 740
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T534 /workspace/coverage/default/6.hmac_error.397839775 Apr 28 03:19:28 PM PDT 24 Apr 28 03:19:48 PM PDT 24 370162371 ps
T535 /workspace/coverage/default/27.hmac_wipe_secret.1106343682 Apr 28 03:20:27 PM PDT 24 Apr 28 03:21:24 PM PDT 24 2950022341 ps
T536 /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.624596368 Apr 28 03:22:48 PM PDT 24 Apr 28 03:39:06 PM PDT 24 82669979142 ps
T537 /workspace/coverage/default/21.hmac_long_msg.1724403813 Apr 28 03:20:11 PM PDT 24 Apr 28 03:20:53 PM PDT 24 696054980 ps
T538 /workspace/coverage/default/13.hmac_smoke.1662222448 Apr 28 03:19:42 PM PDT 24 Apr 28 03:19:44 PM PDT 24 751948374 ps
T539 /workspace/coverage/default/0.hmac_wipe_secret.2945565736 Apr 28 03:19:17 PM PDT 24 Apr 28 03:20:14 PM PDT 24 10803634848 ps
T540 /workspace/coverage/default/33.hmac_test_hmac_vectors.3902173614 Apr 28 03:20:56 PM PDT 24 Apr 28 03:20:57 PM PDT 24 27799056 ps
T48 /workspace/coverage/default/4.hmac_stress_all.4189060083 Apr 28 03:19:30 PM PDT 24 Apr 28 03:47:45 PM PDT 24 122593652365 ps
T541 /workspace/coverage/default/20.hmac_error.1097599366 Apr 28 03:20:05 PM PDT 24 Apr 28 03:20:08 PM PDT 24 156111195 ps
T542 /workspace/coverage/default/29.hmac_stress_all.2374893795 Apr 28 03:20:37 PM PDT 24 Apr 28 04:05:12 PM PDT 24 184567098504 ps
T543 /workspace/coverage/default/49.hmac_stress_all.844815731 Apr 28 03:22:02 PM PDT 24 Apr 28 03:24:11 PM PDT 24 6294830611 ps
T544 /workspace/coverage/default/28.hmac_wipe_secret.2066348821 Apr 28 03:20:30 PM PDT 24 Apr 28 03:21:09 PM PDT 24 13647790492 ps
T545 /workspace/coverage/default/30.hmac_long_msg.2272370863 Apr 28 03:20:38 PM PDT 24 Apr 28 03:22:13 PM PDT 24 9688741456 ps
T546 /workspace/coverage/default/11.hmac_alert_test.1485161589 Apr 28 03:19:42 PM PDT 24 Apr 28 03:19:44 PM PDT 24 15527908 ps
T547 /workspace/coverage/default/21.hmac_stress_all.2040548280 Apr 28 03:20:11 PM PDT 24 Apr 28 03:50:09 PM PDT 24 31445601152 ps
T548 /workspace/coverage/default/46.hmac_wipe_secret.2067565328 Apr 28 03:21:40 PM PDT 24 Apr 28 03:22:09 PM PDT 24 673116494 ps
T34 /workspace/coverage/default/2.hmac_sec_cm.1169832878 Apr 28 03:19:23 PM PDT 24 Apr 28 03:19:24 PM PDT 24 69656389 ps
T549 /workspace/coverage/default/3.hmac_smoke.3525887535 Apr 28 03:19:22 PM PDT 24 Apr 28 03:19:24 PM PDT 24 29186069 ps
T550 /workspace/coverage/default/8.hmac_burst_wr.2315111427 Apr 28 03:19:34 PM PDT 24 Apr 28 03:20:16 PM PDT 24 850203401 ps
T551 /workspace/coverage/default/9.hmac_smoke.1458802944 Apr 28 03:19:36 PM PDT 24 Apr 28 03:19:41 PM PDT 24 269821022 ps
T552 /workspace/coverage/default/41.hmac_smoke.473028530 Apr 28 03:21:21 PM PDT 24 Apr 28 03:21:27 PM PDT 24 413602826 ps
T553 /workspace/coverage/default/44.hmac_smoke.610720448 Apr 28 03:21:31 PM PDT 24 Apr 28 03:21:39 PM PDT 24 450436981 ps
T554 /workspace/coverage/default/6.hmac_datapath_stress.2002984611 Apr 28 03:19:27 PM PDT 24 Apr 28 03:20:08 PM PDT 24 2621352593 ps
T555 /workspace/coverage/default/6.hmac_wipe_secret.2055267512 Apr 28 03:19:28 PM PDT 24 Apr 28 03:20:13 PM PDT 24 9781046930 ps
T556 /workspace/coverage/default/49.hmac_test_hmac_vectors.2091310666 Apr 28 03:21:56 PM PDT 24 Apr 28 03:21:58 PM PDT 24 33786563 ps
T557 /workspace/coverage/default/28.hmac_alert_test.2984193790 Apr 28 03:20:30 PM PDT 24 Apr 28 03:20:32 PM PDT 24 12621742 ps
T558 /workspace/coverage/default/41.hmac_test_sha_vectors.196271571 Apr 28 03:21:22 PM PDT 24 Apr 28 03:29:10 PM PDT 24 37671277792 ps
T559 /workspace/coverage/default/3.hmac_burst_wr.1794354266 Apr 28 03:19:23 PM PDT 24 Apr 28 03:20:00 PM PDT 24 9837437430 ps
T560 /workspace/coverage/default/43.hmac_test_hmac_vectors.3432166832 Apr 28 03:21:30 PM PDT 24 Apr 28 03:21:31 PM PDT 24 102564046 ps
T561 /workspace/coverage/default/7.hmac_datapath_stress.4030899400 Apr 28 03:19:33 PM PDT 24 Apr 28 03:20:17 PM PDT 24 3156929051 ps
T562 /workspace/coverage/default/2.hmac_datapath_stress.3813873066 Apr 28 03:19:19 PM PDT 24 Apr 28 03:21:09 PM PDT 24 1840670713 ps
T563 /workspace/coverage/default/35.hmac_long_msg.1458903016 Apr 28 03:20:59 PM PDT 24 Apr 28 03:21:36 PM PDT 24 1520840729 ps
T564 /workspace/coverage/default/43.hmac_alert_test.76939189 Apr 28 03:21:35 PM PDT 24 Apr 28 03:21:36 PM PDT 24 36189140 ps
T565 /workspace/coverage/default/37.hmac_back_pressure.1557091757 Apr 28 03:21:04 PM PDT 24 Apr 28 03:21:06 PM PDT 24 148521879 ps
T566 /workspace/coverage/default/20.hmac_long_msg.1640233462 Apr 28 03:20:07 PM PDT 24 Apr 28 03:21:19 PM PDT 24 4717218166 ps
T567 /workspace/coverage/default/34.hmac_back_pressure.2850302885 Apr 28 03:20:57 PM PDT 24 Apr 28 03:21:59 PM PDT 24 5606019210 ps
T568 /workspace/coverage/default/26.hmac_long_msg.1091165713 Apr 28 03:20:21 PM PDT 24 Apr 28 03:20:37 PM PDT 24 1083308868 ps
T569 /workspace/coverage/default/39.hmac_long_msg.3405731504 Apr 28 03:21:13 PM PDT 24 Apr 28 03:22:43 PM PDT 24 6925898173 ps
T570 /workspace/coverage/default/1.hmac_stress_all.3743644038 Apr 28 03:19:16 PM PDT 24 Apr 28 03:19:55 PM PDT 24 1001806345 ps
T571 /workspace/coverage/default/25.hmac_error.1344353022 Apr 28 03:20:22 PM PDT 24 Apr 28 03:21:34 PM PDT 24 16406240047 ps
T572 /workspace/coverage/default/4.hmac_error.1666592927 Apr 28 03:19:26 PM PDT 24 Apr 28 03:21:57 PM PDT 24 92336237614 ps
T573 /workspace/coverage/default/27.hmac_stress_all.2759080455 Apr 28 03:20:30 PM PDT 24 Apr 28 03:23:54 PM PDT 24 39389034372 ps
T574 /workspace/coverage/default/14.hmac_error.3091781285 Apr 28 03:19:49 PM PDT 24 Apr 28 03:20:29 PM PDT 24 2963643797 ps
T575 /workspace/coverage/default/18.hmac_long_msg.3998173734 Apr 28 03:19:57 PM PDT 24 Apr 28 03:22:16 PM PDT 24 14252584614 ps
T576 /workspace/coverage/default/2.hmac_error.950002739 Apr 28 03:19:22 PM PDT 24 Apr 28 03:19:58 PM PDT 24 9969357498 ps
T577 /workspace/coverage/default/30.hmac_test_hmac_vectors.1432036192 Apr 28 03:20:45 PM PDT 24 Apr 28 03:20:47 PM PDT 24 42310612 ps
T578 /workspace/coverage/default/45.hmac_test_hmac_vectors.1301343611 Apr 28 03:21:40 PM PDT 24 Apr 28 03:21:43 PM PDT 24 285939381 ps
T579 /workspace/coverage/default/31.hmac_smoke.1571638923 Apr 28 03:20:45 PM PDT 24 Apr 28 03:20:49 PM PDT 24 296040055 ps
T580 /workspace/coverage/default/29.hmac_back_pressure.262990760 Apr 28 03:20:35 PM PDT 24 Apr 28 03:21:26 PM PDT 24 3124623636 ps
T581 /workspace/coverage/default/47.hmac_test_hmac_vectors.3126393164 Apr 28 03:21:51 PM PDT 24 Apr 28 03:21:53 PM PDT 24 225721259 ps
T582 /workspace/coverage/default/30.hmac_alert_test.3294386238 Apr 28 03:20:49 PM PDT 24 Apr 28 03:20:50 PM PDT 24 13033274 ps
T583 /workspace/coverage/default/45.hmac_smoke.2328423163 Apr 28 03:21:36 PM PDT 24 Apr 28 03:21:39 PM PDT 24 62580751 ps
T584 /workspace/coverage/default/42.hmac_test_sha_vectors.1906479275 Apr 28 03:21:26 PM PDT 24 Apr 28 03:29:19 PM PDT 24 52687377420 ps
T585 /workspace/coverage/default/25.hmac_alert_test.809261800 Apr 28 03:20:20 PM PDT 24 Apr 28 03:20:22 PM PDT 24 13661097 ps
T586 /workspace/coverage/default/12.hmac_alert_test.2104441763 Apr 28 03:19:44 PM PDT 24 Apr 28 03:19:45 PM PDT 24 127458770 ps
T587 /workspace/coverage/default/1.hmac_alert_test.2950964936 Apr 28 03:19:18 PM PDT 24 Apr 28 03:19:19 PM PDT 24 22948292 ps
T588 /workspace/coverage/default/10.hmac_test_sha_vectors.1895847287 Apr 28 03:19:37 PM PDT 24 Apr 28 03:28:05 PM PDT 24 42920379872 ps
T589 /workspace/coverage/default/48.hmac_test_hmac_vectors.3798158070 Apr 28 03:21:58 PM PDT 24 Apr 28 03:22:00 PM PDT 24 108284644 ps
T590 /workspace/coverage/default/3.hmac_datapath_stress.1382172180 Apr 28 03:19:26 PM PDT 24 Apr 28 03:19:55 PM PDT 24 1005177758 ps
T591 /workspace/coverage/default/26.hmac_wipe_secret.996947689 Apr 28 03:20:26 PM PDT 24 Apr 28 03:20:50 PM PDT 24 2915975365 ps
T592 /workspace/coverage/default/11.hmac_smoke.1220170814 Apr 28 03:19:39 PM PDT 24 Apr 28 03:19:46 PM PDT 24 1546761144 ps
T593 /workspace/coverage/default/5.hmac_test_hmac_vectors.1299740249 Apr 28 03:19:36 PM PDT 24 Apr 28 03:19:38 PM PDT 24 66043902 ps
T594 /workspace/coverage/default/17.hmac_stress_all.4086880576 Apr 28 03:19:56 PM PDT 24 Apr 28 03:30:08 PM PDT 24 95451416429 ps
T595 /workspace/coverage/default/20.hmac_wipe_secret.2430753551 Apr 28 03:20:06 PM PDT 24 Apr 28 03:20:12 PM PDT 24 182602162 ps
T596 /workspace/coverage/default/12.hmac_wipe_secret.3657951925 Apr 28 03:19:43 PM PDT 24 Apr 28 03:21:23 PM PDT 24 4216292922 ps
T597 /workspace/coverage/default/15.hmac_stress_all.2254019594 Apr 28 03:19:53 PM PDT 24 Apr 28 03:25:38 PM PDT 24 23880673149 ps
T598 /workspace/coverage/default/32.hmac_test_sha_vectors.4015642030 Apr 28 03:20:49 PM PDT 24 Apr 28 03:29:11 PM PDT 24 97729485407 ps
T599 /workspace/coverage/default/34.hmac_long_msg.1384221263 Apr 28 03:20:54 PM PDT 24 Apr 28 03:21:59 PM PDT 24 2233421964 ps
T76 /workspace/coverage/default/28.hmac_stress_all.569843374 Apr 28 03:20:30 PM PDT 24 Apr 28 03:28:57 PM PDT 24 136885491632 ps
T600 /workspace/coverage/default/12.hmac_test_hmac_vectors.422102852 Apr 28 03:19:43 PM PDT 24 Apr 28 03:19:45 PM PDT 24 58351626 ps
T601 /workspace/coverage/default/17.hmac_test_sha_vectors.2127157550 Apr 28 03:19:57 PM PDT 24 Apr 28 03:28:47 PM PDT 24 58893068288 ps
T602 /workspace/coverage/default/24.hmac_long_msg.4090659822 Apr 28 03:20:18 PM PDT 24 Apr 28 03:20:22 PM PDT 24 64882811 ps
T603 /workspace/coverage/default/39.hmac_datapath_stress.2424972839 Apr 28 03:21:15 PM PDT 24 Apr 28 03:22:38 PM PDT 24 2805657357 ps
T604 /workspace/coverage/default/16.hmac_error.36303144 Apr 28 03:19:53 PM PDT 24 Apr 28 03:20:55 PM PDT 24 4546271045 ps
T605 /workspace/coverage/default/7.hmac_burst_wr.3099994032 Apr 28 03:19:33 PM PDT 24 Apr 28 03:20:13 PM PDT 24 822344813 ps
T77 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2305812296 Apr 28 03:08:00 PM PDT 24 Apr 28 03:08:02 PM PDT 24 14897996 ps
T606 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3053274858 Apr 28 03:08:34 PM PDT 24 Apr 28 03:08:36 PM PDT 24 54299617 ps
T607 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3830294544 Apr 28 03:07:55 PM PDT 24 Apr 28 03:07:56 PM PDT 24 13238929 ps
T608 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3288481727 Apr 28 03:08:33 PM PDT 24 Apr 28 03:08:35 PM PDT 24 22148726 ps
T609 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1380210494 Apr 28 03:08:34 PM PDT 24 Apr 28 03:08:35 PM PDT 24 14398419 ps
T610 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1185491828 Apr 28 03:08:02 PM PDT 24 Apr 28 03:08:06 PM PDT 24 852344309 ps
T64 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2721579555 Apr 28 03:08:06 PM PDT 24 Apr 28 03:08:07 PM PDT 24 21374869 ps
T611 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2129159831 Apr 28 03:08:34 PM PDT 24 Apr 28 03:08:35 PM PDT 24 32425685 ps
T612 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2733604286 Apr 28 03:08:35 PM PDT 24 Apr 28 03:08:36 PM PDT 24 51494377 ps
T61 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1083299933 Apr 28 03:07:47 PM PDT 24 Apr 28 03:07:50 PM PDT 24 92771227 ps
T613 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1319921413 Apr 28 03:08:24 PM PDT 24 Apr 28 03:08:25 PM PDT 24 14317497 ps
T65 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2335435143 Apr 28 03:07:41 PM PDT 24 Apr 28 03:07:42 PM PDT 24 54096936 ps
T614 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1038154060 Apr 28 03:08:08 PM PDT 24 Apr 28 03:08:12 PM PDT 24 188595937 ps
T615 /workspace/coverage/cover_reg_top/13.hmac_intr_test.755843621 Apr 28 03:08:19 PM PDT 24 Apr 28 03:08:20 PM PDT 24 39048929 ps
T616 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.707189977 Apr 28 03:07:25 PM PDT 24 Apr 28 03:07:36 PM PDT 24 740979651 ps
T62 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1715979601 Apr 28 03:08:29 PM PDT 24 Apr 28 03:08:32 PM PDT 24 101794097 ps
T617 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3678629710 Apr 28 03:07:56 PM PDT 24 Apr 28 03:07:57 PM PDT 24 39326287 ps
T618 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4262204301 Apr 28 03:08:02 PM PDT 24 Apr 28 03:08:06 PM PDT 24 386684859 ps
T619 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1260571665 Apr 28 03:08:11 PM PDT 24 Apr 28 03:08:12 PM PDT 24 28201060 ps
T620 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3115660252 Apr 28 03:08:38 PM PDT 24 Apr 28 03:08:39 PM PDT 24 41041439 ps
T63 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2389030367 Apr 28 03:08:00 PM PDT 24 Apr 28 03:08:05 PM PDT 24 250993460 ps
T106 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2590599682 Apr 28 03:07:50 PM PDT 24 Apr 28 03:07:52 PM PDT 24 173989362 ps
T621 /workspace/coverage/cover_reg_top/27.hmac_intr_test.294353285 Apr 28 03:08:30 PM PDT 24 Apr 28 03:08:32 PM PDT 24 31793918 ps
T622 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3036948855 Apr 28 03:08:22 PM PDT 24 Apr 28 03:08:24 PM PDT 24 72095913 ps
T623 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1654517435 Apr 28 03:08:24 PM PDT 24 Apr 28 03:08:27 PM PDT 24 1625926646 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2888393622 Apr 28 03:08:07 PM PDT 24 Apr 28 03:08:09 PM PDT 24 93991727 ps
T625 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3468121257 Apr 28 03:08:22 PM PDT 24 Apr 28 03:08:26 PM PDT 24 240836783 ps
T626 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1669874325 Apr 28 03:08:35 PM PDT 24 Apr 28 03:08:36 PM PDT 24 45375416 ps
T92 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3795359632 Apr 28 03:07:29 PM PDT 24 Apr 28 03:07:36 PM PDT 24 2111473980 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1591786031 Apr 28 03:07:40 PM PDT 24 Apr 28 03:07:44 PM PDT 24 193982161 ps
T86 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1522344976 Apr 28 03:07:31 PM PDT 24 Apr 28 03:07:32 PM PDT 24 80118982 ps
T627 /workspace/coverage/cover_reg_top/19.hmac_intr_test.243401279 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:30 PM PDT 24 16444320 ps
T628 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2610675904 Apr 28 03:07:57 PM PDT 24 Apr 28 03:08:00 PM PDT 24 391478709 ps
T629 /workspace/coverage/cover_reg_top/5.hmac_intr_test.308016192 Apr 28 03:07:55 PM PDT 24 Apr 28 03:07:56 PM PDT 24 12570759 ps
T630 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.321169774 Apr 28 03:07:52 PM PDT 24 Apr 28 03:07:54 PM PDT 24 33671926 ps
T631 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1718448229 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:30 PM PDT 24 16111382 ps
T632 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4239788960 Apr 28 03:08:29 PM PDT 24 Apr 28 03:08:31 PM PDT 24 42489600 ps
T633 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2181367527 Apr 28 03:08:30 PM PDT 24 Apr 28 03:08:32 PM PDT 24 40346441 ps
T87 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4194141779 Apr 28 03:07:57 PM PDT 24 Apr 28 03:07:58 PM PDT 24 62566758 ps
T108 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.872725181 Apr 28 03:07:26 PM PDT 24 Apr 28 03:07:28 PM PDT 24 179071310 ps
T634 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2330196109 Apr 28 03:08:17 PM PDT 24 Apr 28 03:08:18 PM PDT 24 18947496 ps
T635 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.696598952 Apr 28 03:08:24 PM PDT 24 Apr 28 03:08:28 PM PDT 24 247716392 ps
T636 /workspace/coverage/cover_reg_top/24.hmac_intr_test.994286869 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:30 PM PDT 24 20106072 ps
T637 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.430868850 Apr 28 03:08:00 PM PDT 24 Apr 28 03:08:02 PM PDT 24 144738093 ps
T638 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2226013972 Apr 28 03:08:26 PM PDT 24 Apr 28 03:08:27 PM PDT 24 16891044 ps
T639 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1599419415 Apr 28 03:08:25 PM PDT 24 Apr 28 03:08:28 PM PDT 24 226023223 ps
T640 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.883981470 Apr 28 03:07:13 PM PDT 24 Apr 28 03:07:17 PM PDT 24 594520399 ps
T641 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1718758814 Apr 28 03:07:34 PM PDT 24 Apr 28 03:07:36 PM PDT 24 357650010 ps
T101 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3216890041 Apr 28 03:08:13 PM PDT 24 Apr 28 03:08:17 PM PDT 24 478574235 ps
T642 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2269660408 Apr 28 03:08:01 PM PDT 24 Apr 28 03:08:03 PM PDT 24 138847463 ps
T643 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3117362608 Apr 28 03:08:06 PM PDT 24 Apr 28 03:08:07 PM PDT 24 59648851 ps
T644 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2420778414 Apr 28 03:08:24 PM PDT 24 Apr 28 03:08:28 PM PDT 24 147883388 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3612684402 Apr 28 03:08:09 PM PDT 24 Apr 28 03:08:10 PM PDT 24 12596057 ps
T646 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2767794934 Apr 28 03:07:34 PM PDT 24 Apr 28 03:07:36 PM PDT 24 66843901 ps
T647 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2294574254 Apr 28 03:08:29 PM PDT 24 Apr 28 03:08:31 PM PDT 24 10252236 ps
T648 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3647807774 Apr 28 03:07:46 PM PDT 24 Apr 28 03:07:48 PM PDT 24 104962604 ps
T649 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3644861535 Apr 28 03:08:24 PM PDT 24 Apr 28 03:08:28 PM PDT 24 842778497 ps
T650 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.593051607 Apr 28 03:07:47 PM PDT 24 Apr 28 03:07:49 PM PDT 24 108048354 ps
T651 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3577903032 Apr 28 03:08:01 PM PDT 24 Apr 28 03:08:02 PM PDT 24 16777317 ps
T88 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2371255506 Apr 28 03:07:36 PM PDT 24 Apr 28 03:07:45 PM PDT 24 1778937772 ps
T652 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1288234187 Apr 28 03:08:36 PM PDT 24 Apr 28 03:08:37 PM PDT 24 13903492 ps
T653 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3902986884 Apr 28 03:08:06 PM PDT 24 Apr 28 03:08:09 PM PDT 24 107170823 ps
T89 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2567912017 Apr 28 03:07:55 PM PDT 24 Apr 28 03:07:56 PM PDT 24 52445892 ps
T90 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4132393051 Apr 28 03:07:22 PM PDT 24 Apr 28 03:07:39 PM PDT 24 1637604416 ps
T654 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3126923319 Apr 28 03:08:18 PM PDT 24 Apr 28 03:08:21 PM PDT 24 504630784 ps
T655 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.320546385 Apr 28 03:08:24 PM PDT 24 Apr 28 03:08:27 PM PDT 24 75770029 ps
T656 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1642271232 Apr 28 03:08:33 PM PDT 24 Apr 28 03:08:34 PM PDT 24 116412527 ps
T91 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4275138878 Apr 28 03:07:47 PM PDT 24 Apr 28 03:07:48 PM PDT 24 25875484 ps
T657 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1836843783 Apr 28 03:08:19 PM PDT 24 Apr 28 03:08:23 PM PDT 24 53285865 ps
T658 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2426297594 Apr 28 03:08:35 PM PDT 24 Apr 28 03:08:36 PM PDT 24 12897583 ps
T659 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3620035376 Apr 28 03:08:00 PM PDT 24 Apr 28 03:08:01 PM PDT 24 53129519 ps
T660 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3376516026 Apr 28 03:07:22 PM PDT 24 Apr 28 03:07:24 PM PDT 24 39631229 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3209490786 Apr 28 03:07:41 PM PDT 24 Apr 28 03:07:47 PM PDT 24 607448893 ps
T661 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2841698062 Apr 28 03:08:34 PM PDT 24 Apr 28 03:08:35 PM PDT 24 18134745 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1899030867 Apr 28 03:07:46 PM PDT 24 Apr 28 03:07:48 PM PDT 24 132451938 ps
T95 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3181267056 Apr 28 03:07:26 PM PDT 24 Apr 28 03:07:28 PM PDT 24 40939802 ps
T662 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3483692889 Apr 28 03:07:31 PM PDT 24 Apr 28 03:07:32 PM PDT 24 43361111 ps
T663 /workspace/coverage/cover_reg_top/3.hmac_intr_test.640839561 Apr 28 03:07:41 PM PDT 24 Apr 28 03:07:42 PM PDT 24 47258031 ps
T664 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.599623184 Apr 28 03:07:20 PM PDT 24 Apr 28 03:07:21 PM PDT 24 62388212 ps
T665 /workspace/coverage/cover_reg_top/16.hmac_intr_test.932264806 Apr 28 03:08:18 PM PDT 24 Apr 28 03:08:19 PM PDT 24 42578138 ps
T666 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3413670257 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:31 PM PDT 24 167162470 ps
T667 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3075045805 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:30 PM PDT 24 19752944 ps
T668 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1723330551 Apr 28 03:08:24 PM PDT 24 Apr 28 03:08:25 PM PDT 24 22971357 ps
T104 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1390147259 Apr 28 03:08:17 PM PDT 24 Apr 28 03:08:20 PM PDT 24 97727557 ps
T669 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2382170873 Apr 28 03:07:50 PM PDT 24 Apr 28 03:07:56 PM PDT 24 369637287 ps
T670 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1715538280 Apr 28 03:07:55 PM PDT 24 Apr 28 03:07:57 PM PDT 24 24606295 ps
T671 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3864037739 Apr 28 03:07:29 PM PDT 24 Apr 28 03:07:30 PM PDT 24 22986398 ps
T672 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1143909632 Apr 28 03:08:31 PM PDT 24 Apr 28 03:08:32 PM PDT 24 19021614 ps
T673 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2379975092 Apr 28 03:07:56 PM PDT 24 Apr 28 03:08:00 PM PDT 24 57995085 ps
T674 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3927675792 Apr 28 03:08:27 PM PDT 24 Apr 28 03:08:29 PM PDT 24 15232239 ps
T675 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1903810222 Apr 28 03:07:47 PM PDT 24 Apr 28 03:07:49 PM PDT 24 156246632 ps
T105 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2750134699 Apr 28 03:08:29 PM PDT 24 Apr 28 03:08:34 PM PDT 24 469119094 ps
T676 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1120503204 Apr 28 03:08:32 PM PDT 24 Apr 28 03:08:33 PM PDT 24 147391474 ps
T677 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.33042034 Apr 28 03:07:52 PM PDT 24 Apr 28 03:07:53 PM PDT 24 23385650 ps
T678 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.102685129 Apr 28 03:08:08 PM PDT 24 Apr 28 03:08:10 PM PDT 24 56083875 ps
T96 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2985237306 Apr 28 03:07:46 PM PDT 24 Apr 28 03:07:55 PM PDT 24 1857718130 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.522784860 Apr 28 03:07:30 PM PDT 24 Apr 28 03:07:34 PM PDT 24 156660086 ps
T679 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1488799352 Apr 28 03:07:50 PM PDT 24 Apr 28 03:07:53 PM PDT 24 66221223 ps
T97 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3336238490 Apr 28 03:08:19 PM PDT 24 Apr 28 03:08:20 PM PDT 24 29694948 ps
T680 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.262745045 Apr 28 03:07:48 PM PDT 24 Apr 28 03:07:50 PM PDT 24 371419700 ps
T681 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.29512822 Apr 28 03:07:24 PM PDT 24 Apr 28 03:07:26 PM PDT 24 234873717 ps
T682 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3716419449 Apr 28 03:08:18 PM PDT 24 Apr 28 03:08:20 PM PDT 24 70916913 ps
T683 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3584540354 Apr 28 03:07:16 PM PDT 24 Apr 28 03:07:19 PM PDT 24 97149949 ps
T98 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1916388055 Apr 28 03:07:40 PM PDT 24 Apr 28 03:07:41 PM PDT 24 23416817 ps
T684 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4005306467 Apr 28 03:07:27 PM PDT 24 Apr 28 03:07:30 PM PDT 24 2180758372 ps
T685 /workspace/coverage/cover_reg_top/15.hmac_intr_test.783044023 Apr 28 03:08:17 PM PDT 24 Apr 28 03:08:18 PM PDT 24 15690089 ps
T686 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1070470108 Apr 28 03:08:08 PM PDT 24 Apr 28 03:08:11 PM PDT 24 172488025 ps
T687 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1929005479 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:30 PM PDT 24 16859874 ps
T688 /workspace/coverage/cover_reg_top/47.hmac_intr_test.158927034 Apr 28 03:08:34 PM PDT 24 Apr 28 03:08:35 PM PDT 24 108050803 ps
T689 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1006059669 Apr 28 03:08:18 PM PDT 24 Apr 28 03:08:21 PM PDT 24 313316721 ps
T690 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1660324354 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:32 PM PDT 24 146334208 ps
T691 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.75437111 Apr 28 03:07:52 PM PDT 24 Apr 28 03:07:53 PM PDT 24 56564591 ps
T692 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3894039338 Apr 28 03:08:30 PM PDT 24 Apr 28 03:08:32 PM PDT 24 13406516 ps
T693 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1814840083 Apr 28 03:07:26 PM PDT 24 Apr 28 03:07:27 PM PDT 24 11142060 ps
T694 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3101541781 Apr 28 03:07:48 PM PDT 24 Apr 28 03:07:51 PM PDT 24 378164624 ps
T695 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2115309612 Apr 28 03:08:06 PM PDT 24 Apr 28 03:08:08 PM PDT 24 144836269 ps
T696 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3961140932 Apr 28 03:08:35 PM PDT 24 Apr 28 03:08:36 PM PDT 24 31079162 ps
T697 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3053276112 Apr 28 03:07:52 PM PDT 24 Apr 28 03:07:55 PM PDT 24 87231742 ps
T99 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2900047309 Apr 28 03:08:13 PM PDT 24 Apr 28 03:08:14 PM PDT 24 14431333 ps
T698 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1349743737 Apr 28 03:08:31 PM PDT 24 Apr 28 03:08:32 PM PDT 24 13244178 ps
T699 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2880472320 Apr 28 03:07:52 PM PDT 24 Apr 28 03:07:55 PM PDT 24 1277915282 ps
T103 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.159062691 Apr 28 03:08:02 PM PDT 24 Apr 28 03:08:05 PM PDT 24 1492158074 ps
T700 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1954558423 Apr 28 03:08:18 PM PDT 24 Apr 28 03:08:21 PM PDT 24 255452650 ps
T701 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2640484060 Apr 28 03:08:06 PM PDT 24 Apr 28 03:08:10 PM PDT 24 174490290 ps
T702 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.134785119 Apr 28 03:08:28 PM PDT 24 Apr 28 03:08:30 PM PDT 24 24931327 ps
T703 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.495434552 Apr 28 03:08:13 PM PDT 24 Apr 28 03:08:17 PM PDT 24 765087015 ps
T704 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2213771724 Apr 28 03:08:01 PM PDT 24 Apr 28 03:08:03 PM PDT 24 34720507 ps
T705 /workspace/coverage/cover_reg_top/26.hmac_intr_test.670393434 Apr 28 03:08:27 PM PDT 24 Apr 28 03:08:29 PM PDT 24 15427597 ps
T706 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.77014884 Apr 28 03:08:27 PM PDT 24 Apr 28 03:08:30 PM PDT 24 179917502 ps
T707 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3039438955 Apr 28 03:07:26 PM PDT 24 Apr 28 03:07:28 PM PDT 24 369361581 ps
T708 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3185170055 Apr 28 03:08:00 PM PDT 24 Apr 28 03:08:03 PM PDT 24 97838725 ps
T709 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1290943085 Apr 28 03:07:29 PM PDT 24 Apr 28 03:07:33 PM PDT 24 58444629 ps
T710 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3588268876 Apr 28 03:08:23 PM PDT 24 Apr 28 03:08:25 PM PDT 24 21211184 ps
T711 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1311641350 Apr 28 03:07:22 PM PDT 24 Apr 28 03:07:23 PM PDT 24 15063167 ps
T712 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.525651925 Apr 28 03:08:11 PM PDT 24 Apr 28 03:08:13 PM PDT 24 36210646 ps
T713 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3913280403 Apr 28 03:07:20 PM PDT 24 Apr 28 03:07:23 PM PDT 24 845025871 ps
T714 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3101391275 Apr 28 03:08:23 PM PDT 24 Apr 28 03:08:26 PM PDT 24 430726676 ps
T715 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2158415556 Apr 28 03:07:53 PM PDT 24 Apr 28 03:07:55 PM PDT 24 516793727 ps
T716 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4006280685 Apr 28 03:08:27 PM PDT 24 Apr 28 03:08:29 PM PDT 24 25208342 ps
T717 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2047007754 Apr 28 03:08:29 PM PDT 24 Apr 28 03:08:34 PM PDT 24 873574887 ps
T718 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2225141032 Apr 28 03:07:51 PM PDT 24 Apr 28 03:07:53 PM PDT 24 312640355 ps
T719 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2071057096 Apr 28 03:07:26 PM PDT 24 Apr 28 03:07:27 PM PDT 24 16968738 ps
T720 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2858721559 Apr 28 03:07:56 PM PDT 24 Apr 28 03:07:58 PM PDT 24 43067176 ps
T721 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.821935782 Apr 28 03:08:29 PM PDT 24 Apr 28 03:08:31 PM PDT 24 44046791 ps
T722 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4240405737 Apr 28 03:07:26 PM PDT 24 Apr 28 03:13:29 PM PDT 24 24005139837 ps
T723 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3282434376 Apr 28 03:07:51 PM PDT 24 Apr 28 03:07:54 PM PDT 24 272327327 ps
T724 /workspace/coverage/cover_reg_top/17.hmac_intr_test.682652310 Apr 28 03:08:25 PM PDT 24 Apr 28 03:08:26 PM PDT 24 32108903 ps
T66 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2992135202 Apr 28 03:08:14 PM PDT 24 Apr 28 03:08:16 PM PDT 24 58490059 ps
T725 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1292072414 Apr 28 03:07:21 PM PDT 24 Apr 28 03:07:22 PM PDT 24 59613730 ps
T726 /workspace/coverage/cover_reg_top/12.hmac_intr_test.499811979 Apr 28 03:08:08 PM PDT 24 Apr 28 03:08:09 PM PDT 24 37263360 ps
T727 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3446169752 Apr 28 03:08:34 PM PDT 24 Apr 28 03:08:35 PM PDT 24 33874139 ps
T728 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.435565555 Apr 28 03:08:13 PM PDT 24 Apr 28 03:08:17 PM PDT 24 189209220 ps
T729 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1946454240 Apr 28 03:07:26 PM PDT 24 Apr 28 03:07:35 PM PDT 24 539654630 ps
T730 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2514373124 Apr 28 03:08:21 PM PDT 24 Apr 28 03:08:22 PM PDT 24 14417614 ps
T731 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2764866263 Apr 28 03:07:45 PM PDT 24 Apr 28 03:07:46 PM PDT 24 33158734 ps
T732 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4065173325 Apr 28 03:07:40 PM PDT 24 Apr 28 03:07:43 PM PDT 24 1195540956 ps
T733 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1004462137 Apr 28 03:08:07 PM PDT 24 Apr 28 03:08:09 PM PDT 24 117505208 ps
T734 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3663107986 Apr 28 03:08:12 PM PDT 24 Apr 28 03:08:14 PM PDT 24 183686525 ps
T735 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2824376793 Apr 28 03:07:51 PM PDT 24 Apr 28 03:07:53 PM PDT 24 22548018 ps
T736 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3921610582 Apr 28 03:08:27 PM PDT 24 Apr 28 03:08:28 PM PDT 24 30791333 ps
T737 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2295741590 Apr 28 03:07:40 PM PDT 24 Apr 28 03:07:51 PM PDT 24 736006257 ps
T738 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.619671364 Apr 28 03:08:12 PM PDT 24 Apr 28 03:08:13 PM PDT 24 124462725 ps
T107 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3189058505 Apr 28 03:07:55 PM PDT 24 Apr 28 03:07:59 PM PDT 24 135366858 ps
T739 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4190551202 Apr 28 03:08:07 PM PDT 24 Apr 28 03:08:10 PM PDT 24 247618940 ps
T740 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3539868638 Apr 28 03:07:51 PM PDT 24 Apr 28 03:20:32 PM PDT 24 194956979433 ps

Test location /workspace/coverage/default/9.hmac_stress_all.3500105571
Short name T2
Test name
Test status
Simulation time 294297629776 ps
CPU time 948.9 seconds
Started Apr 28 03:19:39 PM PDT 24
Finished Apr 28 03:35:28 PM PDT 24
Peak memory 238148 kb
Host smart-048de7df-7042-41a9-964a-ccb2e54c3f35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500105571 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3500105571
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.3270759449
Short name T6
Test name
Test status
Simulation time 80141182999 ps
CPU time 2871.77 seconds
Started Apr 28 03:22:48 PM PDT 24
Finished Apr 28 04:10:42 PM PDT 24
Peak memory 248628 kb
Host smart-39d87907-7d7c-40db-8007-9b00461f770a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270759449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.3270759449
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1487124309
Short name T23
Test name
Test status
Simulation time 1845040887 ps
CPU time 13.87 seconds
Started Apr 28 03:20:17 PM PDT 24
Finished Apr 28 03:20:32 PM PDT 24
Peak memory 199628 kb
Host smart-5e27e0cc-e5fd-4349-8001-5612a56f51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487124309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1487124309
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.31572176
Short name T31
Test name
Test status
Simulation time 525690117 ps
CPU time 0.98 seconds
Started Apr 28 03:19:17 PM PDT 24
Finished Apr 28 03:19:19 PM PDT 24
Peak memory 219116 kb
Host smart-e89fc5a2-9505-46a8-9f61-6acae5275df1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31572176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.31572176
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1083299933
Short name T61
Test name
Test status
Simulation time 92771227 ps
CPU time 2.83 seconds
Started Apr 28 03:07:47 PM PDT 24
Finished Apr 28 03:07:50 PM PDT 24
Peak memory 199348 kb
Host smart-f3937a8e-95b2-44c5-8490-0d1e3213d932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083299933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1083299933
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.687338238
Short name T7
Test name
Test status
Simulation time 137031553256 ps
CPU time 1027.37 seconds
Started Apr 28 03:22:53 PM PDT 24
Finished Apr 28 03:40:01 PM PDT 24
Peak memory 251228 kb
Host smart-98da68bf-7fd8-451b-b11e-cc8c9b40253e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687338238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.687338238
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1129535759
Short name T11
Test name
Test status
Simulation time 15340301865 ps
CPU time 771.75 seconds
Started Apr 28 03:20:55 PM PDT 24
Finished Apr 28 03:33:47 PM PDT 24
Peak memory 226252 kb
Host smart-f08ef740-c732-4976-b009-d8af0e4ea23f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129535759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1129535759
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.2526280861
Short name T9
Test name
Test status
Simulation time 221097305547 ps
CPU time 6165.48 seconds
Started Apr 28 03:23:09 PM PDT 24
Finished Apr 28 05:05:56 PM PDT 24
Peak memory 273496 kb
Host smart-6f6e3b73-deca-4c68-8314-2b8f9f803b67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526280861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.2526280861
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3216890041
Short name T101
Test name
Test status
Simulation time 478574235 ps
CPU time 4 seconds
Started Apr 28 03:08:13 PM PDT 24
Finished Apr 28 03:08:17 PM PDT 24
Peak memory 199328 kb
Host smart-026a38bb-f685-4244-ae73-afd3c50a2918
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216890041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3216890041
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4189060083
Short name T48
Test name
Test status
Simulation time 122593652365 ps
CPU time 1694.31 seconds
Started Apr 28 03:19:30 PM PDT 24
Finished Apr 28 03:47:45 PM PDT 24
Peak memory 240632 kb
Host smart-422633b2-c0fb-4c1e-be3f-3743340f1263
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189060083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4189060083
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3619798606
Short name T123
Test name
Test status
Simulation time 25438347 ps
CPU time 0.56 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:19:55 PM PDT 24
Peak memory 194200 kb
Host smart-e6972547-e22d-46dd-bcf2-68f8f210cfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619798606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3619798606
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1591786031
Short name T100
Test name
Test status
Simulation time 193982161 ps
CPU time 3.29 seconds
Started Apr 28 03:07:40 PM PDT 24
Finished Apr 28 03:07:44 PM PDT 24
Peak memory 199360 kb
Host smart-aceece8e-5a13-4261-83cc-eb18ce65a355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591786031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1591786031
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4132393051
Short name T90
Test name
Test status
Simulation time 1637604416 ps
CPU time 16.64 seconds
Started Apr 28 03:07:22 PM PDT 24
Finished Apr 28 03:07:39 PM PDT 24
Peak memory 199096 kb
Host smart-da16450f-3704-43fd-ad11-266b6f5e5446
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132393051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4132393051
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2992135202
Short name T66
Test name
Test status
Simulation time 58490059 ps
CPU time 1.61 seconds
Started Apr 28 03:08:14 PM PDT 24
Finished Apr 28 03:08:16 PM PDT 24
Peak memory 199356 kb
Host smart-bad67131-f247-430d-81b6-6f4e2177ce56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992135202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2992135202
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.585247716
Short name T43
Test name
Test status
Simulation time 11301512752 ps
CPU time 175.77 seconds
Started Apr 28 03:22:13 PM PDT 24
Finished Apr 28 03:25:09 PM PDT 24
Peak memory 216120 kb
Host smart-dc03c5f2-6668-4836-81c0-958c2119d2a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585247716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.585247716
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3913280403
Short name T713
Test name
Test status
Simulation time 845025871 ps
CPU time 3.16 seconds
Started Apr 28 03:07:20 PM PDT 24
Finished Apr 28 03:07:23 PM PDT 24
Peak memory 197844 kb
Host smart-4f5a6204-2d06-4471-b043-b26a13fb873a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913280403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3913280403
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1292072414
Short name T725
Test name
Test status
Simulation time 59613730 ps
CPU time 0.87 seconds
Started Apr 28 03:07:21 PM PDT 24
Finished Apr 28 03:07:22 PM PDT 24
Peak memory 197980 kb
Host smart-1207bf84-2a2c-41c4-8e37-ddedecb4834d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292072414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1292072414
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4240405737
Short name T722
Test name
Test status
Simulation time 24005139837 ps
CPU time 362.68 seconds
Started Apr 28 03:07:26 PM PDT 24
Finished Apr 28 03:13:29 PM PDT 24
Peak memory 215776 kb
Host smart-c564ea6b-59c9-47dd-8a99-994cc34940ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240405737 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.4240405737
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.599623184
Short name T664
Test name
Test status
Simulation time 62388212 ps
CPU time 0.66 seconds
Started Apr 28 03:07:20 PM PDT 24
Finished Apr 28 03:07:21 PM PDT 24
Peak memory 196752 kb
Host smart-e30f5ef1-caf2-4ed3-b7b3-c7212fbfccbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599623184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.599623184
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1311641350
Short name T711
Test name
Test status
Simulation time 15063167 ps
CPU time 0.58 seconds
Started Apr 28 03:07:22 PM PDT 24
Finished Apr 28 03:07:23 PM PDT 24
Peak memory 194088 kb
Host smart-7d7b1418-ec3c-4eb2-a9ce-e0b105416b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311641350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1311641350
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3376516026
Short name T660
Test name
Test status
Simulation time 39631229 ps
CPU time 1.68 seconds
Started Apr 28 03:07:22 PM PDT 24
Finished Apr 28 03:07:24 PM PDT 24
Peak memory 198972 kb
Host smart-fb684469-fe70-4378-8cf4-74bf43849a4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376516026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3376516026
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.883981470
Short name T640
Test name
Test status
Simulation time 594520399 ps
CPU time 2.71 seconds
Started Apr 28 03:07:13 PM PDT 24
Finished Apr 28 03:07:17 PM PDT 24
Peak memory 199380 kb
Host smart-1e22763d-a3e4-475e-a783-339fac20663b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883981470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.883981470
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3584540354
Short name T683
Test name
Test status
Simulation time 97149949 ps
CPU time 1.8 seconds
Started Apr 28 03:07:16 PM PDT 24
Finished Apr 28 03:07:19 PM PDT 24
Peak memory 199284 kb
Host smart-4705037a-3b01-47d6-9c87-fcb521380e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584540354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3584540354
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1946454240
Short name T729
Test name
Test status
Simulation time 539654630 ps
CPU time 8.74 seconds
Started Apr 28 03:07:26 PM PDT 24
Finished Apr 28 03:07:35 PM PDT 24
Peak memory 198892 kb
Host smart-1f3960b8-4f40-462e-8234-9c7024a4d7e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946454240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1946454240
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.707189977
Short name T616
Test name
Test status
Simulation time 740979651 ps
CPU time 10.64 seconds
Started Apr 28 03:07:25 PM PDT 24
Finished Apr 28 03:07:36 PM PDT 24
Peak memory 199192 kb
Host smart-b0eb3cc8-d3b0-43a2-873d-af6b74b92c6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707189977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.707189977
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3181267056
Short name T95
Test name
Test status
Simulation time 40939802 ps
CPU time 0.98 seconds
Started Apr 28 03:07:26 PM PDT 24
Finished Apr 28 03:07:28 PM PDT 24
Peak memory 199208 kb
Host smart-f42f3907-92ed-4a79-89b4-bb0194c2f4c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181267056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3181267056
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.29512822
Short name T681
Test name
Test status
Simulation time 234873717 ps
CPU time 1.82 seconds
Started Apr 28 03:07:24 PM PDT 24
Finished Apr 28 03:07:26 PM PDT 24
Peak memory 199340 kb
Host smart-d5f80f25-920e-4da1-bd38-df9b682869e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29512822 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.29512822
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2071057096
Short name T719
Test name
Test status
Simulation time 16968738 ps
CPU time 0.78 seconds
Started Apr 28 03:07:26 PM PDT 24
Finished Apr 28 03:07:27 PM PDT 24
Peak memory 198584 kb
Host smart-443d3a4e-57a8-40d5-9735-93087f507058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071057096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2071057096
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1814840083
Short name T693
Test name
Test status
Simulation time 11142060 ps
CPU time 0.57 seconds
Started Apr 28 03:07:26 PM PDT 24
Finished Apr 28 03:07:27 PM PDT 24
Peak memory 194048 kb
Host smart-981e52bd-dbe3-4c57-a53e-4393c9163a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814840083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1814840083
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3039438955
Short name T707
Test name
Test status
Simulation time 369361581 ps
CPU time 2.22 seconds
Started Apr 28 03:07:26 PM PDT 24
Finished Apr 28 03:07:28 PM PDT 24
Peak memory 199284 kb
Host smart-563370ca-6337-4e87-81f6-eadba44874e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039438955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3039438955
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4005306467
Short name T684
Test name
Test status
Simulation time 2180758372 ps
CPU time 2.74 seconds
Started Apr 28 03:07:27 PM PDT 24
Finished Apr 28 03:07:30 PM PDT 24
Peak memory 199436 kb
Host smart-4a0e4a44-c8e6-4043-bd7c-6ac24cdb68f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005306467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4005306467
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.872725181
Short name T108
Test name
Test status
Simulation time 179071310 ps
CPU time 1.88 seconds
Started Apr 28 03:07:26 PM PDT 24
Finished Apr 28 03:07:28 PM PDT 24
Peak memory 199316 kb
Host smart-19534f3b-d99f-4311-8ae5-e69c5e2c6139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872725181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.872725181
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4190551202
Short name T739
Test name
Test status
Simulation time 247618940 ps
CPU time 1.88 seconds
Started Apr 28 03:08:07 PM PDT 24
Finished Apr 28 03:08:10 PM PDT 24
Peak memory 199384 kb
Host smart-ccd08fd2-97c1-4bc3-a6b8-e1d73d2ee436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190551202 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4190551202
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3612684402
Short name T645
Test name
Test status
Simulation time 12596057 ps
CPU time 0.67 seconds
Started Apr 28 03:08:09 PM PDT 24
Finished Apr 28 03:08:10 PM PDT 24
Peak memory 196960 kb
Host smart-f24eacd3-1c9d-4d64-8724-5b4c10489fd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612684402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3612684402
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3577903032
Short name T651
Test name
Test status
Simulation time 16777317 ps
CPU time 0.6 seconds
Started Apr 28 03:08:01 PM PDT 24
Finished Apr 28 03:08:02 PM PDT 24
Peak memory 194060 kb
Host smart-074a4584-bfcb-48a2-814f-cf0705b6a36a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577903032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3577903032
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3902986884
Short name T653
Test name
Test status
Simulation time 107170823 ps
CPU time 2.27 seconds
Started Apr 28 03:08:06 PM PDT 24
Finished Apr 28 03:08:09 PM PDT 24
Peak memory 199304 kb
Host smart-4e58a812-2d13-4649-8426-adc2f9e513a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902986884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3902986884
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3185170055
Short name T708
Test name
Test status
Simulation time 97838725 ps
CPU time 2.14 seconds
Started Apr 28 03:08:00 PM PDT 24
Finished Apr 28 03:08:03 PM PDT 24
Peak memory 199432 kb
Host smart-52ba0f3b-9b0f-4f58-94ce-541cb892a838
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185170055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3185170055
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.159062691
Short name T103
Test name
Test status
Simulation time 1492158074 ps
CPU time 3.16 seconds
Started Apr 28 03:08:02 PM PDT 24
Finished Apr 28 03:08:05 PM PDT 24
Peak memory 199280 kb
Host smart-e133ccb3-d54c-4cfa-93d2-8edda377519b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159062691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.159062691
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2115309612
Short name T695
Test name
Test status
Simulation time 144836269 ps
CPU time 1.61 seconds
Started Apr 28 03:08:06 PM PDT 24
Finished Apr 28 03:08:08 PM PDT 24
Peak memory 199392 kb
Host smart-7a4cfa31-f3ec-4b14-aa26-f2bba8410407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115309612 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2115309612
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2721579555
Short name T64
Test name
Test status
Simulation time 21374869 ps
CPU time 0.7 seconds
Started Apr 28 03:08:06 PM PDT 24
Finished Apr 28 03:08:07 PM PDT 24
Peak memory 197352 kb
Host smart-f64ca9fc-1e18-480e-81ca-88399e6526a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721579555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2721579555
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1260571665
Short name T619
Test name
Test status
Simulation time 28201060 ps
CPU time 0.61 seconds
Started Apr 28 03:08:11 PM PDT 24
Finished Apr 28 03:08:12 PM PDT 24
Peak memory 194176 kb
Host smart-653bb3d6-acfe-403b-8756-7df62423d9f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260571665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1260571665
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1004462137
Short name T733
Test name
Test status
Simulation time 117505208 ps
CPU time 1.65 seconds
Started Apr 28 03:08:07 PM PDT 24
Finished Apr 28 03:08:09 PM PDT 24
Peak memory 199316 kb
Host smart-c860bd5d-1902-4cfa-8496-05af0d766be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004462137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1004462137
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.102685129
Short name T678
Test name
Test status
Simulation time 56083875 ps
CPU time 1.52 seconds
Started Apr 28 03:08:08 PM PDT 24
Finished Apr 28 03:08:10 PM PDT 24
Peak memory 199356 kb
Host smart-27c777fb-d617-4770-8b48-68d5e1bd4806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102685129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.102685129
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1070470108
Short name T686
Test name
Test status
Simulation time 172488025 ps
CPU time 1.69 seconds
Started Apr 28 03:08:08 PM PDT 24
Finished Apr 28 03:08:11 PM PDT 24
Peak memory 199320 kb
Host smart-d163eb1c-c462-4d25-b27a-690c8f7cb200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070470108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1070470108
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1836843783
Short name T657
Test name
Test status
Simulation time 53285865 ps
CPU time 3.54 seconds
Started Apr 28 03:08:19 PM PDT 24
Finished Apr 28 03:08:23 PM PDT 24
Peak memory 207516 kb
Host smart-e5f94cb6-693d-45e9-a634-8f41f6688911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836843783 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1836843783
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2888393622
Short name T624
Test name
Test status
Simulation time 93991727 ps
CPU time 0.98 seconds
Started Apr 28 03:08:07 PM PDT 24
Finished Apr 28 03:08:09 PM PDT 24
Peak memory 198900 kb
Host smart-591d5d93-aefb-4668-bc24-c1c4098c68eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888393622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2888393622
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.499811979
Short name T726
Test name
Test status
Simulation time 37263360 ps
CPU time 0.57 seconds
Started Apr 28 03:08:08 PM PDT 24
Finished Apr 28 03:08:09 PM PDT 24
Peak memory 194004 kb
Host smart-a5cdcda5-a43f-4e39-b2fd-2575e4508312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499811979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.499811979
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3117362608
Short name T643
Test name
Test status
Simulation time 59648851 ps
CPU time 1.18 seconds
Started Apr 28 03:08:06 PM PDT 24
Finished Apr 28 03:08:07 PM PDT 24
Peak memory 197452 kb
Host smart-0ff24014-8502-4fbb-aa90-77e08d7de0ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117362608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3117362608
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1038154060
Short name T614
Test name
Test status
Simulation time 188595937 ps
CPU time 3.36 seconds
Started Apr 28 03:08:08 PM PDT 24
Finished Apr 28 03:08:12 PM PDT 24
Peak memory 199336 kb
Host smart-d3abf037-b3ca-4907-a8c1-c98dd82e895f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038154060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1038154060
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2640484060
Short name T701
Test name
Test status
Simulation time 174490290 ps
CPU time 3.15 seconds
Started Apr 28 03:08:06 PM PDT 24
Finished Apr 28 03:08:10 PM PDT 24
Peak memory 199276 kb
Host smart-3782827d-c97d-418c-80f1-88ef97821dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640484060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2640484060
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.525651925
Short name T712
Test name
Test status
Simulation time 36210646 ps
CPU time 1.21 seconds
Started Apr 28 03:08:11 PM PDT 24
Finished Apr 28 03:08:13 PM PDT 24
Peak memory 199260 kb
Host smart-021b96e6-c9c0-46f5-b314-ef7182154a76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525651925 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.525651925
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.619671364
Short name T738
Test name
Test status
Simulation time 124462725 ps
CPU time 0.81 seconds
Started Apr 28 03:08:12 PM PDT 24
Finished Apr 28 03:08:13 PM PDT 24
Peak memory 199068 kb
Host smart-f96862a1-317e-4144-ae60-40bb9a6eb542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619671364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.619671364
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.755843621
Short name T615
Test name
Test status
Simulation time 39048929 ps
CPU time 0.57 seconds
Started Apr 28 03:08:19 PM PDT 24
Finished Apr 28 03:08:20 PM PDT 24
Peak memory 194004 kb
Host smart-145020fd-433c-4ef7-b4c8-06ae8e9c819f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755843621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.755843621
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3663107986
Short name T734
Test name
Test status
Simulation time 183686525 ps
CPU time 1.19 seconds
Started Apr 28 03:08:12 PM PDT 24
Finished Apr 28 03:08:14 PM PDT 24
Peak memory 199260 kb
Host smart-59f3383f-df42-4653-8b40-d4f7825707c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663107986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3663107986
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.435565555
Short name T728
Test name
Test status
Simulation time 189209220 ps
CPU time 3.81 seconds
Started Apr 28 03:08:13 PM PDT 24
Finished Apr 28 03:08:17 PM PDT 24
Peak memory 199384 kb
Host smart-16848c16-2167-48f2-85d9-4934c03067fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435565555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.435565555
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3101391275
Short name T714
Test name
Test status
Simulation time 430726676 ps
CPU time 2.45 seconds
Started Apr 28 03:08:23 PM PDT 24
Finished Apr 28 03:08:26 PM PDT 24
Peak memory 199392 kb
Host smart-9b218e28-68d5-4e80-9402-c26a43fe1185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101391275 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3101391275
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2900047309
Short name T99
Test name
Test status
Simulation time 14431333 ps
CPU time 0.81 seconds
Started Apr 28 03:08:13 PM PDT 24
Finished Apr 28 03:08:14 PM PDT 24
Peak memory 198676 kb
Host smart-f2eebbb9-3936-430d-9cea-6357be7a7868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900047309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2900047309
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2514373124
Short name T730
Test name
Test status
Simulation time 14417614 ps
CPU time 0.6 seconds
Started Apr 28 03:08:21 PM PDT 24
Finished Apr 28 03:08:22 PM PDT 24
Peak memory 194072 kb
Host smart-a54cc86c-7e85-48fc-b2ad-55f655f31f6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514373124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2514373124
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3126923319
Short name T654
Test name
Test status
Simulation time 504630784 ps
CPU time 2.37 seconds
Started Apr 28 03:08:18 PM PDT 24
Finished Apr 28 03:08:21 PM PDT 24
Peak memory 199108 kb
Host smart-b620db74-1ccb-480c-95d0-6a6a820d4381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126923319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3126923319
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.495434552
Short name T703
Test name
Test status
Simulation time 765087015 ps
CPU time 4.21 seconds
Started Apr 28 03:08:13 PM PDT 24
Finished Apr 28 03:08:17 PM PDT 24
Peak memory 199356 kb
Host smart-a7acf2ac-4f47-4a09-8458-fcf04af6eb42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495434552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.495434552
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3716419449
Short name T682
Test name
Test status
Simulation time 70916913 ps
CPU time 1.75 seconds
Started Apr 28 03:08:18 PM PDT 24
Finished Apr 28 03:08:20 PM PDT 24
Peak memory 199348 kb
Host smart-8f991465-4af8-4a57-a713-97773e509381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716419449 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3716419449
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2330196109
Short name T634
Test name
Test status
Simulation time 18947496 ps
CPU time 0.69 seconds
Started Apr 28 03:08:17 PM PDT 24
Finished Apr 28 03:08:18 PM PDT 24
Peak memory 197364 kb
Host smart-43eab3d8-fda5-48eb-ae7a-3256c2a0d3d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330196109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2330196109
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.783044023
Short name T685
Test name
Test status
Simulation time 15690089 ps
CPU time 0.59 seconds
Started Apr 28 03:08:17 PM PDT 24
Finished Apr 28 03:08:18 PM PDT 24
Peak memory 194112 kb
Host smart-41b32a1a-93c8-4741-b100-82d56abb8fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783044023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.783044023
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1954558423
Short name T700
Test name
Test status
Simulation time 255452650 ps
CPU time 2.23 seconds
Started Apr 28 03:08:18 PM PDT 24
Finished Apr 28 03:08:21 PM PDT 24
Peak memory 199288 kb
Host smart-a4c99ddc-684d-4204-8759-c9af5d241d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954558423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1954558423
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.696598952
Short name T635
Test name
Test status
Simulation time 247716392 ps
CPU time 3.24 seconds
Started Apr 28 03:08:24 PM PDT 24
Finished Apr 28 03:08:28 PM PDT 24
Peak memory 199356 kb
Host smart-6f907f67-7fd1-4db0-b293-87763ce70c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696598952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.696598952
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1390147259
Short name T104
Test name
Test status
Simulation time 97727557 ps
CPU time 2.74 seconds
Started Apr 28 03:08:17 PM PDT 24
Finished Apr 28 03:08:20 PM PDT 24
Peak memory 199284 kb
Host smart-e63d4e90-69f2-4d40-98fb-bc6f545cb944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390147259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1390147259
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.320546385
Short name T655
Test name
Test status
Simulation time 75770029 ps
CPU time 1.77 seconds
Started Apr 28 03:08:24 PM PDT 24
Finished Apr 28 03:08:27 PM PDT 24
Peak memory 199416 kb
Host smart-a092d1f8-2baa-4014-ba49-0e30378ec040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320546385 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.320546385
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3336238490
Short name T97
Test name
Test status
Simulation time 29694948 ps
CPU time 0.92 seconds
Started Apr 28 03:08:19 PM PDT 24
Finished Apr 28 03:08:20 PM PDT 24
Peak memory 199112 kb
Host smart-843d567c-3681-42fa-91f0-d473f9ea34ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336238490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3336238490
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.932264806
Short name T665
Test name
Test status
Simulation time 42578138 ps
CPU time 0.62 seconds
Started Apr 28 03:08:18 PM PDT 24
Finished Apr 28 03:08:19 PM PDT 24
Peak memory 194104 kb
Host smart-b28d9488-dd88-42d9-a977-2513f2ebe533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932264806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.932264806
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1599419415
Short name T639
Test name
Test status
Simulation time 226023223 ps
CPU time 2.15 seconds
Started Apr 28 03:08:25 PM PDT 24
Finished Apr 28 03:08:28 PM PDT 24
Peak memory 199120 kb
Host smart-bea85d4d-eeac-4e89-a9f6-ef65cdfade55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599419415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1599419415
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3468121257
Short name T625
Test name
Test status
Simulation time 240836783 ps
CPU time 3.35 seconds
Started Apr 28 03:08:22 PM PDT 24
Finished Apr 28 03:08:26 PM PDT 24
Peak memory 199388 kb
Host smart-37a24a51-932b-4896-be80-187121c90f40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468121257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3468121257
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1006059669
Short name T689
Test name
Test status
Simulation time 313316721 ps
CPU time 2.93 seconds
Started Apr 28 03:08:18 PM PDT 24
Finished Apr 28 03:08:21 PM PDT 24
Peak memory 199336 kb
Host smart-7f280e51-12b9-4b0b-a408-7333fda032d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006059669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1006059669
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3036948855
Short name T622
Test name
Test status
Simulation time 72095913 ps
CPU time 1.71 seconds
Started Apr 28 03:08:22 PM PDT 24
Finished Apr 28 03:08:24 PM PDT 24
Peak memory 199292 kb
Host smart-d4c25a19-cffc-4c4a-b824-027b5db30021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036948855 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3036948855
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1723330551
Short name T668
Test name
Test status
Simulation time 22971357 ps
CPU time 0.82 seconds
Started Apr 28 03:08:24 PM PDT 24
Finished Apr 28 03:08:25 PM PDT 24
Peak memory 198664 kb
Host smart-da88e4f6-fd16-403c-9459-7b515922a922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723330551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1723330551
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.682652310
Short name T724
Test name
Test status
Simulation time 32108903 ps
CPU time 0.59 seconds
Started Apr 28 03:08:25 PM PDT 24
Finished Apr 28 03:08:26 PM PDT 24
Peak memory 193916 kb
Host smart-a43c6bf2-94f4-4f25-b780-ff35682df294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682652310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.682652310
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3588268876
Short name T710
Test name
Test status
Simulation time 21211184 ps
CPU time 1.05 seconds
Started Apr 28 03:08:23 PM PDT 24
Finished Apr 28 03:08:25 PM PDT 24
Peak memory 199136 kb
Host smart-88a6f3ec-2a84-4d8f-b87f-786b880dc50d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588268876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3588268876
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2420778414
Short name T644
Test name
Test status
Simulation time 147883388 ps
CPU time 2.96 seconds
Started Apr 28 03:08:24 PM PDT 24
Finished Apr 28 03:08:28 PM PDT 24
Peak memory 199332 kb
Host smart-d8db6e24-21b4-4672-a073-fb8c12d10d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420778414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2420778414
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1715979601
Short name T62
Test name
Test status
Simulation time 101794097 ps
CPU time 1.99 seconds
Started Apr 28 03:08:29 PM PDT 24
Finished Apr 28 03:08:32 PM PDT 24
Peak memory 199304 kb
Host smart-3aa82d82-8a09-4c64-8dc1-501990195e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715979601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1715979601
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1654517435
Short name T623
Test name
Test status
Simulation time 1625926646 ps
CPU time 2.43 seconds
Started Apr 28 03:08:24 PM PDT 24
Finished Apr 28 03:08:27 PM PDT 24
Peak memory 199348 kb
Host smart-4ee7ebd5-d8a1-448c-9588-fff25496b07d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654517435 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1654517435
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.821935782
Short name T721
Test name
Test status
Simulation time 44046791 ps
CPU time 0.8 seconds
Started Apr 28 03:08:29 PM PDT 24
Finished Apr 28 03:08:31 PM PDT 24
Peak memory 199152 kb
Host smart-158604e2-fbb3-4cc2-a237-ef46f2940461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821935782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.821935782
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1319921413
Short name T613
Test name
Test status
Simulation time 14317497 ps
CPU time 0.59 seconds
Started Apr 28 03:08:24 PM PDT 24
Finished Apr 28 03:08:25 PM PDT 24
Peak memory 194244 kb
Host smart-f2611bf4-658b-4524-ae9e-17a15f5baeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319921413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1319921413
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3413670257
Short name T666
Test name
Test status
Simulation time 167162470 ps
CPU time 1.13 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:31 PM PDT 24
Peak memory 198924 kb
Host smart-e57d379a-2b53-49ef-a181-3009b296fdbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413670257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3413670257
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3644861535
Short name T649
Test name
Test status
Simulation time 842778497 ps
CPU time 3.34 seconds
Started Apr 28 03:08:24 PM PDT 24
Finished Apr 28 03:08:28 PM PDT 24
Peak memory 199380 kb
Host smart-6f9382c3-a117-43fb-bbf3-d5677938bc91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644861535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3644861535
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1660324354
Short name T690
Test name
Test status
Simulation time 146334208 ps
CPU time 2.64 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:32 PM PDT 24
Peak memory 199340 kb
Host smart-0308c6af-1a6f-494d-84cd-f4c988d9839a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660324354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1660324354
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.134785119
Short name T702
Test name
Test status
Simulation time 24931327 ps
CPU time 1.4 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:30 PM PDT 24
Peak memory 199396 kb
Host smart-c8ca15de-5da4-489e-828d-a5ffec713ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134785119 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.134785119
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3075045805
Short name T667
Test name
Test status
Simulation time 19752944 ps
CPU time 0.7 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:30 PM PDT 24
Peak memory 196480 kb
Host smart-d5e24baa-e8a0-41a8-8214-2f90d3fae5ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075045805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3075045805
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.243401279
Short name T627
Test name
Test status
Simulation time 16444320 ps
CPU time 0.63 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:30 PM PDT 24
Peak memory 194044 kb
Host smart-c5ec5496-6e81-41ab-9a85-7ad69aebed79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243401279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.243401279
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.77014884
Short name T706
Test name
Test status
Simulation time 179917502 ps
CPU time 2.02 seconds
Started Apr 28 03:08:27 PM PDT 24
Finished Apr 28 03:08:30 PM PDT 24
Peak memory 199056 kb
Host smart-0f12019e-796c-4d18-8155-72ff78f01adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77014884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_
outstanding.77014884
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2047007754
Short name T717
Test name
Test status
Simulation time 873574887 ps
CPU time 4.12 seconds
Started Apr 28 03:08:29 PM PDT 24
Finished Apr 28 03:08:34 PM PDT 24
Peak memory 199384 kb
Host smart-f7940947-4e43-4c79-afbd-39ea493e6b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047007754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2047007754
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2750134699
Short name T105
Test name
Test status
Simulation time 469119094 ps
CPU time 3.97 seconds
Started Apr 28 03:08:29 PM PDT 24
Finished Apr 28 03:08:34 PM PDT 24
Peak memory 199336 kb
Host smart-deb4108a-6e98-4bfd-be52-00873a38d8c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750134699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2750134699
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2371255506
Short name T88
Test name
Test status
Simulation time 1778937772 ps
CPU time 8.52 seconds
Started Apr 28 03:07:36 PM PDT 24
Finished Apr 28 03:07:45 PM PDT 24
Peak memory 198932 kb
Host smart-026eda98-601d-4ce5-b314-c8069f13ab5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371255506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2371255506
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3795359632
Short name T92
Test name
Test status
Simulation time 2111473980 ps
CPU time 6.04 seconds
Started Apr 28 03:07:29 PM PDT 24
Finished Apr 28 03:07:36 PM PDT 24
Peak memory 198276 kb
Host smart-b5d5697e-0f16-4a9d-a887-8442934349d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795359632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3795359632
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1522344976
Short name T86
Test name
Test status
Simulation time 80118982 ps
CPU time 0.71 seconds
Started Apr 28 03:07:31 PM PDT 24
Finished Apr 28 03:07:32 PM PDT 24
Peak memory 196788 kb
Host smart-625f4f25-57ea-49ab-b8ad-74c2a11edbba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522344976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1522344976
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2767794934
Short name T646
Test name
Test status
Simulation time 66843901 ps
CPU time 1.6 seconds
Started Apr 28 03:07:34 PM PDT 24
Finished Apr 28 03:07:36 PM PDT 24
Peak memory 199296 kb
Host smart-6ef2cbc8-69f8-4269-8c43-52c5ada6ed37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767794934 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2767794934
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3483692889
Short name T662
Test name
Test status
Simulation time 43361111 ps
CPU time 0.81 seconds
Started Apr 28 03:07:31 PM PDT 24
Finished Apr 28 03:07:32 PM PDT 24
Peak memory 198724 kb
Host smart-ce38cef3-caa2-43c5-80df-869ab8042117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483692889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3483692889
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3864037739
Short name T671
Test name
Test status
Simulation time 22986398 ps
CPU time 0.56 seconds
Started Apr 28 03:07:29 PM PDT 24
Finished Apr 28 03:07:30 PM PDT 24
Peak memory 194060 kb
Host smart-ea9acf8b-3a5f-4d33-9586-8e1363e709e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864037739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3864037739
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1718758814
Short name T641
Test name
Test status
Simulation time 357650010 ps
CPU time 1.19 seconds
Started Apr 28 03:07:34 PM PDT 24
Finished Apr 28 03:07:36 PM PDT 24
Peak memory 197880 kb
Host smart-4ac80bd4-9ba4-418e-aebc-f4bd25700f2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718758814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1718758814
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1290943085
Short name T709
Test name
Test status
Simulation time 58444629 ps
CPU time 2.71 seconds
Started Apr 28 03:07:29 PM PDT 24
Finished Apr 28 03:07:33 PM PDT 24
Peak memory 199428 kb
Host smart-5fffbebb-4fbc-4602-98f8-7f0bdbe7ae1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290943085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1290943085
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.522784860
Short name T102
Test name
Test status
Simulation time 156660086 ps
CPU time 2.76 seconds
Started Apr 28 03:07:30 PM PDT 24
Finished Apr 28 03:07:34 PM PDT 24
Peak memory 199312 kb
Host smart-8e750801-1be1-4661-813c-a75b167502e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522784860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.522784860
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1718448229
Short name T631
Test name
Test status
Simulation time 16111382 ps
CPU time 0.61 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:30 PM PDT 24
Peak memory 194148 kb
Host smart-8e66ea31-3422-4ad5-a29e-de2cd31e2f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718448229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1718448229
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3927675792
Short name T674
Test name
Test status
Simulation time 15232239 ps
CPU time 0.56 seconds
Started Apr 28 03:08:27 PM PDT 24
Finished Apr 28 03:08:29 PM PDT 24
Peak memory 194220 kb
Host smart-0ede790a-5056-47e3-87a1-1bd5cdf156b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927675792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3927675792
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3921610582
Short name T736
Test name
Test status
Simulation time 30791333 ps
CPU time 0.62 seconds
Started Apr 28 03:08:27 PM PDT 24
Finished Apr 28 03:08:28 PM PDT 24
Peak memory 194200 kb
Host smart-adb822a7-0421-456a-8b35-b72badf49d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921610582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3921610582
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1669874325
Short name T626
Test name
Test status
Simulation time 45375416 ps
CPU time 0.59 seconds
Started Apr 28 03:08:35 PM PDT 24
Finished Apr 28 03:08:36 PM PDT 24
Peak memory 194132 kb
Host smart-686b14a3-545f-4b9c-aad8-76f4d5ddb132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669874325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1669874325
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.994286869
Short name T636
Test name
Test status
Simulation time 20106072 ps
CPU time 0.57 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:30 PM PDT 24
Peak memory 194140 kb
Host smart-b37ca418-6a86-4adb-893c-4f4d500ae122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994286869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.994286869
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1929005479
Short name T687
Test name
Test status
Simulation time 16859874 ps
CPU time 0.63 seconds
Started Apr 28 03:08:28 PM PDT 24
Finished Apr 28 03:08:30 PM PDT 24
Peak memory 194240 kb
Host smart-2ca2debf-089f-436a-a6d9-f486d93a7a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929005479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1929005479
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.670393434
Short name T705
Test name
Test status
Simulation time 15427597 ps
CPU time 0.6 seconds
Started Apr 28 03:08:27 PM PDT 24
Finished Apr 28 03:08:29 PM PDT 24
Peak memory 194208 kb
Host smart-7ce8fc1c-7d5b-4d85-bec0-bfb6d3dfc8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670393434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.670393434
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.294353285
Short name T621
Test name
Test status
Simulation time 31793918 ps
CPU time 0.56 seconds
Started Apr 28 03:08:30 PM PDT 24
Finished Apr 28 03:08:32 PM PDT 24
Peak memory 194040 kb
Host smart-0964e687-8034-407d-a2b7-16e11f90505e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294353285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.294353285
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2226013972
Short name T638
Test name
Test status
Simulation time 16891044 ps
CPU time 0.57 seconds
Started Apr 28 03:08:26 PM PDT 24
Finished Apr 28 03:08:27 PM PDT 24
Peak memory 194064 kb
Host smart-80c31e7f-64e2-4a30-b10d-11d6202dfa5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226013972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2226013972
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2294574254
Short name T647
Test name
Test status
Simulation time 10252236 ps
CPU time 0.58 seconds
Started Apr 28 03:08:29 PM PDT 24
Finished Apr 28 03:08:31 PM PDT 24
Peak memory 193984 kb
Host smart-d2057b8a-4b76-4be9-a36d-957c3e1798a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294574254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2294574254
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3209490786
Short name T93
Test name
Test status
Simulation time 607448893 ps
CPU time 5.94 seconds
Started Apr 28 03:07:41 PM PDT 24
Finished Apr 28 03:07:47 PM PDT 24
Peak memory 199264 kb
Host smart-703cd05e-2ed8-47bd-925c-d471631918cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209490786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3209490786
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2295741590
Short name T737
Test name
Test status
Simulation time 736006257 ps
CPU time 10.85 seconds
Started Apr 28 03:07:40 PM PDT 24
Finished Apr 28 03:07:51 PM PDT 24
Peak memory 199228 kb
Host smart-b32c9d2a-1919-4fdc-a1b4-012771a49642
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295741590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2295741590
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1916388055
Short name T98
Test name
Test status
Simulation time 23416817 ps
CPU time 0.75 seconds
Started Apr 28 03:07:40 PM PDT 24
Finished Apr 28 03:07:41 PM PDT 24
Peak memory 197420 kb
Host smart-f4290545-c170-46f6-8682-4a5e5d407d11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916388055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1916388055
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1488799352
Short name T679
Test name
Test status
Simulation time 66221223 ps
CPU time 2.08 seconds
Started Apr 28 03:07:50 PM PDT 24
Finished Apr 28 03:07:53 PM PDT 24
Peak memory 199372 kb
Host smart-395b7d76-d54b-4aed-b09d-2840a97c1166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488799352 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1488799352
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2335435143
Short name T65
Test name
Test status
Simulation time 54096936 ps
CPU time 0.8 seconds
Started Apr 28 03:07:41 PM PDT 24
Finished Apr 28 03:07:42 PM PDT 24
Peak memory 198228 kb
Host smart-f61a2d47-6a65-409f-b08e-d00245e432c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335435143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2335435143
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.640839561
Short name T663
Test name
Test status
Simulation time 47258031 ps
CPU time 0.57 seconds
Started Apr 28 03:07:41 PM PDT 24
Finished Apr 28 03:07:42 PM PDT 24
Peak memory 194060 kb
Host smart-64a4296f-8b8b-4203-86d4-95782c580192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640839561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.640839561
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1903810222
Short name T675
Test name
Test status
Simulation time 156246632 ps
CPU time 1.51 seconds
Started Apr 28 03:07:47 PM PDT 24
Finished Apr 28 03:07:49 PM PDT 24
Peak memory 198992 kb
Host smart-a4963e55-4c6b-45d4-b686-d2721f47c49e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903810222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1903810222
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4065173325
Short name T732
Test name
Test status
Simulation time 1195540956 ps
CPU time 2.9 seconds
Started Apr 28 03:07:40 PM PDT 24
Finished Apr 28 03:07:43 PM PDT 24
Peak memory 199256 kb
Host smart-7015f65d-6a66-4c52-ba0f-46efded4e698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065173325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4065173325
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3894039338
Short name T692
Test name
Test status
Simulation time 13406516 ps
CPU time 0.55 seconds
Started Apr 28 03:08:30 PM PDT 24
Finished Apr 28 03:08:32 PM PDT 24
Peak memory 194096 kb
Host smart-563d11ef-2188-4b0b-9c0f-f7d3d0d14084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894039338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3894039338
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1143909632
Short name T672
Test name
Test status
Simulation time 19021614 ps
CPU time 0.56 seconds
Started Apr 28 03:08:31 PM PDT 24
Finished Apr 28 03:08:32 PM PDT 24
Peak memory 194096 kb
Host smart-9dcbec52-c17f-4e23-868f-f53603c82f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143909632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1143909632
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.4006280685
Short name T716
Test name
Test status
Simulation time 25208342 ps
CPU time 0.61 seconds
Started Apr 28 03:08:27 PM PDT 24
Finished Apr 28 03:08:29 PM PDT 24
Peak memory 194168 kb
Host smart-3364092d-6c45-421a-a323-d15f4058b5e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006280685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.4006280685
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2181367527
Short name T633
Test name
Test status
Simulation time 40346441 ps
CPU time 0.55 seconds
Started Apr 28 03:08:30 PM PDT 24
Finished Apr 28 03:08:32 PM PDT 24
Peak memory 194156 kb
Host smart-8dbc1a52-3652-405b-8a7c-cdbba83f3be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181367527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2181367527
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4239788960
Short name T632
Test name
Test status
Simulation time 42489600 ps
CPU time 0.61 seconds
Started Apr 28 03:08:29 PM PDT 24
Finished Apr 28 03:08:31 PM PDT 24
Peak memory 194136 kb
Host smart-6b77dc49-bfb5-43ce-b204-81ad979fa052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239788960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4239788960
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1349743737
Short name T698
Test name
Test status
Simulation time 13244178 ps
CPU time 0.61 seconds
Started Apr 28 03:08:31 PM PDT 24
Finished Apr 28 03:08:32 PM PDT 24
Peak memory 194220 kb
Host smart-169c753a-c009-49f6-8fa9-b2071bc9b0e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349743737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1349743737
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1642271232
Short name T656
Test name
Test status
Simulation time 116412527 ps
CPU time 0.58 seconds
Started Apr 28 03:08:33 PM PDT 24
Finished Apr 28 03:08:34 PM PDT 24
Peak memory 194096 kb
Host smart-b0c6e4fb-4fc7-4123-a734-5351b7eab266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642271232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1642271232
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3115660252
Short name T620
Test name
Test status
Simulation time 41041439 ps
CPU time 0.58 seconds
Started Apr 28 03:08:38 PM PDT 24
Finished Apr 28 03:08:39 PM PDT 24
Peak memory 194024 kb
Host smart-6ec3bfdd-a12b-4293-9fda-b0b57f65646f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115660252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3115660252
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2129159831
Short name T611
Test name
Test status
Simulation time 32425685 ps
CPU time 0.57 seconds
Started Apr 28 03:08:34 PM PDT 24
Finished Apr 28 03:08:35 PM PDT 24
Peak memory 194036 kb
Host smart-fb92fff0-6fd8-4556-ba8a-538c3f0f3e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129159831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2129159831
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3961140932
Short name T696
Test name
Test status
Simulation time 31079162 ps
CPU time 0.58 seconds
Started Apr 28 03:08:35 PM PDT 24
Finished Apr 28 03:08:36 PM PDT 24
Peak memory 194208 kb
Host smart-910cc873-d6b3-4d00-8927-fd4688033340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961140932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3961140932
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2985237306
Short name T96
Test name
Test status
Simulation time 1857718130 ps
CPU time 8.69 seconds
Started Apr 28 03:07:46 PM PDT 24
Finished Apr 28 03:07:55 PM PDT 24
Peak memory 199188 kb
Host smart-9a142904-09f0-4b4f-9368-3ab025e635e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985237306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2985237306
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2382170873
Short name T669
Test name
Test status
Simulation time 369637287 ps
CPU time 5.45 seconds
Started Apr 28 03:07:50 PM PDT 24
Finished Apr 28 03:07:56 PM PDT 24
Peak memory 199280 kb
Host smart-a5d870da-97e5-4a6d-a26c-fbbd9438977f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382170873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2382170873
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1899030867
Short name T94
Test name
Test status
Simulation time 132451938 ps
CPU time 0.93 seconds
Started Apr 28 03:07:46 PM PDT 24
Finished Apr 28 03:07:48 PM PDT 24
Peak memory 198188 kb
Host smart-66ab4354-085a-47f8-b5a8-a86a93c2e964
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899030867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1899030867
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3101541781
Short name T694
Test name
Test status
Simulation time 378164624 ps
CPU time 2.55 seconds
Started Apr 28 03:07:48 PM PDT 24
Finished Apr 28 03:07:51 PM PDT 24
Peak memory 207568 kb
Host smart-f9736923-4d8c-479b-9316-3a71133f0b03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101541781 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3101541781
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4275138878
Short name T91
Test name
Test status
Simulation time 25875484 ps
CPU time 0.8 seconds
Started Apr 28 03:07:47 PM PDT 24
Finished Apr 28 03:07:48 PM PDT 24
Peak memory 198328 kb
Host smart-707c1bd4-46d7-4782-880e-8ddd80ab9f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275138878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.4275138878
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2764866263
Short name T731
Test name
Test status
Simulation time 33158734 ps
CPU time 0.6 seconds
Started Apr 28 03:07:45 PM PDT 24
Finished Apr 28 03:07:46 PM PDT 24
Peak memory 194240 kb
Host smart-22f48fd0-581d-4c55-a6d9-6be3336dfdd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764866263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2764866263
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.593051607
Short name T650
Test name
Test status
Simulation time 108048354 ps
CPU time 2.18 seconds
Started Apr 28 03:07:47 PM PDT 24
Finished Apr 28 03:07:49 PM PDT 24
Peak memory 199328 kb
Host smart-39bc2b7b-0b19-42da-bb0c-a035f425b015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593051607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.593051607
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3647807774
Short name T648
Test name
Test status
Simulation time 104962604 ps
CPU time 2.02 seconds
Started Apr 28 03:07:46 PM PDT 24
Finished Apr 28 03:07:48 PM PDT 24
Peak memory 199380 kb
Host smart-638c1b86-9dae-4e0f-a83d-504eda37af94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647807774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3647807774
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3053274858
Short name T606
Test name
Test status
Simulation time 54299617 ps
CPU time 0.6 seconds
Started Apr 28 03:08:34 PM PDT 24
Finished Apr 28 03:08:36 PM PDT 24
Peak memory 194016 kb
Host smart-c43eee6c-044e-430c-a342-7040ef7278eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053274858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3053274858
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1120503204
Short name T676
Test name
Test status
Simulation time 147391474 ps
CPU time 0.58 seconds
Started Apr 28 03:08:32 PM PDT 24
Finished Apr 28 03:08:33 PM PDT 24
Peak memory 194180 kb
Host smart-b9e67f0f-e363-4991-a0b1-51783f195d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120503204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1120503204
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2733604286
Short name T612
Test name
Test status
Simulation time 51494377 ps
CPU time 0.63 seconds
Started Apr 28 03:08:35 PM PDT 24
Finished Apr 28 03:08:36 PM PDT 24
Peak memory 194048 kb
Host smart-7baa8cbc-3ede-43be-94db-5c6d31a9064c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733604286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2733604286
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2426297594
Short name T658
Test name
Test status
Simulation time 12897583 ps
CPU time 0.57 seconds
Started Apr 28 03:08:35 PM PDT 24
Finished Apr 28 03:08:36 PM PDT 24
Peak memory 194128 kb
Host smart-9bdce32c-fa80-4790-bc1d-0781b58f50fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426297594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2426297594
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3446169752
Short name T727
Test name
Test status
Simulation time 33874139 ps
CPU time 0.59 seconds
Started Apr 28 03:08:34 PM PDT 24
Finished Apr 28 03:08:35 PM PDT 24
Peak memory 194132 kb
Host smart-89f58476-c5dd-4d80-ac8a-49753d7852c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446169752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3446169752
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2841698062
Short name T661
Test name
Test status
Simulation time 18134745 ps
CPU time 0.61 seconds
Started Apr 28 03:08:34 PM PDT 24
Finished Apr 28 03:08:35 PM PDT 24
Peak memory 194076 kb
Host smart-86bb2640-d71c-4f74-beb1-ce1faf7b1781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841698062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2841698062
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3288481727
Short name T608
Test name
Test status
Simulation time 22148726 ps
CPU time 0.68 seconds
Started Apr 28 03:08:33 PM PDT 24
Finished Apr 28 03:08:35 PM PDT 24
Peak memory 194144 kb
Host smart-c343444b-2df9-43af-a8cc-965f87dcaf25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288481727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3288481727
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.158927034
Short name T688
Test name
Test status
Simulation time 108050803 ps
CPU time 0.6 seconds
Started Apr 28 03:08:34 PM PDT 24
Finished Apr 28 03:08:35 PM PDT 24
Peak memory 194180 kb
Host smart-81d57008-9c6f-4544-8c5c-c24f12188560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158927034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.158927034
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1380210494
Short name T609
Test name
Test status
Simulation time 14398419 ps
CPU time 0.6 seconds
Started Apr 28 03:08:34 PM PDT 24
Finished Apr 28 03:08:35 PM PDT 24
Peak memory 194116 kb
Host smart-fa53e021-871b-446c-ae03-e5430a6487c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380210494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1380210494
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1288234187
Short name T652
Test name
Test status
Simulation time 13903492 ps
CPU time 0.57 seconds
Started Apr 28 03:08:36 PM PDT 24
Finished Apr 28 03:08:37 PM PDT 24
Peak memory 194188 kb
Host smart-0bf19154-0316-49b2-9d13-67136fb6b721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288234187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1288234187
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2225141032
Short name T718
Test name
Test status
Simulation time 312640355 ps
CPU time 1.68 seconds
Started Apr 28 03:07:51 PM PDT 24
Finished Apr 28 03:07:53 PM PDT 24
Peak memory 199252 kb
Host smart-50938347-65a0-4b2f-88bf-ebb206caec2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225141032 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2225141032
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.33042034
Short name T677
Test name
Test status
Simulation time 23385650 ps
CPU time 0.82 seconds
Started Apr 28 03:07:52 PM PDT 24
Finished Apr 28 03:07:53 PM PDT 24
Peak memory 199132 kb
Host smart-a949b7bf-92f5-49de-87c8-efa0bb497069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33042034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.33042034
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.308016192
Short name T629
Test name
Test status
Simulation time 12570759 ps
CPU time 0.6 seconds
Started Apr 28 03:07:55 PM PDT 24
Finished Apr 28 03:07:56 PM PDT 24
Peak memory 194064 kb
Host smart-3eee648c-3035-409a-871a-29db2842b03d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308016192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.308016192
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.321169774
Short name T630
Test name
Test status
Simulation time 33671926 ps
CPU time 1.66 seconds
Started Apr 28 03:07:52 PM PDT 24
Finished Apr 28 03:07:54 PM PDT 24
Peak memory 199060 kb
Host smart-5e92d6a2-97d9-4707-8b2c-ff64c6b5482f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321169774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.321169774
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.262745045
Short name T680
Test name
Test status
Simulation time 371419700 ps
CPU time 1.86 seconds
Started Apr 28 03:07:48 PM PDT 24
Finished Apr 28 03:07:50 PM PDT 24
Peak memory 199368 kb
Host smart-eeb9b89f-eaef-453f-9a05-230b1c619676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262745045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.262745045
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2590599682
Short name T106
Test name
Test status
Simulation time 173989362 ps
CPU time 1.68 seconds
Started Apr 28 03:07:50 PM PDT 24
Finished Apr 28 03:07:52 PM PDT 24
Peak memory 199348 kb
Host smart-7da62718-19da-4cf9-be2d-8891f56a1028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590599682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2590599682
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3539868638
Short name T740
Test name
Test status
Simulation time 194956979433 ps
CPU time 760.25 seconds
Started Apr 28 03:07:51 PM PDT 24
Finished Apr 28 03:20:32 PM PDT 24
Peak memory 223956 kb
Host smart-8ee6d251-d4a2-4bb7-be23-a28e13c7345c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539868638 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3539868638
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.75437111
Short name T691
Test name
Test status
Simulation time 56564591 ps
CPU time 0.8 seconds
Started Apr 28 03:07:52 PM PDT 24
Finished Apr 28 03:07:53 PM PDT 24
Peak memory 198280 kb
Host smart-00ed72f6-b834-478e-a430-017c73ef1caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75437111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.75437111
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2824376793
Short name T735
Test name
Test status
Simulation time 22548018 ps
CPU time 0.56 seconds
Started Apr 28 03:07:51 PM PDT 24
Finished Apr 28 03:07:53 PM PDT 24
Peak memory 194016 kb
Host smart-1030471d-e919-4e9d-ade6-fa7b7be3e0ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824376793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2824376793
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2158415556
Short name T715
Test name
Test status
Simulation time 516793727 ps
CPU time 2.31 seconds
Started Apr 28 03:07:53 PM PDT 24
Finished Apr 28 03:07:55 PM PDT 24
Peak memory 199124 kb
Host smart-eeef9c3f-4c26-4a8c-a686-a982f0d52d01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158415556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2158415556
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3282434376
Short name T723
Test name
Test status
Simulation time 272327327 ps
CPU time 2.61 seconds
Started Apr 28 03:07:51 PM PDT 24
Finished Apr 28 03:07:54 PM PDT 24
Peak memory 199380 kb
Host smart-4f472db8-a29a-4ad4-9abd-3398e913f477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282434376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3282434376
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2880472320
Short name T699
Test name
Test status
Simulation time 1277915282 ps
CPU time 2.8 seconds
Started Apr 28 03:07:52 PM PDT 24
Finished Apr 28 03:07:55 PM PDT 24
Peak memory 199272 kb
Host smart-3cdf85f6-cb0c-4955-9468-e6c29ad1f7dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880472320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2880472320
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2379975092
Short name T673
Test name
Test status
Simulation time 57995085 ps
CPU time 3.86 seconds
Started Apr 28 03:07:56 PM PDT 24
Finished Apr 28 03:08:00 PM PDT 24
Peak memory 214752 kb
Host smart-bca0563a-d4dc-4dec-b1dd-79392bcaef1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379975092 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2379975092
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2567912017
Short name T89
Test name
Test status
Simulation time 52445892 ps
CPU time 0.77 seconds
Started Apr 28 03:07:55 PM PDT 24
Finished Apr 28 03:07:56 PM PDT 24
Peak memory 198372 kb
Host smart-4041d5a6-8fa4-4a93-b3e6-53042211e62c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567912017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2567912017
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3830294544
Short name T607
Test name
Test status
Simulation time 13238929 ps
CPU time 0.57 seconds
Started Apr 28 03:07:55 PM PDT 24
Finished Apr 28 03:07:56 PM PDT 24
Peak memory 194052 kb
Host smart-df8bb689-46c3-4295-9ae9-c0a5593ba264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830294544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3830294544
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2858721559
Short name T720
Test name
Test status
Simulation time 43067176 ps
CPU time 1.15 seconds
Started Apr 28 03:07:56 PM PDT 24
Finished Apr 28 03:07:58 PM PDT 24
Peak memory 198860 kb
Host smart-38016ca0-ce37-41ec-b72c-783b6358cc6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858721559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2858721559
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3053276112
Short name T697
Test name
Test status
Simulation time 87231742 ps
CPU time 1.9 seconds
Started Apr 28 03:07:52 PM PDT 24
Finished Apr 28 03:07:55 PM PDT 24
Peak memory 199364 kb
Host smart-4fa6fae6-5de7-4323-971f-f3c93510ddd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053276112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3053276112
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2610675904
Short name T628
Test name
Test status
Simulation time 391478709 ps
CPU time 1.78 seconds
Started Apr 28 03:07:57 PM PDT 24
Finished Apr 28 03:08:00 PM PDT 24
Peak memory 199300 kb
Host smart-96cc83ff-6856-4cd2-8172-d8f6be7ac392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610675904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2610675904
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.430868850
Short name T637
Test name
Test status
Simulation time 144738093 ps
CPU time 1.25 seconds
Started Apr 28 03:08:00 PM PDT 24
Finished Apr 28 03:08:02 PM PDT 24
Peak memory 199240 kb
Host smart-25b3fa12-407a-44c0-b8da-b68d4ea34226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430868850 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.430868850
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4194141779
Short name T87
Test name
Test status
Simulation time 62566758 ps
CPU time 0.68 seconds
Started Apr 28 03:07:57 PM PDT 24
Finished Apr 28 03:07:58 PM PDT 24
Peak memory 197052 kb
Host smart-5be2073c-5ac9-44e2-8b3e-b6245cb9d5ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194141779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4194141779
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3678629710
Short name T617
Test name
Test status
Simulation time 39326287 ps
CPU time 0.57 seconds
Started Apr 28 03:07:56 PM PDT 24
Finished Apr 28 03:07:57 PM PDT 24
Peak memory 194032 kb
Host smart-1ea149bf-4c14-43a2-b1e5-d815b9a3f863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678629710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3678629710
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2213771724
Short name T704
Test name
Test status
Simulation time 34720507 ps
CPU time 1.56 seconds
Started Apr 28 03:08:01 PM PDT 24
Finished Apr 28 03:08:03 PM PDT 24
Peak memory 199260 kb
Host smart-4be670e8-815b-450a-8eaf-b427984357d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213771724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2213771724
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1715538280
Short name T670
Test name
Test status
Simulation time 24606295 ps
CPU time 1.31 seconds
Started Apr 28 03:07:55 PM PDT 24
Finished Apr 28 03:07:57 PM PDT 24
Peak memory 199404 kb
Host smart-51c76dca-18ae-48a3-bb01-1c3d45b8081d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715538280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1715538280
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3189058505
Short name T107
Test name
Test status
Simulation time 135366858 ps
CPU time 3.9 seconds
Started Apr 28 03:07:55 PM PDT 24
Finished Apr 28 03:07:59 PM PDT 24
Peak memory 199212 kb
Host smart-29635860-1faa-4af5-a695-12cc44acc08f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189058505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3189058505
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4262204301
Short name T618
Test name
Test status
Simulation time 386684859 ps
CPU time 2.77 seconds
Started Apr 28 03:08:02 PM PDT 24
Finished Apr 28 03:08:06 PM PDT 24
Peak memory 207560 kb
Host smart-b3170073-68fe-4aa1-92f1-374674cf3d1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262204301 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.4262204301
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3620035376
Short name T659
Test name
Test status
Simulation time 53129519 ps
CPU time 0.7 seconds
Started Apr 28 03:08:00 PM PDT 24
Finished Apr 28 03:08:01 PM PDT 24
Peak memory 197240 kb
Host smart-47ef9b29-4042-420c-9172-7d0d80d01650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620035376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3620035376
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2305812296
Short name T77
Test name
Test status
Simulation time 14897996 ps
CPU time 0.6 seconds
Started Apr 28 03:08:00 PM PDT 24
Finished Apr 28 03:08:02 PM PDT 24
Peak memory 194036 kb
Host smart-4bda05a7-903a-4f4f-b976-e47bb71460f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305812296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2305812296
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2269660408
Short name T642
Test name
Test status
Simulation time 138847463 ps
CPU time 1.65 seconds
Started Apr 28 03:08:01 PM PDT 24
Finished Apr 28 03:08:03 PM PDT 24
Peak memory 199208 kb
Host smart-bf46f7ee-33e8-45a1-b591-da1392f8fa42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269660408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2269660408
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1185491828
Short name T610
Test name
Test status
Simulation time 852344309 ps
CPU time 3.31 seconds
Started Apr 28 03:08:02 PM PDT 24
Finished Apr 28 03:08:06 PM PDT 24
Peak memory 199324 kb
Host smart-50526ed8-a63a-4b03-9b9e-d30ae132336c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185491828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1185491828
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2389030367
Short name T63
Test name
Test status
Simulation time 250993460 ps
CPU time 4 seconds
Started Apr 28 03:08:00 PM PDT 24
Finished Apr 28 03:08:05 PM PDT 24
Peak memory 199372 kb
Host smart-a4ef7575-f723-4068-bd8a-d40299cf5063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389030367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2389030367
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1178861746
Short name T425
Test name
Test status
Simulation time 13557629 ps
CPU time 0.59 seconds
Started Apr 28 03:19:18 PM PDT 24
Finished Apr 28 03:19:20 PM PDT 24
Peak memory 194288 kb
Host smart-97bf315b-21cf-4b35-a94a-1bc1bab17d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178861746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1178861746
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3728924044
Short name T242
Test name
Test status
Simulation time 1537650388 ps
CPU time 55.82 seconds
Started Apr 28 03:19:13 PM PDT 24
Finished Apr 28 03:20:10 PM PDT 24
Peak memory 212820 kb
Host smart-d99a29b3-4e79-46d1-81ac-e2ee0395ddca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728924044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3728924044
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.123223740
Short name T371
Test name
Test status
Simulation time 1869138870 ps
CPU time 40.16 seconds
Started Apr 28 03:19:14 PM PDT 24
Finished Apr 28 03:19:55 PM PDT 24
Peak memory 199576 kb
Host smart-48ac1b66-14c1-46db-b2e1-cefab9e63abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123223740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.123223740
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3932091484
Short name T336
Test name
Test status
Simulation time 280220319 ps
CPU time 14.16 seconds
Started Apr 28 03:19:15 PM PDT 24
Finished Apr 28 03:19:30 PM PDT 24
Peak memory 199696 kb
Host smart-b9d29759-0038-4f6a-a850-c6ad7118fa77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932091484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3932091484
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2725400293
Short name T484
Test name
Test status
Simulation time 1036041835 ps
CPU time 11.5 seconds
Started Apr 28 03:19:17 PM PDT 24
Finished Apr 28 03:19:29 PM PDT 24
Peak memory 199496 kb
Host smart-fc2fbd28-b2e0-45e9-9898-17ebd8b07a60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725400293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2725400293
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.128268583
Short name T444
Test name
Test status
Simulation time 10031430610 ps
CPU time 72.48 seconds
Started Apr 28 03:19:16 PM PDT 24
Finished Apr 28 03:20:29 PM PDT 24
Peak memory 199740 kb
Host smart-1f8c40e5-680b-43ec-839a-85d24e88ca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128268583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.128268583
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.261211484
Short name T111
Test name
Test status
Simulation time 515335574 ps
CPU time 2.11 seconds
Started Apr 28 03:19:15 PM PDT 24
Finished Apr 28 03:19:18 PM PDT 24
Peak memory 199688 kb
Host smart-05d0cc04-782f-4c55-b078-b92bdf7e8e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261211484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.261211484
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1424863062
Short name T51
Test name
Test status
Simulation time 223062791647 ps
CPU time 2317.92 seconds
Started Apr 28 03:19:15 PM PDT 24
Finished Apr 28 03:57:55 PM PDT 24
Peak memory 232464 kb
Host smart-69297792-58ba-479b-8c53-f8ddad719548
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424863062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1424863062
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1817672756
Short name T208
Test name
Test status
Simulation time 52929230 ps
CPU time 0.99 seconds
Started Apr 28 03:19:17 PM PDT 24
Finished Apr 28 03:19:19 PM PDT 24
Peak memory 199532 kb
Host smart-e1278c9d-cc36-48db-b676-6b8e2aae8340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817672756 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1817672756
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2274419221
Short name T342
Test name
Test status
Simulation time 66293501032 ps
CPU time 436.19 seconds
Started Apr 28 03:19:17 PM PDT 24
Finished Apr 28 03:26:34 PM PDT 24
Peak memory 199704 kb
Host smart-f7af4c1e-fdfd-41a3-8342-c4b75f4779a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274419221 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2274419221
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2945565736
Short name T539
Test name
Test status
Simulation time 10803634848 ps
CPU time 56.31 seconds
Started Apr 28 03:19:17 PM PDT 24
Finished Apr 28 03:20:14 PM PDT 24
Peak memory 199748 kb
Host smart-c585b614-e07d-4e59-8151-0c0d4f88e2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945565736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2945565736
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2950964936
Short name T587
Test name
Test status
Simulation time 22948292 ps
CPU time 0.59 seconds
Started Apr 28 03:19:18 PM PDT 24
Finished Apr 28 03:19:19 PM PDT 24
Peak memory 195324 kb
Host smart-054c7fbe-49a4-49e6-ba52-a31ed44dfbb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950964936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2950964936
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.80622672
Short name T492
Test name
Test status
Simulation time 2342375877 ps
CPU time 42.06 seconds
Started Apr 28 03:19:17 PM PDT 24
Finished Apr 28 03:20:00 PM PDT 24
Peak memory 219080 kb
Host smart-417e8090-2c19-4654-bbca-8a5750aeee59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80622672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.80622672
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.4152924001
Short name T137
Test name
Test status
Simulation time 306772243 ps
CPU time 9.07 seconds
Started Apr 28 03:19:17 PM PDT 24
Finished Apr 28 03:19:26 PM PDT 24
Peak memory 199756 kb
Host smart-fafaeedb-f9a0-47b3-8c2f-37ba859c3aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152924001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.4152924001
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3081952517
Short name T327
Test name
Test status
Simulation time 1753777362 ps
CPU time 82.46 seconds
Started Apr 28 03:19:18 PM PDT 24
Finished Apr 28 03:20:41 PM PDT 24
Peak memory 199600 kb
Host smart-a6fe5896-711e-442a-bad0-6aa6ddc24282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081952517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3081952517
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3904749605
Short name T522
Test name
Test status
Simulation time 81477587131 ps
CPU time 134.02 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:21:34 PM PDT 24
Peak memory 199740 kb
Host smart-180c227c-3871-4d2f-9677-1ce7513d575d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904749605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3904749605
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1004457035
Short name T533
Test name
Test status
Simulation time 13125927877 ps
CPU time 94.49 seconds
Started Apr 28 03:19:16 PM PDT 24
Finished Apr 28 03:20:51 PM PDT 24
Peak memory 199740 kb
Host smart-a75cf2a8-a437-4327-ab4b-42b3de122c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004457035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1004457035
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.863655957
Short name T32
Test name
Test status
Simulation time 580919154 ps
CPU time 0.87 seconds
Started Apr 28 03:19:18 PM PDT 24
Finished Apr 28 03:19:20 PM PDT 24
Peak memory 218052 kb
Host smart-e6eaba07-8ef5-4ca1-a5ac-794a7cc06b6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863655957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.863655957
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1877609568
Short name T150
Test name
Test status
Simulation time 52378747 ps
CPU time 1.96 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:19:22 PM PDT 24
Peak memory 199636 kb
Host smart-5f309d64-012e-4968-b46e-7b53984d1b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877609568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1877609568
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3743644038
Short name T570
Test name
Test status
Simulation time 1001806345 ps
CPU time 37.98 seconds
Started Apr 28 03:19:16 PM PDT 24
Finished Apr 28 03:19:55 PM PDT 24
Peak memory 199620 kb
Host smart-c6a7b858-4a04-4ae1-800b-6118dd252f6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743644038 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3743644038
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2495883201
Short name T344
Test name
Test status
Simulation time 91566585 ps
CPU time 0.99 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:19:21 PM PDT 24
Peak memory 198132 kb
Host smart-a0b9cea3-3b60-44ef-bbe5-823882ec7912
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495883201 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2495883201
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.4230806635
Short name T505
Test name
Test status
Simulation time 155828456457 ps
CPU time 519.82 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:28:00 PM PDT 24
Peak memory 199664 kb
Host smart-929814b2-7aaf-4055-b1f9-6e41a90c22b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230806635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.4230806635
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1447909865
Short name T320
Test name
Test status
Simulation time 1030834889 ps
CPU time 29.23 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:19:49 PM PDT 24
Peak memory 199656 kb
Host smart-03c6a4f1-ea20-4cdb-8abb-d58b293e5125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447909865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1447909865
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2258368360
Short name T353
Test name
Test status
Simulation time 14222230 ps
CPU time 0.58 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:19:44 PM PDT 24
Peak memory 194260 kb
Host smart-1c1b651c-8f68-4c7f-84c7-345f3feed628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258368360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2258368360
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.195372397
Short name T476
Test name
Test status
Simulation time 1399810796 ps
CPU time 52.11 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:20:29 PM PDT 24
Peak memory 240516 kb
Host smart-b4d2495c-df8b-4106-b2d0-eeaa86b6efd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195372397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.195372397
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2686292415
Short name T157
Test name
Test status
Simulation time 1609828644 ps
CPU time 12.38 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:19:49 PM PDT 24
Peak memory 199632 kb
Host smart-b911fd48-d569-40e2-8a95-3f4b86aec7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686292415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2686292415
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4151137922
Short name T416
Test name
Test status
Simulation time 3675030048 ps
CPU time 144.39 seconds
Started Apr 28 03:19:38 PM PDT 24
Finished Apr 28 03:22:04 PM PDT 24
Peak memory 199748 kb
Host smart-89af80b9-1441-4ecd-bd80-d43f8be61f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151137922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4151137922
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2347210552
Short name T400
Test name
Test status
Simulation time 11671831193 ps
CPU time 224.63 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:23:21 PM PDT 24
Peak memory 199716 kb
Host smart-21f45fe0-dd27-4a13-85ca-35b379d91cdc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347210552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2347210552
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3265691692
Short name T180
Test name
Test status
Simulation time 2134496785 ps
CPU time 69.48 seconds
Started Apr 28 03:19:38 PM PDT 24
Finished Apr 28 03:20:49 PM PDT 24
Peak memory 199576 kb
Host smart-a8a1f082-cad1-4e23-9ac8-49d89bd1c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265691692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3265691692
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1613869061
Short name T29
Test name
Test status
Simulation time 627387722 ps
CPU time 6.97 seconds
Started Apr 28 03:19:37 PM PDT 24
Finished Apr 28 03:19:44 PM PDT 24
Peak memory 199576 kb
Host smart-f51bf4b1-244f-464b-91c0-00cb7f4410ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613869061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1613869061
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.755965209
Short name T28
Test name
Test status
Simulation time 429180674441 ps
CPU time 1409.53 seconds
Started Apr 28 03:19:38 PM PDT 24
Finished Apr 28 03:43:09 PM PDT 24
Peak memory 199720 kb
Host smart-47f8e4b5-be98-45b3-acc0-72b41e0ca477
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755965209 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.755965209
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2239871351
Short name T450
Test name
Test status
Simulation time 32659794 ps
CPU time 1.22 seconds
Started Apr 28 03:19:38 PM PDT 24
Finished Apr 28 03:19:40 PM PDT 24
Peak memory 199672 kb
Host smart-81ee99f5-989f-4ec7-aa2a-3e8a2bf7b4a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239871351 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2239871351
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1895847287
Short name T588
Test name
Test status
Simulation time 42920379872 ps
CPU time 507.14 seconds
Started Apr 28 03:19:37 PM PDT 24
Finished Apr 28 03:28:05 PM PDT 24
Peak memory 199728 kb
Host smart-6f9975e8-2199-4ab5-9044-0b8fb2fd01e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895847287 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1895847287
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.4291343769
Short name T462
Test name
Test status
Simulation time 957456052 ps
CPU time 52.36 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:20:30 PM PDT 24
Peak memory 199604 kb
Host smart-e3f03264-742a-46f0-8833-e5e7dde3c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291343769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.4291343769
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.855868005
Short name T12
Test name
Test status
Simulation time 221438430371 ps
CPU time 3156.7 seconds
Started Apr 28 03:22:26 PM PDT 24
Finished Apr 28 04:15:04 PM PDT 24
Peak memory 243560 kb
Host smart-f156d44b-f9a5-48a7-b80c-9a8083c66b24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855868005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.855868005
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1485161589
Short name T546
Test name
Test status
Simulation time 15527908 ps
CPU time 0.59 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:19:44 PM PDT 24
Peak memory 195400 kb
Host smart-3a53a757-e4df-472e-8042-dac5d70cdc3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485161589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1485161589
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1763285517
Short name T397
Test name
Test status
Simulation time 1067409488 ps
CPU time 38.81 seconds
Started Apr 28 03:19:43 PM PDT 24
Finished Apr 28 03:20:23 PM PDT 24
Peak memory 218816 kb
Host smart-8df296e7-c33e-4362-ab4f-1238ab3a086a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763285517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1763285517
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.343274154
Short name T458
Test name
Test status
Simulation time 2511094950 ps
CPU time 35.79 seconds
Started Apr 28 03:19:44 PM PDT 24
Finished Apr 28 03:20:21 PM PDT 24
Peak memory 199692 kb
Host smart-b9fc43a3-341d-4968-94b3-c6c145fe6ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343274154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.343274154
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.762843988
Short name T160
Test name
Test status
Simulation time 1685628182 ps
CPU time 95.92 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:21:19 PM PDT 24
Peak memory 199616 kb
Host smart-28772ab8-f806-4ee5-9089-4e728cabe96c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762843988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.762843988
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2399197407
Short name T140
Test name
Test status
Simulation time 29452977511 ps
CPU time 139.66 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:22:03 PM PDT 24
Peak memory 199724 kb
Host smart-d3e722d3-3cf8-4ee6-b4f7-2d52733da723
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399197407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2399197407
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2508488855
Short name T186
Test name
Test status
Simulation time 164067367 ps
CPU time 9.26 seconds
Started Apr 28 03:19:43 PM PDT 24
Finished Apr 28 03:19:54 PM PDT 24
Peak memory 199648 kb
Host smart-42c7427c-7358-4400-8593-b502c98cfbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508488855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2508488855
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1220170814
Short name T592
Test name
Test status
Simulation time 1546761144 ps
CPU time 6.06 seconds
Started Apr 28 03:19:39 PM PDT 24
Finished Apr 28 03:19:46 PM PDT 24
Peak memory 199552 kb
Host smart-5ef57ccc-5647-47d6-b74b-ad51e30c2c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220170814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1220170814
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2433330811
Short name T431
Test name
Test status
Simulation time 273295519585 ps
CPU time 1345.11 seconds
Started Apr 28 03:19:44 PM PDT 24
Finished Apr 28 03:42:11 PM PDT 24
Peak memory 224316 kb
Host smart-fe65dea1-e4d0-43d5-8b20-7ed85129b30f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433330811 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2433330811
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.891737002
Short name T58
Test name
Test status
Simulation time 122402407 ps
CPU time 1.23 seconds
Started Apr 28 03:19:44 PM PDT 24
Finished Apr 28 03:19:46 PM PDT 24
Peak memory 199664 kb
Host smart-efe2b681-9ae6-4d4e-bc2c-4992a4c9979a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891737002 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.891737002
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1376691906
Short name T163
Test name
Test status
Simulation time 47265142620 ps
CPU time 444.61 seconds
Started Apr 28 03:19:43 PM PDT 24
Finished Apr 28 03:27:09 PM PDT 24
Peak memory 199640 kb
Host smart-ee0f2c44-91d6-489c-95c0-77c42064604b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376691906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1376691906
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1856262292
Short name T253
Test name
Test status
Simulation time 8071925617 ps
CPU time 24.12 seconds
Started Apr 28 03:19:45 PM PDT 24
Finished Apr 28 03:20:10 PM PDT 24
Peak memory 199688 kb
Host smart-f6503358-68f7-49e8-9f11-05bcdc2d371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856262292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1856262292
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.3262296687
Short name T71
Test name
Test status
Simulation time 40937385729 ps
CPU time 2163.21 seconds
Started Apr 28 03:22:30 PM PDT 24
Finished Apr 28 03:58:35 PM PDT 24
Peak memory 229468 kb
Host smart-0dcbf786-f26a-4075-9df0-6ebb18d42f28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262296687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.3262296687
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2104441763
Short name T586
Test name
Test status
Simulation time 127458770 ps
CPU time 0.6 seconds
Started Apr 28 03:19:44 PM PDT 24
Finished Apr 28 03:19:45 PM PDT 24
Peak memory 195336 kb
Host smart-d0d252b6-815a-4dab-a666-8b89c7fe4567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104441763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2104441763
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1426998136
Short name T310
Test name
Test status
Simulation time 5923719432 ps
CPU time 61.58 seconds
Started Apr 28 03:19:43 PM PDT 24
Finished Apr 28 03:20:46 PM PDT 24
Peak memory 227540 kb
Host smart-6e037d03-5315-4014-80c5-92893d750ec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426998136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1426998136
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3525034990
Short name T214
Test name
Test status
Simulation time 890261160 ps
CPU time 5.05 seconds
Started Apr 28 03:19:45 PM PDT 24
Finished Apr 28 03:19:52 PM PDT 24
Peak memory 199640 kb
Host smart-21bc7b8c-1e90-4864-886e-8fb65c6cef97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525034990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3525034990
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.499480982
Short name T79
Test name
Test status
Simulation time 501690530 ps
CPU time 30.69 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:20:14 PM PDT 24
Peak memory 199660 kb
Host smart-977c398e-1aa2-4be3-973d-1b2609d8fa00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499480982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.499480982
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1470190552
Short name T325
Test name
Test status
Simulation time 3750780964 ps
CPU time 47.67 seconds
Started Apr 28 03:19:44 PM PDT 24
Finished Apr 28 03:20:33 PM PDT 24
Peak memory 199708 kb
Host smart-b0e46337-7333-4dc5-b953-39812a1d15a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470190552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1470190552
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1854910286
Short name T308
Test name
Test status
Simulation time 13282863692 ps
CPU time 28.2 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:20:12 PM PDT 24
Peak memory 199752 kb
Host smart-cf280c33-8140-4b9e-b3f4-944ecb1a2d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854910286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1854910286
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3013323327
Short name T239
Test name
Test status
Simulation time 104821018 ps
CPU time 3.25 seconds
Started Apr 28 03:19:44 PM PDT 24
Finished Apr 28 03:19:49 PM PDT 24
Peak memory 199648 kb
Host smart-2d3f4f76-23c2-474f-a385-a2ba79cfb3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013323327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3013323327
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3442909064
Short name T73
Test name
Test status
Simulation time 106444440513 ps
CPU time 1365.36 seconds
Started Apr 28 03:19:44 PM PDT 24
Finished Apr 28 03:42:31 PM PDT 24
Peak memory 199684 kb
Host smart-acf237d6-0493-4ecd-b3fe-7abe8ffd1e25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442909064 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3442909064
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2984287013
Short name T85
Test name
Test status
Simulation time 24474276695 ps
CPU time 1024.08 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:36:46 PM PDT 24
Peak memory 240596 kb
Host smart-cd8be7b9-0b24-4cd7-aabd-abaef2681e9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984287013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.2984287013
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.422102852
Short name T600
Test name
Test status
Simulation time 58351626 ps
CPU time 1.28 seconds
Started Apr 28 03:19:43 PM PDT 24
Finished Apr 28 03:19:45 PM PDT 24
Peak memory 199576 kb
Host smart-597d5ed5-0404-4ab3-bc07-7a8ffb01bdbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422102852 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.422102852
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.318092871
Short name T152
Test name
Test status
Simulation time 7636538509 ps
CPU time 413.83 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:26:38 PM PDT 24
Peak memory 199644 kb
Host smart-3736e999-a5dd-4c7d-8d51-418e7664d536
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318092871 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.318092871
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3657951925
Short name T596
Test name
Test status
Simulation time 4216292922 ps
CPU time 98.64 seconds
Started Apr 28 03:19:43 PM PDT 24
Finished Apr 28 03:21:23 PM PDT 24
Peak memory 199748 kb
Host smart-4fd79c52-bea8-473f-b7a3-117bf65381b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657951925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3657951925
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2635550376
Short name T237
Test name
Test status
Simulation time 16419106 ps
CPU time 0.58 seconds
Started Apr 28 03:19:46 PM PDT 24
Finished Apr 28 03:19:48 PM PDT 24
Peak memory 195372 kb
Host smart-0f839496-64d9-4957-be77-d7db781ba050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635550376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2635550376
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1193301340
Short name T524
Test name
Test status
Simulation time 2859625035 ps
CPU time 27.14 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:20:15 PM PDT 24
Peak memory 215336 kb
Host smart-35471db3-2ee6-403a-8493-0baa91aa18cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193301340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1193301340
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2837296694
Short name T392
Test name
Test status
Simulation time 6166472766 ps
CPU time 80.44 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:21:08 PM PDT 24
Peak memory 199732 kb
Host smart-a1ca6a86-d2a2-48ae-bd6c-5acf710ef929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837296694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2837296694
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.708331266
Short name T475
Test name
Test status
Simulation time 1039156013 ps
CPU time 41.87 seconds
Started Apr 28 03:19:46 PM PDT 24
Finished Apr 28 03:20:29 PM PDT 24
Peak memory 199608 kb
Host smart-01edfd6f-f48b-4a2c-8701-db01384fccf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=708331266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.708331266
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.257132677
Short name T315
Test name
Test status
Simulation time 43521181601 ps
CPU time 201.39 seconds
Started Apr 28 03:19:49 PM PDT 24
Finished Apr 28 03:23:11 PM PDT 24
Peak memory 199696 kb
Host smart-8467eb6a-7be7-444f-8005-03cd517b99e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257132677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.257132677
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.998449731
Short name T264
Test name
Test status
Simulation time 361429128 ps
CPU time 22.05 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:20:06 PM PDT 24
Peak memory 199628 kb
Host smart-c5828153-b768-4232-b575-97dabd815421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998449731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.998449731
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1662222448
Short name T538
Test name
Test status
Simulation time 751948374 ps
CPU time 1.6 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:19:44 PM PDT 24
Peak memory 199632 kb
Host smart-a856372c-4f76-4f2c-b6c9-37786648e84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662222448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1662222448
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.431360442
Short name T268
Test name
Test status
Simulation time 43556932010 ps
CPU time 791.42 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:33:00 PM PDT 24
Peak memory 232460 kb
Host smart-868b2844-25d2-48a7-a8da-01e7555d679f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431360442 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.431360442
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.270281888
Short name T373
Test name
Test status
Simulation time 97336170 ps
CPU time 0.91 seconds
Started Apr 28 03:19:49 PM PDT 24
Finished Apr 28 03:19:51 PM PDT 24
Peak memory 198496 kb
Host smart-9e4e7795-eb0b-4f04-aced-80c1e1a11762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270281888 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.270281888
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.457492605
Short name T244
Test name
Test status
Simulation time 201286908624 ps
CPU time 480.17 seconds
Started Apr 28 03:19:45 PM PDT 24
Finished Apr 28 03:27:46 PM PDT 24
Peak memory 199676 kb
Host smart-c21924ff-02de-4168-b56b-c8bc21b3c5db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457492605 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.457492605
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3301428793
Short name T133
Test name
Test status
Simulation time 1052247698 ps
CPU time 43.09 seconds
Started Apr 28 03:19:49 PM PDT 24
Finished Apr 28 03:20:33 PM PDT 24
Peak memory 199636 kb
Host smart-ada4c2fe-6451-429d-9a43-aecabaaed55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301428793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3301428793
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.716045373
Short name T457
Test name
Test status
Simulation time 24081944 ps
CPU time 0.59 seconds
Started Apr 28 03:19:49 PM PDT 24
Finished Apr 28 03:19:50 PM PDT 24
Peak memory 194288 kb
Host smart-c1f05180-a76d-48aa-97df-5696d714f516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716045373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.716045373
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.722675477
Short name T17
Test name
Test status
Simulation time 8455587617 ps
CPU time 54.97 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:20:49 PM PDT 24
Peak memory 207892 kb
Host smart-8e0997b5-c01f-4bb1-a018-989dd0cf3088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722675477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.722675477
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2032041139
Short name T531
Test name
Test status
Simulation time 1042546314 ps
CPU time 49.96 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:20:39 PM PDT 24
Peak memory 199668 kb
Host smart-21396843-eb0e-4163-a2c5-230bc927efb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032041139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2032041139
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2853115385
Short name T267
Test name
Test status
Simulation time 554836049 ps
CPU time 16.62 seconds
Started Apr 28 03:19:48 PM PDT 24
Finished Apr 28 03:20:06 PM PDT 24
Peak memory 199620 kb
Host smart-0a467209-806e-4a15-91a3-f86a7467bc12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853115385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2853115385
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3091781285
Short name T574
Test name
Test status
Simulation time 2963643797 ps
CPU time 39.51 seconds
Started Apr 28 03:19:49 PM PDT 24
Finished Apr 28 03:20:29 PM PDT 24
Peak memory 199560 kb
Host smart-a6abb697-7d24-4793-8c5f-324ceb7be2b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091781285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3091781285
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2715874066
Short name T234
Test name
Test status
Simulation time 3767433967 ps
CPU time 7.14 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:19:55 PM PDT 24
Peak memory 199664 kb
Host smart-9cfcef54-1a85-4c89-b087-e871725ad397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715874066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2715874066
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3741286347
Short name T387
Test name
Test status
Simulation time 708094936 ps
CPU time 5.67 seconds
Started Apr 28 03:19:46 PM PDT 24
Finished Apr 28 03:19:53 PM PDT 24
Peak memory 199648 kb
Host smart-7146cca3-b6c9-456c-a8b1-27ff63b0d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741286347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3741286347
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1385936058
Short name T47
Test name
Test status
Simulation time 80610805840 ps
CPU time 810.65 seconds
Started Apr 28 03:19:45 PM PDT 24
Finished Apr 28 03:33:17 PM PDT 24
Peak memory 219880 kb
Host smart-aef85ab7-e76d-4f5f-b834-4b648eebf6a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385936058 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1385936058
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1144284229
Short name T198
Test name
Test status
Simulation time 70335174 ps
CPU time 1.2 seconds
Started Apr 28 03:19:49 PM PDT 24
Finished Apr 28 03:19:51 PM PDT 24
Peak memory 199560 kb
Host smart-5aa109de-41df-4744-8760-d6e877ff3316
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144284229 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1144284229
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2169650706
Short name T448
Test name
Test status
Simulation time 186801819651 ps
CPU time 544.5 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:28:52 PM PDT 24
Peak memory 199676 kb
Host smart-8db8fe85-c347-45c1-bdae-b55a986691a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169650706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2169650706
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3897142380
Short name T292
Test name
Test status
Simulation time 5644300029 ps
CPU time 82.19 seconds
Started Apr 28 03:19:54 PM PDT 24
Finished Apr 28 03:21:17 PM PDT 24
Peak memory 199656 kb
Host smart-04c7cfba-9977-4e23-9800-09d3093d783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897142380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3897142380
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3694774674
Short name T249
Test name
Test status
Simulation time 1424333768 ps
CPU time 18.89 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:20:07 PM PDT 24
Peak memory 215656 kb
Host smart-b0b0c325-15e9-45d2-a748-67868a5412bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694774674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3694774674
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2855218311
Short name T395
Test name
Test status
Simulation time 2684873091 ps
CPU time 66.51 seconds
Started Apr 28 03:19:48 PM PDT 24
Finished Apr 28 03:20:56 PM PDT 24
Peak memory 199688 kb
Host smart-69de3a37-e9da-4a6e-a0e4-04835323960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855218311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2855218311
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3984609662
Short name T372
Test name
Test status
Simulation time 1516441119 ps
CPU time 90.64 seconds
Started Apr 28 03:19:47 PM PDT 24
Finished Apr 28 03:21:19 PM PDT 24
Peak memory 199716 kb
Host smart-c0d7bd7c-af40-4383-9025-c03ac2fa3296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984609662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3984609662
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1354149707
Short name T241
Test name
Test status
Simulation time 51059343366 ps
CPU time 158.42 seconds
Started Apr 28 03:19:48 PM PDT 24
Finished Apr 28 03:22:27 PM PDT 24
Peak memory 199780 kb
Host smart-3605813f-dc52-441e-a574-52de0629531d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354149707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1354149707
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3286509361
Short name T134
Test name
Test status
Simulation time 976112272 ps
CPU time 19.72 seconds
Started Apr 28 03:19:48 PM PDT 24
Finished Apr 28 03:20:09 PM PDT 24
Peak memory 199648 kb
Host smart-7a3642d1-8325-46f1-a4f3-f5e196ea3360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286509361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3286509361
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4017952634
Short name T232
Test name
Test status
Simulation time 809031006 ps
CPU time 4.97 seconds
Started Apr 28 03:19:46 PM PDT 24
Finished Apr 28 03:19:52 PM PDT 24
Peak memory 199628 kb
Host smart-5c8802f0-7e7e-4906-9416-7453fabce682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017952634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4017952634
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2254019594
Short name T597
Test name
Test status
Simulation time 23880673149 ps
CPU time 344.25 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:25:38 PM PDT 24
Peak memory 199716 kb
Host smart-5575860d-69b5-4652-a068-37a064093f6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254019594 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2254019594
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1836586429
Short name T465
Test name
Test status
Simulation time 96054739 ps
CPU time 1.13 seconds
Started Apr 28 03:19:48 PM PDT 24
Finished Apr 28 03:19:50 PM PDT 24
Peak memory 199244 kb
Host smart-d658e20a-8961-4f1f-a999-216c2b12c998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836586429 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1836586429
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.811361772
Short name T153
Test name
Test status
Simulation time 34479809540 ps
CPU time 510.73 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:28:25 PM PDT 24
Peak memory 199620 kb
Host smart-50238c36-4381-4bf4-a890-3ccf9ce76f41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811361772 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.811361772
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1875357323
Short name T519
Test name
Test status
Simulation time 13253609018 ps
CPU time 71.93 seconds
Started Apr 28 03:19:46 PM PDT 24
Finished Apr 28 03:20:59 PM PDT 24
Peak memory 199748 kb
Host smart-344136d8-95d9-4ac3-a70c-6787c32c282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875357323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1875357323
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.3511349741
Short name T366
Test name
Test status
Simulation time 40520496386 ps
CPU time 409.28 seconds
Started Apr 28 03:22:46 PM PDT 24
Finished Apr 28 03:29:36 PM PDT 24
Peak memory 247328 kb
Host smart-03b563f5-658d-49e3-b4a2-4ad0cf9e9946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511349741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.3511349741
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3959744760
Short name T477
Test name
Test status
Simulation time 15125627 ps
CPU time 0.61 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:19:54 PM PDT 24
Peak memory 195356 kb
Host smart-2801f6e0-ba44-4bd9-9940-0ea5c57f5026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959744760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3959744760
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1824169339
Short name T155
Test name
Test status
Simulation time 2729013801 ps
CPU time 50.48 seconds
Started Apr 28 03:19:51 PM PDT 24
Finished Apr 28 03:20:43 PM PDT 24
Peak memory 207880 kb
Host smart-59c5107a-621b-42db-a92d-e9b5344ae36c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824169339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1824169339
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.508826684
Short name T466
Test name
Test status
Simulation time 4817145784 ps
CPU time 21.88 seconds
Started Apr 28 03:19:52 PM PDT 24
Finished Apr 28 03:20:14 PM PDT 24
Peak memory 199740 kb
Host smart-81b3781e-dd2b-432b-9bad-3685fc8c7899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508826684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.508826684
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.760346820
Short name T136
Test name
Test status
Simulation time 1761421549 ps
CPU time 59.74 seconds
Started Apr 28 03:19:51 PM PDT 24
Finished Apr 28 03:20:51 PM PDT 24
Peak memory 199640 kb
Host smart-91646aa5-f169-4998-8321-f2b0b6ec5a2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760346820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.760346820
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.36303144
Short name T604
Test name
Test status
Simulation time 4546271045 ps
CPU time 61.58 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:20:55 PM PDT 24
Peak memory 199716 kb
Host smart-ad7c9860-68a8-41fd-b03b-9570db32c838
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.36303144
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3237867702
Short name T57
Test name
Test status
Simulation time 5601272634 ps
CPU time 52.13 seconds
Started Apr 28 03:19:55 PM PDT 24
Finished Apr 28 03:20:48 PM PDT 24
Peak memory 199716 kb
Host smart-db3634c0-e766-4a90-ae41-2faebb06cf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237867702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3237867702
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4217911716
Short name T283
Test name
Test status
Simulation time 2612605824 ps
CPU time 6.85 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:20:01 PM PDT 24
Peak memory 199720 kb
Host smart-ccc58a64-e154-48a0-9a8f-2489663b4feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217911716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4217911716
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.769866888
Short name T177
Test name
Test status
Simulation time 3536805914 ps
CPU time 163.24 seconds
Started Apr 28 03:19:51 PM PDT 24
Finished Apr 28 03:22:35 PM PDT 24
Peak memory 224272 kb
Host smart-72d70c77-6d29-483c-91e8-f18fe2902b24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769866888 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.769866888
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.15747168
Short name T195
Test name
Test status
Simulation time 32617306 ps
CPU time 0.97 seconds
Started Apr 28 03:19:52 PM PDT 24
Finished Apr 28 03:19:54 PM PDT 24
Peak memory 198088 kb
Host smart-8692ee60-fe62-42a8-a76e-c404930aeef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15747168 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.hmac_test_hmac_vectors.15747168
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3898430799
Short name T309
Test name
Test status
Simulation time 74446053291 ps
CPU time 487.54 seconds
Started Apr 28 03:19:54 PM PDT 24
Finished Apr 28 03:28:03 PM PDT 24
Peak memory 199604 kb
Host smart-856ab37e-f076-45d3-adb3-a2291020670c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898430799 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.3898430799
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.636631881
Short name T278
Test name
Test status
Simulation time 20700230106 ps
CPU time 77.18 seconds
Started Apr 28 03:19:57 PM PDT 24
Finished Apr 28 03:21:15 PM PDT 24
Peak memory 199708 kb
Host smart-b49ddf95-a591-4ff8-88a7-fc630dba6189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636631881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.636631881
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.624596368
Short name T536
Test name
Test status
Simulation time 82669979142 ps
CPU time 976.93 seconds
Started Apr 28 03:22:48 PM PDT 24
Finished Apr 28 03:39:06 PM PDT 24
Peak memory 227000 kb
Host smart-c507439f-2917-44a5-8e83-6331647e4f26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624596368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.624596368
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3450902531
Short name T122
Test name
Test status
Simulation time 18852086 ps
CPU time 0.54 seconds
Started Apr 28 03:19:56 PM PDT 24
Finished Apr 28 03:19:58 PM PDT 24
Peak memory 194288 kb
Host smart-442be087-7c3b-4bb9-a87c-87dcc776d9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450902531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3450902531
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3639589675
Short name T376
Test name
Test status
Simulation time 1892883523 ps
CPU time 70.08 seconds
Started Apr 28 03:19:51 PM PDT 24
Finished Apr 28 03:21:02 PM PDT 24
Peak memory 236836 kb
Host smart-667cbb3a-4e30-4507-953a-24faa276ae8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639589675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3639589675
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.989518870
Short name T500
Test name
Test status
Simulation time 2065239783 ps
CPU time 46.53 seconds
Started Apr 28 03:19:51 PM PDT 24
Finished Apr 28 03:20:38 PM PDT 24
Peak memory 199664 kb
Host smart-e275e5ea-7b09-4560-b850-58637fd42cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989518870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.989518870
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1320575313
Short name T496
Test name
Test status
Simulation time 707377628 ps
CPU time 40.7 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:20:34 PM PDT 24
Peak memory 199492 kb
Host smart-ae91393b-e6ba-40e7-a9e3-735481390b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320575313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1320575313
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.429439888
Short name T306
Test name
Test status
Simulation time 971943036 ps
CPU time 27.98 seconds
Started Apr 28 03:19:51 PM PDT 24
Finished Apr 28 03:20:20 PM PDT 24
Peak memory 199508 kb
Host smart-907ab3d3-05fd-4a97-b5f7-d72bd6a72e04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429439888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.429439888
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2967552913
Short name T454
Test name
Test status
Simulation time 6137709555 ps
CPU time 116.87 seconds
Started Apr 28 03:19:52 PM PDT 24
Finished Apr 28 03:21:50 PM PDT 24
Peak memory 199728 kb
Host smart-c0fd284b-4ea1-445c-be9c-fdbadf8a2e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967552913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2967552913
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2412474086
Short name T194
Test name
Test status
Simulation time 793505604 ps
CPU time 3.57 seconds
Started Apr 28 03:19:53 PM PDT 24
Finished Apr 28 03:19:57 PM PDT 24
Peak memory 199692 kb
Host smart-1ce45608-483a-4f93-a1c8-d3a7d5902710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412474086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2412474086
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4086880576
Short name T594
Test name
Test status
Simulation time 95451416429 ps
CPU time 612.31 seconds
Started Apr 28 03:19:56 PM PDT 24
Finished Apr 28 03:30:08 PM PDT 24
Peak memory 199748 kb
Host smart-9c14cb91-92d3-4ce0-9792-f9362014ebc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086880576 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4086880576
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1458670334
Short name T390
Test name
Test status
Simulation time 100094692 ps
CPU time 0.94 seconds
Started Apr 28 03:19:56 PM PDT 24
Finished Apr 28 03:19:58 PM PDT 24
Peak memory 198272 kb
Host smart-e876e747-9321-4fe7-9110-779c546194dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458670334 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1458670334
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2127157550
Short name T601
Test name
Test status
Simulation time 58893068288 ps
CPU time 529.39 seconds
Started Apr 28 03:19:57 PM PDT 24
Finished Apr 28 03:28:47 PM PDT 24
Peak memory 199628 kb
Host smart-32ecb96e-0228-44dc-8da2-3f28d2da76ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127157550 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2127157550
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1222395206
Short name T220
Test name
Test status
Simulation time 2648783264 ps
CPU time 88.38 seconds
Started Apr 28 03:19:55 PM PDT 24
Finished Apr 28 03:21:24 PM PDT 24
Peak memory 199708 kb
Host smart-874978ca-30b4-4df6-81eb-04b14e2dffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222395206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1222395206
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.4080457781
Short name T10
Test name
Test status
Simulation time 126417801381 ps
CPU time 1816.94 seconds
Started Apr 28 03:22:52 PM PDT 24
Finished Apr 28 03:53:09 PM PDT 24
Peak memory 244288 kb
Host smart-914a054a-5952-4cd3-bb35-4f51d173652b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080457781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.4080457781
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.127340985
Short name T322
Test name
Test status
Simulation time 35104106 ps
CPU time 0.57 seconds
Started Apr 28 03:20:02 PM PDT 24
Finished Apr 28 03:20:03 PM PDT 24
Peak memory 195320 kb
Host smart-f7abbd25-ed36-4678-8cb1-5a529511ad50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127340985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.127340985
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.897956381
Short name T229
Test name
Test status
Simulation time 1182237862 ps
CPU time 20.86 seconds
Started Apr 28 03:19:57 PM PDT 24
Finished Apr 28 03:20:19 PM PDT 24
Peak memory 215668 kb
Host smart-7a333661-69e9-4dfa-9574-3d03f0345a23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=897956381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.897956381
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.476408906
Short name T355
Test name
Test status
Simulation time 470449710 ps
CPU time 4.89 seconds
Started Apr 28 03:19:56 PM PDT 24
Finished Apr 28 03:20:01 PM PDT 24
Peak memory 199680 kb
Host smart-db0dc3c6-4f06-48b3-a30d-ef35067386e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476408906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.476408906
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3731079332
Short name T129
Test name
Test status
Simulation time 907435737 ps
CPU time 60.15 seconds
Started Apr 28 03:19:57 PM PDT 24
Finished Apr 28 03:20:58 PM PDT 24
Peak memory 199648 kb
Host smart-6a3c6a4e-649e-4386-9f89-c9846996a62a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731079332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3731079332
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1659998783
Short name T146
Test name
Test status
Simulation time 12545423300 ps
CPU time 126.45 seconds
Started Apr 28 03:19:59 PM PDT 24
Finished Apr 28 03:22:06 PM PDT 24
Peak memory 199744 kb
Host smart-2b986b57-b89b-4f30-aabd-2c1e043bee07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659998783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1659998783
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3998173734
Short name T575
Test name
Test status
Simulation time 14252584614 ps
CPU time 137.61 seconds
Started Apr 28 03:19:57 PM PDT 24
Finished Apr 28 03:22:16 PM PDT 24
Peak memory 199640 kb
Host smart-71823660-bdb9-4fe8-a02e-5920c199433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998173734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3998173734
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3005351123
Short name T328
Test name
Test status
Simulation time 401369184 ps
CPU time 6.13 seconds
Started Apr 28 03:19:58 PM PDT 24
Finished Apr 28 03:20:05 PM PDT 24
Peak memory 199596 kb
Host smart-1d3461ed-9273-4f68-9f9d-e7b89579f90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005351123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3005351123
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3906055308
Short name T297
Test name
Test status
Simulation time 25149053920 ps
CPU time 123.35 seconds
Started Apr 28 03:19:58 PM PDT 24
Finished Apr 28 03:22:02 PM PDT 24
Peak memory 199736 kb
Host smart-4d7b988c-d74f-4574-9889-a8c8fe804df5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906055308 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3906055308
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1247551990
Short name T447
Test name
Test status
Simulation time 229098780 ps
CPU time 1.28 seconds
Started Apr 28 03:19:59 PM PDT 24
Finished Apr 28 03:20:01 PM PDT 24
Peak memory 199696 kb
Host smart-8c27ae51-db36-4d29-a368-c6b34dda8d7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247551990 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1247551990
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2107761136
Short name T321
Test name
Test status
Simulation time 15291873649 ps
CPU time 452.97 seconds
Started Apr 28 03:19:56 PM PDT 24
Finished Apr 28 03:27:30 PM PDT 24
Peak memory 199720 kb
Host smart-8e767d81-dba5-4468-8882-8b7f65347727
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107761136 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2107761136
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3773917639
Short name T432
Test name
Test status
Simulation time 1808088098 ps
CPU time 85.36 seconds
Started Apr 28 03:19:58 PM PDT 24
Finished Apr 28 03:21:24 PM PDT 24
Peak memory 199636 kb
Host smart-4700e117-3833-4cc9-9861-d42d00d8d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773917639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3773917639
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.883484255
Short name T70
Test name
Test status
Simulation time 20476735522 ps
CPU time 129.05 seconds
Started Apr 28 03:23:00 PM PDT 24
Finished Apr 28 03:25:09 PM PDT 24
Peak memory 208088 kb
Host smart-532684a6-0af9-4628-ac27-6f47f3c46ce0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883484255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.883484255
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1472306449
Short name T216
Test name
Test status
Simulation time 12291926 ps
CPU time 0.58 seconds
Started Apr 28 03:20:08 PM PDT 24
Finished Apr 28 03:20:09 PM PDT 24
Peak memory 195016 kb
Host smart-2e1ee2e8-4658-4137-9555-e9da017e9b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472306449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1472306449
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2091286429
Short name T512
Test name
Test status
Simulation time 2995279527 ps
CPU time 30.59 seconds
Started Apr 28 03:20:01 PM PDT 24
Finished Apr 28 03:20:32 PM PDT 24
Peak memory 218292 kb
Host smart-f0dc8d92-59d9-412e-94b9-983a132801cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091286429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2091286429
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1485150729
Short name T529
Test name
Test status
Simulation time 2033030136 ps
CPU time 7.34 seconds
Started Apr 28 03:20:04 PM PDT 24
Finished Apr 28 03:20:12 PM PDT 24
Peak memory 199648 kb
Host smart-ffbc3c74-90ce-4208-9a69-0706d8274202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485150729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1485150729
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1593133517
Short name T275
Test name
Test status
Simulation time 9541348450 ps
CPU time 112.03 seconds
Started Apr 28 03:20:02 PM PDT 24
Finished Apr 28 03:21:55 PM PDT 24
Peak memory 199688 kb
Host smart-43a197d2-250a-4ad3-959c-59ceb0dfb242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593133517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1593133517
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3642080299
Short name T483
Test name
Test status
Simulation time 6454532217 ps
CPU time 63.86 seconds
Started Apr 28 03:20:04 PM PDT 24
Finished Apr 28 03:21:08 PM PDT 24
Peak memory 199772 kb
Host smart-41a8ef2c-f556-4c20-b374-4c52f22f4764
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642080299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3642080299
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1490210096
Short name T430
Test name
Test status
Simulation time 12030450486 ps
CPU time 117.92 seconds
Started Apr 28 03:20:01 PM PDT 24
Finished Apr 28 03:22:00 PM PDT 24
Peak memory 199752 kb
Host smart-eec510ef-51ad-4e23-91a8-65a58a6dd1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490210096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1490210096
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3998362948
Short name T453
Test name
Test status
Simulation time 102024476 ps
CPU time 1.75 seconds
Started Apr 28 03:20:04 PM PDT 24
Finished Apr 28 03:20:06 PM PDT 24
Peak memory 199664 kb
Host smart-694d1cd9-c9ed-4c00-b139-a74f984720bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998362948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3998362948
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1699679734
Short name T513
Test name
Test status
Simulation time 57449700464 ps
CPU time 1557.94 seconds
Started Apr 28 03:20:06 PM PDT 24
Finished Apr 28 03:46:05 PM PDT 24
Peak memory 199684 kb
Host smart-26ba999b-5a49-454a-818b-6237a619365c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699679734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1699679734
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1634071144
Short name T16
Test name
Test status
Simulation time 175713575 ps
CPU time 1.01 seconds
Started Apr 28 03:20:04 PM PDT 24
Finished Apr 28 03:20:05 PM PDT 24
Peak memory 199392 kb
Host smart-2f80efe4-7dd7-42b5-8a73-aa793dcd8420
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634071144 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1634071144
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2181293119
Short name T405
Test name
Test status
Simulation time 7346024632 ps
CPU time 378.74 seconds
Started Apr 28 03:20:01 PM PDT 24
Finished Apr 28 03:26:21 PM PDT 24
Peak memory 199644 kb
Host smart-c5678274-efc8-44c5-a772-d69d5a489e6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181293119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2181293119
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2659592116
Short name T343
Test name
Test status
Simulation time 22762993719 ps
CPU time 82.69 seconds
Started Apr 28 03:20:02 PM PDT 24
Finished Apr 28 03:21:25 PM PDT 24
Peak memory 199736 kb
Host smart-d1a6c549-6ee4-4505-8b54-6cd460743820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659592116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2659592116
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2265088136
Short name T19
Test name
Test status
Simulation time 18871866 ps
CPU time 0.57 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:19:24 PM PDT 24
Peak memory 194352 kb
Host smart-9599eb49-e1c9-4661-8868-8d097d10940a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265088136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2265088136
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3666992933
Short name T518
Test name
Test status
Simulation time 989511634 ps
CPU time 43.41 seconds
Started Apr 28 03:19:18 PM PDT 24
Finished Apr 28 03:20:02 PM PDT 24
Peak memory 240492 kb
Host smart-8df8e7e9-ab19-44d5-b926-8ff543fb11a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666992933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3666992933
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1938916655
Short name T348
Test name
Test status
Simulation time 11918506695 ps
CPU time 39.93 seconds
Started Apr 28 03:19:20 PM PDT 24
Finished Apr 28 03:20:00 PM PDT 24
Peak memory 199676 kb
Host smart-76556877-9cd3-4c12-afef-086d0535a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938916655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1938916655
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3813873066
Short name T562
Test name
Test status
Simulation time 1840670713 ps
CPU time 109.04 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:21:09 PM PDT 24
Peak memory 199608 kb
Host smart-3fb7788a-fc60-4b51-abfb-45f5bb24d642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813873066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3813873066
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.950002739
Short name T576
Test name
Test status
Simulation time 9969357498 ps
CPU time 35.12 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:19:58 PM PDT 24
Peak memory 199716 kb
Host smart-00c87f6d-56db-4df6-beff-034406461e8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950002739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.950002739
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.541719867
Short name T112
Test name
Test status
Simulation time 6499759097 ps
CPU time 91.92 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:20:52 PM PDT 24
Peak memory 199668 kb
Host smart-ab401cee-5f3d-41f6-8f9a-b75b632d1378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541719867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.541719867
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1169832878
Short name T34
Test name
Test status
Simulation time 69656389 ps
CPU time 0.84 seconds
Started Apr 28 03:19:23 PM PDT 24
Finished Apr 28 03:19:24 PM PDT 24
Peak memory 218072 kb
Host smart-0de5ff98-669c-40dd-a315-01dd2c93b436
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169832878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1169832878
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3078465906
Short name T204
Test name
Test status
Simulation time 579978295 ps
CPU time 4.44 seconds
Started Apr 28 03:19:19 PM PDT 24
Finished Apr 28 03:19:24 PM PDT 24
Peak memory 199688 kb
Host smart-5d3c76a4-1e8d-4e8b-ad27-b0fe9b9ceb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078465906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3078465906
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3005948968
Short name T324
Test name
Test status
Simulation time 23408932867 ps
CPU time 1258.79 seconds
Started Apr 28 03:19:24 PM PDT 24
Finished Apr 28 03:40:23 PM PDT 24
Peak memory 236580 kb
Host smart-29c04861-a6bd-42dc-8885-82f04856e129
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005948968 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3005948968
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1427781614
Short name T498
Test name
Test status
Simulation time 130150097 ps
CPU time 1.21 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:19:23 PM PDT 24
Peak memory 199696 kb
Host smart-6a6f3ef5-bc2f-4c4b-b813-3e67bf53dd2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427781614 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1427781614
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2284165454
Short name T304
Test name
Test status
Simulation time 51285189973 ps
CPU time 464.11 seconds
Started Apr 28 03:19:21 PM PDT 24
Finished Apr 28 03:27:06 PM PDT 24
Peak memory 199672 kb
Host smart-6bd2da22-cfa2-4b02-8bba-823a8d8cde18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284165454 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2284165454
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2498447699
Short name T24
Test name
Test status
Simulation time 1258620045 ps
CPU time 22.48 seconds
Started Apr 28 03:19:24 PM PDT 24
Finished Apr 28 03:19:47 PM PDT 24
Peak memory 199692 kb
Host smart-533716b1-3fd9-44e3-940a-d7099f964abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498447699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2498447699
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1554834928
Short name T259
Test name
Test status
Simulation time 38507223 ps
CPU time 0.6 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:20:12 PM PDT 24
Peak memory 195404 kb
Host smart-96b0408f-d03f-4ad5-a2f5-467a69dfbb5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554834928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1554834928
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3795903745
Short name T170
Test name
Test status
Simulation time 21838036455 ps
CPU time 46.47 seconds
Started Apr 28 03:20:07 PM PDT 24
Finished Apr 28 03:20:54 PM PDT 24
Peak memory 210072 kb
Host smart-3e8ee3e5-7c11-4a97-87c0-d5cee5f377e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795903745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3795903745
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3877574138
Short name T382
Test name
Test status
Simulation time 1037521296 ps
CPU time 52.25 seconds
Started Apr 28 03:20:07 PM PDT 24
Finished Apr 28 03:20:59 PM PDT 24
Peak memory 199656 kb
Host smart-97762077-8991-447b-8f0e-83befe2f10e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877574138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3877574138
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3864631281
Short name T207
Test name
Test status
Simulation time 323419730 ps
CPU time 17.81 seconds
Started Apr 28 03:20:07 PM PDT 24
Finished Apr 28 03:20:26 PM PDT 24
Peak memory 199656 kb
Host smart-ec99145d-b9a0-4d9e-84d8-cc3a003d755b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864631281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3864631281
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1097599366
Short name T541
Test name
Test status
Simulation time 156111195 ps
CPU time 2.82 seconds
Started Apr 28 03:20:05 PM PDT 24
Finished Apr 28 03:20:08 PM PDT 24
Peak memory 199648 kb
Host smart-825e5638-cdf5-4458-ae5a-83d1b39099fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097599366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1097599366
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1640233462
Short name T566
Test name
Test status
Simulation time 4717218166 ps
CPU time 71.38 seconds
Started Apr 28 03:20:07 PM PDT 24
Finished Apr 28 03:21:19 PM PDT 24
Peak memory 199712 kb
Host smart-f09f85e5-d687-4bc6-8a94-4db59d7c3d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640233462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1640233462
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1887660971
Short name T270
Test name
Test status
Simulation time 686770205 ps
CPU time 5.15 seconds
Started Apr 28 03:20:06 PM PDT 24
Finished Apr 28 03:20:11 PM PDT 24
Peak memory 199684 kb
Host smart-ad5356cf-3325-4eb4-bb7f-96a73bdf6b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887660971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1887660971
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1317353242
Short name T335
Test name
Test status
Simulation time 20330604314 ps
CPU time 834.71 seconds
Started Apr 28 03:20:08 PM PDT 24
Finished Apr 28 03:34:03 PM PDT 24
Peak memory 199632 kb
Host smart-31cedd19-1973-4ef8-99d4-9ac52f72d25d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317353242 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1317353242
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.3975182534
Short name T68
Test name
Test status
Simulation time 74506966796 ps
CPU time 1874.01 seconds
Started Apr 28 03:20:06 PM PDT 24
Finished Apr 28 03:51:20 PM PDT 24
Peak memory 216132 kb
Host smart-cb939e03-35ab-4b56-a87d-808f5a9fd84f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975182534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.3975182534
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.36728098
Short name T117
Test name
Test status
Simulation time 181592242 ps
CPU time 1.04 seconds
Started Apr 28 03:20:07 PM PDT 24
Finished Apr 28 03:20:08 PM PDT 24
Peak memory 199268 kb
Host smart-6ea5a459-06d3-4a12-9929-120b6e3951ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36728098 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.hmac_test_hmac_vectors.36728098
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3748777053
Short name T252
Test name
Test status
Simulation time 53585017022 ps
CPU time 531.78 seconds
Started Apr 28 03:20:08 PM PDT 24
Finished Apr 28 03:29:01 PM PDT 24
Peak memory 199696 kb
Host smart-4a39cfa1-46f7-4d5c-8096-8a9deb46dcf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748777053 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3748777053
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2430753551
Short name T595
Test name
Test status
Simulation time 182602162 ps
CPU time 4.87 seconds
Started Apr 28 03:20:06 PM PDT 24
Finished Apr 28 03:20:12 PM PDT 24
Peak memory 199576 kb
Host smart-21da02a5-6579-4f8f-a361-99f771c77515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430753551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2430753551
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2315605432
Short name T303
Test name
Test status
Simulation time 44694703 ps
CPU time 0.63 seconds
Started Apr 28 03:20:14 PM PDT 24
Finished Apr 28 03:20:15 PM PDT 24
Peak memory 195356 kb
Host smart-fb5ebdaa-c210-4e5a-8844-3a97dca10c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315605432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2315605432
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.809799895
Short name T286
Test name
Test status
Simulation time 780302030 ps
CPU time 22.36 seconds
Started Apr 28 03:20:12 PM PDT 24
Finished Apr 28 03:20:35 PM PDT 24
Peak memory 215756 kb
Host smart-40f44e8b-c594-4248-9c16-00263b2bdf83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809799895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.809799895
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1385671716
Short name T39
Test name
Test status
Simulation time 2751227478 ps
CPU time 42.04 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:20:54 PM PDT 24
Peak memory 199668 kb
Host smart-afadd72c-304f-4d20-a2a7-be50099c5f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385671716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1385671716
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1538384919
Short name T80
Test name
Test status
Simulation time 9456588866 ps
CPU time 137.94 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:22:30 PM PDT 24
Peak memory 199716 kb
Host smart-9c599385-7773-40ff-90d8-0261a2d14353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538384919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1538384919
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.490427554
Short name T394
Test name
Test status
Simulation time 4456177355 ps
CPU time 55.57 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:21:07 PM PDT 24
Peak memory 199648 kb
Host smart-7f3eb144-e926-482d-8012-7b17ca39c765
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490427554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.490427554
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1724403813
Short name T537
Test name
Test status
Simulation time 696054980 ps
CPU time 41.15 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:20:53 PM PDT 24
Peak memory 199728 kb
Host smart-7796aecd-8d7a-4c13-a191-367a22e79b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724403813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1724403813
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1007824969
Short name T276
Test name
Test status
Simulation time 605096858 ps
CPU time 6.62 seconds
Started Apr 28 03:20:10 PM PDT 24
Finished Apr 28 03:20:16 PM PDT 24
Peak memory 199624 kb
Host smart-efdf35df-a14f-4f83-a938-cb5069e97944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007824969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1007824969
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2040548280
Short name T547
Test name
Test status
Simulation time 31445601152 ps
CPU time 1796.72 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:50:09 PM PDT 24
Peak memory 199660 kb
Host smart-dea1acae-ca91-45cb-b530-2e6e50c37e43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040548280 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2040548280
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2722856966
Short name T456
Test name
Test status
Simulation time 137972742 ps
CPU time 1.33 seconds
Started Apr 28 03:20:14 PM PDT 24
Finished Apr 28 03:20:16 PM PDT 24
Peak memory 199380 kb
Host smart-229ff698-e83e-4faa-9ca0-ade3cc32e947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722856966 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2722856966
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1427971635
Short name T414
Test name
Test status
Simulation time 41062982094 ps
CPU time 493.98 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:28:26 PM PDT 24
Peak memory 199632 kb
Host smart-809444b3-d185-48ce-86f6-e80c916fde7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427971635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1427971635
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4055698957
Short name T499
Test name
Test status
Simulation time 1362572609 ps
CPU time 62.57 seconds
Started Apr 28 03:20:10 PM PDT 24
Finished Apr 28 03:21:13 PM PDT 24
Peak memory 199684 kb
Host smart-a52ebb80-7157-429c-97f6-b13c60ddc4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055698957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4055698957
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1234632982
Short name T190
Test name
Test status
Simulation time 34413373 ps
CPU time 0.56 seconds
Started Apr 28 03:20:16 PM PDT 24
Finished Apr 28 03:20:17 PM PDT 24
Peak memory 195268 kb
Host smart-b993a11b-7195-45b1-afba-00174e3c7592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234632982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1234632982
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.4202711092
Short name T217
Test name
Test status
Simulation time 1397620273 ps
CPU time 45.64 seconds
Started Apr 28 03:20:12 PM PDT 24
Finished Apr 28 03:20:58 PM PDT 24
Peak memory 207880 kb
Host smart-57f6fd1e-5d7b-4829-83e0-3ff727719c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202711092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4202711092
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4185460193
Short name T167
Test name
Test status
Simulation time 19162398554 ps
CPU time 39.15 seconds
Started Apr 28 03:20:18 PM PDT 24
Finished Apr 28 03:20:58 PM PDT 24
Peak memory 199764 kb
Host smart-8212f2e2-ab11-4f29-bde4-783f89467da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185460193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4185460193
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.339004779
Short name T428
Test name
Test status
Simulation time 309931387 ps
CPU time 8.51 seconds
Started Apr 28 03:20:14 PM PDT 24
Finished Apr 28 03:20:23 PM PDT 24
Peak memory 199644 kb
Host smart-5b8592c8-4179-43ae-8a0f-4d0b61e064b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339004779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.339004779
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3012400639
Short name T329
Test name
Test status
Simulation time 5935041062 ps
CPU time 62.56 seconds
Started Apr 28 03:20:18 PM PDT 24
Finished Apr 28 03:21:21 PM PDT 24
Peak memory 199716 kb
Host smart-864dd494-c805-408a-af7c-1d83d226b373
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012400639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3012400639
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3904444402
Short name T35
Test name
Test status
Simulation time 3064644452 ps
CPU time 92.91 seconds
Started Apr 28 03:20:11 PM PDT 24
Finished Apr 28 03:21:45 PM PDT 24
Peak memory 199764 kb
Host smart-cb0aa905-44cc-467f-ae86-a9d23d50228b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904444402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3904444402
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2266220416
Short name T351
Test name
Test status
Simulation time 503580237 ps
CPU time 5.53 seconds
Started Apr 28 03:20:15 PM PDT 24
Finished Apr 28 03:20:21 PM PDT 24
Peak memory 199644 kb
Host smart-b2d5a745-33f8-4fcc-bbf8-8ffc1d2a3e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266220416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2266220416
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.972472257
Short name T27
Test name
Test status
Simulation time 50897117197 ps
CPU time 946.98 seconds
Started Apr 28 03:20:17 PM PDT 24
Finished Apr 28 03:36:05 PM PDT 24
Peak memory 225312 kb
Host smart-3bc40553-330c-45e0-bf22-1427b2c416f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972472257 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.972472257
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2253213299
Short name T115
Test name
Test status
Simulation time 55119632 ps
CPU time 1.27 seconds
Started Apr 28 03:20:18 PM PDT 24
Finished Apr 28 03:20:21 PM PDT 24
Peak memory 199716 kb
Host smart-d72b25cd-1a96-4d55-91a8-a4009b5768f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253213299 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2253213299
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2662653186
Short name T118
Test name
Test status
Simulation time 38721015815 ps
CPU time 465.32 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:28:06 PM PDT 24
Peak memory 199660 kb
Host smart-273d83f4-3061-48f5-88fc-2acc30d24d8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662653186 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2662653186
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3689270510
Short name T411
Test name
Test status
Simulation time 15037605 ps
CPU time 0.6 seconds
Started Apr 28 03:20:18 PM PDT 24
Finished Apr 28 03:20:19 PM PDT 24
Peak memory 195392 kb
Host smart-57fdc0e0-5d5c-4638-8300-558a88e58bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689270510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3689270510
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3202252249
Short name T193
Test name
Test status
Simulation time 660294259 ps
CPU time 10.21 seconds
Started Apr 28 03:20:17 PM PDT 24
Finished Apr 28 03:20:27 PM PDT 24
Peak memory 199620 kb
Host smart-4011d0cb-19fe-420e-acf5-d6e174b5234b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202252249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3202252249
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1412649453
Short name T407
Test name
Test status
Simulation time 11615978536 ps
CPU time 51.48 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:21:12 PM PDT 24
Peak memory 199780 kb
Host smart-618a93dc-9bdb-4ef5-b566-1420d4635e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412649453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1412649453
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2607044295
Short name T176
Test name
Test status
Simulation time 1086172762 ps
CPU time 63.27 seconds
Started Apr 28 03:20:17 PM PDT 24
Finished Apr 28 03:21:20 PM PDT 24
Peak memory 199656 kb
Host smart-289efce2-061f-4ffd-b0d8-887de531f6b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607044295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2607044295
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3234601045
Short name T421
Test name
Test status
Simulation time 4345926187 ps
CPU time 119.18 seconds
Started Apr 28 03:20:19 PM PDT 24
Finished Apr 28 03:22:19 PM PDT 24
Peak memory 199688 kb
Host smart-c2c70a34-7a0e-45c2-836e-2b847a913ed9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234601045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3234601045
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2808715308
Short name T339
Test name
Test status
Simulation time 5724476414 ps
CPU time 41.46 seconds
Started Apr 28 03:20:18 PM PDT 24
Finished Apr 28 03:21:01 PM PDT 24
Peak memory 199776 kb
Host smart-746274ab-ac37-414a-896a-2ba1e17d6787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808715308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2808715308
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2667688672
Short name T330
Test name
Test status
Simulation time 431446085 ps
CPU time 6.5 seconds
Started Apr 28 03:20:16 PM PDT 24
Finished Apr 28 03:20:23 PM PDT 24
Peak memory 199676 kb
Host smart-4aadf387-4842-4a34-96ec-180dfd00d271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667688672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2667688672
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.318954121
Short name T284
Test name
Test status
Simulation time 35849255655 ps
CPU time 644.39 seconds
Started Apr 28 03:20:16 PM PDT 24
Finished Apr 28 03:31:00 PM PDT 24
Peak memory 199744 kb
Host smart-88e0d42a-0bee-4b06-86c1-2e7dad79f7d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318954121 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.318954121
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2806960651
Short name T307
Test name
Test status
Simulation time 188012188 ps
CPU time 1.2 seconds
Started Apr 28 03:20:16 PM PDT 24
Finished Apr 28 03:20:18 PM PDT 24
Peak memory 199612 kb
Host smart-6256f7cf-e773-4005-89ea-b3b9f609262f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806960651 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2806960651
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2975813567
Short name T147
Test name
Test status
Simulation time 106808739036 ps
CPU time 469.45 seconds
Started Apr 28 03:20:17 PM PDT 24
Finished Apr 28 03:28:07 PM PDT 24
Peak memory 199648 kb
Host smart-7f45b5b1-1b2f-413f-b86f-652ae5f06928
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975813567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.2975813567
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2483909820
Short name T487
Test name
Test status
Simulation time 1512181687 ps
CPU time 41.06 seconds
Started Apr 28 03:20:19 PM PDT 24
Finished Apr 28 03:21:01 PM PDT 24
Peak memory 199632 kb
Host smart-8e7dc282-b998-403e-b48d-e038eeb78c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483909820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2483909820
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.756260040
Short name T446
Test name
Test status
Simulation time 24937393 ps
CPU time 0.57 seconds
Started Apr 28 03:20:22 PM PDT 24
Finished Apr 28 03:20:23 PM PDT 24
Peak memory 195264 kb
Host smart-298d6506-b395-45f5-b1f5-d9aa8bc4dc69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756260040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.756260040
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1481393651
Short name T258
Test name
Test status
Simulation time 1875160758 ps
CPU time 16.16 seconds
Started Apr 28 03:20:18 PM PDT 24
Finished Apr 28 03:20:35 PM PDT 24
Peak memory 199684 kb
Host smart-47e8b3b4-bece-45d2-91b1-2304fb45a96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481393651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1481393651
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1385384128
Short name T179
Test name
Test status
Simulation time 155718113 ps
CPU time 3.53 seconds
Started Apr 28 03:20:21 PM PDT 24
Finished Apr 28 03:20:26 PM PDT 24
Peak memory 199648 kb
Host smart-c1ebc04c-28cd-4f7c-84b6-d497400b837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385384128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1385384128
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2307160254
Short name T436
Test name
Test status
Simulation time 7802138733 ps
CPU time 119.59 seconds
Started Apr 28 03:20:23 PM PDT 24
Finished Apr 28 03:22:23 PM PDT 24
Peak memory 199760 kb
Host smart-b12c8a03-8ced-4125-81f3-d30d333910b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307160254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2307160254
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2560183039
Short name T345
Test name
Test status
Simulation time 9534017785 ps
CPU time 160.43 seconds
Started Apr 28 03:20:21 PM PDT 24
Finished Apr 28 03:23:02 PM PDT 24
Peak memory 199740 kb
Host smart-c3527d87-b539-41fb-8c5a-ca173e7c5813
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560183039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2560183039
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4090659822
Short name T602
Test name
Test status
Simulation time 64882811 ps
CPU time 3.89 seconds
Started Apr 28 03:20:18 PM PDT 24
Finished Apr 28 03:20:22 PM PDT 24
Peak memory 199624 kb
Host smart-5c83802c-d4fb-47a9-85c7-553aab7dcf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090659822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4090659822
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1121144209
Short name T523
Test name
Test status
Simulation time 77689559 ps
CPU time 1.7 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:20:23 PM PDT 24
Peak memory 199660 kb
Host smart-9556e02e-aa79-4d21-9620-d1953b6e1dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121144209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1121144209
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3588819453
Short name T474
Test name
Test status
Simulation time 39054352331 ps
CPU time 593.87 seconds
Started Apr 28 03:20:21 PM PDT 24
Finished Apr 28 03:30:16 PM PDT 24
Peak memory 199712 kb
Host smart-0408e259-7ed6-430a-8eb3-89fb68bea4f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588819453 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3588819453
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.4261039931
Short name T257
Test name
Test status
Simulation time 203075440 ps
CPU time 1.09 seconds
Started Apr 28 03:20:23 PM PDT 24
Finished Apr 28 03:20:25 PM PDT 24
Peak memory 199008 kb
Host smart-ab1fbc1c-0dda-419f-8964-adff5ec52b47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261039931 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.4261039931
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3465614464
Short name T285
Test name
Test status
Simulation time 42209556257 ps
CPU time 515.83 seconds
Started Apr 28 03:20:19 PM PDT 24
Finished Apr 28 03:28:56 PM PDT 24
Peak memory 199652 kb
Host smart-e87d96c8-4d7b-4476-8763-e61bd3ad1d88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465614464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3465614464
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2835678107
Short name T504
Test name
Test status
Simulation time 297630237 ps
CPU time 8.91 seconds
Started Apr 28 03:20:21 PM PDT 24
Finished Apr 28 03:20:30 PM PDT 24
Peak memory 199668 kb
Host smart-57b9dbe1-42a2-4cf6-8a34-d4d9e881e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835678107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2835678107
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.809261800
Short name T585
Test name
Test status
Simulation time 13661097 ps
CPU time 0.6 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:20:22 PM PDT 24
Peak memory 194480 kb
Host smart-c4d4a693-8611-4d1e-91ea-e73e0d5dc08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809261800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.809261800
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2657278304
Short name T393
Test name
Test status
Simulation time 653102217 ps
CPU time 21.58 seconds
Started Apr 28 03:20:22 PM PDT 24
Finished Apr 28 03:20:44 PM PDT 24
Peak memory 207876 kb
Host smart-498d585c-4848-42f5-9f9c-31c8341111eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657278304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2657278304
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3330341148
Short name T528
Test name
Test status
Simulation time 5360136209 ps
CPU time 21.14 seconds
Started Apr 28 03:20:22 PM PDT 24
Finished Apr 28 03:20:43 PM PDT 24
Peak memory 199688 kb
Host smart-b1c61f24-5f4a-470c-8f62-96420f6984f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330341148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3330341148
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.213805628
Short name T42
Test name
Test status
Simulation time 9408916015 ps
CPU time 146.28 seconds
Started Apr 28 03:20:22 PM PDT 24
Finished Apr 28 03:22:49 PM PDT 24
Peak memory 199664 kb
Host smart-0560e908-28dd-416b-9307-58f33efb119d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213805628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.213805628
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1344353022
Short name T571
Test name
Test status
Simulation time 16406240047 ps
CPU time 70.88 seconds
Started Apr 28 03:20:22 PM PDT 24
Finished Apr 28 03:21:34 PM PDT 24
Peak memory 199768 kb
Host smart-21cf9a4c-5062-4a25-b8fc-4fd407f21739
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344353022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1344353022
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3507402670
Short name T84
Test name
Test status
Simulation time 1401913230 ps
CPU time 79.34 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:21:40 PM PDT 24
Peak memory 199704 kb
Host smart-de73ae13-ee79-4613-b1c8-9df00ba65adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507402670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3507402670
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3554159989
Short name T30
Test name
Test status
Simulation time 60496076 ps
CPU time 0.92 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:20:21 PM PDT 24
Peak memory 198292 kb
Host smart-64c7b0ff-a401-4603-a08c-d02b43951020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554159989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3554159989
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3908733600
Short name T75
Test name
Test status
Simulation time 8302103231 ps
CPU time 122.66 seconds
Started Apr 28 03:20:23 PM PDT 24
Finished Apr 28 03:22:26 PM PDT 24
Peak memory 199692 kb
Host smart-9d1be688-33d5-4cde-b421-b72d15f407e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908733600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3908733600
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3930708842
Short name T213
Test name
Test status
Simulation time 261055113 ps
CPU time 1.28 seconds
Started Apr 28 03:20:23 PM PDT 24
Finished Apr 28 03:20:25 PM PDT 24
Peak memory 199600 kb
Host smart-72766cd4-7e25-4981-b998-5e8d1cb66907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930708842 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3930708842
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.558309667
Short name T159
Test name
Test status
Simulation time 7952819059 ps
CPU time 433.68 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:27:35 PM PDT 24
Peak memory 199624 kb
Host smart-bb321b72-560b-44bb-9c6a-e93dac43b5ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558309667 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.558309667
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.4170946600
Short name T532
Test name
Test status
Simulation time 6415044035 ps
CPU time 69.28 seconds
Started Apr 28 03:20:24 PM PDT 24
Finished Apr 28 03:21:33 PM PDT 24
Peak memory 199660 kb
Host smart-5fb96ae1-3504-4cf5-abfd-5ab825ed3607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170946600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.4170946600
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3005352722
Short name T248
Test name
Test status
Simulation time 53666039 ps
CPU time 0.59 seconds
Started Apr 28 03:20:28 PM PDT 24
Finished Apr 28 03:20:29 PM PDT 24
Peak memory 195328 kb
Host smart-6d481463-be29-492c-ac48-ccc2b285467e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005352722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3005352722
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.638714071
Short name T199
Test name
Test status
Simulation time 4256003179 ps
CPU time 42.82 seconds
Started Apr 28 03:20:25 PM PDT 24
Finished Apr 28 03:21:09 PM PDT 24
Peak memory 215664 kb
Host smart-8dd05d70-6276-45c2-9a8b-7620605e00ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638714071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.638714071
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3403825641
Short name T417
Test name
Test status
Simulation time 3900097969 ps
CPU time 10.79 seconds
Started Apr 28 03:20:27 PM PDT 24
Finished Apr 28 03:20:38 PM PDT 24
Peak memory 199776 kb
Host smart-09aa2080-619c-4c82-b8f5-dbcac367b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403825641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3403825641
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4103209074
Short name T316
Test name
Test status
Simulation time 485756695 ps
CPU time 27.81 seconds
Started Apr 28 03:20:25 PM PDT 24
Finished Apr 28 03:20:54 PM PDT 24
Peak memory 199616 kb
Host smart-08505c27-efc1-4745-9627-58f6d9b4085d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103209074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4103209074
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4055437123
Short name T301
Test name
Test status
Simulation time 1794501415 ps
CPU time 33.12 seconds
Started Apr 28 03:20:26 PM PDT 24
Finished Apr 28 03:20:59 PM PDT 24
Peak memory 199664 kb
Host smart-79368ce7-a28d-4483-8527-6f1ac858c417
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055437123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4055437123
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1091165713
Short name T568
Test name
Test status
Simulation time 1083308868 ps
CPU time 15.51 seconds
Started Apr 28 03:20:21 PM PDT 24
Finished Apr 28 03:20:37 PM PDT 24
Peak memory 199648 kb
Host smart-757ee68b-dbfc-4901-a26b-70bd31481500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091165713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1091165713
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2029324333
Short name T317
Test name
Test status
Simulation time 1002064547 ps
CPU time 4.28 seconds
Started Apr 28 03:20:20 PM PDT 24
Finished Apr 28 03:20:25 PM PDT 24
Peak memory 199664 kb
Host smart-732e7f37-59df-46c7-bd42-d51d9414177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029324333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2029324333
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3341824892
Short name T205
Test name
Test status
Simulation time 2012509495 ps
CPU time 92.36 seconds
Started Apr 28 03:20:27 PM PDT 24
Finished Apr 28 03:22:00 PM PDT 24
Peak memory 199632 kb
Host smart-deff2775-1b94-4bf2-b59f-257bae49fdd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341824892 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3341824892
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3746476004
Short name T15
Test name
Test status
Simulation time 50898389 ps
CPU time 1.08 seconds
Started Apr 28 03:20:25 PM PDT 24
Finished Apr 28 03:20:27 PM PDT 24
Peak memory 199520 kb
Host smart-f47f1c8a-c536-4a07-a133-00e3a36965b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746476004 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3746476004
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2720751907
Short name T506
Test name
Test status
Simulation time 18759227935 ps
CPU time 480.14 seconds
Started Apr 28 03:20:25 PM PDT 24
Finished Apr 28 03:28:26 PM PDT 24
Peak memory 199676 kb
Host smart-334e4d49-aba2-4dcf-afda-bce155569007
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720751907 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.2720751907
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.996947689
Short name T591
Test name
Test status
Simulation time 2915975365 ps
CPU time 22.56 seconds
Started Apr 28 03:20:26 PM PDT 24
Finished Apr 28 03:20:50 PM PDT 24
Peak memory 199760 kb
Host smart-9ce29dd0-1bb1-4790-b200-cfa5dd5d6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996947689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.996947689
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1420049959
Short name T164
Test name
Test status
Simulation time 55528822 ps
CPU time 0.62 seconds
Started Apr 28 03:20:31 PM PDT 24
Finished Apr 28 03:20:32 PM PDT 24
Peak memory 195340 kb
Host smart-1c53cc5f-f0dd-4cfd-a109-4e4ca2c49653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420049959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1420049959
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4041109588
Short name T211
Test name
Test status
Simulation time 1984497981 ps
CPU time 40.07 seconds
Started Apr 28 03:20:25 PM PDT 24
Finished Apr 28 03:21:05 PM PDT 24
Peak memory 224208 kb
Host smart-e780e65c-56af-41a8-9e5b-c3dc054480ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041109588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4041109588
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3098375991
Short name T1
Test name
Test status
Simulation time 2595766492 ps
CPU time 4.09 seconds
Started Apr 28 03:20:26 PM PDT 24
Finished Apr 28 03:20:31 PM PDT 24
Peak memory 199616 kb
Host smart-252fcbac-7c78-4599-ab9f-7a150357aaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098375991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3098375991
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3756138875
Short name T41
Test name
Test status
Simulation time 5813846430 ps
CPU time 67.38 seconds
Started Apr 28 03:20:25 PM PDT 24
Finished Apr 28 03:21:32 PM PDT 24
Peak memory 199716 kb
Host smart-bd5e5cc1-7f14-4f7e-815e-e92b09bb5707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756138875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3756138875
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2187408872
Short name T415
Test name
Test status
Simulation time 2171948566 ps
CPU time 67.19 seconds
Started Apr 28 03:20:25 PM PDT 24
Finished Apr 28 03:21:33 PM PDT 24
Peak memory 199768 kb
Host smart-99d8e219-028c-466d-bb92-e08d0d9ef99b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187408872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2187408872
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3139515420
Short name T269
Test name
Test status
Simulation time 10991578342 ps
CPU time 26.96 seconds
Started Apr 28 03:20:26 PM PDT 24
Finished Apr 28 03:20:53 PM PDT 24
Peak memory 199736 kb
Host smart-73bb5765-36ef-4844-98e3-5be6e6efde49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139515420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3139515420
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3909732520
Short name T158
Test name
Test status
Simulation time 182297915 ps
CPU time 2.37 seconds
Started Apr 28 03:20:33 PM PDT 24
Finished Apr 28 03:20:36 PM PDT 24
Peak memory 199656 kb
Host smart-2bd82e63-4cdd-48c5-9db3-9d7525b14e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909732520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3909732520
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2759080455
Short name T573
Test name
Test status
Simulation time 39389034372 ps
CPU time 203.3 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:23:54 PM PDT 24
Peak memory 224356 kb
Host smart-0cdd08e7-01ee-44b2-88d4-ad61d320bbae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759080455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2759080455
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.2702526001
Short name T67
Test name
Test status
Simulation time 160454404368 ps
CPU time 2231.2 seconds
Started Apr 28 03:20:29 PM PDT 24
Finished Apr 28 03:57:41 PM PDT 24
Peak memory 224368 kb
Host smart-59ecc715-bce7-4c31-b471-2d9f7c291fd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702526001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.2702526001
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2181608542
Short name T233
Test name
Test status
Simulation time 278966582 ps
CPU time 1.4 seconds
Started Apr 28 03:20:31 PM PDT 24
Finished Apr 28 03:20:33 PM PDT 24
Peak memory 199572 kb
Host smart-00fd26e6-c7af-4808-bad2-ed82195e4dea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181608542 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2181608542
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1159770003
Short name T81
Test name
Test status
Simulation time 30786274557 ps
CPU time 436.56 seconds
Started Apr 28 03:20:31 PM PDT 24
Finished Apr 28 03:27:48 PM PDT 24
Peak memory 199604 kb
Host smart-3d66e5a9-45cb-47e4-ba33-c25573b8d9f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159770003 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1159770003
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1106343682
Short name T535
Test name
Test status
Simulation time 2950022341 ps
CPU time 56.16 seconds
Started Apr 28 03:20:27 PM PDT 24
Finished Apr 28 03:21:24 PM PDT 24
Peak memory 199720 kb
Host smart-7c30d319-1d6f-492f-8297-90dfe79c3147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106343682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1106343682
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2984193790
Short name T557
Test name
Test status
Simulation time 12621742 ps
CPU time 0.6 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:20:32 PM PDT 24
Peak memory 195332 kb
Host smart-525e787d-007d-4af1-aa28-990cf0e15b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984193790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2984193790
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2272634058
Short name T53
Test name
Test status
Simulation time 7419297914 ps
CPU time 65.92 seconds
Started Apr 28 03:20:32 PM PDT 24
Finished Apr 28 03:21:38 PM PDT 24
Peak memory 240672 kb
Host smart-fe5e7644-cf4a-4ca5-8b09-8dfe37b654a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272634058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2272634058
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1735648065
Short name T493
Test name
Test status
Simulation time 1652676934 ps
CPU time 38.23 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:21:09 PM PDT 24
Peak memory 199628 kb
Host smart-2d506a36-8d75-4394-b99c-de1ea73b47f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735648065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1735648065
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4124865152
Short name T369
Test name
Test status
Simulation time 13474791862 ps
CPU time 71.05 seconds
Started Apr 28 03:20:32 PM PDT 24
Finished Apr 28 03:21:44 PM PDT 24
Peak memory 199724 kb
Host smart-309a1285-6e6a-4d95-8639-278e814c537d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124865152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4124865152
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3163782111
Short name T508
Test name
Test status
Simulation time 822767026 ps
CPU time 12.93 seconds
Started Apr 28 03:20:31 PM PDT 24
Finished Apr 28 03:20:45 PM PDT 24
Peak memory 199620 kb
Host smart-7ae8b5fd-2389-4882-a773-ec21787f1c71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163782111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3163782111
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1386449239
Short name T467
Test name
Test status
Simulation time 669153470 ps
CPU time 37.76 seconds
Started Apr 28 03:20:29 PM PDT 24
Finished Apr 28 03:21:08 PM PDT 24
Peak memory 199680 kb
Host smart-19cf12a8-ca1b-42cf-9c77-616d97ec9db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386449239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1386449239
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2701261237
Short name T263
Test name
Test status
Simulation time 1517729945 ps
CPU time 4.3 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:20:35 PM PDT 24
Peak memory 199664 kb
Host smart-99d7e69f-c062-400c-be66-f756234cb939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701261237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2701261237
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.569843374
Short name T76
Test name
Test status
Simulation time 136885491632 ps
CPU time 506.84 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:28:57 PM PDT 24
Peak memory 224620 kb
Host smart-d7df90c3-5ce8-47dc-a478-149f2770d748
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569843374 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.569843374
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3081238449
Short name T389
Test name
Test status
Simulation time 39249900 ps
CPU time 0.97 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:20:31 PM PDT 24
Peak memory 198196 kb
Host smart-1de8c2e9-3c26-43f7-af37-de1af366c8e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081238449 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3081238449
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2903338057
Short name T399
Test name
Test status
Simulation time 28136812192 ps
CPU time 380.78 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:26:51 PM PDT 24
Peak memory 199624 kb
Host smart-79fa8598-9e49-4724-b1d6-b46d3a9209cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903338057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2903338057
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2066348821
Short name T544
Test name
Test status
Simulation time 13647790492 ps
CPU time 39.26 seconds
Started Apr 28 03:20:30 PM PDT 24
Finished Apr 28 03:21:09 PM PDT 24
Peak memory 199664 kb
Host smart-734a5274-e1cf-48d6-86c3-81cf888bc363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066348821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2066348821
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.20030492
Short name T143
Test name
Test status
Simulation time 16105372 ps
CPU time 0.65 seconds
Started Apr 28 03:20:43 PM PDT 24
Finished Apr 28 03:20:44 PM PDT 24
Peak memory 195356 kb
Host smart-ab97e7ce-c4cc-46e9-b9e7-d4376613c292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20030492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.20030492
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.262990760
Short name T580
Test name
Test status
Simulation time 3124623636 ps
CPU time 50.13 seconds
Started Apr 28 03:20:35 PM PDT 24
Finished Apr 28 03:21:26 PM PDT 24
Peak memory 215328 kb
Host smart-7a27c207-0596-47af-addb-405abab6acfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262990760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.262990760
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2427765
Short name T502
Test name
Test status
Simulation time 1983004576 ps
CPU time 41.41 seconds
Started Apr 28 03:20:35 PM PDT 24
Finished Apr 28 03:21:17 PM PDT 24
Peak memory 199668 kb
Host smart-b8538a66-b7d9-4354-931f-fddc42bac2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2427765
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3843675304
Short name T406
Test name
Test status
Simulation time 5285702165 ps
CPU time 30.03 seconds
Started Apr 28 03:20:35 PM PDT 24
Finished Apr 28 03:21:06 PM PDT 24
Peak memory 199736 kb
Host smart-580b01be-c4b9-494b-8a39-ab797e86f516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843675304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3843675304
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4148242736
Short name T419
Test name
Test status
Simulation time 735135932 ps
CPU time 14.22 seconds
Started Apr 28 03:20:35 PM PDT 24
Finished Apr 28 03:20:49 PM PDT 24
Peak memory 199600 kb
Host smart-b77f2060-1af1-4e9f-ba85-c23d3911c6e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148242736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4148242736
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3985735022
Short name T260
Test name
Test status
Simulation time 6600806213 ps
CPU time 80.48 seconds
Started Apr 28 03:20:35 PM PDT 24
Finished Apr 28 03:21:56 PM PDT 24
Peak memory 199796 kb
Host smart-85fa9f09-2a1a-4c04-99ae-819e8c177ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985735022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3985735022
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2175699566
Short name T403
Test name
Test status
Simulation time 14338812 ps
CPU time 0.67 seconds
Started Apr 28 03:20:35 PM PDT 24
Finished Apr 28 03:20:37 PM PDT 24
Peak memory 196964 kb
Host smart-4dfff067-28a1-4228-8bd5-55c2932d3190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175699566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2175699566
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2374893795
Short name T542
Test name
Test status
Simulation time 184567098504 ps
CPU time 2674.8 seconds
Started Apr 28 03:20:37 PM PDT 24
Finished Apr 28 04:05:12 PM PDT 24
Peak memory 215448 kb
Host smart-269ad7a8-0365-4df7-accc-23a8f5f2a782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374893795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2374893795
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.4173602193
Short name T82
Test name
Test status
Simulation time 186786002 ps
CPU time 1.31 seconds
Started Apr 28 03:20:38 PM PDT 24
Finished Apr 28 03:20:40 PM PDT 24
Peak memory 199620 kb
Host smart-28a65d7f-c020-45a5-8907-bad52af8a204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173602193 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.4173602193
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2112698727
Short name T509
Test name
Test status
Simulation time 81806033321 ps
CPU time 500.23 seconds
Started Apr 28 03:20:36 PM PDT 24
Finished Apr 28 03:28:57 PM PDT 24
Peak memory 199584 kb
Host smart-90d9047c-77fd-449b-a724-44e76b8086d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112698727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2112698727
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.916147091
Short name T132
Test name
Test status
Simulation time 3373509736 ps
CPU time 44.83 seconds
Started Apr 28 03:20:38 PM PDT 24
Finished Apr 28 03:21:23 PM PDT 24
Peak memory 199696 kb
Host smart-ce3606f4-83e9-400e-af35-5e3d3e883c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916147091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.916147091
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3876553353
Short name T200
Test name
Test status
Simulation time 44779665 ps
CPU time 0.59 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:19:23 PM PDT 24
Peak memory 194312 kb
Host smart-eb844c24-cb83-4955-91d2-e61ae77a1e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876553353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3876553353
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3158083452
Short name T168
Test name
Test status
Simulation time 3557815062 ps
CPU time 18.34 seconds
Started Apr 28 03:19:24 PM PDT 24
Finished Apr 28 03:19:43 PM PDT 24
Peak memory 207904 kb
Host smart-5cd43956-7fe1-4f95-9304-f18380d6e27f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158083452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3158083452
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1794354266
Short name T559
Test name
Test status
Simulation time 9837437430 ps
CPU time 36.2 seconds
Started Apr 28 03:19:23 PM PDT 24
Finished Apr 28 03:20:00 PM PDT 24
Peak memory 199736 kb
Host smart-bb6edef9-eb45-4eb4-a965-5198949e0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794354266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1794354266
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1382172180
Short name T590
Test name
Test status
Simulation time 1005177758 ps
CPU time 28.76 seconds
Started Apr 28 03:19:26 PM PDT 24
Finished Apr 28 03:19:55 PM PDT 24
Peak memory 199640 kb
Host smart-dad1fb3d-0892-4be8-b19a-bdb86d169c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382172180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1382172180
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3221442083
Short name T295
Test name
Test status
Simulation time 35263429014 ps
CPU time 157.13 seconds
Started Apr 28 03:19:23 PM PDT 24
Finished Apr 28 03:22:01 PM PDT 24
Peak memory 199732 kb
Host smart-8dd305d0-ac34-4e05-b97f-6f91c6fabb7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221442083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3221442083
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3785525952
Short name T473
Test name
Test status
Simulation time 226487724 ps
CPU time 13.24 seconds
Started Apr 28 03:19:23 PM PDT 24
Finished Apr 28 03:19:37 PM PDT 24
Peak memory 199628 kb
Host smart-aceb241f-ad7f-4326-948f-d0fca44be7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785525952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3785525952
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3977708100
Short name T22
Test name
Test status
Simulation time 213146506 ps
CPU time 0.86 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:19:23 PM PDT 24
Peak memory 218108 kb
Host smart-bdfdcbba-9df9-4405-9814-7b40faf7f712
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977708100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3977708100
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3525887535
Short name T549
Test name
Test status
Simulation time 29186069 ps
CPU time 1.16 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:19:24 PM PDT 24
Peak memory 199612 kb
Host smart-73e95272-7a08-411c-9f4c-7ecc06b0129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525887535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3525887535
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.471757476
Short name T471
Test name
Test status
Simulation time 53774143783 ps
CPU time 1045.7 seconds
Started Apr 28 03:19:24 PM PDT 24
Finished Apr 28 03:36:50 PM PDT 24
Peak memory 199728 kb
Host smart-af148e92-7930-49fb-be8e-fe9bebc79dc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471757476 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.471757476
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2032704626
Short name T318
Test name
Test status
Simulation time 318758263 ps
CPU time 1.01 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:19:24 PM PDT 24
Peak memory 199332 kb
Host smart-ae135a0d-5bcd-4bb1-8dac-149580f15d4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032704626 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2032704626
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2565145826
Short name T206
Test name
Test status
Simulation time 7391630096 ps
CPU time 396.22 seconds
Started Apr 28 03:19:22 PM PDT 24
Finished Apr 28 03:25:59 PM PDT 24
Peak memory 199620 kb
Host smart-77b598f9-0dc5-43f4-87f6-cfcd20da5fda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565145826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2565145826
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.132141974
Short name T515
Test name
Test status
Simulation time 4472249772 ps
CPU time 89.26 seconds
Started Apr 28 03:19:25 PM PDT 24
Finished Apr 28 03:20:55 PM PDT 24
Peak memory 199724 kb
Host smart-6d0395dc-4709-490d-9ce7-4716d7f6dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132141974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.132141974
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3294386238
Short name T582
Test name
Test status
Simulation time 13033274 ps
CPU time 0.56 seconds
Started Apr 28 03:20:49 PM PDT 24
Finished Apr 28 03:20:50 PM PDT 24
Peak memory 195304 kb
Host smart-a8516be3-d5ce-4f58-8e04-c513517e0fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294386238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3294386238
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2790358684
Short name T52
Test name
Test status
Simulation time 3707333681 ps
CPU time 31.9 seconds
Started Apr 28 03:20:42 PM PDT 24
Finished Apr 28 03:21:14 PM PDT 24
Peak memory 215596 kb
Host smart-a0be9dec-b9a5-4b3b-a10e-524fa8a1b82a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790358684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2790358684
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.802888726
Short name T443
Test name
Test status
Simulation time 2176793530 ps
CPU time 23.24 seconds
Started Apr 28 03:20:40 PM PDT 24
Finished Apr 28 03:21:04 PM PDT 24
Peak memory 199740 kb
Host smart-f7facdc1-9f64-4376-b475-c7104ad8fd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802888726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.802888726
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2331073860
Short name T312
Test name
Test status
Simulation time 6361128696 ps
CPU time 91.91 seconds
Started Apr 28 03:20:40 PM PDT 24
Finished Apr 28 03:22:12 PM PDT 24
Peak memory 199660 kb
Host smart-8904f86e-c760-4d93-8335-bb655c4c6f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331073860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2331073860
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1738982323
Short name T113
Test name
Test status
Simulation time 9905544042 ps
CPU time 64.12 seconds
Started Apr 28 03:20:43 PM PDT 24
Finished Apr 28 03:21:48 PM PDT 24
Peak memory 199744 kb
Host smart-4b5c3b6b-b5bb-4741-9977-185b55090a54
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738982323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1738982323
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2272370863
Short name T545
Test name
Test status
Simulation time 9688741456 ps
CPU time 93.95 seconds
Started Apr 28 03:20:38 PM PDT 24
Finished Apr 28 03:22:13 PM PDT 24
Peak memory 199704 kb
Host smart-f271f1f1-38cb-4e1e-8be9-d5ed8c289256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272370863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2272370863
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3304249981
Short name T374
Test name
Test status
Simulation time 338289365 ps
CPU time 5.29 seconds
Started Apr 28 03:20:40 PM PDT 24
Finished Apr 28 03:20:46 PM PDT 24
Peak memory 199684 kb
Host smart-4a1eb2cb-b53e-4c78-90b4-049f0b9b4cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304249981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3304249981
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.807468637
Short name T181
Test name
Test status
Simulation time 115689773500 ps
CPU time 1031.13 seconds
Started Apr 28 03:20:39 PM PDT 24
Finished Apr 28 03:37:51 PM PDT 24
Peak memory 223876 kb
Host smart-3a7b2fc7-af78-4e5b-9e83-3298f789c934
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807468637 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.807468637
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1432036192
Short name T577
Test name
Test status
Simulation time 42310612 ps
CPU time 1.06 seconds
Started Apr 28 03:20:45 PM PDT 24
Finished Apr 28 03:20:47 PM PDT 24
Peak memory 199204 kb
Host smart-1c2e71e8-36b6-4c7f-80c3-9198ee0b6a96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432036192 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1432036192
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1815939483
Short name T422
Test name
Test status
Simulation time 109689212047 ps
CPU time 487.32 seconds
Started Apr 28 03:20:41 PM PDT 24
Finished Apr 28 03:28:49 PM PDT 24
Peak memory 199636 kb
Host smart-f4dc605f-7832-4c47-943d-36ff38e30964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815939483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1815939483
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.4079660460
Short name T38
Test name
Test status
Simulation time 70746106 ps
CPU time 0.78 seconds
Started Apr 28 03:20:44 PM PDT 24
Finished Apr 28 03:20:45 PM PDT 24
Peak memory 197352 kb
Host smart-ba410ee7-b918-4118-9e57-40bb72e03134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079660460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.4079660460
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1511770416
Short name T489
Test name
Test status
Simulation time 41652606 ps
CPU time 0.6 seconds
Started Apr 28 03:20:46 PM PDT 24
Finished Apr 28 03:20:47 PM PDT 24
Peak memory 195332 kb
Host smart-0cfc2d83-0288-4247-af41-e4e8c2227c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511770416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1511770416
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1153023812
Short name T451
Test name
Test status
Simulation time 2801453276 ps
CPU time 32.12 seconds
Started Apr 28 03:20:46 PM PDT 24
Finished Apr 28 03:21:19 PM PDT 24
Peak memory 226208 kb
Host smart-5c6c43ef-6835-46ee-916c-390416e25b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153023812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1153023812
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1147002586
Short name T346
Test name
Test status
Simulation time 87459818 ps
CPU time 1.77 seconds
Started Apr 28 03:20:46 PM PDT 24
Finished Apr 28 03:20:48 PM PDT 24
Peak memory 199644 kb
Host smart-ac059276-c5a9-4f81-8d9b-f07abfd6ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147002586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1147002586
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2625424455
Short name T60
Test name
Test status
Simulation time 755004324 ps
CPU time 40.33 seconds
Started Apr 28 03:20:44 PM PDT 24
Finished Apr 28 03:21:24 PM PDT 24
Peak memory 199628 kb
Host smart-08820211-e273-4b66-b565-bc9f50e5521f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625424455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2625424455
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.109835610
Short name T26
Test name
Test status
Simulation time 1958349370 ps
CPU time 109.97 seconds
Started Apr 28 03:20:50 PM PDT 24
Finished Apr 28 03:22:41 PM PDT 24
Peak memory 199640 kb
Host smart-540aacc2-f490-40c1-9e81-07c17902e52c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109835610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.109835610
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3888267882
Short name T510
Test name
Test status
Simulation time 2121262867 ps
CPU time 59.79 seconds
Started Apr 28 03:20:49 PM PDT 24
Finished Apr 28 03:21:49 PM PDT 24
Peak memory 199640 kb
Host smart-f7c72cc0-89c3-47e2-b801-1dce00990e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888267882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3888267882
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1571638923
Short name T579
Test name
Test status
Simulation time 296040055 ps
CPU time 4.05 seconds
Started Apr 28 03:20:45 PM PDT 24
Finished Apr 28 03:20:49 PM PDT 24
Peak memory 199668 kb
Host smart-63e2bdcf-1d3d-4796-ad86-154633485af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571638923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1571638923
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.114072594
Short name T202
Test name
Test status
Simulation time 453472084902 ps
CPU time 2077.14 seconds
Started Apr 28 03:20:47 PM PDT 24
Finished Apr 28 03:55:25 PM PDT 24
Peak memory 199764 kb
Host smart-a635dca2-0f71-4665-a22f-76b6d6fe93c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114072594 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.114072594
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1580321336
Short name T319
Test name
Test status
Simulation time 325917823 ps
CPU time 0.94 seconds
Started Apr 28 03:20:44 PM PDT 24
Finished Apr 28 03:20:46 PM PDT 24
Peak memory 198112 kb
Host smart-720e00d7-eee9-4894-ab20-b900e8d79cd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580321336 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1580321336
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1901626290
Short name T145
Test name
Test status
Simulation time 7470057271 ps
CPU time 423.19 seconds
Started Apr 28 03:20:45 PM PDT 24
Finished Apr 28 03:27:49 PM PDT 24
Peak memory 199636 kb
Host smart-724c2257-2822-4119-a3fe-a246edc34c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901626290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1901626290
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2718821739
Short name T497
Test name
Test status
Simulation time 1533235833 ps
CPU time 73.93 seconds
Started Apr 28 03:20:47 PM PDT 24
Finished Apr 28 03:22:02 PM PDT 24
Peak memory 199700 kb
Host smart-85e53e75-4dcc-4ad5-97d6-aedba04e1f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718821739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2718821739
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.485950422
Short name T388
Test name
Test status
Simulation time 24792822 ps
CPU time 0.56 seconds
Started Apr 28 03:20:50 PM PDT 24
Finished Apr 28 03:20:51 PM PDT 24
Peak memory 194340 kb
Host smart-ef25c1ca-43b2-46c4-b8ec-59ea0cee0293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485950422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.485950422
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.552546977
Short name T191
Test name
Test status
Simulation time 4363509575 ps
CPU time 39.38 seconds
Started Apr 28 03:20:46 PM PDT 24
Finished Apr 28 03:21:26 PM PDT 24
Peak memory 225312 kb
Host smart-08476ab8-729f-4651-b1cb-0b560604619a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552546977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.552546977
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.143094327
Short name T302
Test name
Test status
Simulation time 17112915140 ps
CPU time 64.4 seconds
Started Apr 28 03:20:51 PM PDT 24
Finished Apr 28 03:21:56 PM PDT 24
Peak memory 199696 kb
Host smart-2ed4283e-64fd-40f7-abeb-def0323882b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143094327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.143094327
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1687762675
Short name T501
Test name
Test status
Simulation time 5984506579 ps
CPU time 97.51 seconds
Started Apr 28 03:20:46 PM PDT 24
Finished Apr 28 03:22:24 PM PDT 24
Peak memory 199700 kb
Host smart-530689e0-7cb2-4844-92ae-60853e6ecc21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687762675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1687762675
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3059312241
Short name T350
Test name
Test status
Simulation time 48731878844 ps
CPU time 159.78 seconds
Started Apr 28 03:20:48 PM PDT 24
Finished Apr 28 03:23:28 PM PDT 24
Peak memory 199716 kb
Host smart-d7748737-90a9-4c05-b68e-0ad672f22091
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059312241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3059312241
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.967341356
Short name T4
Test name
Test status
Simulation time 7792058341 ps
CPU time 108.37 seconds
Started Apr 28 03:20:44 PM PDT 24
Finished Apr 28 03:22:33 PM PDT 24
Peak memory 199684 kb
Host smart-632dae6b-6d83-45a1-b0b4-99167cbab64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967341356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.967341356
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2563870640
Short name T83
Test name
Test status
Simulation time 1232197859 ps
CPU time 2.72 seconds
Started Apr 28 03:20:46 PM PDT 24
Finished Apr 28 03:20:49 PM PDT 24
Peak memory 199668 kb
Host smart-f6149182-1ac1-45b6-83be-e854f94c1274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563870640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2563870640
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1925937967
Short name T162
Test name
Test status
Simulation time 69969492786 ps
CPU time 210.7 seconds
Started Apr 28 03:20:49 PM PDT 24
Finished Apr 28 03:24:20 PM PDT 24
Peak memory 199712 kb
Host smart-5c22ffb0-6f7b-4f5c-84af-7820862ca9b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925937967 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1925937967
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1427258524
Short name T413
Test name
Test status
Simulation time 111091169 ps
CPU time 1.17 seconds
Started Apr 28 03:20:49 PM PDT 24
Finished Apr 28 03:20:51 PM PDT 24
Peak memory 199544 kb
Host smart-dbb38383-8fb7-4cbd-bdf3-69485cd38f19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427258524 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1427258524
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.4015642030
Short name T598
Test name
Test status
Simulation time 97729485407 ps
CPU time 501.73 seconds
Started Apr 28 03:20:49 PM PDT 24
Finished Apr 28 03:29:11 PM PDT 24
Peak memory 199664 kb
Host smart-657082e1-6daf-4ee2-a6d6-44a7f6ba2842
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015642030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.4015642030
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1112478691
Short name T401
Test name
Test status
Simulation time 2832294143 ps
CPU time 46.65 seconds
Started Apr 28 03:20:49 PM PDT 24
Finished Apr 28 03:21:36 PM PDT 24
Peak memory 199752 kb
Host smart-79711142-9d5c-4d92-956b-add31f0a82ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112478691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1112478691
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2343448357
Short name T313
Test name
Test status
Simulation time 13692824 ps
CPU time 0.57 seconds
Started Apr 28 03:20:54 PM PDT 24
Finished Apr 28 03:20:56 PM PDT 24
Peak memory 194312 kb
Host smart-b96aa651-9e6b-4114-b4d9-23a261611b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343448357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2343448357
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.97289681
Short name T227
Test name
Test status
Simulation time 2225397994 ps
CPU time 38.45 seconds
Started Apr 28 03:20:50 PM PDT 24
Finished Apr 28 03:21:29 PM PDT 24
Peak memory 221004 kb
Host smart-2030960e-e2fa-4fdc-b817-af2ece3af430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97289681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.97289681
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2848304769
Short name T527
Test name
Test status
Simulation time 266284328 ps
CPU time 5.02 seconds
Started Apr 28 03:20:51 PM PDT 24
Finished Apr 28 03:20:57 PM PDT 24
Peak memory 199660 kb
Host smart-763d0f24-7d41-49ae-a557-0a1cf6c568a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848304769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2848304769
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.477132166
Short name T5
Test name
Test status
Simulation time 1115795874 ps
CPU time 64.17 seconds
Started Apr 28 03:20:52 PM PDT 24
Finished Apr 28 03:21:56 PM PDT 24
Peak memory 199656 kb
Host smart-013a848d-270a-43a4-a94c-49bc7a279e2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477132166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.477132166
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2708925573
Short name T45
Test name
Test status
Simulation time 5150545887 ps
CPU time 75.17 seconds
Started Apr 28 03:20:50 PM PDT 24
Finished Apr 28 03:22:06 PM PDT 24
Peak memory 199724 kb
Host smart-78558ca0-3f16-41c5-a98d-d8fadde4936c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708925573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2708925573
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1676313000
Short name T296
Test name
Test status
Simulation time 8232572127 ps
CPU time 49.25 seconds
Started Apr 28 03:20:51 PM PDT 24
Finished Apr 28 03:21:40 PM PDT 24
Peak memory 199788 kb
Host smart-c258be30-333b-4c34-95b1-13c671e176e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676313000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1676313000
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1758761982
Short name T37
Test name
Test status
Simulation time 235396985 ps
CPU time 7.25 seconds
Started Apr 28 03:20:51 PM PDT 24
Finished Apr 28 03:20:59 PM PDT 24
Peak memory 199684 kb
Host smart-1b5f7a53-7f5b-4914-ace9-a35f7e14d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758761982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1758761982
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3777064297
Short name T44
Test name
Test status
Simulation time 7816087441 ps
CPU time 163.79 seconds
Started Apr 28 03:20:57 PM PDT 24
Finished Apr 28 03:23:41 PM PDT 24
Peak memory 216056 kb
Host smart-ed4d2cd9-69fc-4b9d-be20-727e6912a130
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777064297 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3777064297
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3902173614
Short name T540
Test name
Test status
Simulation time 27799056 ps
CPU time 1.02 seconds
Started Apr 28 03:20:56 PM PDT 24
Finished Apr 28 03:20:57 PM PDT 24
Peak memory 199112 kb
Host smart-9d78d6fe-b5ae-4acf-a92c-e056d69fd58d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902173614 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3902173614
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2515051742
Short name T183
Test name
Test status
Simulation time 88537154022 ps
CPU time 501.91 seconds
Started Apr 28 03:20:58 PM PDT 24
Finished Apr 28 03:29:21 PM PDT 24
Peak memory 199740 kb
Host smart-e9236806-0be8-4ca6-b617-70495aa69121
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515051742 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2515051742
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2897088881
Short name T166
Test name
Test status
Simulation time 1758944604 ps
CPU time 78.75 seconds
Started Apr 28 03:20:51 PM PDT 24
Finished Apr 28 03:22:10 PM PDT 24
Peak memory 199668 kb
Host smart-b660cdc5-aec3-45d1-b208-f471410854ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897088881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2897088881
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1197721049
Short name T485
Test name
Test status
Simulation time 38087006 ps
CPU time 0.58 seconds
Started Apr 28 03:20:57 PM PDT 24
Finished Apr 28 03:20:58 PM PDT 24
Peak memory 195392 kb
Host smart-f60ffa94-e9a8-43be-96fe-ed28671f4412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197721049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1197721049
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2850302885
Short name T567
Test name
Test status
Simulation time 5606019210 ps
CPU time 60.99 seconds
Started Apr 28 03:20:57 PM PDT 24
Finished Apr 28 03:21:59 PM PDT 24
Peak memory 232520 kb
Host smart-da8db4f2-a11f-40cb-ac4d-7b56ca629d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850302885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2850302885
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1197717864
Short name T3
Test name
Test status
Simulation time 847481339 ps
CPU time 20.63 seconds
Started Apr 28 03:20:57 PM PDT 24
Finished Apr 28 03:21:18 PM PDT 24
Peak memory 199708 kb
Host smart-6ced8b05-650a-4669-bcf7-6f92484c33ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197717864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1197717864
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1726663217
Short name T173
Test name
Test status
Simulation time 2637843392 ps
CPU time 157.67 seconds
Started Apr 28 03:20:55 PM PDT 24
Finished Apr 28 03:23:33 PM PDT 24
Peak memory 199764 kb
Host smart-00076cf8-63da-4d42-9ac5-796c3cf76081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726663217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1726663217
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.740588113
Short name T174
Test name
Test status
Simulation time 20865238828 ps
CPU time 136.45 seconds
Started Apr 28 03:20:54 PM PDT 24
Finished Apr 28 03:23:11 PM PDT 24
Peak memory 199720 kb
Host smart-b6743c8d-aecf-415c-bfa5-3ae9610b3507
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740588113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.740588113
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1384221263
Short name T599
Test name
Test status
Simulation time 2233421964 ps
CPU time 64.33 seconds
Started Apr 28 03:20:54 PM PDT 24
Finished Apr 28 03:21:59 PM PDT 24
Peak memory 199696 kb
Host smart-eedb0330-3790-4f5b-adcd-e83bb4b90ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384221263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1384221263
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2427778496
Short name T254
Test name
Test status
Simulation time 163640975 ps
CPU time 4.95 seconds
Started Apr 28 03:20:55 PM PDT 24
Finished Apr 28 03:21:00 PM PDT 24
Peak memory 199668 kb
Host smart-583eb5a3-5e83-4915-b644-5d58d9d430ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427778496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2427778496
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.963192517
Short name T445
Test name
Test status
Simulation time 42207772866 ps
CPU time 2403.75 seconds
Started Apr 28 03:20:54 PM PDT 24
Finished Apr 28 04:00:59 PM PDT 24
Peak memory 228016 kb
Host smart-a40ccad4-f14d-4f36-961b-27ff87b516a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963192517 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.963192517
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3060246478
Short name T526
Test name
Test status
Simulation time 144998864 ps
CPU time 1.27 seconds
Started Apr 28 03:20:55 PM PDT 24
Finished Apr 28 03:20:57 PM PDT 24
Peak memory 199540 kb
Host smart-35222a2f-acab-42e5-9e8f-68492986f274
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060246478 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3060246478
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2167957367
Short name T245
Test name
Test status
Simulation time 61626965157 ps
CPU time 399.12 seconds
Started Apr 28 03:20:56 PM PDT 24
Finished Apr 28 03:27:36 PM PDT 24
Peak memory 199696 kb
Host smart-60ef45f9-aef6-4703-a6cd-6a9153e124d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167957367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2167957367
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3835248971
Short name T262
Test name
Test status
Simulation time 1970624736 ps
CPU time 37.88 seconds
Started Apr 28 03:20:54 PM PDT 24
Finished Apr 28 03:21:32 PM PDT 24
Peak memory 199688 kb
Host smart-083af2ee-1537-4e82-9e09-0a1cecb29452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835248971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3835248971
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3313468917
Short name T274
Test name
Test status
Simulation time 38110362 ps
CPU time 0.57 seconds
Started Apr 28 03:21:00 PM PDT 24
Finished Apr 28 03:21:01 PM PDT 24
Peak memory 195416 kb
Host smart-c66f950e-ef50-49b1-b664-38af36ca7731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313468917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3313468917
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.751330218
Short name T151
Test name
Test status
Simulation time 17448444140 ps
CPU time 41.83 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:21:42 PM PDT 24
Peak memory 222180 kb
Host smart-7d41b840-f55e-4b56-9518-fde4a75e777d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751330218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.751330218
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2920614417
Short name T266
Test name
Test status
Simulation time 1017645962 ps
CPU time 50.91 seconds
Started Apr 28 03:20:58 PM PDT 24
Finished Apr 28 03:21:50 PM PDT 24
Peak memory 199628 kb
Host smart-e49119b0-6a12-460b-9e56-77686638aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920614417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2920614417
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.461654571
Short name T383
Test name
Test status
Simulation time 2757637025 ps
CPU time 67.39 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:22:07 PM PDT 24
Peak memory 199668 kb
Host smart-ebc2b3a0-da6b-4f13-bfda-558048c29cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461654571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.461654571
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1606549012
Short name T441
Test name
Test status
Simulation time 4326972507 ps
CPU time 240.17 seconds
Started Apr 28 03:20:58 PM PDT 24
Finished Apr 28 03:24:59 PM PDT 24
Peak memory 199688 kb
Host smart-2e808615-ecf3-4238-ac62-2e6ea60bd216
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606549012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1606549012
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1458903016
Short name T563
Test name
Test status
Simulation time 1520840729 ps
CPU time 37.05 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:21:36 PM PDT 24
Peak memory 199652 kb
Host smart-fd578329-782d-4cf6-b1e4-ae5b23788237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458903016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1458903016
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.93767289
Short name T277
Test name
Test status
Simulation time 591885384 ps
CPU time 2.17 seconds
Started Apr 28 03:20:58 PM PDT 24
Finished Apr 28 03:21:01 PM PDT 24
Peak memory 199596 kb
Host smart-fe961547-2dbf-4ffa-8800-a3984da3281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93767289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.93767289
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.891386000
Short name T525
Test name
Test status
Simulation time 273505482379 ps
CPU time 1228.51 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:41:29 PM PDT 24
Peak memory 199760 kb
Host smart-6ff13d7c-98ce-4770-bfc9-89502d95c584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891386000 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.891386000
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1631691565
Short name T437
Test name
Test status
Simulation time 103730442 ps
CPU time 0.99 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:21:01 PM PDT 24
Peak memory 199368 kb
Host smart-5757a69d-abd5-4fb3-ab11-a2f50db2e94d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631691565 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1631691565
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2843072950
Short name T212
Test name
Test status
Simulation time 164818938365 ps
CPU time 520.06 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:29:40 PM PDT 24
Peak memory 199640 kb
Host smart-46336c95-0e4a-4d0c-9e68-ef107c831dfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843072950 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2843072950
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1001882489
Short name T40
Test name
Test status
Simulation time 955000378 ps
CPU time 41.01 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:21:41 PM PDT 24
Peak memory 199660 kb
Host smart-f186dfc6-026c-46e2-b7ad-926e4499f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001882489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1001882489
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2182195378
Short name T121
Test name
Test status
Simulation time 33205239 ps
CPU time 0.58 seconds
Started Apr 28 03:21:03 PM PDT 24
Finished Apr 28 03:21:04 PM PDT 24
Peak memory 195328 kb
Host smart-2e006356-848d-4d38-80a5-ae206442a36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182195378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2182195378
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1548436136
Short name T294
Test name
Test status
Simulation time 1545419782 ps
CPU time 55.37 seconds
Started Apr 28 03:20:58 PM PDT 24
Finished Apr 28 03:21:54 PM PDT 24
Peak memory 232164 kb
Host smart-05e4b247-697b-49a0-a5aa-66f07a30f067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548436136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1548436136
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3596598737
Short name T185
Test name
Test status
Simulation time 1738554433 ps
CPU time 35.3 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:21:35 PM PDT 24
Peak memory 199672 kb
Host smart-19718809-7f3c-4c04-a639-647d5acad039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596598737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3596598737
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2223817366
Short name T361
Test name
Test status
Simulation time 1391374885 ps
CPU time 36.24 seconds
Started Apr 28 03:21:01 PM PDT 24
Finished Apr 28 03:21:37 PM PDT 24
Peak memory 199680 kb
Host smart-2b9c13c7-9792-4c19-89f4-c4757fb3e13d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223817366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2223817366
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.616625766
Short name T141
Test name
Test status
Simulation time 47764062134 ps
CPU time 223.67 seconds
Started Apr 28 03:21:00 PM PDT 24
Finished Apr 28 03:24:44 PM PDT 24
Peak memory 199748 kb
Host smart-8df9eae1-eef1-49ab-be59-b92cbf34675d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616625766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.616625766
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.605764282
Short name T282
Test name
Test status
Simulation time 4177166049 ps
CPU time 23.29 seconds
Started Apr 28 03:21:01 PM PDT 24
Finished Apr 28 03:21:24 PM PDT 24
Peak memory 199708 kb
Host smart-f1741e36-6710-427e-b31b-83143d3d2ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605764282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.605764282
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1072062551
Short name T424
Test name
Test status
Simulation time 420256833 ps
CPU time 6.41 seconds
Started Apr 28 03:20:59 PM PDT 24
Finished Apr 28 03:21:06 PM PDT 24
Peak memory 199656 kb
Host smart-6012734e-8a4f-41e5-8172-c815cf0f1663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072062551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1072062551
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.724458302
Short name T21
Test name
Test status
Simulation time 28951230524 ps
CPU time 742.77 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:33:29 PM PDT 24
Peak memory 199688 kb
Host smart-e4758c4a-9d28-494c-a4bc-81972bba2434
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724458302 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.724458302
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1844516299
Short name T380
Test name
Test status
Simulation time 377460070 ps
CPU time 1.35 seconds
Started Apr 28 03:21:04 PM PDT 24
Finished Apr 28 03:21:06 PM PDT 24
Peak memory 198840 kb
Host smart-bc2779c1-c0cd-44ee-a692-6d207a73674d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844516299 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1844516299
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2172581048
Short name T461
Test name
Test status
Simulation time 32274470992 ps
CPU time 495.12 seconds
Started Apr 28 03:21:11 PM PDT 24
Finished Apr 28 03:29:26 PM PDT 24
Peak memory 199624 kb
Host smart-3870e8ee-b69a-4207-882f-56c0ac6ca788
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172581048 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2172581048
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2651039353
Short name T332
Test name
Test status
Simulation time 1999531900 ps
CPU time 36.45 seconds
Started Apr 28 03:21:02 PM PDT 24
Finished Apr 28 03:21:39 PM PDT 24
Peak memory 199636 kb
Host smart-8f8c6b93-f1f6-41da-9bb6-aa880b559b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651039353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2651039353
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1452328508
Short name T481
Test name
Test status
Simulation time 44709421 ps
CPU time 0.6 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:21:06 PM PDT 24
Peak memory 195332 kb
Host smart-e1c94fcd-6096-428c-b78a-a95c732108ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452328508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1452328508
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1557091757
Short name T565
Test name
Test status
Simulation time 148521879 ps
CPU time 1.6 seconds
Started Apr 28 03:21:04 PM PDT 24
Finished Apr 28 03:21:06 PM PDT 24
Peak memory 199676 kb
Host smart-f079f46d-3064-4287-828d-791163506237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557091757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1557091757
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.353914604
Short name T156
Test name
Test status
Simulation time 1383533235 ps
CPU time 19.61 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:21:25 PM PDT 24
Peak memory 199660 kb
Host smart-a66c41b5-5cdc-4d37-adab-998d640839da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353914604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.353914604
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2782804396
Short name T222
Test name
Test status
Simulation time 3618628304 ps
CPU time 57.38 seconds
Started Apr 28 03:21:04 PM PDT 24
Finished Apr 28 03:22:02 PM PDT 24
Peak memory 199724 kb
Host smart-11f90b20-3e3c-4ac5-8bc3-cdf661c967c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782804396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2782804396
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3244191675
Short name T226
Test name
Test status
Simulation time 3959955118 ps
CPU time 213.23 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:24:39 PM PDT 24
Peak memory 199764 kb
Host smart-d52feea7-fc09-4fe4-a8ba-6e6f0864ce8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244191675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3244191675
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2100341091
Short name T530
Test name
Test status
Simulation time 30068148323 ps
CPU time 109.73 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:22:55 PM PDT 24
Peak memory 199672 kb
Host smart-dbb5c891-3da4-4b73-ad21-1617ff16b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100341091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2100341091
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1801459602
Short name T130
Test name
Test status
Simulation time 84892875 ps
CPU time 0.79 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:21:06 PM PDT 24
Peak memory 196936 kb
Host smart-e5579b7a-f76a-4e97-bce7-2b378da16248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801459602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1801459602
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.976196984
Short name T230
Test name
Test status
Simulation time 6657526671 ps
CPU time 74.9 seconds
Started Apr 28 03:21:03 PM PDT 24
Finished Apr 28 03:22:18 PM PDT 24
Peak memory 215656 kb
Host smart-75a2819b-c3e3-494d-82a2-0835d6f70c6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976196984 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.976196984
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2787654990
Short name T398
Test name
Test status
Simulation time 105911055 ps
CPU time 1.01 seconds
Started Apr 28 03:21:03 PM PDT 24
Finished Apr 28 03:21:05 PM PDT 24
Peak memory 199324 kb
Host smart-a7ba64f7-956f-44ea-8810-ed4ce19b4274
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787654990 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2787654990
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2106949715
Short name T165
Test name
Test status
Simulation time 101380897862 ps
CPU time 432.16 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:28:18 PM PDT 24
Peak memory 199704 kb
Host smart-db572037-7550-4757-ae6e-48101f8cbbd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106949715 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.2106949715
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1968825569
Short name T125
Test name
Test status
Simulation time 9696462395 ps
CPU time 49.29 seconds
Started Apr 28 03:21:03 PM PDT 24
Finished Apr 28 03:21:53 PM PDT 24
Peak memory 199760 kb
Host smart-0ca10289-e54a-49bd-8202-cd3734f1e1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968825569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1968825569
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.4152125887
Short name T251
Test name
Test status
Simulation time 12190165 ps
CPU time 0.58 seconds
Started Apr 28 03:21:09 PM PDT 24
Finished Apr 28 03:21:10 PM PDT 24
Peak memory 195280 kb
Host smart-f9f206e3-40fd-47f8-b116-212c083cb055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152125887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4152125887
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3810153520
Short name T175
Test name
Test status
Simulation time 505846534 ps
CPU time 9.1 seconds
Started Apr 28 03:21:09 PM PDT 24
Finished Apr 28 03:21:19 PM PDT 24
Peak memory 199644 kb
Host smart-b2f950eb-3776-44cd-8020-9d23c3bc01e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810153520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3810153520
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4009773718
Short name T507
Test name
Test status
Simulation time 704983871 ps
CPU time 35.55 seconds
Started Apr 28 03:21:08 PM PDT 24
Finished Apr 28 03:21:44 PM PDT 24
Peak memory 199680 kb
Host smart-01fb4fb0-c1cc-40a7-8d19-44a8c4d4dabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009773718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4009773718
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.89506799
Short name T511
Test name
Test status
Simulation time 1454759584 ps
CPU time 97.03 seconds
Started Apr 28 03:21:09 PM PDT 24
Finished Apr 28 03:22:47 PM PDT 24
Peak memory 199648 kb
Host smart-fe6300bc-5eec-411f-9df6-ffec13f214bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89506799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.89506799
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1509282029
Short name T281
Test name
Test status
Simulation time 78096578195 ps
CPU time 152.21 seconds
Started Apr 28 03:21:09 PM PDT 24
Finished Apr 28 03:23:41 PM PDT 24
Peak memory 199716 kb
Host smart-b95e6e71-144f-4872-8df9-3ce702c1ef6c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509282029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1509282029
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1762075153
Short name T478
Test name
Test status
Simulation time 3387369869 ps
CPU time 47.51 seconds
Started Apr 28 03:21:07 PM PDT 24
Finished Apr 28 03:21:55 PM PDT 24
Peak memory 199660 kb
Host smart-025d6bfe-8ad9-47ce-9127-08cad4609f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762075153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1762075153
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2212762088
Short name T365
Test name
Test status
Simulation time 1998246836 ps
CPU time 5.69 seconds
Started Apr 28 03:21:05 PM PDT 24
Finished Apr 28 03:21:12 PM PDT 24
Peak memory 199652 kb
Host smart-f146ab6a-2717-407b-868c-d82ad547b242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212762088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2212762088
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3259896009
Short name T391
Test name
Test status
Simulation time 39610586745 ps
CPU time 2464.25 seconds
Started Apr 28 03:21:09 PM PDT 24
Finished Apr 28 04:02:14 PM PDT 24
Peak memory 224348 kb
Host smart-5f53904e-125f-4af3-b9f5-dc3460c09e80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259896009 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3259896009
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.798455024
Short name T261
Test name
Test status
Simulation time 32962008 ps
CPU time 1.15 seconds
Started Apr 28 03:21:09 PM PDT 24
Finished Apr 28 03:21:11 PM PDT 24
Peak memory 199572 kb
Host smart-c0e3d74d-c711-42d6-a724-e324edd63903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798455024 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.798455024
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2741591898
Short name T197
Test name
Test status
Simulation time 28981421015 ps
CPU time 520.33 seconds
Started Apr 28 03:21:10 PM PDT 24
Finished Apr 28 03:29:51 PM PDT 24
Peak memory 199668 kb
Host smart-ed581b72-7c18-4710-9ebb-012b3967d5e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741591898 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.2741591898
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3851383340
Short name T184
Test name
Test status
Simulation time 1145897559 ps
CPU time 55.91 seconds
Started Apr 28 03:21:08 PM PDT 24
Finished Apr 28 03:22:05 PM PDT 24
Peak memory 199616 kb
Host smart-257fd842-5553-4d61-ad6a-7e209a6ebb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851383340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3851383340
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.591400064
Short name T418
Test name
Test status
Simulation time 37484933 ps
CPU time 0.59 seconds
Started Apr 28 03:21:17 PM PDT 24
Finished Apr 28 03:21:18 PM PDT 24
Peak memory 195368 kb
Host smart-ee6b400e-686f-4ceb-a1b2-c27045b9adc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591400064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.591400064
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4217317958
Short name T449
Test name
Test status
Simulation time 1352453144 ps
CPU time 45.29 seconds
Started Apr 28 03:21:13 PM PDT 24
Finished Apr 28 03:21:58 PM PDT 24
Peak memory 216088 kb
Host smart-18ca280a-50c5-4b36-b451-a3018ca9a0d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217317958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4217317958
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2496563107
Short name T455
Test name
Test status
Simulation time 30629720290 ps
CPU time 57.68 seconds
Started Apr 28 03:21:18 PM PDT 24
Finished Apr 28 03:22:17 PM PDT 24
Peak memory 199744 kb
Host smart-bfd0f36e-43a4-4fb7-9957-f54eaed09ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496563107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2496563107
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2424972839
Short name T603
Test name
Test status
Simulation time 2805657357 ps
CPU time 83.07 seconds
Started Apr 28 03:21:15 PM PDT 24
Finished Apr 28 03:22:38 PM PDT 24
Peak memory 199764 kb
Host smart-ad78a3a3-2fb7-4e95-b26a-cde0b727adf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424972839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2424972839
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1530025008
Short name T272
Test name
Test status
Simulation time 1842795705 ps
CPU time 32.92 seconds
Started Apr 28 03:21:18 PM PDT 24
Finished Apr 28 03:21:51 PM PDT 24
Peak memory 199504 kb
Host smart-559683d4-b23a-4ac6-bf1f-6076039e8537
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530025008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1530025008
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3405731504
Short name T569
Test name
Test status
Simulation time 6925898173 ps
CPU time 89.96 seconds
Started Apr 28 03:21:13 PM PDT 24
Finished Apr 28 03:22:43 PM PDT 24
Peak memory 199736 kb
Host smart-5ebc38c2-369b-4926-84b9-b6d32fd3c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405731504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3405731504
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1653719946
Short name T124
Test name
Test status
Simulation time 416613669 ps
CPU time 6.76 seconds
Started Apr 28 03:21:15 PM PDT 24
Finished Apr 28 03:21:22 PM PDT 24
Peak memory 199648 kb
Host smart-31b3d303-7e1c-4242-915f-5a06a7fabc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653719946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1653719946
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4053461835
Short name T279
Test name
Test status
Simulation time 67784668477 ps
CPU time 611.72 seconds
Started Apr 28 03:21:18 PM PDT 24
Finished Apr 28 03:31:30 PM PDT 24
Peak memory 199728 kb
Host smart-68272aad-3a6a-4fb1-880f-b15b30794b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053461835 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4053461835
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3057658900
Short name T385
Test name
Test status
Simulation time 49884060 ps
CPU time 0.97 seconds
Started Apr 28 03:21:18 PM PDT 24
Finished Apr 28 03:21:20 PM PDT 24
Peak memory 198324 kb
Host smart-c3607726-5a0a-405f-a4bf-7e70755ef194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057658900 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3057658900
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2015433357
Short name T131
Test name
Test status
Simulation time 87941040932 ps
CPU time 431.12 seconds
Started Apr 28 03:21:20 PM PDT 24
Finished Apr 28 03:28:31 PM PDT 24
Peak memory 199700 kb
Host smart-3f513fdb-dae7-4fee-a9cb-8916160ff323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015433357 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2015433357
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.164834399
Short name T169
Test name
Test status
Simulation time 591529530 ps
CPU time 3.66 seconds
Started Apr 28 03:21:19 PM PDT 24
Finished Apr 28 03:21:23 PM PDT 24
Peak memory 199624 kb
Host smart-fe545cfa-e49a-4edd-862a-50140109fba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164834399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.164834399
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4281971854
Short name T290
Test name
Test status
Simulation time 62909085 ps
CPU time 0.55 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:19:37 PM PDT 24
Peak memory 195308 kb
Host smart-4439afdb-5982-4abb-95fe-b1d70b293123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281971854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4281971854
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.556749809
Short name T228
Test name
Test status
Simulation time 1492811248 ps
CPU time 12.2 seconds
Started Apr 28 03:19:26 PM PDT 24
Finished Apr 28 03:19:39 PM PDT 24
Peak memory 215280 kb
Host smart-7d3b8c72-1fb9-4d97-9409-96877a65032f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556749809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.556749809
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1834619645
Short name T142
Test name
Test status
Simulation time 929717157 ps
CPU time 11.14 seconds
Started Apr 28 03:19:29 PM PDT 24
Finished Apr 28 03:19:40 PM PDT 24
Peak memory 199624 kb
Host smart-add075ee-b6b4-43b8-933b-0dbce559ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834619645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1834619645
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1333431669
Short name T187
Test name
Test status
Simulation time 3731367035 ps
CPU time 45.99 seconds
Started Apr 28 03:19:29 PM PDT 24
Finished Apr 28 03:20:15 PM PDT 24
Peak memory 199692 kb
Host smart-1b09b3bf-2ba8-4cf0-bbeb-8c6de54640df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333431669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1333431669
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1666592927
Short name T572
Test name
Test status
Simulation time 92336237614 ps
CPU time 150.21 seconds
Started Apr 28 03:19:26 PM PDT 24
Finished Apr 28 03:21:57 PM PDT 24
Peak memory 199660 kb
Host smart-e64e0523-d708-4ce1-ac8c-95295acf6a36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666592927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1666592927
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1763597502
Short name T521
Test name
Test status
Simulation time 970884904 ps
CPU time 54.79 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:20:24 PM PDT 24
Peak memory 199680 kb
Host smart-e4eea103-7e95-4139-a2e4-3a9a49ccb334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763597502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1763597502
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1126783645
Short name T33
Test name
Test status
Simulation time 336192303 ps
CPU time 0.96 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:19:29 PM PDT 24
Peak memory 219128 kb
Host smart-5b29545b-84c9-4a74-974b-a19cd6e761cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126783645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1126783645
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4121542808
Short name T139
Test name
Test status
Simulation time 598917094 ps
CPU time 4.68 seconds
Started Apr 28 03:19:26 PM PDT 24
Finished Apr 28 03:19:31 PM PDT 24
Peak memory 199664 kb
Host smart-442acf8e-ee7a-4651-a755-e52c3213c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121542808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4121542808
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.949568471
Short name T69
Test name
Test status
Simulation time 9619978128 ps
CPU time 485.01 seconds
Started Apr 28 03:19:27 PM PDT 24
Finished Apr 28 03:27:33 PM PDT 24
Peak memory 248024 kb
Host smart-e1157fe5-271e-4c8a-8fe5-b9c170096b94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949568471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.949568471
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1570489755
Short name T429
Test name
Test status
Simulation time 89539779 ps
CPU time 0.96 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:19:30 PM PDT 24
Peak memory 198220 kb
Host smart-cfc81247-1d2c-41e0-8ed6-e255f1d443d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570489755 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1570489755
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.67715155
Short name T196
Test name
Test status
Simulation time 188827130703 ps
CPU time 545.95 seconds
Started Apr 28 03:19:30 PM PDT 24
Finished Apr 28 03:28:36 PM PDT 24
Peak memory 199672 kb
Host smart-62cbd77e-383d-4adc-9a16-534fb3b86763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67715155 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.67715155
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1185755704
Short name T364
Test name
Test status
Simulation time 211543614 ps
CPU time 7.82 seconds
Started Apr 28 03:19:27 PM PDT 24
Finished Apr 28 03:19:36 PM PDT 24
Peak memory 199704 kb
Host smart-6017e10b-cee0-4de3-91ad-4f5dd65015e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185755704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1185755704
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3238078368
Short name T247
Test name
Test status
Simulation time 27341666 ps
CPU time 0.57 seconds
Started Apr 28 03:21:22 PM PDT 24
Finished Apr 28 03:21:23 PM PDT 24
Peak memory 195364 kb
Host smart-639d9102-5c35-45ad-afa6-1536a3517042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238078368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3238078368
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3222669306
Short name T54
Test name
Test status
Simulation time 1487521582 ps
CPU time 59.88 seconds
Started Apr 28 03:21:17 PM PDT 24
Finished Apr 28 03:22:17 PM PDT 24
Peak memory 221900 kb
Host smart-631fba10-d546-4b64-8cd7-5fb516628491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222669306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3222669306
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2959041997
Short name T331
Test name
Test status
Simulation time 1311024761 ps
CPU time 19.99 seconds
Started Apr 28 03:21:19 PM PDT 24
Finished Apr 28 03:21:39 PM PDT 24
Peak memory 199648 kb
Host smart-7ada11ea-f34f-4f3a-96c2-3c59ed46594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959041997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2959041997
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1505520587
Short name T215
Test name
Test status
Simulation time 10172276735 ps
CPU time 157.22 seconds
Started Apr 28 03:21:19 PM PDT 24
Finished Apr 28 03:23:56 PM PDT 24
Peak memory 199748 kb
Host smart-6110c75a-55b4-49fa-bd7b-feba2c796070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505520587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1505520587
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2744076222
Short name T25
Test name
Test status
Simulation time 30332548275 ps
CPU time 203.24 seconds
Started Apr 28 03:21:18 PM PDT 24
Finished Apr 28 03:24:41 PM PDT 24
Peak memory 199688 kb
Host smart-81054f40-c8c4-4c76-9d6e-67c832ecee6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744076222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2744076222
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1724273599
Short name T289
Test name
Test status
Simulation time 2928439372 ps
CPU time 88.26 seconds
Started Apr 28 03:21:16 PM PDT 24
Finished Apr 28 03:22:45 PM PDT 24
Peak memory 199728 kb
Host smart-0b032917-dc69-4217-9fd9-004a692b37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724273599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1724273599
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2480128029
Short name T439
Test name
Test status
Simulation time 249394615 ps
CPU time 2.09 seconds
Started Apr 28 03:21:20 PM PDT 24
Finished Apr 28 03:21:22 PM PDT 24
Peak memory 199652 kb
Host smart-ec527877-02a3-499b-8323-da59c59be8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480128029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2480128029
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2482507233
Short name T50
Test name
Test status
Simulation time 106905160899 ps
CPU time 1401.89 seconds
Started Apr 28 03:21:25 PM PDT 24
Finished Apr 28 03:44:48 PM PDT 24
Peak memory 239904 kb
Host smart-4ca62132-0a84-42e4-9fb9-50c7e1bd227f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482507233 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2482507233
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2297798291
Short name T203
Test name
Test status
Simulation time 194387602 ps
CPU time 1.1 seconds
Started Apr 28 03:21:22 PM PDT 24
Finished Apr 28 03:21:24 PM PDT 24
Peak memory 199400 kb
Host smart-28d309c4-7f90-4762-8264-5015a4750554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297798291 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2297798291
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2369103839
Short name T120
Test name
Test status
Simulation time 30992472111 ps
CPU time 452.43 seconds
Started Apr 28 03:21:22 PM PDT 24
Finished Apr 28 03:28:55 PM PDT 24
Peak memory 199680 kb
Host smart-f8526f69-75ed-4f0e-9248-6697f58bc58f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369103839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2369103839
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2763605743
Short name T221
Test name
Test status
Simulation time 24770554458 ps
CPU time 81.37 seconds
Started Apr 28 03:21:21 PM PDT 24
Finished Apr 28 03:22:43 PM PDT 24
Peak memory 199732 kb
Host smart-da91cf05-1100-43ae-87c4-f60115bc5f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763605743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2763605743
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.451401943
Short name T271
Test name
Test status
Simulation time 11192229 ps
CPU time 0.56 seconds
Started Apr 28 03:21:20 PM PDT 24
Finished Apr 28 03:21:21 PM PDT 24
Peak memory 195252 kb
Host smart-b4486597-c8fb-4c3f-84f8-dc4c2fa4f58f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451401943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.451401943
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2006411033
Short name T359
Test name
Test status
Simulation time 6006335950 ps
CPU time 57.68 seconds
Started Apr 28 03:21:22 PM PDT 24
Finished Apr 28 03:22:20 PM PDT 24
Peak memory 240668 kb
Host smart-a0d228d0-5857-4874-8ce8-42477bfd71f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006411033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2006411033
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3119884121
Short name T314
Test name
Test status
Simulation time 723017380 ps
CPU time 5.36 seconds
Started Apr 28 03:21:24 PM PDT 24
Finished Apr 28 03:21:30 PM PDT 24
Peak memory 199632 kb
Host smart-264b2a2c-01c9-48bc-9219-99d45e585842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119884121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3119884121
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1984306605
Short name T293
Test name
Test status
Simulation time 8730509565 ps
CPU time 133.5 seconds
Started Apr 28 03:21:24 PM PDT 24
Finished Apr 28 03:23:38 PM PDT 24
Peak memory 199716 kb
Host smart-7e386f21-45c7-4e68-80f7-7513309a1bb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984306605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1984306605
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2529548510
Short name T420
Test name
Test status
Simulation time 7972226961 ps
CPU time 80.83 seconds
Started Apr 28 03:21:22 PM PDT 24
Finished Apr 28 03:22:43 PM PDT 24
Peak memory 199724 kb
Host smart-d7be68db-0c2b-4844-b1af-03d94b1ed67c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529548510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2529548510
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1913005499
Short name T503
Test name
Test status
Simulation time 25447536987 ps
CPU time 93.16 seconds
Started Apr 28 03:21:21 PM PDT 24
Finished Apr 28 03:22:55 PM PDT 24
Peak memory 199736 kb
Host smart-6d004e33-92ca-4fc5-92f8-0d67f865348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913005499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1913005499
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.473028530
Short name T552
Test name
Test status
Simulation time 413602826 ps
CPU time 5.89 seconds
Started Apr 28 03:21:21 PM PDT 24
Finished Apr 28 03:21:27 PM PDT 24
Peak memory 199688 kb
Host smart-f3b7b5ef-c266-450c-94b8-d21f10df1495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473028530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.473028530
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.654326087
Short name T460
Test name
Test status
Simulation time 347536241718 ps
CPU time 1125.93 seconds
Started Apr 28 03:21:23 PM PDT 24
Finished Apr 28 03:40:09 PM PDT 24
Peak memory 248136 kb
Host smart-583306f4-cce3-4c54-854f-c1e3eb3767b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654326087 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.654326087
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2469082805
Short name T116
Test name
Test status
Simulation time 38382020 ps
CPU time 1.17 seconds
Started Apr 28 03:21:21 PM PDT 24
Finished Apr 28 03:21:22 PM PDT 24
Peak memory 199608 kb
Host smart-72970ecb-fb24-46e0-acbe-a71974bff7fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469082805 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2469082805
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.196271571
Short name T558
Test name
Test status
Simulation time 37671277792 ps
CPU time 466.6 seconds
Started Apr 28 03:21:22 PM PDT 24
Finished Apr 28 03:29:10 PM PDT 24
Peak memory 199684 kb
Host smart-0f962595-70b1-4181-a593-ec4b43d6b965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196271571 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.196271571
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.4190527486
Short name T495
Test name
Test status
Simulation time 818454502 ps
CPU time 14.88 seconds
Started Apr 28 03:21:22 PM PDT 24
Finished Apr 28 03:21:37 PM PDT 24
Peak memory 199612 kb
Host smart-992f5c66-13ab-458c-943e-bfd6304321a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190527486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4190527486
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2398390857
Short name T360
Test name
Test status
Simulation time 94395120 ps
CPU time 0.58 seconds
Started Apr 28 03:21:27 PM PDT 24
Finished Apr 28 03:21:28 PM PDT 24
Peak memory 195388 kb
Host smart-cb90502a-909b-41d9-9a5a-6b22eb8780b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398390857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2398390857
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3418442956
Short name T491
Test name
Test status
Simulation time 648568505 ps
CPU time 35.16 seconds
Started Apr 28 03:21:26 PM PDT 24
Finished Apr 28 03:22:02 PM PDT 24
Peak memory 240552 kb
Host smart-6b9bb325-bbfd-43d6-b029-e7b34ef726b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418442956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3418442956
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1113095464
Short name T119
Test name
Test status
Simulation time 4070622009 ps
CPU time 42.42 seconds
Started Apr 28 03:21:27 PM PDT 24
Finished Apr 28 03:22:10 PM PDT 24
Peak memory 199804 kb
Host smart-23e42578-3935-4115-9239-e2313b8db19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113095464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1113095464
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1608152648
Short name T410
Test name
Test status
Simulation time 11963492895 ps
CPU time 50.66 seconds
Started Apr 28 03:21:29 PM PDT 24
Finished Apr 28 03:22:20 PM PDT 24
Peak memory 199788 kb
Host smart-8105bc5b-45b9-42f1-83ba-02aa7654aae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608152648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1608152648
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2505060508
Short name T46
Test name
Test status
Simulation time 12226229759 ps
CPU time 96.55 seconds
Started Apr 28 03:21:27 PM PDT 24
Finished Apr 28 03:23:04 PM PDT 24
Peak memory 199644 kb
Host smart-017b8776-fb69-47cf-bf10-28cff2408d92
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505060508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2505060508
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1607807131
Short name T323
Test name
Test status
Simulation time 1362698913 ps
CPU time 84.18 seconds
Started Apr 28 03:21:23 PM PDT 24
Finished Apr 28 03:22:48 PM PDT 24
Peak memory 199660 kb
Host smart-d91ef850-d46e-4f18-9322-f7c41f3c32a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607807131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1607807131
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3290008511
Short name T326
Test name
Test status
Simulation time 196974835 ps
CPU time 3.31 seconds
Started Apr 28 03:21:23 PM PDT 24
Finished Apr 28 03:21:27 PM PDT 24
Peak memory 199664 kb
Host smart-80c66662-28c2-4928-9267-2f51463995a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290008511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3290008511
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3522045505
Short name T298
Test name
Test status
Simulation time 88576667669 ps
CPU time 645.32 seconds
Started Apr 28 03:21:28 PM PDT 24
Finished Apr 28 03:32:14 PM PDT 24
Peak memory 199692 kb
Host smart-f1345100-15c9-4a76-adc1-515e1180e329
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522045505 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3522045505
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.337305894
Short name T367
Test name
Test status
Simulation time 91597381 ps
CPU time 0.95 seconds
Started Apr 28 03:21:27 PM PDT 24
Finished Apr 28 03:21:29 PM PDT 24
Peak memory 198844 kb
Host smart-54e6cfa0-d5db-437a-b841-c5b8524d576f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337305894 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.337305894
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1906479275
Short name T584
Test name
Test status
Simulation time 52687377420 ps
CPU time 472.17 seconds
Started Apr 28 03:21:26 PM PDT 24
Finished Apr 28 03:29:19 PM PDT 24
Peak memory 199660 kb
Host smart-b1ce8357-ed3c-4a59-beaf-816559ff5f56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906479275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1906479275
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3803675763
Short name T240
Test name
Test status
Simulation time 400926141 ps
CPU time 11.01 seconds
Started Apr 28 03:21:26 PM PDT 24
Finished Apr 28 03:21:38 PM PDT 24
Peak memory 199628 kb
Host smart-71862ad2-58fa-447b-b409-af93001e86b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803675763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3803675763
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.76939189
Short name T564
Test name
Test status
Simulation time 36189140 ps
CPU time 0.57 seconds
Started Apr 28 03:21:35 PM PDT 24
Finished Apr 28 03:21:36 PM PDT 24
Peak memory 194300 kb
Host smart-0685904c-96c5-458d-9baf-0868eb13ceec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76939189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.76939189
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.626512078
Short name T427
Test name
Test status
Simulation time 932358638 ps
CPU time 16.64 seconds
Started Apr 28 03:21:26 PM PDT 24
Finished Apr 28 03:21:43 PM PDT 24
Peak memory 209444 kb
Host smart-8b2a1989-50c2-4f4e-9e8d-e2b199f40863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626512078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.626512078
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.976800850
Short name T402
Test name
Test status
Simulation time 2707247694 ps
CPU time 40.65 seconds
Started Apr 28 03:21:30 PM PDT 24
Finished Apr 28 03:22:11 PM PDT 24
Peak memory 199704 kb
Host smart-db18e064-26cf-48e0-8845-9954b7694d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976800850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.976800850
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1940710921
Short name T386
Test name
Test status
Simulation time 718215966 ps
CPU time 42.99 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:22:14 PM PDT 24
Peak memory 199712 kb
Host smart-491613d5-4822-4af4-ae33-d0780bb1208c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940710921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1940710921
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4164533903
Short name T490
Test name
Test status
Simulation time 1845903439 ps
CPU time 49.49 seconds
Started Apr 28 03:21:30 PM PDT 24
Finished Apr 28 03:22:20 PM PDT 24
Peak memory 199576 kb
Host smart-93cabaf4-db25-45ac-aec0-cfb7ab592c48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164533903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4164533903
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.135393851
Short name T243
Test name
Test status
Simulation time 15472012326 ps
CPU time 142.95 seconds
Started Apr 28 03:21:27 PM PDT 24
Finished Apr 28 03:23:51 PM PDT 24
Peak memory 199720 kb
Host smart-c8a3dad9-493c-44d8-85d5-4e5bca4c0a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135393851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.135393851
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.4238417824
Short name T469
Test name
Test status
Simulation time 262023568 ps
CPU time 1.39 seconds
Started Apr 28 03:21:25 PM PDT 24
Finished Apr 28 03:21:28 PM PDT 24
Peak memory 199648 kb
Host smart-bd662bff-2781-4279-9992-d888a2af86f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238417824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.4238417824
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2549012484
Short name T72
Test name
Test status
Simulation time 92529074655 ps
CPU time 1247.52 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:42:19 PM PDT 24
Peak memory 199724 kb
Host smart-dc8147d9-d98d-4584-8135-017077452d5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549012484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2549012484
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3432166832
Short name T560
Test name
Test status
Simulation time 102564046 ps
CPU time 1 seconds
Started Apr 28 03:21:30 PM PDT 24
Finished Apr 28 03:21:31 PM PDT 24
Peak memory 198664 kb
Host smart-94689f1b-f641-4535-99b7-64cea69b68c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432166832 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3432166832
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1745027748
Short name T224
Test name
Test status
Simulation time 33696298839 ps
CPU time 473.73 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:29:25 PM PDT 24
Peak memory 199600 kb
Host smart-2a3a2555-6852-4b2c-a0ed-74668df91910
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745027748 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1745027748
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2080532050
Short name T520
Test name
Test status
Simulation time 4204081037 ps
CPU time 60.56 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:22:32 PM PDT 24
Peak memory 199700 kb
Host smart-78c55d1f-8e97-42ee-b76a-34f44f241b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080532050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2080532050
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2375871382
Short name T178
Test name
Test status
Simulation time 31885484 ps
CPU time 0.6 seconds
Started Apr 28 03:21:36 PM PDT 24
Finished Apr 28 03:21:37 PM PDT 24
Peak memory 195360 kb
Host smart-18d51afe-8f21-4d73-8dcc-c20c06e0ac16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375871382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2375871382
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3203691240
Short name T311
Test name
Test status
Simulation time 1415618914 ps
CPU time 54.13 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:22:26 PM PDT 24
Peak memory 232464 kb
Host smart-90daaad4-979f-48be-9686-8f54df97ab3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203691240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3203691240
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3792495447
Short name T149
Test name
Test status
Simulation time 6913427280 ps
CPU time 24.66 seconds
Started Apr 28 03:21:30 PM PDT 24
Finished Apr 28 03:21:55 PM PDT 24
Peak memory 199800 kb
Host smart-78df1fd6-a1d6-4328-9ecd-b4bb97d4fc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792495447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3792495447
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.124069128
Short name T368
Test name
Test status
Simulation time 5913196084 ps
CPU time 96.09 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:23:07 PM PDT 24
Peak memory 199708 kb
Host smart-75089dcf-9bfd-4a1b-b7f8-801c9a44cee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124069128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.124069128
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3869866338
Short name T494
Test name
Test status
Simulation time 10367071727 ps
CPU time 171.48 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:24:23 PM PDT 24
Peak memory 199740 kb
Host smart-2a455fc8-f2ad-48da-8b1f-b2e424a420c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869866338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3869866338
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3036870682
Short name T480
Test name
Test status
Simulation time 1386779302 ps
CPU time 27.11 seconds
Started Apr 28 03:21:47 PM PDT 24
Finished Apr 28 03:22:14 PM PDT 24
Peak memory 199684 kb
Host smart-728dd787-354f-4b08-925e-64eba97108fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036870682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3036870682
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.610720448
Short name T553
Test name
Test status
Simulation time 450436981 ps
CPU time 7.01 seconds
Started Apr 28 03:21:31 PM PDT 24
Finished Apr 28 03:21:39 PM PDT 24
Peak memory 199668 kb
Host smart-66c505eb-5c0c-43fc-a7a0-60c411cb833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610720448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.610720448
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.888067021
Short name T433
Test name
Test status
Simulation time 19534019274 ps
CPU time 943.3 seconds
Started Apr 28 03:21:36 PM PDT 24
Finished Apr 28 03:37:20 PM PDT 24
Peak memory 222628 kb
Host smart-eebf587e-374e-4981-a2ee-b26945b31971
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888067021 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.888067021
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1475637860
Short name T219
Test name
Test status
Simulation time 50015394 ps
CPU time 1.01 seconds
Started Apr 28 03:21:37 PM PDT 24
Finished Apr 28 03:21:38 PM PDT 24
Peak memory 199612 kb
Host smart-e696b051-9d1a-4159-8534-5572c97f5cb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475637860 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1475637860
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2355676966
Short name T356
Test name
Test status
Simulation time 53134558775 ps
CPU time 498.54 seconds
Started Apr 28 03:21:37 PM PDT 24
Finished Apr 28 03:29:57 PM PDT 24
Peak memory 199648 kb
Host smart-f5df3952-96e3-4f34-8e54-f18dfbd34ba1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355676966 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2355676966
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1364328758
Short name T375
Test name
Test status
Simulation time 5360190979 ps
CPU time 70.75 seconds
Started Apr 28 03:21:39 PM PDT 24
Finished Apr 28 03:22:50 PM PDT 24
Peak memory 199724 kb
Host smart-6c925b02-647f-4f32-a9dd-4497573cb40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364328758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1364328758
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.506239577
Short name T459
Test name
Test status
Simulation time 15974250 ps
CPU time 0.63 seconds
Started Apr 28 03:21:47 PM PDT 24
Finished Apr 28 03:21:48 PM PDT 24
Peak memory 195356 kb
Host smart-2b779ac2-3bd5-4af0-a60b-424a8547da21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506239577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.506239577
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.395703227
Short name T377
Test name
Test status
Simulation time 875454042 ps
CPU time 15.72 seconds
Started Apr 28 03:21:36 PM PDT 24
Finished Apr 28 03:21:52 PM PDT 24
Peak memory 207856 kb
Host smart-4c0cb75a-df43-4081-aa08-688790750572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395703227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.395703227
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.651720812
Short name T468
Test name
Test status
Simulation time 4585117108 ps
CPU time 17.95 seconds
Started Apr 28 03:21:39 PM PDT 24
Finished Apr 28 03:21:58 PM PDT 24
Peak memory 199716 kb
Host smart-8464eb06-72d1-40d7-84b8-f9d4ff6ab156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651720812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.651720812
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.744917608
Short name T287
Test name
Test status
Simulation time 7548723319 ps
CPU time 101.81 seconds
Started Apr 28 03:21:47 PM PDT 24
Finished Apr 28 03:23:29 PM PDT 24
Peak memory 199696 kb
Host smart-968b5dd9-e800-4c24-9e78-4ab1a255b79f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744917608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.744917608
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4017414621
Short name T49
Test name
Test status
Simulation time 13358496482 ps
CPU time 195.98 seconds
Started Apr 28 03:21:41 PM PDT 24
Finished Apr 28 03:24:58 PM PDT 24
Peak memory 199748 kb
Host smart-3f2008cb-ccac-48dc-bdd6-b821d0ec5586
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017414621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4017414621
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3026868549
Short name T300
Test name
Test status
Simulation time 2586818414 ps
CPU time 15.17 seconds
Started Apr 28 03:21:37 PM PDT 24
Finished Apr 28 03:21:52 PM PDT 24
Peak memory 199640 kb
Host smart-5a95b662-1bc5-4d6c-885a-a9cd46dcba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026868549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3026868549
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2328423163
Short name T583
Test name
Test status
Simulation time 62580751 ps
CPU time 2.26 seconds
Started Apr 28 03:21:36 PM PDT 24
Finished Apr 28 03:21:39 PM PDT 24
Peak memory 199668 kb
Host smart-7fb329f6-31ac-4f2e-b941-7656e065f579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328423163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2328423163
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2479216930
Short name T74
Test name
Test status
Simulation time 22798285979 ps
CPU time 162.19 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:24:23 PM PDT 24
Peak memory 207920 kb
Host smart-d45ce489-2af2-4ccc-9fed-c494d1856723
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479216930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2479216930
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1301343611
Short name T578
Test name
Test status
Simulation time 285939381 ps
CPU time 1.2 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:21:43 PM PDT 24
Peak memory 199332 kb
Host smart-d0663935-9981-42ee-969b-19513aaaf78c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301343611 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1301343611
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1894127051
Short name T144
Test name
Test status
Simulation time 8619069311 ps
CPU time 485.37 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:29:46 PM PDT 24
Peak memory 199720 kb
Host smart-3e4d9b01-7a33-4eda-b061-109ccec8b921
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894127051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1894127051
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.958536959
Short name T110
Test name
Test status
Simulation time 8624293201 ps
CPU time 57.69 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:22:39 PM PDT 24
Peak memory 199784 kb
Host smart-e0ba34e9-4a74-4002-be7d-df41fc99f67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958536959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.958536959
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2575035872
Short name T218
Test name
Test status
Simulation time 18192856 ps
CPU time 0.56 seconds
Started Apr 28 03:21:44 PM PDT 24
Finished Apr 28 03:21:46 PM PDT 24
Peak memory 194292 kb
Host smart-286bf207-7395-48a8-92b1-8cc903a9feff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575035872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2575035872
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1572644808
Short name T209
Test name
Test status
Simulation time 501093522 ps
CPU time 18.65 seconds
Started Apr 28 03:21:44 PM PDT 24
Finished Apr 28 03:22:03 PM PDT 24
Peak memory 215724 kb
Host smart-a49935a2-4ad6-41b4-a84b-764f7953f0b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572644808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1572644808
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1256159090
Short name T192
Test name
Test status
Simulation time 5120202980 ps
CPU time 19.23 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:22:00 PM PDT 24
Peak memory 199724 kb
Host smart-e4766cd8-34f3-4a20-aaf8-ab86e3438426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256159090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1256159090
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1042065054
Short name T404
Test name
Test status
Simulation time 1701667370 ps
CPU time 46.57 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:22:27 PM PDT 24
Peak memory 199644 kb
Host smart-5e0d350f-3a3e-4032-a799-3d7793b266ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042065054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1042065054
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.546543445
Short name T341
Test name
Test status
Simulation time 9917148211 ps
CPU time 180.52 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:24:42 PM PDT 24
Peak memory 199716 kb
Host smart-f41ca1b4-6376-4165-a4c0-99fb012d08a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546543445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.546543445
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2111009740
Short name T128
Test name
Test status
Simulation time 5259114796 ps
CPU time 81.19 seconds
Started Apr 28 03:21:47 PM PDT 24
Finished Apr 28 03:23:08 PM PDT 24
Peak memory 199680 kb
Host smart-79ece4eb-1491-4986-a761-efafd72d1d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111009740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2111009740
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3565420913
Short name T434
Test name
Test status
Simulation time 281333528 ps
CPU time 2.39 seconds
Started Apr 28 03:21:43 PM PDT 24
Finished Apr 28 03:21:46 PM PDT 24
Peak memory 199668 kb
Host smart-1b393a07-deaa-4cf7-a21d-98c5d5a13893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565420913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3565420913
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2516274805
Short name T470
Test name
Test status
Simulation time 13564743017 ps
CPU time 74.2 seconds
Started Apr 28 03:21:46 PM PDT 24
Finished Apr 28 03:23:01 PM PDT 24
Peak memory 199728 kb
Host smart-9109e188-2fae-45b4-b162-be2551567b2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516274805 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2516274805
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1443033614
Short name T161
Test name
Test status
Simulation time 50354242 ps
CPU time 0.98 seconds
Started Apr 28 03:21:44 PM PDT 24
Finished Apr 28 03:21:45 PM PDT 24
Peak memory 197876 kb
Host smart-fc46a4ce-bff1-4c36-8f5d-07bf89a59667
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443033614 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1443033614
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.590245450
Short name T352
Test name
Test status
Simulation time 37745245344 ps
CPU time 501.75 seconds
Started Apr 28 03:21:41 PM PDT 24
Finished Apr 28 03:30:04 PM PDT 24
Peak memory 199644 kb
Host smart-39b0c1fe-4e6d-48a7-b6e1-3819defcadcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590245450 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.590245450
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2067565328
Short name T548
Test name
Test status
Simulation time 673116494 ps
CPU time 27.96 seconds
Started Apr 28 03:21:40 PM PDT 24
Finished Apr 28 03:22:09 PM PDT 24
Peak memory 199720 kb
Host smart-3b034ad0-1637-4415-81f9-ea7978b5693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067565328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2067565328
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2955004554
Short name T357
Test name
Test status
Simulation time 45136184 ps
CPU time 0.57 seconds
Started Apr 28 03:21:51 PM PDT 24
Finished Apr 28 03:21:53 PM PDT 24
Peak memory 195316 kb
Host smart-b3804a84-3b79-4cc0-aaf5-a27af87184cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955004554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2955004554
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.565890462
Short name T438
Test name
Test status
Simulation time 2197673473 ps
CPU time 36.16 seconds
Started Apr 28 03:21:50 PM PDT 24
Finished Apr 28 03:22:26 PM PDT 24
Peak memory 247828 kb
Host smart-74f89b98-3908-4988-bef6-d726dadb1cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565890462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.565890462
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.84140817
Short name T280
Test name
Test status
Simulation time 1060778290 ps
CPU time 4.37 seconds
Started Apr 28 03:21:52 PM PDT 24
Finished Apr 28 03:21:57 PM PDT 24
Peak memory 199592 kb
Host smart-991d906b-e294-46cd-bc34-152daf1a6d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84140817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.84140817
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1164339477
Short name T182
Test name
Test status
Simulation time 423825618 ps
CPU time 10.91 seconds
Started Apr 28 03:21:50 PM PDT 24
Finished Apr 28 03:22:01 PM PDT 24
Peak memory 199656 kb
Host smart-34ad2fde-2a6d-477e-a294-a7f19f937518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164339477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1164339477
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1524941369
Short name T231
Test name
Test status
Simulation time 13567218339 ps
CPU time 24.98 seconds
Started Apr 28 03:21:51 PM PDT 24
Finished Apr 28 03:22:17 PM PDT 24
Peak memory 199636 kb
Host smart-bf1b1697-df56-4ffc-81c3-e61186fb9947
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524941369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1524941369
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1891557436
Short name T517
Test name
Test status
Simulation time 6880352728 ps
CPU time 73.06 seconds
Started Apr 28 03:21:44 PM PDT 24
Finished Apr 28 03:22:58 PM PDT 24
Peak memory 199684 kb
Host smart-4a1f94c0-11b1-4437-bc64-9e584b815b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891557436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1891557436
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1612439886
Short name T114
Test name
Test status
Simulation time 466302108 ps
CPU time 5.49 seconds
Started Apr 28 03:21:45 PM PDT 24
Finished Apr 28 03:21:51 PM PDT 24
Peak memory 199656 kb
Host smart-ba54b25b-6de0-4b86-841e-1900bd263f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612439886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1612439886
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1067138340
Short name T223
Test name
Test status
Simulation time 70113364534 ps
CPU time 898.52 seconds
Started Apr 28 03:21:51 PM PDT 24
Finished Apr 28 03:36:50 PM PDT 24
Peak memory 231244 kb
Host smart-7630029e-e87b-4593-b8d9-dabfbd63a30f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067138340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1067138340
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3126393164
Short name T581
Test name
Test status
Simulation time 225721259 ps
CPU time 1.33 seconds
Started Apr 28 03:21:51 PM PDT 24
Finished Apr 28 03:21:53 PM PDT 24
Peak memory 199604 kb
Host smart-ea6fc42c-e11d-4e0e-8ac8-47ced6988871
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126393164 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3126393164
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.4088287326
Short name T189
Test name
Test status
Simulation time 67474702658 ps
CPU time 400.56 seconds
Started Apr 28 03:21:49 PM PDT 24
Finished Apr 28 03:28:30 PM PDT 24
Peak memory 199708 kb
Host smart-c3994c99-fe3a-4910-b87f-e4e599f2a5b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088287326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.4088287326
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.25230350
Short name T338
Test name
Test status
Simulation time 1811783032 ps
CPU time 60.32 seconds
Started Apr 28 03:21:51 PM PDT 24
Finished Apr 28 03:22:52 PM PDT 24
Peak memory 199684 kb
Host smart-1d6a430b-52e8-429c-a658-af722f50c85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25230350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.25230350
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2590269389
Short name T423
Test name
Test status
Simulation time 15925493 ps
CPU time 0.57 seconds
Started Apr 28 03:21:55 PM PDT 24
Finished Apr 28 03:21:56 PM PDT 24
Peak memory 195340 kb
Host smart-9992b481-7b7e-4e7c-850b-b3fb0afd923b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590269389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2590269389
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2684485209
Short name T172
Test name
Test status
Simulation time 3484791069 ps
CPU time 22.97 seconds
Started Apr 28 03:21:56 PM PDT 24
Finished Apr 28 03:22:20 PM PDT 24
Peak memory 219020 kb
Host smart-6625a7b4-807f-44f3-95b6-ea6f32f62336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684485209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2684485209
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3172561590
Short name T138
Test name
Test status
Simulation time 4926252182 ps
CPU time 15.54 seconds
Started Apr 28 03:21:55 PM PDT 24
Finished Apr 28 03:22:11 PM PDT 24
Peak memory 199740 kb
Host smart-f0397c34-8645-490d-8a9b-0b81a41f5124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172561590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3172561590
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3350414824
Short name T265
Test name
Test status
Simulation time 8879283469 ps
CPU time 120.06 seconds
Started Apr 28 03:21:58 PM PDT 24
Finished Apr 28 03:23:59 PM PDT 24
Peak memory 199736 kb
Host smart-4277d092-9452-4c64-b06b-ab41e4676df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350414824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3350414824
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3755862513
Short name T154
Test name
Test status
Simulation time 20861334795 ps
CPU time 49.81 seconds
Started Apr 28 03:21:58 PM PDT 24
Finished Apr 28 03:22:48 PM PDT 24
Peak memory 199716 kb
Host smart-9bb069c7-105e-4d8f-a04d-f162d69dd98e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755862513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3755862513
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1199475831
Short name T362
Test name
Test status
Simulation time 15042262695 ps
CPU time 53.76 seconds
Started Apr 28 03:21:55 PM PDT 24
Finished Apr 28 03:22:49 PM PDT 24
Peak memory 199764 kb
Host smart-7de83c01-d558-43e3-b99c-4c701caa4b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199475831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1199475831
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2543910500
Short name T370
Test name
Test status
Simulation time 337662127 ps
CPU time 5.43 seconds
Started Apr 28 03:21:50 PM PDT 24
Finished Apr 28 03:21:56 PM PDT 24
Peak memory 199556 kb
Host smart-a446ad04-9527-4c2c-a842-7dcf37b39713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543910500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2543910500
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2250928588
Short name T337
Test name
Test status
Simulation time 8767274792 ps
CPU time 171.19 seconds
Started Apr 28 03:21:58 PM PDT 24
Finished Apr 28 03:24:49 PM PDT 24
Peak memory 216044 kb
Host smart-6e881e25-aa1e-4b2b-8916-3cdf6d02bdf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250928588 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2250928588
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3798158070
Short name T589
Test name
Test status
Simulation time 108284644 ps
CPU time 1.25 seconds
Started Apr 28 03:21:58 PM PDT 24
Finished Apr 28 03:22:00 PM PDT 24
Peak memory 199648 kb
Host smart-faf12a5e-ff35-43da-b378-29e72a050674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798158070 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3798158070
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.482967248
Short name T452
Test name
Test status
Simulation time 357105647016 ps
CPU time 474.76 seconds
Started Apr 28 03:21:57 PM PDT 24
Finished Apr 28 03:29:52 PM PDT 24
Peak memory 199616 kb
Host smart-84401603-9242-4c65-9be6-20daf904f30b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482967248 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.482967248
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2790483120
Short name T412
Test name
Test status
Simulation time 422398950 ps
CPU time 17.38 seconds
Started Apr 28 03:21:58 PM PDT 24
Finished Apr 28 03:22:16 PM PDT 24
Peak memory 199640 kb
Host smart-8f4224c3-91b6-4d3e-b41b-aaab4bb2784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790483120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2790483120
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.993979679
Short name T379
Test name
Test status
Simulation time 204120170 ps
CPU time 0.59 seconds
Started Apr 28 03:22:00 PM PDT 24
Finished Apr 28 03:22:01 PM PDT 24
Peak memory 195344 kb
Host smart-28609666-ffa8-4fce-8b21-7e7706fb78be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993979679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.993979679
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.981843947
Short name T358
Test name
Test status
Simulation time 646818577 ps
CPU time 23.13 seconds
Started Apr 28 03:21:54 PM PDT 24
Finished Apr 28 03:22:17 PM PDT 24
Peak memory 208936 kb
Host smart-c583df58-09b9-4a3a-a101-f63a44cd9cc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981843947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.981843947
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3260006835
Short name T135
Test name
Test status
Simulation time 11872216057 ps
CPU time 35.6 seconds
Started Apr 28 03:21:54 PM PDT 24
Finished Apr 28 03:22:31 PM PDT 24
Peak memory 199724 kb
Host smart-256c4789-7dc5-45dc-b28e-9e4766b713be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260006835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3260006835
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3828685264
Short name T305
Test name
Test status
Simulation time 10007138148 ps
CPU time 164.97 seconds
Started Apr 28 03:21:56 PM PDT 24
Finished Apr 28 03:24:42 PM PDT 24
Peak memory 199736 kb
Host smart-1655302c-8312-47ad-8b44-e87212b225e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828685264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3828685264
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2996842565
Short name T354
Test name
Test status
Simulation time 23753067837 ps
CPU time 73.24 seconds
Started Apr 28 03:21:58 PM PDT 24
Finished Apr 28 03:23:11 PM PDT 24
Peak memory 199672 kb
Host smart-6bc6e4f6-94bc-4d6a-8a85-d117c2407bb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996842565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2996842565
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2908839949
Short name T171
Test name
Test status
Simulation time 4457222784 ps
CPU time 72.28 seconds
Started Apr 28 03:21:56 PM PDT 24
Finished Apr 28 03:23:09 PM PDT 24
Peak memory 199764 kb
Host smart-d4b4c3e2-9cb3-47ed-9bba-a991adb24859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908839949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2908839949
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3463308135
Short name T333
Test name
Test status
Simulation time 262355520 ps
CPU time 3.36 seconds
Started Apr 28 03:21:57 PM PDT 24
Finished Apr 28 03:22:01 PM PDT 24
Peak memory 199568 kb
Host smart-b2c5abcb-7b1c-445c-88e9-4b4617b9695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463308135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3463308135
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.844815731
Short name T543
Test name
Test status
Simulation time 6294830611 ps
CPU time 128.58 seconds
Started Apr 28 03:22:02 PM PDT 24
Finished Apr 28 03:24:11 PM PDT 24
Peak memory 199852 kb
Host smart-9e9ae62f-9818-424b-9433-272ab0c3f0f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844815731 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.844815731
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2091310666
Short name T556
Test name
Test status
Simulation time 33786563 ps
CPU time 1.3 seconds
Started Apr 28 03:21:56 PM PDT 24
Finished Apr 28 03:21:58 PM PDT 24
Peak memory 199624 kb
Host smart-279e5f25-483a-4fe9-a91a-6277e944dfbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091310666 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2091310666
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2981760071
Short name T236
Test name
Test status
Simulation time 50440116343 ps
CPU time 441.36 seconds
Started Apr 28 03:21:55 PM PDT 24
Finished Apr 28 03:29:17 PM PDT 24
Peak memory 199660 kb
Host smart-c803e740-075a-4a77-b846-556c3de9cb40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981760071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2981760071
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3919771193
Short name T384
Test name
Test status
Simulation time 2864751850 ps
CPU time 10.42 seconds
Started Apr 28 03:21:56 PM PDT 24
Finished Apr 28 03:22:07 PM PDT 24
Peak memory 199712 kb
Host smart-145886d9-e8fa-440e-89da-e8d9ceea59b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919771193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3919771193
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2548803415
Short name T20
Test name
Test status
Simulation time 11184183 ps
CPU time 0.56 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:19:29 PM PDT 24
Peak memory 195260 kb
Host smart-fa28e0b2-b839-4ae8-9e55-7d8e4a65ee5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548803415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2548803415
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3795935412
Short name T378
Test name
Test status
Simulation time 2347512444 ps
CPU time 45.39 seconds
Started Apr 28 03:19:27 PM PDT 24
Finished Apr 28 03:20:13 PM PDT 24
Peak memory 230452 kb
Host smart-d3d10a79-2896-4c25-a9c4-491c120dd7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795935412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3795935412
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1286788114
Short name T201
Test name
Test status
Simulation time 1289604556 ps
CPU time 12.76 seconds
Started Apr 28 03:19:29 PM PDT 24
Finished Apr 28 03:19:43 PM PDT 24
Peak memory 199680 kb
Host smart-78de7c1b-bc19-4677-98b9-c0c523c5e46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286788114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1286788114
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1372073651
Short name T408
Test name
Test status
Simulation time 7500266889 ps
CPU time 106.02 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:21:20 PM PDT 24
Peak memory 199660 kb
Host smart-0442646f-f7ea-43a3-a241-4ae6192939d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372073651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1372073651
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3039032595
Short name T486
Test name
Test status
Simulation time 36396177 ps
CPU time 0.67 seconds
Started Apr 28 03:19:30 PM PDT 24
Finished Apr 28 03:19:31 PM PDT 24
Peak memory 195676 kb
Host smart-d5c9ab26-7f5b-482d-ae3e-2df247f1c47d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039032595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3039032595
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1342533411
Short name T396
Test name
Test status
Simulation time 12997825747 ps
CPU time 93.7 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:21:02 PM PDT 24
Peak memory 199724 kb
Host smart-ccdb0042-41e7-4db2-8c2e-9213b2a602ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342533411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1342533411
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1068192135
Short name T127
Test name
Test status
Simulation time 391839991 ps
CPU time 4.89 seconds
Started Apr 28 03:19:26 PM PDT 24
Finished Apr 28 03:19:32 PM PDT 24
Peak memory 199640 kb
Host smart-d105c5b1-6e4a-4ad7-9fb9-99766330c18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068192135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1068192135
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2477705119
Short name T256
Test name
Test status
Simulation time 7806737815 ps
CPU time 420.11 seconds
Started Apr 28 03:19:29 PM PDT 24
Finished Apr 28 03:26:30 PM PDT 24
Peak memory 199748 kb
Host smart-2deefd75-3d64-4f44-962d-c2505b1cd495
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477705119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2477705119
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1299740249
Short name T593
Test name
Test status
Simulation time 66043902 ps
CPU time 1.26 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:19:38 PM PDT 24
Peak memory 199596 kb
Host smart-12782860-4c1f-40b2-b5fa-53b5977e7425
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299740249 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1299740249
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.651483437
Short name T225
Test name
Test status
Simulation time 32888793816 ps
CPU time 468.22 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:27:17 PM PDT 24
Peak memory 199712 kb
Host smart-6036068a-b784-48c6-96d6-16fabb74e750
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651483437 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.651483437
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.507144784
Short name T488
Test name
Test status
Simulation time 1044816392 ps
CPU time 16.18 seconds
Started Apr 28 03:19:27 PM PDT 24
Finished Apr 28 03:19:44 PM PDT 24
Peak memory 199680 kb
Host smart-5608ea93-3270-413a-bc12-d14ff938959d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507144784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.507144784
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.3639488985
Short name T464
Test name
Test status
Simulation time 46924230025 ps
CPU time 710.72 seconds
Started Apr 28 03:22:00 PM PDT 24
Finished Apr 28 03:33:52 PM PDT 24
Peak memory 248768 kb
Host smart-7fa20f86-1a0f-4d9c-a806-40096eb33ea4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639488985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.3639488985
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2604254225
Short name T255
Test name
Test status
Simulation time 30282765 ps
CPU time 0.59 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:19:37 PM PDT 24
Peak memory 195228 kb
Host smart-a82e550f-3c2e-49f2-9e4f-907aa97c1eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604254225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2604254225
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1288761321
Short name T55
Test name
Test status
Simulation time 2110671917 ps
CPU time 11.26 seconds
Started Apr 28 03:19:31 PM PDT 24
Finished Apr 28 03:19:42 PM PDT 24
Peak memory 207788 kb
Host smart-b0c9cd5e-fb0c-4b83-9aa4-c1dd4339dcea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288761321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1288761321
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3947497860
Short name T109
Test name
Test status
Simulation time 299665198 ps
CPU time 14.86 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:19:49 PM PDT 24
Peak memory 199620 kb
Host smart-0d0c23c1-1c86-4f4a-8ecd-f741ea535fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947497860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3947497860
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2002984611
Short name T554
Test name
Test status
Simulation time 2621352593 ps
CPU time 39.73 seconds
Started Apr 28 03:19:27 PM PDT 24
Finished Apr 28 03:20:08 PM PDT 24
Peak memory 199700 kb
Host smart-c79f735e-1c33-4444-afc8-81aaf28dc3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002984611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2002984611
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.397839775
Short name T534
Test name
Test status
Simulation time 370162371 ps
CPU time 20.22 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:19:48 PM PDT 24
Peak memory 199676 kb
Host smart-b5d26e57-c901-4dbe-844d-7256ad31c9eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397839775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.397839775
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.565479259
Short name T246
Test name
Test status
Simulation time 3044491168 ps
CPU time 45.43 seconds
Started Apr 28 03:19:30 PM PDT 24
Finished Apr 28 03:20:16 PM PDT 24
Peak memory 199684 kb
Host smart-dcfac433-6c30-467a-9bd9-dd240e31a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565479259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.565479259
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2890244292
Short name T381
Test name
Test status
Simulation time 294219548 ps
CPU time 4.65 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:19:33 PM PDT 24
Peak memory 199608 kb
Host smart-ada7c20f-a998-4683-bcb3-6eaee64f4f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890244292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2890244292
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1113274569
Short name T426
Test name
Test status
Simulation time 83108842949 ps
CPU time 1492.87 seconds
Started Apr 28 03:19:37 PM PDT 24
Finished Apr 28 03:44:31 PM PDT 24
Peak memory 199724 kb
Host smart-31945375-070a-4666-8844-7514c321c3cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113274569 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1113274569
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2640433942
Short name T238
Test name
Test status
Simulation time 42987403 ps
CPU time 1.01 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:19:35 PM PDT 24
Peak memory 198160 kb
Host smart-37be714a-58d5-4aff-8afc-7fd7f8dbad9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640433942 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2640433942
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.784721671
Short name T210
Test name
Test status
Simulation time 25857864964 ps
CPU time 428.39 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:26:46 PM PDT 24
Peak memory 199584 kb
Host smart-c05df76b-cd52-4464-a800-6dcd10d6ecbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784721671 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.784721671
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2055267512
Short name T555
Test name
Test status
Simulation time 9781046930 ps
CPU time 44.3 seconds
Started Apr 28 03:19:28 PM PDT 24
Finished Apr 28 03:20:13 PM PDT 24
Peak memory 199748 kb
Host smart-d8c90d34-df8b-4d6d-b1e9-63bd738ded3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055267512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2055267512
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.3015784313
Short name T479
Test name
Test status
Simulation time 78471655872 ps
CPU time 2905.03 seconds
Started Apr 28 03:22:04 PM PDT 24
Finished Apr 28 04:10:30 PM PDT 24
Peak memory 264780 kb
Host smart-d67f4172-a15b-45d9-9910-2ad015aec63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015784313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.3015784313
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.1056009474
Short name T363
Test name
Test status
Simulation time 157716766664 ps
CPU time 3082.81 seconds
Started Apr 28 03:22:05 PM PDT 24
Finished Apr 28 04:13:30 PM PDT 24
Peak memory 244316 kb
Host smart-3e560831-e43a-424d-979f-614c075bcc56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056009474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.1056009474
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1562786374
Short name T347
Test name
Test status
Simulation time 35823495 ps
CPU time 0.53 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:19:36 PM PDT 24
Peak memory 194360 kb
Host smart-11d9002c-f1bb-49db-bd85-4a794642714a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562786374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1562786374
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.928124167
Short name T288
Test name
Test status
Simulation time 3810660278 ps
CPU time 36.9 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:20:13 PM PDT 24
Peak memory 225120 kb
Host smart-f185ebfd-4c6d-417e-b8ef-768f37dbdcb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928124167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.928124167
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3099994032
Short name T605
Test name
Test status
Simulation time 822344813 ps
CPU time 38.81 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:20:13 PM PDT 24
Peak memory 199672 kb
Host smart-6e70d798-ae5e-4c9b-91b6-9f8d36ca4276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099994032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3099994032
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4030899400
Short name T561
Test name
Test status
Simulation time 3156929051 ps
CPU time 43.63 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:20:17 PM PDT 24
Peak memory 199672 kb
Host smart-b57039a2-311d-40b2-bb74-bbfbe7ac25ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030899400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4030899400
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1424908973
Short name T14
Test name
Test status
Simulation time 4084693108 ps
CPU time 55.28 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:20:30 PM PDT 24
Peak memory 199720 kb
Host smart-11d0b062-352a-443b-ae50-48e939d090fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424908973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1424908973
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3131937064
Short name T148
Test name
Test status
Simulation time 3091825638 ps
CPU time 46.52 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:20:24 PM PDT 24
Peak memory 199624 kb
Host smart-7aae9c4a-1ed0-448d-9fbb-425826359bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131937064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3131937064
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3663008563
Short name T349
Test name
Test status
Simulation time 117619460 ps
CPU time 0.94 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:19:36 PM PDT 24
Peak memory 198536 kb
Host smart-d61e5489-e94e-4a2b-bf9d-9f17ad801fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663008563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3663008563
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3531255466
Short name T514
Test name
Test status
Simulation time 153490169983 ps
CPU time 1015.95 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:36:33 PM PDT 24
Peak memory 240464 kb
Host smart-d9645997-02b6-4bb4-9c0c-6367413e2619
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531255466 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3531255466
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1300028613
Short name T59
Test name
Test status
Simulation time 137509173 ps
CPU time 1.02 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:19:37 PM PDT 24
Peak memory 198480 kb
Host smart-9ef46927-a356-4c3a-baac-5198342e2357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300028613 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1300028613
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2298641538
Short name T299
Test name
Test status
Simulation time 8433326821 ps
CPU time 477.24 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:27:34 PM PDT 24
Peak memory 199584 kb
Host smart-cff6b1ad-de77-48ec-9fb3-69969b26b055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298641538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2298641538
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1018713843
Short name T78
Test name
Test status
Simulation time 12029887499 ps
CPU time 46.47 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:20:21 PM PDT 24
Peak memory 199768 kb
Host smart-2b4623ea-fdb6-4cbd-8616-a04e9c5bf83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018713843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1018713843
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3102079192
Short name T18
Test name
Test status
Simulation time 14018192 ps
CPU time 0.59 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:19:34 PM PDT 24
Peak memory 195504 kb
Host smart-849c11e5-70f5-48ad-877f-abb81e751209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102079192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3102079192
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.264121959
Short name T516
Test name
Test status
Simulation time 579893196 ps
CPU time 24.74 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:19:58 PM PDT 24
Peak memory 226916 kb
Host smart-49f65e6e-bec2-4e3a-84a3-225fb39acf2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264121959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.264121959
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2315111427
Short name T550
Test name
Test status
Simulation time 850203401 ps
CPU time 41.02 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:20:16 PM PDT 24
Peak memory 199696 kb
Host smart-baf4a586-cb5b-46c6-842a-193256c204ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315111427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2315111427
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4005665287
Short name T472
Test name
Test status
Simulation time 2393497795 ps
CPU time 138.62 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:21:54 PM PDT 24
Peak memory 199608 kb
Host smart-c7f74614-11ee-46c7-a9ba-6e5ef5c5a9c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005665287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4005665287
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.304606951
Short name T13
Test name
Test status
Simulation time 9765325346 ps
CPU time 174.27 seconds
Started Apr 28 03:19:38 PM PDT 24
Finished Apr 28 03:22:33 PM PDT 24
Peak memory 199728 kb
Host smart-85e36411-e9fd-4a13-8bca-f417793d2d54
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304606951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.304606951
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1082605525
Short name T291
Test name
Test status
Simulation time 4798521125 ps
CPU time 85.45 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:21:00 PM PDT 24
Peak memory 199776 kb
Host smart-4dca1216-8edc-4aab-b282-3fddfa353921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082605525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1082605525
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1499850200
Short name T126
Test name
Test status
Simulation time 365851204 ps
CPU time 2.22 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:19:36 PM PDT 24
Peak memory 199664 kb
Host smart-f619625c-4ad6-41af-959b-01a0f467eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499850200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1499850200
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3089104908
Short name T463
Test name
Test status
Simulation time 41861916880 ps
CPU time 262.8 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:23:59 PM PDT 24
Peak memory 247796 kb
Host smart-5f896656-a218-4706-9cf1-a5277d67b6f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089104908 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3089104908
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2327280026
Short name T409
Test name
Test status
Simulation time 51189473 ps
CPU time 1.03 seconds
Started Apr 28 03:19:33 PM PDT 24
Finished Apr 28 03:19:35 PM PDT 24
Peak memory 199272 kb
Host smart-86d5cf88-45e9-4e57-89cc-1ba2b52033c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327280026 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2327280026
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1815554527
Short name T440
Test name
Test status
Simulation time 35143465354 ps
CPU time 410.52 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:26:28 PM PDT 24
Peak memory 199588 kb
Host smart-66811958-4e21-41bd-8d15-5492589ad771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815554527 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1815554527
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.606503003
Short name T36
Test name
Test status
Simulation time 9195305805 ps
CPU time 32.66 seconds
Started Apr 28 03:19:37 PM PDT 24
Finished Apr 28 03:20:11 PM PDT 24
Peak memory 199712 kb
Host smart-7a638525-ca56-4654-b217-c452f76f4e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606503003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.606503003
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.2087781338
Short name T334
Test name
Test status
Simulation time 18312185791 ps
CPU time 476.32 seconds
Started Apr 28 03:22:09 PM PDT 24
Finished Apr 28 03:30:06 PM PDT 24
Peak memory 208020 kb
Host smart-ef0850ee-c809-476b-b1a5-a20772183be2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087781338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.2087781338
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.1392454627
Short name T8
Test name
Test status
Simulation time 13980948616 ps
CPU time 168.29 seconds
Started Apr 28 03:22:08 PM PDT 24
Finished Apr 28 03:24:57 PM PDT 24
Peak memory 207964 kb
Host smart-10a8ddf4-8894-40d8-9f7c-56db7aa20296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392454627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.1392454627
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1956735468
Short name T273
Test name
Test status
Simulation time 40148563 ps
CPU time 0.56 seconds
Started Apr 28 03:19:42 PM PDT 24
Finished Apr 28 03:19:44 PM PDT 24
Peak memory 195300 kb
Host smart-db5fa7e9-ee6b-4a9b-bef5-e54acbce2df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956735468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1956735468
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4262959647
Short name T56
Test name
Test status
Simulation time 867531017 ps
CPU time 33.19 seconds
Started Apr 28 03:19:34 PM PDT 24
Finished Apr 28 03:20:08 PM PDT 24
Peak memory 225228 kb
Host smart-d56f01a4-aebb-4e1a-a453-e0c8b18b240f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262959647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4262959647
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.638102202
Short name T435
Test name
Test status
Simulation time 4663426489 ps
CPU time 38.92 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:20:15 PM PDT 24
Peak memory 199712 kb
Host smart-594e3a83-0b12-460a-95e2-ab68a8af282c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638102202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.638102202
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2713568188
Short name T340
Test name
Test status
Simulation time 487780534 ps
CPU time 6.64 seconds
Started Apr 28 03:19:43 PM PDT 24
Finished Apr 28 03:19:51 PM PDT 24
Peak memory 199620 kb
Host smart-a660c8af-eca9-429a-b9f8-caff59a37a99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713568188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2713568188
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3732422106
Short name T250
Test name
Test status
Simulation time 1577231630 ps
CPU time 45.87 seconds
Started Apr 28 03:19:39 PM PDT 24
Finished Apr 28 03:20:26 PM PDT 24
Peak memory 199576 kb
Host smart-a142b2a0-e82b-4cbb-9341-54ee35a230aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732422106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3732422106
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1170827286
Short name T235
Test name
Test status
Simulation time 959277719 ps
CPU time 53.68 seconds
Started Apr 28 03:19:32 PM PDT 24
Finished Apr 28 03:20:26 PM PDT 24
Peak memory 199664 kb
Host smart-ee618b8c-62a9-4d31-a520-c16bd23d654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170827286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1170827286
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1458802944
Short name T551
Test name
Test status
Simulation time 269821022 ps
CPU time 3.41 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:19:41 PM PDT 24
Peak memory 199452 kb
Host smart-b8a68622-653a-4163-96c4-8f477f475134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458802944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1458802944
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3976367494
Short name T482
Test name
Test status
Simulation time 76592743 ps
CPU time 1.38 seconds
Started Apr 28 03:19:35 PM PDT 24
Finished Apr 28 03:19:38 PM PDT 24
Peak memory 199640 kb
Host smart-c166070a-6296-457c-a189-d96e05def698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976367494 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3976367494
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3041607833
Short name T442
Test name
Test status
Simulation time 26977550941 ps
CPU time 491.95 seconds
Started Apr 28 03:19:38 PM PDT 24
Finished Apr 28 03:27:51 PM PDT 24
Peak memory 198544 kb
Host smart-c6f9b3cf-58dd-4543-bb8d-bc0b55b45f2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041607833 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3041607833
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.939479939
Short name T188
Test name
Test status
Simulation time 1156058433 ps
CPU time 3.6 seconds
Started Apr 28 03:19:36 PM PDT 24
Finished Apr 28 03:19:41 PM PDT 24
Peak memory 199600 kb
Host smart-01da38c3-ecee-4bc1-94af-8a5cf3238eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939479939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.939479939
Directory /workspace/9.hmac_wipe_secret/latest
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