Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14513990	1			T1	17828		T3	15432		T4	54077
all_values[1]	14513990	1			T1	17828		T3	15432		T4	54077
all_values[2]	14513990	1			T1	17828		T3	15432		T4	54077

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109558

1

T4

3

T5

57

T6

2

auto[1]

43432412

1

T1

53484

T3

46296

T4

162228

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41230909

1

T1

43572

T3

46252

T4

142965

auto[1]

2311061

1

T1

9912

T3

44

T4

19266

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	28537	1			T4	1		T42	82		T11	5
all_values[0]	auto[0]	auto[1]	461	1			T42	2		T11	9		T37	4
all_values[0]	auto[1]	auto[0]	14435128	1			T1	17821		T3	15388		T4	53860
all_values[0]	auto[1]	auto[1]	49864	1			T1	7		T3	44		T4	216
all_values[1]	auto[0]	auto[0]	38662	1			T4	1		T19	771		T42	1176
all_values[1]	auto[0]	auto[1]	244	1			T11	6		T14	5		T47	5
all_values[1]	auto[1]	auto[0]	14474495	1			T1	17828		T3	15432		T4	54075
all_values[1]	auto[1]	auto[1]	589	1			T4	1		T11	5		T38	3
all_values[2]	auto[0]	auto[0]	30099	1			T4	1		T5	57		T6	2
all_values[2]	auto[0]	auto[1]	11555	1			T11	5		T14	3		T26	2179
all_values[2]	auto[1]	auto[0]	12223988	1			T1	7923		T3	15432		T4	35027
all_values[2]	auto[1]	auto[1]	2248348	1			T1	9905		T4	19049		T18	11352