Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7006800

1

T1

885

T3

6890

T4

17866

auto[1]

2781531

1

T1

3250

T3

8488

T4

23667

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2791208

1

T1

2121

T3

8525

T4

18344

auto[1]

6997123

1

T1

2014

T3

6853

T4

23189

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6320483

1

T1

1321

T3

8162

T4

23566

auto[1]

3467848

1

T1

2814

T3

7216

T4

17967

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5941241	1			T1	3154		T3	14216		T4	17043
fifo_depth[1]	492808	1			T1	240		T3	723		T4	1730
fifo_depth[2]	427089	1			T1	237		T3	312		T4	1707
fifo_depth[3]	358622	1			T1	161		T3	98		T4	1550
fifo_depth[4]	312353	1			T1	104		T3	23		T4	1617
fifo_depth[5]	279571	1			T1	72		T3	5		T4	1392
fifo_depth[6]	267761	1			T1	48		T3	1		T4	1458
fifo_depth[7]	234478	1			T1	39		T4	1132		T5	1043
fifo_depth[8]	209882	1			T1	26		T4	1334		T5	917
fifo_depth[9]	144208	1			T1	22		T4	799		T5	642
fifo_depth[10]	109587	1			T1	16		T4	961		T5	466
fifo_depth[11]	66591	1			T1	7		T4	443		T5	257
fifo_depth[12]	65734	1			T1	2		T4	894		T5	127
fifo_depth[13]	32473	1			T1	3		T4	260		T5	61
fifo_depth[14]	41640	1			T1	2		T4	851		T5	22
fifo_depth[15]	27180	1			T1	1		T4	190		T5	12
fifo_depth[16]	98490	1			T1	1		T4	943		T5	4

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3969361

1

T1

981

T3

1162

T4

26057

auto[1]

5818970

1

T1

3154

T3

14216

T4

15476

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9666060

1

T1

4135

T3

15378

T4

39966

auto[1]

122271

1

T4

1567

T6

3

T19

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

274473

1

T1

21

T3

34

T4

2861

auto[0]

auto[0]

auto[0]

auto[1]

278115

1

T3

219

T4

5604

T6

3

auto[0]

auto[0]

auto[1]

auto[0]

1238662

1

T1

116

T3

157

T4

1363

auto[0]

auto[0]

auto[1]

auto[1]

274840

1

T1

139

T3

197

T4

5482

auto[0]

auto[1]

auto[0]

auto[0]

491074

1

T3

258

T4

1773

T5

2125

auto[0]

auto[1]

auto[0]

auto[1]

464687

1

T1

388

T3

144

T4

2069

auto[0]

auto[1]

auto[1]

auto[0]

464123

1

T3

66

T4

4995

T5

3620

auto[0]

auto[1]

auto[1]

auto[1]

483387

1

T1

317

T3

87

T4

1910

auto[1]

auto[0]

auto[0]

auto[0]

239834

1

T1

133

T3

457

T4

1185

auto[1]

auto[0]

auto[0]

auto[1]

248214

1

T1

3

T3

2693

T4

2296

auto[1]

auto[0]

auto[1]

auto[0]

3534928

1

T1

612

T3

1890

T4

2587

auto[1]

auto[0]

auto[1]

auto[1]

231417

1

T1

297

T3

2515

T4

2188

auto[1]

auto[1]

auto[0]

auto[0]

389014

1

T1

2

T3

3116

T4

1405

auto[1]

auto[1]

auto[0]

auto[1]

405797

1

T1

1574

T3

1604

T4

1151

auto[1]

auto[1]

auto[1]

auto[0]

374692

1

T1

1

T3

912

T4

1697

auto[1]

auto[1]

auto[1]

auto[1]

395074

1

T1

532

T3

1029

T4

2967

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

497992

1

T1

154

T3

491

T4

3953

auto[0]

auto[0]

auto[0]

auto[1]

511503

1

T1

3

T3

2912

T4

7612

auto[0]

auto[0]

auto[1]

auto[0]

4756063

1

T1

728

T3

2047

T4

3950

auto[0]

auto[0]

auto[1]

auto[1]

491212

1

T1

436

T3

2712

T4

7647

auto[0]

auto[1]

auto[0]

auto[0]

865747

1

T1

2

T3

3374

T4

3017

auto[0]

auto[1]

auto[0]

auto[1]

858712

1

T1

1962

T3

1748

T4

3135

auto[0]

auto[1]

auto[1]

auto[0]

821891

1

T1

1

T3

978

T4

5775

auto[0]

auto[1]

auto[1]

auto[1]

862940

1

T1

849

T3

1116

T4

4877

auto[1]

auto[0]

auto[0]

auto[0]

16315

1

T4

93

T19

1

T25

140

auto[1]

auto[0]

auto[0]

auto[1]

14826

1

T4

288

T25

1

T11

274

auto[1]

auto[0]

auto[1]

auto[0]

17527

1

T6

1

T25

1447

T38

7

auto[1]

auto[0]

auto[1]

auto[1]

15045

1

T4

23

T20

1

T25

302

auto[1]

auto[1]

auto[0]

auto[0]

14341

1

T4

161

T25

5

T11

60

auto[1]

auto[1]

auto[0]

auto[1]

11772

1

T4

85

T6

1

T25

2

auto[1]

auto[1]

auto[1]

auto[0]

16924

1

T4

917

T20

1

T25

5

auto[1]

auto[1]

auto[1]

auto[1]

15521

1

T6

1

T19

1

T20

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	256149	1			T1	133		T3	457		T4	1278
fifo_depth[0]	auto[0]	auto[0]	auto[1]	263040	1			T1	3		T3	2693		T4	2584
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3552455	1			T1	612		T3	1890		T4	2587
fifo_depth[0]	auto[0]	auto[1]	auto[1]	246462	1			T1	297		T3	2515		T4	2211
fifo_depth[0]	auto[1]	auto[0]	auto[0]	403355	1			T1	2		T3	3116		T4	1566
fifo_depth[0]	auto[1]	auto[0]	auto[1]	417569	1			T1	1574		T3	1604		T4	1236
fifo_depth[0]	auto[1]	auto[1]	auto[0]	391616	1			T1	1		T3	912		T4	2614
fifo_depth[0]	auto[1]	auto[1]	auto[1]	410595	1			T1	532		T3	1029		T4	2967
fifo_depth[1]	auto[0]	auto[0]	auto[0]	21684	1			T1	6		T3	19		T4	54
fifo_depth[1]	auto[0]	auto[0]	auto[1]	21489	1			T3	135		T4	200		T25	11
fifo_depth[1]	auto[0]	auto[1]	auto[0]	242177	1			T1	53		T3	90		T4	235
fifo_depth[1]	auto[0]	auto[1]	auto[1]	21386	1			T1	15		T3	132		T4	297
fifo_depth[1]	auto[1]	auto[0]	auto[0]	45566	1			T3	156		T4	173		T5	224
fifo_depth[1]	auto[1]	auto[0]	auto[1]	47809	1			T1	136		T3	92		T4	197
fifo_depth[1]	auto[1]	auto[1]	auto[0]	45883	1			T3	42		T4	243		T5	402
fifo_depth[1]	auto[1]	auto[1]	auto[1]	46814	1			T1	30		T3	57		T4	331
fifo_depth[2]	auto[0]	auto[0]	auto[0]	18688	1			T1	6		T3	10		T4	46
fifo_depth[2]	auto[0]	auto[0]	auto[1]	19082	1			T3	54		T4	200		T25	46
fifo_depth[2]	auto[0]	auto[1]	auto[0]	200171	1			T1	39		T3	51		T4	224
fifo_depth[2]	auto[0]	auto[1]	auto[1]	18956	1			T1	25		T3	50		T4	328
fifo_depth[2]	auto[1]	auto[0]	auto[0]	41547	1			T3	76		T4	184		T5	227
fifo_depth[2]	auto[1]	auto[0]	auto[1]	44023	1			T1	132		T3	34		T4	177
fifo_depth[2]	auto[1]	auto[1]	auto[0]	41920	1			T3	16		T4	234		T5	399
fifo_depth[2]	auto[1]	auto[1]	auto[1]	42702	1			T1	35		T3	21		T4	314
fifo_depth[3]	auto[0]	auto[0]	auto[0]	15880	1			T1	6		T3	5		T4	35
fifo_depth[3]	auto[0]	auto[0]	auto[1]	16038	1			T3	21		T4	187		T25	42
fifo_depth[3]	auto[0]	auto[1]	auto[0]	156599	1			T1	19		T3	13		T4	197
fifo_depth[3]	auto[0]	auto[1]	auto[1]	16373	1			T1	21		T3	12		T4	296
fifo_depth[3]	auto[1]	auto[0]	auto[0]	37450	1			T3	21		T4	149		T5	260
fifo_depth[3]	auto[1]	auto[0]	auto[1]	39607	1			T1	80		T3	12		T4	180
fifo_depth[3]	auto[1]	auto[1]	auto[0]	37755	1			T3	6		T4	219		T5	412
fifo_depth[3]	auto[1]	auto[1]	auto[1]	38920	1			T1	35		T3	8		T4	287
fifo_depth[4]	auto[0]	auto[0]	auto[0]	15672	1			T1	3		T4	54		T11	7
fifo_depth[4]	auto[0]	auto[0]	auto[1]	15371	1			T3	8		T4	204		T25	46
fifo_depth[4]	auto[0]	auto[1]	auto[0]	115933	1			T1	5		T3	2		T4	139
fifo_depth[4]	auto[0]	auto[1]	auto[1]	15608	1			T1	20		T3	2		T4	489
fifo_depth[4]	auto[1]	auto[0]	auto[0]	37133	1			T3	3		T4	131		T5	238
fifo_depth[4]	auto[1]	auto[0]	auto[1]	38642	1			T1	34		T3	5		T4	154
fifo_depth[4]	auto[1]	auto[1]	auto[0]	36390	1			T3	2		T4	218		T5	394
fifo_depth[4]	auto[1]	auto[1]	auto[1]	37604	1			T1	42		T3	1		T4	228
fifo_depth[5]	auto[0]	auto[0]	auto[0]	14152	1			T4	65		T11	9		T36	209
fifo_depth[5]	auto[0]	auto[0]	auto[1]	13867	1			T3	1		T4	204		T25	43
fifo_depth[5]	auto[0]	auto[1]	auto[0]	95552	1			T4	115		T18	10		T25	2
fifo_depth[5]	auto[0]	auto[1]	auto[1]	14199	1			T1	25		T3	1		T4	275
fifo_depth[5]	auto[1]	auto[0]	auto[0]	34456	1			T3	2		T4	132		T5	232
fifo_depth[5]	auto[1]	auto[0]	auto[1]	36471	1			T1	6		T3	1		T4	165
fifo_depth[5]	auto[1]	auto[1]	auto[0]	34948	1			T4	240		T5	365		T30	144
fifo_depth[5]	auto[1]	auto[1]	auto[1]	35926	1			T1	41		T4	196		T5	226
fifo_depth[6]	auto[0]	auto[0]	auto[0]	14873	1			T4	67		T25	1		T11	7
fifo_depth[6]	auto[0]	auto[0]	auto[1]	13779	1			T4	204		T25	46		T11	74
fifo_depth[6]	auto[0]	auto[1]	auto[0]	84274	1			T3	1		T4	123		T18	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	14473	1			T1	20		T4	469		T25	44
fifo_depth[6]	auto[1]	auto[0]	auto[0]	35137	1			T4	137		T5	225		T30	57
fifo_depth[6]	auto[1]	auto[0]	auto[1]	36137	1			T4	143		T5	332		T30	49
fifo_depth[6]	auto[1]	auto[1]	auto[0]	34042	1			T4	156		T5	371		T30	150
fifo_depth[6]	auto[1]	auto[1]	auto[1]	35046	1			T1	28		T4	159		T5	205
fifo_depth[7]	auto[0]	auto[0]	auto[0]	13006	1			T4	67		T11	9		T36	198
fifo_depth[7]	auto[0]	auto[0]	auto[1]	12536	1			T4	196		T25	44		T11	78
fifo_depth[7]	auto[0]	auto[1]	auto[0]	67699	1			T4	99		T25	7		T11	59
fifo_depth[7]	auto[0]	auto[1]	auto[1]	12783	1			T1	6		T4	241		T25	74
fifo_depth[7]	auto[1]	auto[0]	auto[0]	31529	1			T4	123		T5	213		T30	53
fifo_depth[7]	auto[1]	auto[0]	auto[1]	32369	1			T4	143		T5	258		T30	29
fifo_depth[7]	auto[1]	auto[1]	auto[0]	31735	1			T4	119		T5	390		T30	142
fifo_depth[7]	auto[1]	auto[1]	auto[1]	32821	1			T1	33		T4	144		T5	182
fifo_depth[8]	auto[0]	auto[0]	auto[0]	13908	1			T4	224		T25	4		T11	8
fifo_depth[8]	auto[0]	auto[0]	auto[1]	12797	1			T4	200		T25	46		T11	61
fifo_depth[8]	auto[0]	auto[1]	auto[0]	51759	1			T4	81		T25	20		T11	64
fifo_depth[8]	auto[0]	auto[1]	auto[1]	13523	1			T1	4		T4	424		T25	46
fifo_depth[8]	auto[1]	auto[0]	auto[0]	29913	1			T4	112		T5	175		T30	46
fifo_depth[8]	auto[1]	auto[0]	auto[1]	29477	1			T4	100		T5	254		T30	33
fifo_depth[8]	auto[1]	auto[1]	auto[0]	28686	1			T4	88		T5	319		T30	108
fifo_depth[8]	auto[1]	auto[1]	auto[1]	29819	1			T1	22		T4	105		T5	169
fifo_depth[9]	auto[0]	auto[0]	auto[0]	8818	1			T4	52		T25	1		T11	7
fifo_depth[9]	auto[0]	auto[0]	auto[1]	8510	1			T4	188		T25	43		T11	48
fifo_depth[9]	auto[0]	auto[1]	auto[0]	35375	1			T4	66		T25	12		T11	53
fifo_depth[9]	auto[0]	auto[1]	auto[1]	8333	1			T1	3		T4	179		T25	42
fifo_depth[9]	auto[1]	auto[0]	auto[0]	20314	1			T4	81		T5	134		T30	29
fifo_depth[9]	auto[1]	auto[0]	auto[1]	21052	1			T4	92		T5	153		T30	30
fifo_depth[9]	auto[1]	auto[1]	auto[0]	20402	1			T4	65		T5	234		T30	90
fifo_depth[9]	auto[1]	auto[1]	auto[1]	21404	1			T1	19		T4	76		T5	121
fifo_depth[10]	auto[0]	auto[0]	auto[0]	7897	1			T4	181		T11	4		T36	57
fifo_depth[10]	auto[0]	auto[0]	auto[1]	7329	1			T4	139		T25	78		T11	26
fifo_depth[10]	auto[0]	auto[1]	auto[0]	24382	1			T4	38		T25	11		T11	51
fifo_depth[10]	auto[0]	auto[1]	auto[1]	7230	1			T4	372		T25	79		T11	5
fifo_depth[10]	auto[1]	auto[0]	auto[0]	16243	1			T4	51		T5	89		T30	22
fifo_depth[10]	auto[1]	auto[0]	auto[1]	15783	1			T4	53		T5	110		T30	18
fifo_depth[10]	auto[1]	auto[1]	auto[0]	15387	1			T4	91		T5	162		T30	47
fifo_depth[10]	auto[1]	auto[1]	auto[1]	15336	1			T1	16		T4	36		T5	105
fifo_depth[11]	auto[0]	auto[0]	auto[0]	5026	1			T4	37		T25	1		T11	1
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4763	1			T4	176		T25	75		T11	30
fifo_depth[11]	auto[0]	auto[1]	auto[0]	14682	1			T4	18		T25	12		T11	46
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4268	1			T4	84		T25	42		T11	4
fifo_depth[11]	auto[1]	auto[0]	auto[0]	9384	1			T4	38		T5	50		T30	23
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9580	1			T4	22		T5	55		T30	13
fifo_depth[11]	auto[1]	auto[1]	auto[0]	9179	1			T4	44		T5	97		T30	34
fifo_depth[11]	auto[1]	auto[1]	auto[1]	9709	1			T1	7		T4	24		T5	55
fifo_depth[12]	auto[0]	auto[0]	auto[0]	7038	1			T4	184		T25	1		T11	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	5521	1			T4	112		T25	77		T11	30
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10402	1			T4	11		T25	13		T11	45
fifo_depth[12]	auto[0]	auto[1]	auto[1]	7530	1			T4	279		T25	46		T11	6
fifo_depth[12]	auto[1]	auto[0]	auto[0]	10202	1			T4	29		T5	27		T30	6
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7984	1			T4	17		T5	29		T30	5
fifo_depth[12]	auto[1]	auto[1]	auto[0]	8276	1			T4	257		T5	45		T30	14
fifo_depth[12]	auto[1]	auto[1]	auto[1]	8781	1			T1	2		T4	5		T5	26
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3390	1			T4	23		T25	20		T11	1
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3061	1			T4	133		T25	75		T11	35
fifo_depth[13]	auto[0]	auto[1]	auto[0]	5593	1			T4	12		T25	13		T11	28
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2635	1			T4	43		T25	64		T11	4
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4462	1			T4	12		T5	18		T30	3
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4288	1			T4	5		T5	17		T30	4
fifo_depth[13]	auto[1]	auto[1]	auto[0]	4274	1			T4	28		T5	15		T30	8
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4770	1			T1	3		T4	4		T5	11
fifo_depth[14]	auto[0]	auto[0]	auto[0]	5368	1			T4	180		T25	42		T11	1
fifo_depth[14]	auto[0]	auto[0]	auto[1]	4192	1			T4	101		T25	77		T11	36
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5896	1			T4	3		T25	11		T11	41
fifo_depth[14]	auto[0]	auto[1]	auto[1]	5351	1			T4	261		T25	45		T11	7
fifo_depth[14]	auto[1]	auto[0]	auto[0]	5992	1			T4	10		T5	9		T30	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4720	1			T4	2		T5	2		T30	4
fifo_depth[14]	auto[1]	auto[1]	auto[0]	5371	1			T4	294		T5	8		T30	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4750	1			T1	2		T5	3		T30	5
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3506	1			T4	19		T25	44		T36	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2988	1			T4	66		T25	60		T11	41
fifo_depth[15]	auto[0]	auto[1]	auto[0]	4016	1			T4	2		T25	12		T11	24
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2640	1			T4	33		T25	43		T11	5
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3307	1			T4	6		T5	4		T30	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3086	1			T4	2		T5	2		T19	3
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3741	1			T4	62		T5	3		T30	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3896	1			T1	1		T5	3		T30	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	13200	1			T4	148		T25	268		T73	88
fifo_depth[16]	auto[0]	auto[0]	auto[1]	11787	1			T4	257		T25	42		T11	400
fifo_depth[16]	auto[0]	auto[1]	auto[0]	14484	1			T25	478		T11	7		T38	43
fifo_depth[16]	auto[0]	auto[1]	auto[1]	9000	1			T4	253		T25	45		T11	128
fifo_depth[16]	auto[1]	auto[0]	auto[0]	16889	1			T4	10		T42	1		T25	56
fifo_depth[16]	auto[1]	auto[0]	auto[1]	8330	1			T4	1		T19	1		T42	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	12175	1			T4	273		T5	3		T25	51
fifo_depth[16]	auto[1]	auto[1]	auto[1]	12625	1			T1	1		T4	1		T5	1