Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14513990	1			T1	17828		T3	15432		T4	54077
all_pins[1]	14513990	1			T1	17828		T3	15432		T4	54077
all_pins[2]	14513990	1			T1	17828		T3	15432		T4	54077

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	41241782	1			T1	43572		T3	46252		T4	142954
values[0x1]	2300188	1			T1	9912		T3	44		T4	19277
transitions[0x0=>0x1]	2300024	1			T1	9912		T3	44		T4	19277
transitions[0x1=>0x0]	2300047	1			T1	9912		T3	44		T4	19277

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14462762	1			T1	17821		T3	15388		T4	53851
all_pins[0]	values[0x1]	51228	1			T1	7		T3	44		T4	226
all_pins[0]	transitions[0x0=>0x1]	51163	1			T1	7		T3	44		T4	226
all_pins[0]	transitions[0x1=>0x0]	2248306	1			T1	9905		T4	19049		T18	11352
all_pins[1]	values[0x0]	14513378	1			T1	17828		T3	15432		T4	54075
all_pins[1]	values[0x1]	612	1			T4	2		T11	5		T38	3
all_pins[1]	transitions[0x0=>0x1]	565	1			T4	2		T11	5		T38	3
all_pins[1]	transitions[0x1=>0x0]	51181	1			T1	7		T3	44		T4	226
all_pins[2]	values[0x0]	12265642	1			T1	7923		T3	15432		T4	35028
all_pins[2]	values[0x1]	2248348	1			T1	9905		T4	19049		T18	11352
all_pins[2]	transitions[0x0=>0x1]	2248296	1			T1	9905		T4	19049		T18	11352
all_pins[2]	transitions[0x1=>0x0]	560	1			T4	2		T11	4		T38	3