Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1067 1 T11 18 T14 17 T47 27
all_values[1] 1067 1 T11 18 T14 17 T47 27
all_values[2] 1067 1 T11 18 T14 17 T47 27


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1569 1 T11 20 T14 23 T47 35
auto[1] 1632 1 T11 34 T14 28 T47 46


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1172 1 T11 13 T14 15 T47 27
auto[1] 2029 1 T11 41 T14 36 T47 54


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1825 1 T11 28 T14 24 T47 49
auto[1] 1376 1 T11 26 T14 27 T47 32


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 200 1 T14 4 T47 7 T17 2
all_values[0] auto[0] auto[0] auto[1] 100 1 T11 5 T14 1 T47 5
all_values[0] auto[0] auto[1] auto[0] 219 1 T11 6 T14 1 T47 7
all_values[0] auto[0] auto[1] auto[1] 86 1 T14 1 T17 1 T7 3
all_values[0] auto[1] auto[0] auto[1] 229 1 T11 3 T14 5 T47 3
all_values[0] auto[1] auto[1] auto[1] 233 1 T11 4 T14 5 T47 5
all_values[1] auto[0] auto[0] auto[0] 162 1 T14 1 T47 1 T17 2
all_values[1] auto[0] auto[0] auto[1] 131 1 T11 2 T14 4 T47 2
all_values[1] auto[0] auto[1] auto[0] 152 1 T11 2 T14 1 T47 5
all_values[1] auto[0] auto[1] auto[1] 144 1 T11 3 T14 1 T47 4
all_values[1] auto[1] auto[0] auto[1] 252 1 T11 5 T14 3 T47 6
all_values[1] auto[1] auto[1] auto[1] 226 1 T11 6 T14 7 T47 9
all_values[2] auto[0] auto[0] auto[0] 202 1 T11 1 T14 1 T47 3
all_values[2] auto[0] auto[0] auto[1] 95 1 T11 2 T47 4 T7 4
all_values[2] auto[0] auto[1] auto[0] 237 1 T11 4 T14 7 T47 4
all_values[2] auto[0] auto[1] auto[1] 97 1 T11 3 T14 2 T47 7
all_values[2] auto[1] auto[0] auto[1] 198 1 T11 2 T14 4 T47 4
all_values[2] auto[1] auto[1] auto[1] 238 1 T11 6 T14 3 T47 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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