Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.32 92.47 85.27 100.00 78.95 85.98 99.49 69.08


Total test records in report: 742
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T531 /workspace/coverage/default/25.hmac_back_pressure.709146810 Apr 30 12:25:19 PM PDT 24 Apr 30 12:25:58 PM PDT 24 3886556187 ps
T532 /workspace/coverage/default/35.hmac_test_sha_vectors.1640155532 Apr 30 12:25:41 PM PDT 24 Apr 30 12:33:52 PM PDT 24 128161396841 ps
T533 /workspace/coverage/default/14.hmac_error.2317352654 Apr 30 12:25:04 PM PDT 24 Apr 30 12:25:48 PM PDT 24 3048896265 ps
T534 /workspace/coverage/default/2.hmac_smoke.1788746441 Apr 30 12:24:12 PM PDT 24 Apr 30 12:24:20 PM PDT 24 1889278404 ps
T535 /workspace/coverage/default/15.hmac_datapath_stress.2973730346 Apr 30 12:24:55 PM PDT 24 Apr 30 12:25:28 PM PDT 24 2218085686 ps
T536 /workspace/coverage/default/21.hmac_long_msg.3687765326 Apr 30 12:25:14 PM PDT 24 Apr 30 12:25:48 PM PDT 24 2480776179 ps
T537 /workspace/coverage/default/47.hmac_long_msg.3529729569 Apr 30 12:26:14 PM PDT 24 Apr 30 12:27:05 PM PDT 24 5769034439 ps
T538 /workspace/coverage/default/6.hmac_alert_test.950109813 Apr 30 12:24:29 PM PDT 24 Apr 30 12:24:31 PM PDT 24 11183326 ps
T539 /workspace/coverage/default/37.hmac_wipe_secret.3086393182 Apr 30 12:26:51 PM PDT 24 Apr 30 12:27:13 PM PDT 24 461215276 ps
T540 /workspace/coverage/default/11.hmac_wipe_secret.2802660809 Apr 30 12:24:40 PM PDT 24 Apr 30 12:25:46 PM PDT 24 3818806791 ps
T541 /workspace/coverage/default/11.hmac_stress_all.3569955369 Apr 30 12:25:00 PM PDT 24 Apr 30 12:25:02 PM PDT 24 334378794 ps
T542 /workspace/coverage/default/5.hmac_datapath_stress.1526654718 Apr 30 12:24:28 PM PDT 24 Apr 30 12:24:46 PM PDT 24 1367596972 ps
T543 /workspace/coverage/default/22.hmac_stress_all.4202360179 Apr 30 12:25:12 PM PDT 24 Apr 30 12:52:07 PM PDT 24 68375009870 ps
T544 /workspace/coverage/default/31.hmac_datapath_stress.739975047 Apr 30 12:25:26 PM PDT 24 Apr 30 12:26:46 PM PDT 24 2581111035 ps
T545 /workspace/coverage/default/24.hmac_error.2614073089 Apr 30 12:25:15 PM PDT 24 Apr 30 12:26:00 PM PDT 24 3293962258 ps
T546 /workspace/coverage/default/38.hmac_test_hmac_vectors.1775765629 Apr 30 12:25:41 PM PDT 24 Apr 30 12:25:43 PM PDT 24 464562718 ps
T547 /workspace/coverage/default/42.hmac_stress_all.3151357059 Apr 30 12:25:40 PM PDT 24 Apr 30 12:41:28 PM PDT 24 18099838827 ps
T548 /workspace/coverage/default/14.hmac_test_sha_vectors.2362184416 Apr 30 12:24:50 PM PDT 24 Apr 30 12:33:23 PM PDT 24 35662886145 ps
T549 /workspace/coverage/default/43.hmac_wipe_secret.1567613578 Apr 30 12:25:44 PM PDT 24 Apr 30 12:26:11 PM PDT 24 2188583323 ps
T550 /workspace/coverage/default/12.hmac_error.100838454 Apr 30 12:24:44 PM PDT 24 Apr 30 12:26:27 PM PDT 24 10193888450 ps
T551 /workspace/coverage/default/25.hmac_test_hmac_vectors.3324897006 Apr 30 12:25:16 PM PDT 24 Apr 30 12:25:18 PM PDT 24 44273687 ps
T552 /workspace/coverage/default/3.hmac_back_pressure.893624505 Apr 30 12:21:44 PM PDT 24 Apr 30 12:22:18 PM PDT 24 4575340126 ps
T553 /workspace/coverage/default/26.hmac_test_sha_vectors.173782521 Apr 30 12:25:24 PM PDT 24 Apr 30 12:32:42 PM PDT 24 105352510049 ps
T554 /workspace/coverage/default/10.hmac_wipe_secret.3789489851 Apr 30 12:26:01 PM PDT 24 Apr 30 12:27:16 PM PDT 24 1449661376 ps
T555 /workspace/coverage/default/38.hmac_alert_test.2241502871 Apr 30 12:27:05 PM PDT 24 Apr 30 12:27:06 PM PDT 24 14383073 ps
T556 /workspace/coverage/default/7.hmac_test_sha_vectors.867245927 Apr 30 12:24:25 PM PDT 24 Apr 30 12:32:24 PM PDT 24 101416710736 ps
T557 /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.2764426247 Apr 30 12:26:21 PM PDT 24 Apr 30 12:29:24 PM PDT 24 56324163591 ps
T558 /workspace/coverage/default/1.hmac_datapath_stress.2375502311 Apr 30 12:18:19 PM PDT 24 Apr 30 12:19:46 PM PDT 24 3065244813 ps
T559 /workspace/coverage/default/33.hmac_stress_all.905060066 Apr 30 12:25:33 PM PDT 24 Apr 30 12:52:04 PM PDT 24 28668259721 ps
T560 /workspace/coverage/default/4.hmac_wipe_secret.2778508556 Apr 30 12:24:08 PM PDT 24 Apr 30 12:24:42 PM PDT 24 3453846711 ps
T34 /workspace/coverage/default/0.hmac_sec_cm.3378782974 Apr 30 12:22:45 PM PDT 24 Apr 30 12:22:47 PM PDT 24 100090513 ps
T561 /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.3423908507 Apr 30 12:26:34 PM PDT 24 Apr 30 12:55:17 PM PDT 24 36949553360 ps
T562 /workspace/coverage/default/17.hmac_wipe_secret.1785488381 Apr 30 12:24:58 PM PDT 24 Apr 30 12:25:02 PM PDT 24 197823527 ps
T563 /workspace/coverage/default/19.hmac_long_msg.2112128687 Apr 30 12:25:01 PM PDT 24 Apr 30 12:27:00 PM PDT 24 33794165592 ps
T564 /workspace/coverage/default/23.hmac_back_pressure.584290945 Apr 30 12:25:20 PM PDT 24 Apr 30 12:25:57 PM PDT 24 3968054786 ps
T565 /workspace/coverage/default/7.hmac_alert_test.1946835422 Apr 30 12:24:29 PM PDT 24 Apr 30 12:24:31 PM PDT 24 37490951 ps
T566 /workspace/coverage/default/31.hmac_burst_wr.1108368384 Apr 30 12:25:24 PM PDT 24 Apr 30 12:25:45 PM PDT 24 1980331687 ps
T567 /workspace/coverage/default/39.hmac_back_pressure.3479248299 Apr 30 12:25:42 PM PDT 24 Apr 30 12:26:28 PM PDT 24 4911004453 ps
T568 /workspace/coverage/default/43.hmac_back_pressure.1482638415 Apr 30 12:25:42 PM PDT 24 Apr 30 12:25:59 PM PDT 24 391322657 ps
T569 /workspace/coverage/default/38.hmac_burst_wr.3917091468 Apr 30 12:25:45 PM PDT 24 Apr 30 12:26:04 PM PDT 24 2714766971 ps
T570 /workspace/coverage/default/36.hmac_alert_test.3494678372 Apr 30 12:25:36 PM PDT 24 Apr 30 12:25:37 PM PDT 24 38211023 ps
T571 /workspace/coverage/default/14.hmac_back_pressure.3841987781 Apr 30 12:24:48 PM PDT 24 Apr 30 12:25:28 PM PDT 24 1184145104 ps
T572 /workspace/coverage/default/47.hmac_stress_all.3927848517 Apr 30 12:25:50 PM PDT 24 Apr 30 12:51:20 PM PDT 24 1356839255218 ps
T573 /workspace/coverage/default/26.hmac_long_msg.2917089958 Apr 30 12:25:27 PM PDT 24 Apr 30 12:26:12 PM PDT 24 1501492752 ps
T574 /workspace/coverage/default/26.hmac_alert_test.1163654115 Apr 30 12:25:30 PM PDT 24 Apr 30 12:25:31 PM PDT 24 23443051 ps
T575 /workspace/coverage/default/17.hmac_back_pressure.1611026348 Apr 30 12:24:57 PM PDT 24 Apr 30 12:25:44 PM PDT 24 9380300835 ps
T576 /workspace/coverage/default/38.hmac_long_msg.3230686475 Apr 30 12:25:41 PM PDT 24 Apr 30 12:27:42 PM PDT 24 20165934283 ps
T577 /workspace/coverage/default/40.hmac_back_pressure.419508670 Apr 30 12:25:37 PM PDT 24 Apr 30 12:26:23 PM PDT 24 2346264778 ps
T578 /workspace/coverage/default/45.hmac_wipe_secret.3781579040 Apr 30 12:25:50 PM PDT 24 Apr 30 12:25:56 PM PDT 24 344587489 ps
T579 /workspace/coverage/default/13.hmac_test_sha_vectors.1850370889 Apr 30 12:24:48 PM PDT 24 Apr 30 12:32:14 PM PDT 24 35810625270 ps
T580 /workspace/coverage/default/9.hmac_smoke.3486654873 Apr 30 12:24:34 PM PDT 24 Apr 30 12:24:38 PM PDT 24 121389644 ps
T581 /workspace/coverage/default/48.hmac_alert_test.2069474596 Apr 30 12:25:50 PM PDT 24 Apr 30 12:25:51 PM PDT 24 47664246 ps
T582 /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.2245411209 Apr 30 12:26:29 PM PDT 24 Apr 30 12:45:16 PM PDT 24 20761258982 ps
T583 /workspace/coverage/default/4.hmac_datapath_stress.2165716428 Apr 30 12:24:08 PM PDT 24 Apr 30 12:24:44 PM PDT 24 827662588 ps
T584 /workspace/coverage/default/21.hmac_stress_all.3491907271 Apr 30 12:25:27 PM PDT 24 Apr 30 12:33:53 PM PDT 24 35958553703 ps
T585 /workspace/coverage/default/40.hmac_alert_test.1180422996 Apr 30 12:25:42 PM PDT 24 Apr 30 12:25:43 PM PDT 24 17743963 ps
T586 /workspace/coverage/default/47.hmac_burst_wr.4023575288 Apr 30 12:26:18 PM PDT 24 Apr 30 12:26:33 PM PDT 24 1288166982 ps
T587 /workspace/coverage/default/8.hmac_test_hmac_vectors.3118774875 Apr 30 12:26:02 PM PDT 24 Apr 30 12:26:04 PM PDT 24 185923767 ps
T588 /workspace/coverage/default/19.hmac_datapath_stress.42029354 Apr 30 12:25:02 PM PDT 24 Apr 30 12:25:18 PM PDT 24 2220495538 ps
T589 /workspace/coverage/default/16.hmac_test_sha_vectors.855679128 Apr 30 12:25:00 PM PDT 24 Apr 30 12:33:31 PM PDT 24 172310226920 ps
T590 /workspace/coverage/default/26.hmac_burst_wr.1679167881 Apr 30 12:25:18 PM PDT 24 Apr 30 12:26:09 PM PDT 24 3398928021 ps
T591 /workspace/coverage/default/37.hmac_test_hmac_vectors.1359136625 Apr 30 12:26:51 PM PDT 24 Apr 30 12:26:53 PM PDT 24 162001299 ps
T592 /workspace/coverage/default/34.hmac_error.288249434 Apr 30 12:25:38 PM PDT 24 Apr 30 12:27:22 PM PDT 24 35232038330 ps
T593 /workspace/coverage/default/49.hmac_error.736868033 Apr 30 12:25:54 PM PDT 24 Apr 30 12:29:07 PM PDT 24 10530210757 ps
T594 /workspace/coverage/default/10.hmac_datapath_stress.93898002 Apr 30 12:24:49 PM PDT 24 Apr 30 12:25:44 PM PDT 24 943352113 ps
T595 /workspace/coverage/default/5.hmac_burst_wr.3752300777 Apr 30 12:24:26 PM PDT 24 Apr 30 12:25:20 PM PDT 24 7973328579 ps
T596 /workspace/coverage/default/17.hmac_error.824100329 Apr 30 12:25:00 PM PDT 24 Apr 30 12:28:09 PM PDT 24 3582752025 ps
T597 /workspace/coverage/default/15.hmac_long_msg.4036590956 Apr 30 12:24:53 PM PDT 24 Apr 30 12:25:34 PM PDT 24 2029096573 ps
T598 /workspace/coverage/default/7.hmac_error.12899573 Apr 30 12:24:30 PM PDT 24 Apr 30 12:26:55 PM PDT 24 11147093034 ps
T599 /workspace/coverage/default/28.hmac_wipe_secret.3445746454 Apr 30 12:25:29 PM PDT 24 Apr 30 12:25:42 PM PDT 24 3398325136 ps
T600 /workspace/coverage/default/37.hmac_long_msg.1475065559 Apr 30 12:25:41 PM PDT 24 Apr 30 12:28:08 PM PDT 24 40079575520 ps
T601 /workspace/coverage/default/28.hmac_long_msg.2011731454 Apr 30 12:25:34 PM PDT 24 Apr 30 12:26:20 PM PDT 24 2825377373 ps
T602 /workspace/coverage/default/3.hmac_wipe_secret.3298076795 Apr 30 12:22:07 PM PDT 24 Apr 30 12:22:46 PM PDT 24 9231108479 ps
T603 /workspace/coverage/default/46.hmac_test_hmac_vectors.3384920729 Apr 30 12:25:48 PM PDT 24 Apr 30 12:25:50 PM PDT 24 64680933 ps
T604 /workspace/coverage/default/15.hmac_burst_wr.4231471872 Apr 30 12:24:49 PM PDT 24 Apr 30 12:25:25 PM PDT 24 1380701034 ps
T605 /workspace/coverage/default/47.hmac_smoke.3418947682 Apr 30 12:25:52 PM PDT 24 Apr 30 12:25:55 PM PDT 24 124469254 ps
T606 /workspace/coverage/default/12.hmac_back_pressure.1843536862 Apr 30 12:24:41 PM PDT 24 Apr 30 12:25:31 PM PDT 24 1042338552 ps
T59 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3604645571 Apr 30 12:35:38 PM PDT 24 Apr 30 12:35:39 PM PDT 24 31298327 ps
T607 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1436851905 Apr 30 12:35:53 PM PDT 24 Apr 30 12:35:55 PM PDT 24 57414504 ps
T608 /workspace/coverage/cover_reg_top/5.hmac_intr_test.501671894 Apr 30 12:35:48 PM PDT 24 Apr 30 12:35:49 PM PDT 24 15159332 ps
T71 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3794001628 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:10 PM PDT 24 20953256 ps
T60 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3414048298 Apr 30 12:35:44 PM PDT 24 Apr 30 12:35:46 PM PDT 24 29398726 ps
T609 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3120752419 Apr 30 12:35:55 PM PDT 24 Apr 30 12:35:56 PM PDT 24 91880900 ps
T72 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3242170186 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 17944969 ps
T61 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2009961550 Apr 30 12:36:07 PM PDT 24 Apr 30 12:36:08 PM PDT 24 21415845 ps
T610 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2642344845 Apr 30 12:36:13 PM PDT 24 Apr 30 12:36:14 PM PDT 24 182238690 ps
T89 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.544236152 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:45 PM PDT 24 54993478 ps
T90 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1686242087 Apr 30 12:35:47 PM PDT 24 Apr 30 12:35:48 PM PDT 24 102442928 ps
T611 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3722833822 Apr 30 12:35:57 PM PDT 24 Apr 30 12:36:00 PM PDT 24 41596502 ps
T56 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.914521311 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:04 PM PDT 24 388157240 ps
T57 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.668471588 Apr 30 12:36:03 PM PDT 24 Apr 30 12:36:06 PM PDT 24 153950032 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.475654943 Apr 30 12:35:41 PM PDT 24 Apr 30 12:35:53 PM PDT 24 4383981596 ps
T612 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3329618608 Apr 30 12:36:00 PM PDT 24 Apr 30 12:36:01 PM PDT 24 16550682 ps
T613 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3062617618 Apr 30 12:35:53 PM PDT 24 Apr 30 12:35:55 PM PDT 24 49835502 ps
T614 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2833187095 Apr 30 12:35:38 PM PDT 24 Apr 30 12:35:43 PM PDT 24 1142407481 ps
T615 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3010792855 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:54 PM PDT 24 68500649 ps
T616 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1645037504 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:54 PM PDT 24 85295014 ps
T617 /workspace/coverage/cover_reg_top/38.hmac_intr_test.4261775254 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:10 PM PDT 24 19704247 ps
T92 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3317691253 Apr 30 12:35:44 PM PDT 24 Apr 30 12:35:45 PM PDT 24 19903417 ps
T618 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.98928669 Apr 30 12:35:41 PM PDT 24 Apr 30 12:35:42 PM PDT 24 35807803 ps
T619 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1819771319 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:52 PM PDT 24 27469429 ps
T620 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2265172592 Apr 30 12:36:00 PM PDT 24 Apr 30 12:36:03 PM PDT 24 1010039501 ps
T621 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3579679899 Apr 30 12:36:07 PM PDT 24 Apr 30 12:36:26 PM PDT 24 2310673300 ps
T622 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1871229954 Apr 30 12:36:08 PM PDT 24 Apr 30 12:36:09 PM PDT 24 60151445 ps
T623 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3070171069 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:45 PM PDT 24 143046222 ps
T58 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.947057317 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:04 PM PDT 24 302996386 ps
T624 /workspace/coverage/cover_reg_top/11.hmac_intr_test.4111011968 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:54 PM PDT 24 13905413 ps
T625 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1461503569 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:53 PM PDT 24 182566602 ps
T626 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3082759187 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:10 PM PDT 24 23648060 ps
T627 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.556862192 Apr 30 12:36:01 PM PDT 24 Apr 30 12:36:02 PM PDT 24 44442803 ps
T628 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4021352636 Apr 30 12:35:34 PM PDT 24 Apr 30 12:35:36 PM PDT 24 94005066 ps
T93 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1905990054 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:05 PM PDT 24 19259008 ps
T629 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2751578499 Apr 30 12:35:45 PM PDT 24 Apr 30 12:44:02 PM PDT 24 92543918024 ps
T630 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2336773581 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:55 PM PDT 24 99426920 ps
T631 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1544936006 Apr 30 12:36:14 PM PDT 24 Apr 30 12:36:16 PM PDT 24 46340542 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3275976419 Apr 30 12:35:41 PM PDT 24 Apr 30 12:35:50 PM PDT 24 2310742297 ps
T632 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3450924988 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:10 PM PDT 24 17768919 ps
T633 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3092610569 Apr 30 12:36:00 PM PDT 24 Apr 30 12:36:02 PM PDT 24 209504425 ps
T634 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2531338534 Apr 30 12:36:03 PM PDT 24 Apr 30 12:36:05 PM PDT 24 29631082 ps
T635 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.218451796 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:45 PM PDT 24 46094215 ps
T636 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.103084797 Apr 30 12:35:47 PM PDT 24 Apr 30 12:35:52 PM PDT 24 132844482 ps
T637 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1120665200 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:44 PM PDT 24 22356587 ps
T638 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2383003519 Apr 30 12:35:49 PM PDT 24 Apr 30 12:44:47 PM PDT 24 72686862521 ps
T639 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1359759886 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:47 PM PDT 24 175612131 ps
T640 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2115149406 Apr 30 12:35:59 PM PDT 24 Apr 30 12:36:03 PM PDT 24 126344858 ps
T641 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1192851977 Apr 30 12:35:47 PM PDT 24 Apr 30 12:35:49 PM PDT 24 46054124 ps
T642 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3000203571 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:05 PM PDT 24 826307842 ps
T643 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1735991991 Apr 30 12:35:53 PM PDT 24 Apr 30 12:35:56 PM PDT 24 338841243 ps
T644 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1364909774 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:45 PM PDT 24 315140291 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2515551499 Apr 30 12:35:34 PM PDT 24 Apr 30 12:35:44 PM PDT 24 939176915 ps
T645 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.799658419 Apr 30 12:35:54 PM PDT 24 Apr 30 12:35:57 PM PDT 24 157516212 ps
T103 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3920033373 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:54 PM PDT 24 610200636 ps
T646 /workspace/coverage/cover_reg_top/22.hmac_intr_test.182829262 Apr 30 12:36:01 PM PDT 24 Apr 30 12:36:02 PM PDT 24 19940707 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3937747972 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:53 PM PDT 24 76821891 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3585505491 Apr 30 12:35:45 PM PDT 24 Apr 30 12:35:53 PM PDT 24 158589794 ps
T648 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2948970569 Apr 30 12:35:56 PM PDT 24 Apr 30 12:35:58 PM PDT 24 44307561 ps
T104 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.829763385 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:53 PM PDT 24 397710351 ps
T649 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1027224983 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:07 PM PDT 24 44528953 ps
T650 /workspace/coverage/cover_reg_top/44.hmac_intr_test.519193597 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:11 PM PDT 24 35265464 ps
T651 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2496548864 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:44 PM PDT 24 53049477 ps
T96 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1161090682 Apr 30 12:36:01 PM PDT 24 Apr 30 12:36:02 PM PDT 24 165366174 ps
T652 /workspace/coverage/cover_reg_top/40.hmac_intr_test.736877390 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:11 PM PDT 24 12541207 ps
T653 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1128558418 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:54 PM PDT 24 1441693130 ps
T654 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1853909710 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 19677332 ps
T98 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1226685937 Apr 30 12:35:55 PM PDT 24 Apr 30 12:35:56 PM PDT 24 103021316 ps
T655 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.746158559 Apr 30 12:35:33 PM PDT 24 Apr 30 12:35:37 PM PDT 24 106690661 ps
T656 /workspace/coverage/cover_reg_top/14.hmac_intr_test.994495013 Apr 30 12:36:07 PM PDT 24 Apr 30 12:36:08 PM PDT 24 20435037 ps
T108 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3673856211 Apr 30 12:35:41 PM PDT 24 Apr 30 12:35:44 PM PDT 24 906394585 ps
T106 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1197846687 Apr 30 12:36:03 PM PDT 24 Apr 30 12:36:05 PM PDT 24 86535140 ps
T657 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.961741143 Apr 30 12:36:01 PM PDT 24 Apr 30 12:39:56 PM PDT 24 22535500445 ps
T658 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1315622269 Apr 30 12:36:05 PM PDT 24 Apr 30 12:36:06 PM PDT 24 14848360 ps
T659 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.123154716 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:52 PM PDT 24 138662100 ps
T99 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3308847548 Apr 30 12:35:40 PM PDT 24 Apr 30 12:35:58 PM PDT 24 1568073701 ps
T660 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2211586306 Apr 30 12:35:56 PM PDT 24 Apr 30 12:35:57 PM PDT 24 212432366 ps
T100 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1782334597 Apr 30 12:35:49 PM PDT 24 Apr 30 12:35:51 PM PDT 24 359523272 ps
T661 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2784679502 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 67484139 ps
T662 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1950326495 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:05 PM PDT 24 63810230 ps
T62 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2863462673 Apr 30 12:35:35 PM PDT 24 Apr 30 12:35:40 PM PDT 24 519401868 ps
T101 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.193428357 Apr 30 12:35:53 PM PDT 24 Apr 30 12:35:58 PM PDT 24 898432230 ps
T663 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3976292778 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:55 PM PDT 24 323952317 ps
T664 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3715533209 Apr 30 12:35:53 PM PDT 24 Apr 30 12:35:55 PM PDT 24 30013916 ps
T102 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3458180364 Apr 30 12:36:08 PM PDT 24 Apr 30 12:36:10 PM PDT 24 52386303 ps
T665 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.198842163 Apr 30 12:35:32 PM PDT 24 Apr 30 12:35:35 PM PDT 24 87948132 ps
T666 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2239217652 Apr 30 12:35:54 PM PDT 24 Apr 30 12:35:55 PM PDT 24 38796148 ps
T107 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.344094288 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:08 PM PDT 24 190556518 ps
T667 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4094651892 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:55 PM PDT 24 41129754 ps
T668 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.119065057 Apr 30 12:35:42 PM PDT 24 Apr 30 12:35:50 PM PDT 24 834536981 ps
T669 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2362508354 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:45 PM PDT 24 84465447 ps
T670 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2741481716 Apr 30 12:35:54 PM PDT 24 Apr 30 12:35:57 PM PDT 24 65899388 ps
T671 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.794455013 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:05 PM PDT 24 32326821 ps
T672 /workspace/coverage/cover_reg_top/17.hmac_intr_test.643348557 Apr 30 12:35:58 PM PDT 24 Apr 30 12:35:59 PM PDT 24 13034633 ps
T673 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.628160183 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:52 PM PDT 24 93925136 ps
T674 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1378192803 Apr 30 12:35:41 PM PDT 24 Apr 30 12:35:42 PM PDT 24 19945704 ps
T675 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3933446152 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:04 PM PDT 24 20622052 ps
T676 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3407830825 Apr 30 12:35:45 PM PDT 24 Apr 30 12:35:48 PM PDT 24 398916431 ps
T677 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2114240100 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:52 PM PDT 24 42309565 ps
T678 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1127855933 Apr 30 12:35:42 PM PDT 24 Apr 30 12:35:46 PM PDT 24 1748551564 ps
T679 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4234540900 Apr 30 12:36:10 PM PDT 24 Apr 30 12:36:11 PM PDT 24 11845713 ps
T680 /workspace/coverage/cover_reg_top/30.hmac_intr_test.97786433 Apr 30 12:36:00 PM PDT 24 Apr 30 12:36:02 PM PDT 24 11180467 ps
T681 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.716182809 Apr 30 12:35:53 PM PDT 24 Apr 30 12:35:56 PM PDT 24 27090315 ps
T682 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.272291701 Apr 30 12:35:35 PM PDT 24 Apr 30 12:35:36 PM PDT 24 35481176 ps
T683 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.178645359 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:53 PM PDT 24 145001268 ps
T684 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1075399526 Apr 30 12:35:44 PM PDT 24 Apr 30 12:35:45 PM PDT 24 40372570 ps
T685 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2434241034 Apr 30 12:35:43 PM PDT 24 Apr 30 12:36:02 PM PDT 24 6281039714 ps
T686 /workspace/coverage/cover_reg_top/47.hmac_intr_test.217608822 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:11 PM PDT 24 53658198 ps
T687 /workspace/coverage/cover_reg_top/33.hmac_intr_test.153961726 Apr 30 12:36:12 PM PDT 24 Apr 30 12:36:14 PM PDT 24 15307493 ps
T688 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2177600383 Apr 30 12:35:54 PM PDT 24 Apr 30 12:35:56 PM PDT 24 581915203 ps
T689 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.442723207 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:52 PM PDT 24 27344773 ps
T690 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2397139598 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 180220255 ps
T691 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1400567101 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:56 PM PDT 24 98418281 ps
T692 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3025263317 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:11 PM PDT 24 21231263 ps
T693 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3553536471 Apr 30 12:35:54 PM PDT 24 Apr 30 12:35:55 PM PDT 24 38124449 ps
T694 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.518252886 Apr 30 12:35:44 PM PDT 24 Apr 30 12:35:45 PM PDT 24 15993524 ps
T695 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1684174224 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:44 PM PDT 24 12518267 ps
T696 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2394980309 Apr 30 12:35:41 PM PDT 24 Apr 30 12:35:46 PM PDT 24 191279614 ps
T697 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2779505066 Apr 30 12:35:41 PM PDT 24 Apr 30 12:35:43 PM PDT 24 62785285 ps
T698 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1234838485 Apr 30 12:35:34 PM PDT 24 Apr 30 12:35:36 PM PDT 24 80640475 ps
T699 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2869962254 Apr 30 12:36:01 PM PDT 24 Apr 30 12:36:02 PM PDT 24 60351765 ps
T700 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.339214435 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:04 PM PDT 24 110320421 ps
T701 /workspace/coverage/cover_reg_top/16.hmac_intr_test.385815423 Apr 30 12:36:03 PM PDT 24 Apr 30 12:36:04 PM PDT 24 12230825 ps
T702 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3669103595 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:51 PM PDT 24 54309238 ps
T703 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1830235174 Apr 30 12:35:49 PM PDT 24 Apr 30 12:35:51 PM PDT 24 164601394 ps
T704 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1746635941 Apr 30 12:35:56 PM PDT 24 Apr 30 12:35:59 PM PDT 24 398894055 ps
T705 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3999738308 Apr 30 12:36:12 PM PDT 24 Apr 30 12:36:14 PM PDT 24 15039048 ps
T706 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4032078299 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:53 PM PDT 24 43623592 ps
T707 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3026720542 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:04 PM PDT 24 20610285 ps
T708 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3230466452 Apr 30 12:35:55 PM PDT 24 Apr 30 12:35:56 PM PDT 24 18013900 ps
T709 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2716766552 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 12171494 ps
T710 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1403204936 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:52 PM PDT 24 32392908 ps
T711 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1332535968 Apr 30 12:35:44 PM PDT 24 Apr 30 12:35:46 PM PDT 24 82955231 ps
T712 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3377828706 Apr 30 12:36:01 PM PDT 24 Apr 30 12:36:02 PM PDT 24 24592124 ps
T713 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2941483 Apr 30 12:35:34 PM PDT 24 Apr 30 12:35:36 PM PDT 24 88857670 ps
T714 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3393298999 Apr 30 12:35:49 PM PDT 24 Apr 30 12:35:50 PM PDT 24 25782691 ps
T715 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3149707934 Apr 30 12:35:43 PM PDT 24 Apr 30 12:35:46 PM PDT 24 137821197 ps
T716 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1076660268 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:53 PM PDT 24 52771522 ps
T717 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2220380224 Apr 30 12:35:56 PM PDT 24 Apr 30 12:36:00 PM PDT 24 3687827737 ps
T718 /workspace/coverage/cover_reg_top/18.hmac_intr_test.393982339 Apr 30 12:36:02 PM PDT 24 Apr 30 12:36:03 PM PDT 24 12365164 ps
T105 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1887459571 Apr 30 12:35:42 PM PDT 24 Apr 30 12:35:47 PM PDT 24 238350128 ps
T719 /workspace/coverage/cover_reg_top/46.hmac_intr_test.276841912 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:10 PM PDT 24 83492233 ps
T720 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3961081756 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 75077078 ps
T721 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4114764694 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:55 PM PDT 24 194378132 ps
T722 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3359867285 Apr 30 12:35:50 PM PDT 24 Apr 30 12:35:51 PM PDT 24 16573413 ps
T723 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1110470935 Apr 30 12:36:03 PM PDT 24 Apr 30 12:36:04 PM PDT 24 14173709 ps
T724 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1585809015 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 119473389 ps
T725 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3643279018 Apr 30 12:35:42 PM PDT 24 Apr 30 12:35:43 PM PDT 24 18397637 ps
T726 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.456825743 Apr 30 12:35:42 PM PDT 24 Apr 30 12:35:47 PM PDT 24 1101453992 ps
T727 /workspace/coverage/cover_reg_top/0.hmac_intr_test.741403245 Apr 30 12:35:35 PM PDT 24 Apr 30 12:35:36 PM PDT 24 16966298 ps
T728 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2935098244 Apr 30 12:36:05 PM PDT 24 Apr 30 12:36:08 PM PDT 24 132528144 ps
T729 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2039949597 Apr 30 12:36:10 PM PDT 24 Apr 30 12:36:11 PM PDT 24 38325153 ps
T730 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1117240422 Apr 30 12:35:59 PM PDT 24 Apr 30 12:36:03 PM PDT 24 344885700 ps
T731 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1899267371 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:05 PM PDT 24 27426486 ps
T732 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1837175046 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:54 PM PDT 24 45094211 ps
T733 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1964986665 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:53 PM PDT 24 15355889 ps
T734 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3534980035 Apr 30 12:35:51 PM PDT 24 Apr 30 12:35:55 PM PDT 24 156083969 ps
T735 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2883389342 Apr 30 12:35:42 PM PDT 24 Apr 30 12:35:44 PM PDT 24 97287469 ps
T736 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2994185486 Apr 30 12:36:04 PM PDT 24 Apr 30 12:36:06 PM PDT 24 24284900 ps
T737 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2280657817 Apr 30 12:36:10 PM PDT 24 Apr 30 12:36:11 PM PDT 24 30632500 ps
T738 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3798883025 Apr 30 12:36:10 PM PDT 24 Apr 30 12:36:11 PM PDT 24 141533410 ps
T739 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3160774613 Apr 30 12:36:09 PM PDT 24 Apr 30 12:36:10 PM PDT 24 10866686 ps
T740 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.107613634 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:53 PM PDT 24 196185497 ps
T741 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.790985517 Apr 30 12:35:52 PM PDT 24 Apr 30 12:35:56 PM PDT 24 630007853 ps
T742 /workspace/coverage/cover_reg_top/24.hmac_intr_test.402505141 Apr 30 12:36:03 PM PDT 24 Apr 30 12:36:04 PM PDT 24 16847168 ps

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.874614291
Short name T4
Test name
Test status
Simulation time 16961302307 ps
CPU time 441.26 seconds
Started Apr 30 12:26:08 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 214972 kb
Host smart-339f9252-9d5f-4be0-b726-1210247f3cf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874614291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.874614291
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.1117276337
Short name T7
Test name
Test status
Simulation time 73712867838 ps
CPU time 2377.88 seconds
Started Apr 30 12:26:10 PM PDT 24
Finished Apr 30 01:05:49 PM PDT 24
Peak memory 248156 kb
Host smart-4b55f23d-af89-488d-9d7a-f562aee392fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117276337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.1117276337
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1098313488
Short name T24
Test name
Test status
Simulation time 66081016 ps
CPU time 0.9 seconds
Started Apr 30 12:18:58 PM PDT 24
Finished Apr 30 12:19:00 PM PDT 24
Peak memory 217916 kb
Host smart-f81acd92-6f5b-4900-9956-54a9936e4c5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098313488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1098313488
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1677233342
Short name T20
Test name
Test status
Simulation time 1395731318 ps
CPU time 11.03 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:43 PM PDT 24
Peak memory 215128 kb
Host smart-45dd5721-c63e-404a-aff2-a5a462cd1eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677233342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1677233342
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.668471588
Short name T57
Test name
Test status
Simulation time 153950032 ps
CPU time 3.03 seconds
Started Apr 30 12:36:03 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 199188 kb
Host smart-a580db10-f942-4bff-8838-7898cc68b771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668471588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.668471588
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3003236779
Short name T8
Test name
Test status
Simulation time 14283860495 ps
CPU time 680.46 seconds
Started Apr 30 12:21:59 PM PDT 24
Finished Apr 30 12:33:20 PM PDT 24
Peak memory 247968 kb
Host smart-12954b0e-e6cd-43de-a71b-74bb4674b60a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003236779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3003236779
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1905990054
Short name T93
Test name
Test status
Simulation time 19259008 ps
CPU time 0.84 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 198472 kb
Host smart-63c6ab75-d31b-4b6a-8460-f9b8eb7946a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905990054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1905990054
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/default/16.hmac_error.135160083
Short name T1
Test name
Test status
Simulation time 8568408613 ps
CPU time 90.67 seconds
Started Apr 30 12:25:02 PM PDT 24
Finished Apr 30 12:26:33 PM PDT 24
Peak memory 199448 kb
Host smart-bf33e133-924c-41a7-8b98-a181295450c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135160083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.135160083
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.193428357
Short name T101
Test name
Test status
Simulation time 898432230 ps
CPU time 4.3 seconds
Started Apr 30 12:35:53 PM PDT 24
Finished Apr 30 12:35:58 PM PDT 24
Peak memory 199508 kb
Host smart-6c976274-6202-49dc-a909-a20f0b7bf72c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193428357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.193428357
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/19.hmac_stress_all.4131860602
Short name T14
Test name
Test status
Simulation time 175345622601 ps
CPU time 667.97 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:36:08 PM PDT 24
Peak memory 232316 kb
Host smart-28b55cbe-875c-41d2-9e6c-628fe9a31c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131860602 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.4131860602
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3592248141
Short name T21
Test name
Test status
Simulation time 36010683 ps
CPU time 0.62 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:25:02 PM PDT 24
Peak memory 194032 kb
Host smart-100023e8-62ab-4991-af6d-46a12a71a0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592248141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3592248141
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1646118050
Short name T6
Test name
Test status
Simulation time 5628018758 ps
CPU time 54.59 seconds
Started Apr 30 12:25:52 PM PDT 24
Finished Apr 30 12:26:47 PM PDT 24
Peak memory 240388 kb
Host smart-1ecef896-1241-4396-a4c9-e86523d2915d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646118050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1646118050
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3564625153
Short name T73
Test name
Test status
Simulation time 909411121 ps
CPU time 41.46 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 198644 kb
Host smart-53e5c3c2-f732-4122-b213-7bd8751056e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564625153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3564625153
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_error.1235806181
Short name T48
Test name
Test status
Simulation time 16593257031 ps
CPU time 71.97 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:26:29 PM PDT 24
Peak memory 199520 kb
Host smart-280dc0fa-a137-44ad-94c3-44675c464045
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235806181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1235806181
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2863462673
Short name T62
Test name
Test status
Simulation time 519401868 ps
CPU time 3.92 seconds
Started Apr 30 12:35:35 PM PDT 24
Finished Apr 30 12:35:40 PM PDT 24
Peak memory 199236 kb
Host smart-a7dea4c1-c826-4c75-aa53-d52180e3154e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863462673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2863462673
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.914521311
Short name T56
Test name
Test status
Simulation time 388157240 ps
CPU time 1.94 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 199148 kb
Host smart-4833d318-317a-4ed9-a672-3475e23e3423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914521311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.914521311
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.590332836
Short name T44
Test name
Test status
Simulation time 94782988491 ps
CPU time 421.97 seconds
Started Apr 30 12:26:11 PM PDT 24
Finished Apr 30 12:33:14 PM PDT 24
Peak memory 209472 kb
Host smart-545b9a1b-aebc-4041-a249-82a67bca8ddb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590332836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.590332836
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_stress_all.713187905
Short name T51
Test name
Test status
Simulation time 122979143889 ps
CPU time 465.04 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:33:22 PM PDT 24
Peak memory 231048 kb
Host smart-f042dea1-a44f-458f-84ac-8ac23f95f061
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713187905 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.713187905
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2833187095
Short name T614
Test name
Test status
Simulation time 1142407481 ps
CPU time 5.42 seconds
Started Apr 30 12:35:38 PM PDT 24
Finished Apr 30 12:35:43 PM PDT 24
Peak memory 199448 kb
Host smart-f927eb67-b165-4af6-ac08-1e3c81b1425e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833187095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2833187095
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2515551499
Short name T97
Test name
Test status
Simulation time 939176915 ps
CPU time 9.51 seconds
Started Apr 30 12:35:34 PM PDT 24
Finished Apr 30 12:35:44 PM PDT 24
Peak memory 198132 kb
Host smart-faa850b9-2393-41b1-aabd-b17b1605eaca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515551499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2515551499
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.272291701
Short name T682
Test name
Test status
Simulation time 35481176 ps
CPU time 1.01 seconds
Started Apr 30 12:35:35 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 199156 kb
Host smart-b7b0d1a6-6190-42ad-be0c-f59308eb0f14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272291701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.272291701
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.746158559
Short name T655
Test name
Test status
Simulation time 106690661 ps
CPU time 3.53 seconds
Started Apr 30 12:35:33 PM PDT 24
Finished Apr 30 12:35:37 PM PDT 24
Peak memory 207412 kb
Host smart-4cb64c3d-4549-4e7d-9ec6-21b46b571293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746158559 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.746158559
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3604645571
Short name T59
Test name
Test status
Simulation time 31298327 ps
CPU time 0.92 seconds
Started Apr 30 12:35:38 PM PDT 24
Finished Apr 30 12:35:39 PM PDT 24
Peak memory 198696 kb
Host smart-f2449a3a-f576-4604-8531-465af75c8137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604645571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3604645571
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.741403245
Short name T727
Test name
Test status
Simulation time 16966298 ps
CPU time 0.66 seconds
Started Apr 30 12:35:35 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 194084 kb
Host smart-921b6c3b-d61e-477d-b3f1-f5a6dd7971b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741403245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.741403245
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2941483
Short name T713
Test name
Test status
Simulation time 88857670 ps
CPU time 1.24 seconds
Started Apr 30 12:35:34 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 199168 kb
Host smart-2df8a73b-1a45-4f6a-a16c-78d7e44d1c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_ou
tstanding.2941483
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1234838485
Short name T698
Test name
Test status
Simulation time 80640475 ps
CPU time 1.76 seconds
Started Apr 30 12:35:34 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 199248 kb
Host smart-ec8ee399-eead-453d-89dd-cd71bfdd22e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234838485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1234838485
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.198842163
Short name T665
Test name
Test status
Simulation time 87948132 ps
CPU time 2.78 seconds
Started Apr 30 12:35:32 PM PDT 24
Finished Apr 30 12:35:35 PM PDT 24
Peak memory 199160 kb
Host smart-ee66ea1e-0730-4e2e-9e73-34b4f4768e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198842163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.198842163
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1127855933
Short name T678
Test name
Test status
Simulation time 1748551564 ps
CPU time 3.45 seconds
Started Apr 30 12:35:42 PM PDT 24
Finished Apr 30 12:35:46 PM PDT 24
Peak memory 199004 kb
Host smart-84d00da4-8855-4548-8d5e-16befd3fd715
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127855933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1127855933
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.475654943
Short name T91
Test name
Test status
Simulation time 4383981596 ps
CPU time 11.19 seconds
Started Apr 30 12:35:41 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 199148 kb
Host smart-e1e49f04-b6ee-4890-9fb1-973bd873c5c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475654943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.475654943
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.98928669
Short name T618
Test name
Test status
Simulation time 35807803 ps
CPU time 0.79 seconds
Started Apr 30 12:35:41 PM PDT 24
Finished Apr 30 12:35:42 PM PDT 24
Peak memory 197312 kb
Host smart-e7f5861e-0434-49e4-b783-948eb802cb9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98928669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.98928669
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2751578499
Short name T629
Test name
Test status
Simulation time 92543918024 ps
CPU time 496.89 seconds
Started Apr 30 12:35:45 PM PDT 24
Finished Apr 30 12:44:02 PM PDT 24
Peak memory 214780 kb
Host smart-611e4da7-1748-4feb-b91c-49de67904372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751578499 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2751578499
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3643279018
Short name T725
Test name
Test status
Simulation time 18397637 ps
CPU time 0.69 seconds
Started Apr 30 12:35:42 PM PDT 24
Finished Apr 30 12:35:43 PM PDT 24
Peak memory 196732 kb
Host smart-3def30e9-5615-452d-9359-d4a3e631baec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643279018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3643279018
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1684174224
Short name T695
Test name
Test status
Simulation time 12518267 ps
CPU time 0.55 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:44 PM PDT 24
Peak memory 193964 kb
Host smart-809d659f-8930-495f-bb71-7b8b14fd6871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684174224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1684174224
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3407830825
Short name T676
Test name
Test status
Simulation time 398916431 ps
CPU time 1.89 seconds
Started Apr 30 12:35:45 PM PDT 24
Finished Apr 30 12:35:48 PM PDT 24
Peak memory 198340 kb
Host smart-8e6221ed-4982-4b17-b913-364aae61cdca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407830825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3407830825
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4021352636
Short name T628
Test name
Test status
Simulation time 94005066 ps
CPU time 1.22 seconds
Started Apr 30 12:35:34 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 199328 kb
Host smart-80e8280d-f079-469d-a3f0-de5af81b3e85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021352636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4021352636
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.178645359
Short name T683
Test name
Test status
Simulation time 145001268 ps
CPU time 1.83 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 199256 kb
Host smart-3f0d47fe-2602-4958-9aa2-cc7ea9fedb31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178645359 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.178645359
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3359867285
Short name T722
Test name
Test status
Simulation time 16573413 ps
CPU time 0.88 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:51 PM PDT 24
Peak memory 199032 kb
Host smart-a1048af8-45b6-4b3f-ba6c-cbd48b25ca7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359867285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3359867285
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1964986665
Short name T733
Test name
Test status
Simulation time 15355889 ps
CPU time 0.58 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 194092 kb
Host smart-95fe8d99-4e8a-4b0d-83e0-a818379a0e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964986665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1964986665
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1735991991
Short name T643
Test name
Test status
Simulation time 338841243 ps
CPU time 2.45 seconds
Started Apr 30 12:35:53 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 198968 kb
Host smart-4ee0c915-b789-43e1-8e12-7d508d1fb65d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735991991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1735991991
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2948970569
Short name T648
Test name
Test status
Simulation time 44307561 ps
CPU time 1.3 seconds
Started Apr 30 12:35:56 PM PDT 24
Finished Apr 30 12:35:58 PM PDT 24
Peak memory 199164 kb
Host smart-c92aaf30-ce92-4516-a7f5-43e26d580297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948970569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2948970569
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1782334597
Short name T100
Test name
Test status
Simulation time 359523272 ps
CPU time 1.71 seconds
Started Apr 30 12:35:49 PM PDT 24
Finished Apr 30 12:35:51 PM PDT 24
Peak memory 199228 kb
Host smart-3c6035d8-bb91-4f4e-b417-c82820ab9ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782334597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1782334597
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4032078299
Short name T706
Test name
Test status
Simulation time 43623592 ps
CPU time 1.19 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 199132 kb
Host smart-e8bd8eb8-413c-4978-9f89-6c3ae95a9215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032078299 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4032078299
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1819771319
Short name T619
Test name
Test status
Simulation time 27469429 ps
CPU time 0.67 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 196892 kb
Host smart-dcf076df-ee26-42d4-88f4-a47bf765dd3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819771319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1819771319
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.4111011968
Short name T624
Test name
Test status
Simulation time 13905413 ps
CPU time 0.61 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:54 PM PDT 24
Peak memory 194160 kb
Host smart-062403be-63e4-4eb1-b90c-d5d6a25d59c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111011968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.4111011968
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3062617618
Short name T613
Test name
Test status
Simulation time 49835502 ps
CPU time 1.25 seconds
Started Apr 30 12:35:53 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 199120 kb
Host smart-f8de27cc-8b31-4b58-8d0d-89582c1c41ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062617618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3062617618
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1436851905
Short name T607
Test name
Test status
Simulation time 57414504 ps
CPU time 1.57 seconds
Started Apr 30 12:35:53 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 199264 kb
Host smart-faffb39b-e910-4f2a-ae59-b5f2a6faafdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436851905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1436851905
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3976292778
Short name T663
Test name
Test status
Simulation time 323952317 ps
CPU time 3.87 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 199220 kb
Host smart-5226fb68-dd85-45ac-90d0-fa3079604df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976292778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3976292778
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1128558418
Short name T653
Test name
Test status
Simulation time 1441693130 ps
CPU time 1.82 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:54 PM PDT 24
Peak memory 199184 kb
Host smart-d04c0d46-9c43-45b0-99c8-ad166d7c9939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128558418 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1128558418
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.107613634
Short name T740
Test name
Test status
Simulation time 196185497 ps
CPU time 0.74 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 198104 kb
Host smart-25256d1d-ee1e-4181-9408-8b2f85ea3c42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107613634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.107613634
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1403204936
Short name T710
Test name
Test status
Simulation time 32392908 ps
CPU time 0.55 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 193960 kb
Host smart-7cfe6796-ebc8-4e90-b54e-1271045d9faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403204936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1403204936
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1645037504
Short name T616
Test name
Test status
Simulation time 85295014 ps
CPU time 1.77 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:54 PM PDT 24
Peak memory 199056 kb
Host smart-3292e278-3a06-439c-9b02-fe010a3243da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645037504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1645037504
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3010792855
Short name T615
Test name
Test status
Simulation time 68500649 ps
CPU time 2.01 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:54 PM PDT 24
Peak memory 199260 kb
Host smart-6c204ac0-26ec-4ce6-890b-cd7dde42eb37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010792855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3010792855
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.799658419
Short name T645
Test name
Test status
Simulation time 157516212 ps
CPU time 2.58 seconds
Started Apr 30 12:35:54 PM PDT 24
Finished Apr 30 12:35:57 PM PDT 24
Peak memory 214956 kb
Host smart-cd76b261-b6b3-42c8-815e-b179fc96dd5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799658419 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.799658419
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2239217652
Short name T666
Test name
Test status
Simulation time 38796148 ps
CPU time 0.82 seconds
Started Apr 30 12:35:54 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 198680 kb
Host smart-043d258f-0cd0-4c3b-90a8-0deb385fa4ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239217652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2239217652
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3553536471
Short name T693
Test name
Test status
Simulation time 38124449 ps
CPU time 0.58 seconds
Started Apr 30 12:35:54 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 194108 kb
Host smart-8d3f92d2-6754-4715-b6dd-26dae9aa28dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553536471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3553536471
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2177600383
Short name T688
Test name
Test status
Simulation time 581915203 ps
CPU time 1.75 seconds
Started Apr 30 12:35:54 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 199204 kb
Host smart-51f3b96f-30bb-49da-9847-f359047e946a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177600383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2177600383
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2211586306
Short name T660
Test name
Test status
Simulation time 212432366 ps
CPU time 1.44 seconds
Started Apr 30 12:35:56 PM PDT 24
Finished Apr 30 12:35:57 PM PDT 24
Peak memory 199272 kb
Host smart-fa7e7fcb-02ce-4075-9952-2c0076fa1381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211586306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2211586306
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3534980035
Short name T734
Test name
Test status
Simulation time 156083969 ps
CPU time 3.2 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 199208 kb
Host smart-d6034894-cb24-4069-b11a-08a058f517ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534980035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3534980035
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.961741143
Short name T657
Test name
Test status
Simulation time 22535500445 ps
CPU time 235.13 seconds
Started Apr 30 12:36:01 PM PDT 24
Finished Apr 30 12:39:56 PM PDT 24
Peak memory 214964 kb
Host smart-7efc43bf-bef2-4406-b9e0-712639354922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961741143 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.961741143
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1161090682
Short name T96
Test name
Test status
Simulation time 165366174 ps
CPU time 0.92 seconds
Started Apr 30 12:36:01 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 198748 kb
Host smart-7cdfb684-b498-4387-a6c0-9256ae668e52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161090682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1161090682
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.994495013
Short name T656
Test name
Test status
Simulation time 20435037 ps
CPU time 0.64 seconds
Started Apr 30 12:36:07 PM PDT 24
Finished Apr 30 12:36:08 PM PDT 24
Peak memory 194116 kb
Host smart-fd613e44-b560-468e-bb03-ea0c56d3dbcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994495013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.994495013
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2009961550
Short name T61
Test name
Test status
Simulation time 21415845 ps
CPU time 1.13 seconds
Started Apr 30 12:36:07 PM PDT 24
Finished Apr 30 12:36:08 PM PDT 24
Peak memory 197476 kb
Host smart-1e9f864b-ac16-4c8a-aa7b-9bcb8f038ad6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009961550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2009961550
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3377828706
Short name T712
Test name
Test status
Simulation time 24592124 ps
CPU time 1.21 seconds
Started Apr 30 12:36:01 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 199188 kb
Host smart-19cbb9cd-a04c-4d0c-955a-f9c9d7f1e8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377828706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3377828706
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2935098244
Short name T728
Test name
Test status
Simulation time 132528144 ps
CPU time 1.68 seconds
Started Apr 30 12:36:05 PM PDT 24
Finished Apr 30 12:36:08 PM PDT 24
Peak memory 199228 kb
Host smart-27909ede-4646-4ce5-b673-86ee79f88253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935098244 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2935098244
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2784679502
Short name T661
Test name
Test status
Simulation time 67484139 ps
CPU time 0.6 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 194028 kb
Host smart-3bbc21ee-3980-41ac-b853-a89bf1ccb221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784679502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2784679502
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2265172592
Short name T620
Test name
Test status
Simulation time 1010039501 ps
CPU time 2.35 seconds
Started Apr 30 12:36:00 PM PDT 24
Finished Apr 30 12:36:03 PM PDT 24
Peak memory 199016 kb
Host smart-6f475007-c6f2-49b7-8aa6-62d44f9658e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265172592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2265172592
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1585809015
Short name T724
Test name
Test status
Simulation time 119473389 ps
CPU time 1.27 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 199196 kb
Host smart-e86eeda8-3011-4ac6-beca-bde58e5ed8b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585809015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1585809015
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1197846687
Short name T106
Test name
Test status
Simulation time 86535140 ps
CPU time 1.71 seconds
Started Apr 30 12:36:03 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 199260 kb
Host smart-f9576b8b-fd5b-44c2-9f26-11c915a65699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197846687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1197846687
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3579679899
Short name T621
Test name
Test status
Simulation time 2310673300 ps
CPU time 18.11 seconds
Started Apr 30 12:36:07 PM PDT 24
Finished Apr 30 12:36:26 PM PDT 24
Peak memory 214872 kb
Host smart-9f82172a-cd10-4cc8-b01e-077d96cc0774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579679899 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3579679899
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3961081756
Short name T720
Test name
Test status
Simulation time 75077078 ps
CPU time 0.7 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 196732 kb
Host smart-997f734e-3915-42d3-8a4b-dfea98323e34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961081756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3961081756
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.385815423
Short name T701
Test name
Test status
Simulation time 12230825 ps
CPU time 0.61 seconds
Started Apr 30 12:36:03 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 194076 kb
Host smart-1ac125c2-00ff-4c73-97e2-fa6f55902fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385815423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.385815423
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3722833822
Short name T611
Test name
Test status
Simulation time 41596502 ps
CPU time 2.02 seconds
Started Apr 30 12:35:57 PM PDT 24
Finished Apr 30 12:36:00 PM PDT 24
Peak memory 199060 kb
Host smart-1dfad1ec-e402-4ac9-bd22-7c13fded6f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722833822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3722833822
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1027224983
Short name T649
Test name
Test status
Simulation time 44528953 ps
CPU time 2.12 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:07 PM PDT 24
Peak memory 199332 kb
Host smart-f33b596d-6a49-4ca9-8ac6-ec065335b31f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027224983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1027224983
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.947057317
Short name T58
Test name
Test status
Simulation time 302996386 ps
CPU time 1.73 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 199220 kb
Host smart-8045e144-3d26-4c02-adc3-597c63e5a3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947057317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.947057317
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2115149406
Short name T640
Test name
Test status
Simulation time 126344858 ps
CPU time 3.86 seconds
Started Apr 30 12:35:59 PM PDT 24
Finished Apr 30 12:36:03 PM PDT 24
Peak memory 199264 kb
Host smart-903f4537-c216-4085-9689-a0667c12b390
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115149406 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2115149406
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3329618608
Short name T612
Test name
Test status
Simulation time 16550682 ps
CPU time 0.78 seconds
Started Apr 30 12:36:00 PM PDT 24
Finished Apr 30 12:36:01 PM PDT 24
Peak memory 198540 kb
Host smart-32012ca3-3d2c-44de-8171-48678d8a349e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329618608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3329618608
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.643348557
Short name T672
Test name
Test status
Simulation time 13034633 ps
CPU time 0.55 seconds
Started Apr 30 12:35:58 PM PDT 24
Finished Apr 30 12:35:59 PM PDT 24
Peak memory 194056 kb
Host smart-434432a6-f123-4853-803d-e0ee4e516ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643348557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.643348557
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.556862192
Short name T627
Test name
Test status
Simulation time 44442803 ps
CPU time 1.1 seconds
Started Apr 30 12:36:01 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 197636 kb
Host smart-98466d72-ed16-419b-9f64-8ea24bddbf20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556862192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.556862192
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1117240422
Short name T730
Test name
Test status
Simulation time 344885700 ps
CPU time 3.95 seconds
Started Apr 30 12:35:59 PM PDT 24
Finished Apr 30 12:36:03 PM PDT 24
Peak memory 199368 kb
Host smart-0f5e0107-13a4-46e2-a683-4faada843c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117240422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1117240422
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1950326495
Short name T662
Test name
Test status
Simulation time 63810230 ps
CPU time 1.83 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 199228 kb
Host smart-9ced05e3-cbf7-4fd7-8a2e-5d0ab6a3c60a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950326495 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1950326495
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2531338534
Short name T634
Test name
Test status
Simulation time 29631082 ps
CPU time 0.95 seconds
Started Apr 30 12:36:03 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 198472 kb
Host smart-97ffbd09-6c14-4293-bf7e-71dd42a6b8c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531338534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2531338534
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.393982339
Short name T718
Test name
Test status
Simulation time 12365164 ps
CPU time 0.64 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:03 PM PDT 24
Peak memory 193908 kb
Host smart-f3e64e9a-63cd-477a-afbe-8ebf9879572c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393982339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.393982339
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3092610569
Short name T633
Test name
Test status
Simulation time 209504425 ps
CPU time 1.84 seconds
Started Apr 30 12:36:00 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 198868 kb
Host smart-c8f82ad8-9e01-415c-a93e-72ceb7cb9305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092610569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3092610569
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.339214435
Short name T700
Test name
Test status
Simulation time 110320421 ps
CPU time 1.32 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 199264 kb
Host smart-07a934df-c35c-4100-a396-de81e82444ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339214435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.339214435
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.344094288
Short name T107
Test name
Test status
Simulation time 190556518 ps
CPU time 3.29 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:08 PM PDT 24
Peak memory 199348 kb
Host smart-72e2d0bf-d817-4218-b330-69698748bbc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344094288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.344094288
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2397139598
Short name T690
Test name
Test status
Simulation time 180220255 ps
CPU time 1.24 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 199152 kb
Host smart-3b5a52d0-681e-42d1-94e8-c2c866ecdb1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397139598 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2397139598
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.794455013
Short name T671
Test name
Test status
Simulation time 32326821 ps
CPU time 0.66 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 196764 kb
Host smart-49ff807b-2ddd-4f89-a77c-2d74ab656d2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794455013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.794455013
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1899267371
Short name T731
Test name
Test status
Simulation time 27426486 ps
CPU time 0.59 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 193904 kb
Host smart-e177ae59-7138-4b60-86ee-e68c5a08851b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899267371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1899267371
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3026720542
Short name T707
Test name
Test status
Simulation time 20610285 ps
CPU time 1.06 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 198876 kb
Host smart-9c24f70d-300a-4282-a7e9-0a1294cd00c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026720542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3026720542
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3000203571
Short name T642
Test name
Test status
Simulation time 826307842 ps
CPU time 2.94 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 199208 kb
Host smart-56ea6660-fae5-4c0d-b540-0f32df2ced34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000203571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3000203571
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3458180364
Short name T102
Test name
Test status
Simulation time 52386303 ps
CPU time 1.74 seconds
Started Apr 30 12:36:08 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 199096 kb
Host smart-cc69212f-97e1-46e6-84ed-797e08851cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458180364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3458180364
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3585505491
Short name T95
Test name
Test status
Simulation time 158589794 ps
CPU time 7.63 seconds
Started Apr 30 12:35:45 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 199168 kb
Host smart-f842b5c8-da76-44da-8954-3492849e5a54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585505491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3585505491
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2434241034
Short name T685
Test name
Test status
Simulation time 6281039714 ps
CPU time 17.59 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 199100 kb
Host smart-73bba767-19fc-4077-8274-60c3db373d08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434241034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2434241034
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.544236152
Short name T89
Test name
Test status
Simulation time 54993478 ps
CPU time 0.87 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 198104 kb
Host smart-98d5232e-b11c-4424-a39c-76b38eceff99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544236152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.544236152
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1192851977
Short name T641
Test name
Test status
Simulation time 46054124 ps
CPU time 1.32 seconds
Started Apr 30 12:35:47 PM PDT 24
Finished Apr 30 12:35:49 PM PDT 24
Peak memory 199172 kb
Host smart-1286e947-0be4-49c0-baf8-593e31a0ead0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192851977 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1192851977
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2883389342
Short name T735
Test name
Test status
Simulation time 97287469 ps
CPU time 0.9 seconds
Started Apr 30 12:35:42 PM PDT 24
Finished Apr 30 12:35:44 PM PDT 24
Peak memory 198648 kb
Host smart-86ac5fa0-9f46-4b16-8330-7708f8909585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883389342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2883389342
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2114240100
Short name T677
Test name
Test status
Simulation time 42309565 ps
CPU time 0.57 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 194040 kb
Host smart-776de4f5-68d7-497f-aae5-ff2e79867ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114240100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2114240100
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3070171069
Short name T623
Test name
Test status
Simulation time 143046222 ps
CPU time 1.59 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 198900 kb
Host smart-56e713e9-5d23-4c17-9a79-16d58dc6f912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070171069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3070171069
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2779505066
Short name T697
Test name
Test status
Simulation time 62785285 ps
CPU time 1.48 seconds
Started Apr 30 12:35:41 PM PDT 24
Finished Apr 30 12:35:43 PM PDT 24
Peak memory 199188 kb
Host smart-7d2e4348-8752-497e-a252-ec8d77ab1f51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779505066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2779505066
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.790985517
Short name T741
Test name
Test status
Simulation time 630007853 ps
CPU time 3.24 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 199264 kb
Host smart-48e8b04c-0e11-428e-8a57-1a81e4435cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790985517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.790985517
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2716766552
Short name T709
Test name
Test status
Simulation time 12171494 ps
CPU time 0.61 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 194200 kb
Host smart-f7e890dd-c443-489d-b013-796dea9f49db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716766552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2716766552
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3242170186
Short name T72
Test name
Test status
Simulation time 17944969 ps
CPU time 0.6 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 193912 kb
Host smart-227794db-0829-49b2-8587-75b9ce7c3602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242170186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3242170186
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.182829262
Short name T646
Test name
Test status
Simulation time 19940707 ps
CPU time 0.57 seconds
Started Apr 30 12:36:01 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 194080 kb
Host smart-a43d6092-c442-41dc-aa55-7c39807a852a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182829262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.182829262
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1853909710
Short name T654
Test name
Test status
Simulation time 19677332 ps
CPU time 0.61 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 194048 kb
Host smart-2bf94006-10be-4e17-a120-b96417be1aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853909710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1853909710
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.402505141
Short name T742
Test name
Test status
Simulation time 16847168 ps
CPU time 0.54 seconds
Started Apr 30 12:36:03 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 194000 kb
Host smart-597bcc7a-444b-4745-9666-83a36df9462d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402505141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.402505141
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1315622269
Short name T658
Test name
Test status
Simulation time 14848360 ps
CPU time 0.63 seconds
Started Apr 30 12:36:05 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 194044 kb
Host smart-d0c266b1-c895-4c45-9b86-87ad7fafe58d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315622269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1315622269
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2869962254
Short name T699
Test name
Test status
Simulation time 60351765 ps
CPU time 0.62 seconds
Started Apr 30 12:36:01 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 194000 kb
Host smart-e551d187-1f54-47d4-9cbe-59c49b33daad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869962254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2869962254
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3933446152
Short name T675
Test name
Test status
Simulation time 20622052 ps
CPU time 0.68 seconds
Started Apr 30 12:36:02 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 193988 kb
Host smart-4a5e632d-9ed4-4b34-a4ba-61e1fe00f439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933446152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3933446152
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2994185486
Short name T736
Test name
Test status
Simulation time 24284900 ps
CPU time 0.58 seconds
Started Apr 30 12:36:04 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 194216 kb
Host smart-e777981d-606c-481a-969f-51b29f4f5194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994185486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2994185486
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1110470935
Short name T723
Test name
Test status
Simulation time 14173709 ps
CPU time 0.55 seconds
Started Apr 30 12:36:03 PM PDT 24
Finished Apr 30 12:36:04 PM PDT 24
Peak memory 194064 kb
Host smart-29592907-b73c-4eff-bfec-0170d461331c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110470935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1110470935
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3275976419
Short name T94
Test name
Test status
Simulation time 2310742297 ps
CPU time 8.73 seconds
Started Apr 30 12:35:41 PM PDT 24
Finished Apr 30 12:35:50 PM PDT 24
Peak memory 199360 kb
Host smart-abdae6b7-acf4-40ba-9e5e-4dfc97defa9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275976419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3275976419
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.103084797
Short name T636
Test name
Test status
Simulation time 132844482 ps
CPU time 4.8 seconds
Started Apr 30 12:35:47 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 198060 kb
Host smart-08719b3f-acb9-4721-bc83-46403aad63d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103084797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.103084797
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3317691253
Short name T92
Test name
Test status
Simulation time 19903417 ps
CPU time 0.84 seconds
Started Apr 30 12:35:44 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 198320 kb
Host smart-e191daef-138c-4ea7-84b7-c3bc804cf10f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317691253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3317691253
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2362508354
Short name T669
Test name
Test status
Simulation time 84465447 ps
CPU time 1.3 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 199080 kb
Host smart-3555375c-87d0-4e8d-a9df-a4d4f0a3b252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362508354 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2362508354
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.518252886
Short name T694
Test name
Test status
Simulation time 15993524 ps
CPU time 0.81 seconds
Started Apr 30 12:35:44 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 198028 kb
Host smart-d99e09da-ba2f-41cd-8202-bd44ea10f13d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518252886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.518252886
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1075399526
Short name T684
Test name
Test status
Simulation time 40372570 ps
CPU time 0.56 seconds
Started Apr 30 12:35:44 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 193984 kb
Host smart-15804d3d-d38f-403a-87a6-d4cb96f09a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075399526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1075399526
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1332535968
Short name T711
Test name
Test status
Simulation time 82955231 ps
CPU time 1.21 seconds
Started Apr 30 12:35:44 PM PDT 24
Finished Apr 30 12:35:46 PM PDT 24
Peak memory 199152 kb
Host smart-20c689c7-f082-4155-825e-8a5eb15e9048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332535968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1332535968
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1359759886
Short name T639
Test name
Test status
Simulation time 175612131 ps
CPU time 3.79 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:47 PM PDT 24
Peak memory 199224 kb
Host smart-07fd0383-6e05-4371-bd39-d32d2055600f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359759886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1359759886
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4114764694
Short name T721
Test name
Test status
Simulation time 194378132 ps
CPU time 1.87 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 199216 kb
Host smart-f8b415be-ac7c-4790-ad97-08c9c192490f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114764694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4114764694
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.97786433
Short name T680
Test name
Test status
Simulation time 11180467 ps
CPU time 0.55 seconds
Started Apr 30 12:36:00 PM PDT 24
Finished Apr 30 12:36:02 PM PDT 24
Peak memory 193920 kb
Host smart-df36438e-eb9a-4e8a-98af-1e8432ed7489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97786433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.97786433
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3450924988
Short name T632
Test name
Test status
Simulation time 17768919 ps
CPU time 0.58 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 193904 kb
Host smart-b1397681-e78c-49bb-b17f-e7e82d242484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450924988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3450924988
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1871229954
Short name T622
Test name
Test status
Simulation time 60151445 ps
CPU time 0.61 seconds
Started Apr 30 12:36:08 PM PDT 24
Finished Apr 30 12:36:09 PM PDT 24
Peak memory 194060 kb
Host smart-e09f707b-d6f3-4c28-8e30-281c5172fbec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871229954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1871229954
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.153961726
Short name T687
Test name
Test status
Simulation time 15307493 ps
CPU time 0.6 seconds
Started Apr 30 12:36:12 PM PDT 24
Finished Apr 30 12:36:14 PM PDT 24
Peak memory 194028 kb
Host smart-def869b4-0828-4c4f-b769-5af0147678c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153961726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.153961726
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3082759187
Short name T626
Test name
Test status
Simulation time 23648060 ps
CPU time 0.62 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 194220 kb
Host smart-128a6ea8-f814-4ffa-89e9-b341357a094c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082759187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3082759187
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3160774613
Short name T739
Test name
Test status
Simulation time 10866686 ps
CPU time 0.58 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 193916 kb
Host smart-8a288f37-7828-424b-8215-fe64360b03e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160774613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3160774613
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4234540900
Short name T679
Test name
Test status
Simulation time 11845713 ps
CPU time 0.56 seconds
Started Apr 30 12:36:10 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 194000 kb
Host smart-7be298e3-59d2-4bc7-8a19-bae2998d2cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234540900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4234540900
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2039949597
Short name T729
Test name
Test status
Simulation time 38325153 ps
CPU time 0.59 seconds
Started Apr 30 12:36:10 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 193932 kb
Host smart-3c71932c-315f-4927-b1d9-c39aa71f8249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039949597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2039949597
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.4261775254
Short name T617
Test name
Test status
Simulation time 19704247 ps
CPU time 0.61 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 194196 kb
Host smart-1d9c23b2-9a42-44fb-ac93-a046d5123d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261775254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4261775254
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3999738308
Short name T705
Test name
Test status
Simulation time 15039048 ps
CPU time 0.6 seconds
Started Apr 30 12:36:12 PM PDT 24
Finished Apr 30 12:36:14 PM PDT 24
Peak memory 194088 kb
Host smart-01ab1d89-9eeb-4f80-9797-31bb712c0bbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999738308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3999738308
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.119065057
Short name T668
Test name
Test status
Simulation time 834536981 ps
CPU time 7.76 seconds
Started Apr 30 12:35:42 PM PDT 24
Finished Apr 30 12:35:50 PM PDT 24
Peak memory 199148 kb
Host smart-2df06e70-4526-498c-bc3e-bbb89bd7eb9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119065057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.119065057
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3308847548
Short name T99
Test name
Test status
Simulation time 1568073701 ps
CPU time 16.91 seconds
Started Apr 30 12:35:40 PM PDT 24
Finished Apr 30 12:35:58 PM PDT 24
Peak memory 198964 kb
Host smart-3aa2fc4a-426a-40f2-9db8-facdd746621d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308847548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3308847548
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1378192803
Short name T674
Test name
Test status
Simulation time 19945704 ps
CPU time 0.72 seconds
Started Apr 30 12:35:41 PM PDT 24
Finished Apr 30 12:35:42 PM PDT 24
Peak memory 197316 kb
Host smart-e44c765e-7972-4ff5-bf66-548295f7d52f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378192803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1378192803
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1364909774
Short name T644
Test name
Test status
Simulation time 315140291 ps
CPU time 1.85 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 199220 kb
Host smart-f8371642-b443-4a5c-b1f3-f616f2433a05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364909774 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1364909774
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3414048298
Short name T60
Test name
Test status
Simulation time 29398726 ps
CPU time 0.94 seconds
Started Apr 30 12:35:44 PM PDT 24
Finished Apr 30 12:35:46 PM PDT 24
Peak memory 198452 kb
Host smart-cd9e877e-9185-47c3-b1f4-a16052f276b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414048298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3414048298
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2496548864
Short name T651
Test name
Test status
Simulation time 53049477 ps
CPU time 0.6 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:44 PM PDT 24
Peak memory 194088 kb
Host smart-a5326eef-d158-4b13-9df0-0ca0f23fa5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496548864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2496548864
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3149707934
Short name T715
Test name
Test status
Simulation time 137821197 ps
CPU time 2.43 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:46 PM PDT 24
Peak memory 198552 kb
Host smart-cf091832-d3e4-427a-ba09-6326df1669ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149707934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3149707934
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3937747972
Short name T647
Test name
Test status
Simulation time 76821891 ps
CPU time 1.52 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 199260 kb
Host smart-5ac3c59f-97f4-4595-a0dd-6209dc696714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937747972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3937747972
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.456825743
Short name T726
Test name
Test status
Simulation time 1101453992 ps
CPU time 4.67 seconds
Started Apr 30 12:35:42 PM PDT 24
Finished Apr 30 12:35:47 PM PDT 24
Peak memory 199096 kb
Host smart-9dd085ef-dbf0-453b-8a52-b39f6b370cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456825743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.456825743
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.736877390
Short name T652
Test name
Test status
Simulation time 12541207 ps
CPU time 0.56 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 194056 kb
Host smart-cf12c110-8803-4f4c-bb25-a831198b0ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736877390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.736877390
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1544936006
Short name T631
Test name
Test status
Simulation time 46340542 ps
CPU time 0.6 seconds
Started Apr 30 12:36:14 PM PDT 24
Finished Apr 30 12:36:16 PM PDT 24
Peak memory 194052 kb
Host smart-32dbddfc-e7bf-4943-aa6b-ae6af2bf65f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544936006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1544936006
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3025263317
Short name T692
Test name
Test status
Simulation time 21231263 ps
CPU time 0.59 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 193940 kb
Host smart-ed03167c-2c8a-4ae7-b688-9920962e2d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025263317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3025263317
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3794001628
Short name T71
Test name
Test status
Simulation time 20953256 ps
CPU time 0.6 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 194076 kb
Host smart-91e6d900-3d32-404c-a116-ce58286d7f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794001628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3794001628
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.519193597
Short name T650
Test name
Test status
Simulation time 35265464 ps
CPU time 0.57 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 194148 kb
Host smart-7330a3bd-bce1-4360-bae6-b0a7fca482a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519193597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.519193597
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2280657817
Short name T737
Test name
Test status
Simulation time 30632500 ps
CPU time 0.56 seconds
Started Apr 30 12:36:10 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 193912 kb
Host smart-47191868-35ed-4580-919f-5f0090b19276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280657817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2280657817
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.276841912
Short name T719
Test name
Test status
Simulation time 83492233 ps
CPU time 0.56 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 194000 kb
Host smart-f8fbad42-aa58-4376-9d8a-db9a7d996409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276841912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.276841912
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.217608822
Short name T686
Test name
Test status
Simulation time 53658198 ps
CPU time 0.58 seconds
Started Apr 30 12:36:09 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 193968 kb
Host smart-38d3e015-aed4-42f1-b997-311e18e12d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217608822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.217608822
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3798883025
Short name T738
Test name
Test status
Simulation time 141533410 ps
CPU time 0.63 seconds
Started Apr 30 12:36:10 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 193920 kb
Host smart-0d2c4946-d59e-45d1-9f53-c484b17799b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798883025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3798883025
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2642344845
Short name T610
Test name
Test status
Simulation time 182238690 ps
CPU time 0.61 seconds
Started Apr 30 12:36:13 PM PDT 24
Finished Apr 30 12:36:14 PM PDT 24
Peak memory 193956 kb
Host smart-732556ff-8a97-4b24-b0fb-0bb06abe6e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642344845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2642344845
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.218451796
Short name T635
Test name
Test status
Simulation time 46094215 ps
CPU time 1.43 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:45 PM PDT 24
Peak memory 199184 kb
Host smart-5091f71f-f561-4969-80f4-76fc63499c82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218451796 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.218451796
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1686242087
Short name T90
Test name
Test status
Simulation time 102442928 ps
CPU time 0.7 seconds
Started Apr 30 12:35:47 PM PDT 24
Finished Apr 30 12:35:48 PM PDT 24
Peak memory 196756 kb
Host smart-7eda0e12-50f1-4eab-8b3e-584760fe7180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686242087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1686242087
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.501671894
Short name T608
Test name
Test status
Simulation time 15159332 ps
CPU time 0.55 seconds
Started Apr 30 12:35:48 PM PDT 24
Finished Apr 30 12:35:49 PM PDT 24
Peak memory 193984 kb
Host smart-d1422c6e-de7f-4dc2-bd27-60672c1bb070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501671894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.501671894
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1837175046
Short name T732
Test name
Test status
Simulation time 45094211 ps
CPU time 2.11 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:54 PM PDT 24
Peak memory 198192 kb
Host smart-8cb23baf-4e91-4970-80cb-4807d2340cce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837175046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1837175046
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1400567101
Short name T691
Test name
Test status
Simulation time 98418281 ps
CPU time 2.35 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 199276 kb
Host smart-2a2e0d78-9cb1-4cb6-8396-3e7f1526ba73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400567101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1400567101
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3673856211
Short name T108
Test name
Test status
Simulation time 906394585 ps
CPU time 3.06 seconds
Started Apr 30 12:35:41 PM PDT 24
Finished Apr 30 12:35:44 PM PDT 24
Peak memory 199316 kb
Host smart-2868413e-11c8-4568-936c-039700f3f5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673856211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3673856211
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.716182809
Short name T681
Test name
Test status
Simulation time 27090315 ps
CPU time 1.57 seconds
Started Apr 30 12:35:53 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 199292 kb
Host smart-a17466e8-107c-473f-bc67-1c78f49297d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716182809 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.716182809
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3230466452
Short name T708
Test name
Test status
Simulation time 18013900 ps
CPU time 0.83 seconds
Started Apr 30 12:35:55 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 198512 kb
Host smart-5a8a6478-05fb-46ac-a94a-eca1d912d25a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230466452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3230466452
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1120665200
Short name T637
Test name
Test status
Simulation time 22356587 ps
CPU time 0.59 seconds
Started Apr 30 12:35:43 PM PDT 24
Finished Apr 30 12:35:44 PM PDT 24
Peak memory 193928 kb
Host smart-ed5647b3-2e3a-4668-8aa1-7a0cc73ca82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120665200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1120665200
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2741481716
Short name T670
Test name
Test status
Simulation time 65899388 ps
CPU time 1.76 seconds
Started Apr 30 12:35:54 PM PDT 24
Finished Apr 30 12:35:57 PM PDT 24
Peak memory 199108 kb
Host smart-b17beed8-8d37-4f88-aacd-c8c6feae2f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741481716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2741481716
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2394980309
Short name T696
Test name
Test status
Simulation time 191279614 ps
CPU time 3.92 seconds
Started Apr 30 12:35:41 PM PDT 24
Finished Apr 30 12:35:46 PM PDT 24
Peak memory 199292 kb
Host smart-f0797aa7-8f0f-4507-95ff-8f640d5f31e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394980309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2394980309
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1887459571
Short name T105
Test name
Test status
Simulation time 238350128 ps
CPU time 4.01 seconds
Started Apr 30 12:35:42 PM PDT 24
Finished Apr 30 12:35:47 PM PDT 24
Peak memory 199208 kb
Host smart-2c028ed4-3df8-4cb8-8c76-266eee1fbe3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887459571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1887459571
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1830235174
Short name T703
Test name
Test status
Simulation time 164601394 ps
CPU time 1.36 seconds
Started Apr 30 12:35:49 PM PDT 24
Finished Apr 30 12:35:51 PM PDT 24
Peak memory 199228 kb
Host smart-6ff58b89-e506-4c26-9ec4-2085650693b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830235174 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1830235174
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3715533209
Short name T664
Test name
Test status
Simulation time 30013916 ps
CPU time 0.93 seconds
Started Apr 30 12:35:53 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 199068 kb
Host smart-f2de3a58-085f-48c1-ad08-3e5270331d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715533209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3715533209
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3120752419
Short name T609
Test name
Test status
Simulation time 91880900 ps
CPU time 0.61 seconds
Started Apr 30 12:35:55 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 194072 kb
Host smart-38435340-87a6-44d1-b2e2-badbc8e9120a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120752419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3120752419
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1461503569
Short name T625
Test name
Test status
Simulation time 182566602 ps
CPU time 2.29 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 198956 kb
Host smart-c4812bf1-3b63-4f1a-9935-a44b414af7e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461503569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1461503569
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4094651892
Short name T667
Test name
Test status
Simulation time 41129754 ps
CPU time 1.86 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 199260 kb
Host smart-6abb1d65-7df1-4447-a9ac-d90732120d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094651892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4094651892
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3920033373
Short name T103
Test name
Test status
Simulation time 610200636 ps
CPU time 3.11 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:54 PM PDT 24
Peak memory 199264 kb
Host smart-f67b2722-e542-4fe1-b39a-6736bac5ee8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920033373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3920033373
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2383003519
Short name T638
Test name
Test status
Simulation time 72686862521 ps
CPU time 537.85 seconds
Started Apr 30 12:35:49 PM PDT 24
Finished Apr 30 12:44:47 PM PDT 24
Peak memory 215324 kb
Host smart-afd23484-ba95-403c-be2c-7bc871961fab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383003519 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2383003519
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3393298999
Short name T714
Test name
Test status
Simulation time 25782691 ps
CPU time 0.89 seconds
Started Apr 30 12:35:49 PM PDT 24
Finished Apr 30 12:35:50 PM PDT 24
Peak memory 198112 kb
Host smart-526127e2-6901-4a52-a55e-c36c2966c13d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393298999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3393298999
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3669103595
Short name T702
Test name
Test status
Simulation time 54309238 ps
CPU time 0.63 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:51 PM PDT 24
Peak memory 193960 kb
Host smart-0e09b677-fe74-4c2c-b36c-3d773a328661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669103595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3669103595
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.628160183
Short name T673
Test name
Test status
Simulation time 93925136 ps
CPU time 1.11 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 198796 kb
Host smart-e5922d54-6aa9-445a-b884-4abf271f3acc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628160183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.628160183
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2220380224
Short name T717
Test name
Test status
Simulation time 3687827737 ps
CPU time 3.45 seconds
Started Apr 30 12:35:56 PM PDT 24
Finished Apr 30 12:36:00 PM PDT 24
Peak memory 199332 kb
Host smart-3e1ffe40-ba47-4e78-926d-1ff1ddf62cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220380224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2220380224
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1746635941
Short name T704
Test name
Test status
Simulation time 398894055 ps
CPU time 2.71 seconds
Started Apr 30 12:35:56 PM PDT 24
Finished Apr 30 12:35:59 PM PDT 24
Peak memory 199216 kb
Host smart-a2f7e5e8-d54e-4906-9aec-f8af59546264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746635941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1746635941
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.123154716
Short name T659
Test name
Test status
Simulation time 138662100 ps
CPU time 1.81 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 199220 kb
Host smart-c0110e02-10d7-42fb-8a25-8ab1d1d8ebbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123154716 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.123154716
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1226685937
Short name T98
Test name
Test status
Simulation time 103021316 ps
CPU time 0.85 seconds
Started Apr 30 12:35:55 PM PDT 24
Finished Apr 30 12:35:56 PM PDT 24
Peak memory 198268 kb
Host smart-64081361-2710-4248-b487-d4ca94838cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226685937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1226685937
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1076660268
Short name T716
Test name
Test status
Simulation time 52771522 ps
CPU time 0.57 seconds
Started Apr 30 12:35:51 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 193912 kb
Host smart-91c6c0a9-cce2-4fec-bd1f-818482d56bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076660268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1076660268
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2336773581
Short name T630
Test name
Test status
Simulation time 99426920 ps
CPU time 1.79 seconds
Started Apr 30 12:35:52 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 198940 kb
Host smart-20bd4a8a-9eba-4ac3-ba86-51811fd9d0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336773581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2336773581
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.442723207
Short name T689
Test name
Test status
Simulation time 27344773 ps
CPU time 1.45 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 199284 kb
Host smart-be679055-674e-495c-9013-94f12e44a26a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442723207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.442723207
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.829763385
Short name T104
Test name
Test status
Simulation time 397710351 ps
CPU time 3.11 seconds
Started Apr 30 12:35:50 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 199136 kb
Host smart-e0ba7772-cd10-44cb-a808-fb5f97a9b5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829763385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.829763385
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4236725264
Short name T166
Test name
Test status
Simulation time 36698587 ps
CPU time 0.6 seconds
Started Apr 30 12:19:46 PM PDT 24
Finished Apr 30 12:19:48 PM PDT 24
Peak memory 195560 kb
Host smart-6bf693ed-baad-499f-b699-f4c7846af57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236725264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4236725264
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2382855102
Short name T362
Test name
Test status
Simulation time 999378273 ps
CPU time 33.23 seconds
Started Apr 30 12:22:47 PM PDT 24
Finished Apr 30 12:23:22 PM PDT 24
Peak memory 220616 kb
Host smart-d50ca939-cab0-48fa-91d0-584e24c3d649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382855102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2382855102
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.411331406
Short name T136
Test name
Test status
Simulation time 413086855 ps
CPU time 5.91 seconds
Started Apr 30 12:22:04 PM PDT 24
Finished Apr 30 12:22:11 PM PDT 24
Peak memory 199092 kb
Host smart-8f2906cf-4533-4058-b62c-94c131117128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411331406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.411331406
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1842980532
Short name T443
Test name
Test status
Simulation time 1712768968 ps
CPU time 23.24 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:22:30 PM PDT 24
Peak memory 198732 kb
Host smart-8173ede4-ad40-468b-bb70-2fd1ea4bed9d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842980532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1842980532
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.863226345
Short name T421
Test name
Test status
Simulation time 11396093368 ps
CPU time 45.95 seconds
Started Apr 30 12:22:03 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 199088 kb
Host smart-61ca7f1d-a01b-450f-9af0-ff42107afc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863226345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.863226345
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3378782974
Short name T34
Test name
Test status
Simulation time 100090513 ps
CPU time 0.91 seconds
Started Apr 30 12:22:45 PM PDT 24
Finished Apr 30 12:22:47 PM PDT 24
Peak memory 216844 kb
Host smart-c12ec070-038e-46dd-b506-81f178b604f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378782974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3378782974
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.77979180
Short name T300
Test name
Test status
Simulation time 515331343 ps
CPU time 5.73 seconds
Started Apr 30 12:22:03 PM PDT 24
Finished Apr 30 12:22:10 PM PDT 24
Peak memory 199180 kb
Host smart-5937f63b-d07d-460e-b2f6-a12a34192ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77979180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.77979180
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3193733567
Short name T283
Test name
Test status
Simulation time 43746065606 ps
CPU time 734.23 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:34:22 PM PDT 24
Peak memory 199292 kb
Host smart-31a90590-6f48-4f09-aca8-d744ac57974d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193733567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3193733567
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3383787619
Short name T263
Test name
Test status
Simulation time 69047953 ps
CPU time 1.32 seconds
Started Apr 30 12:22:48 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 199236 kb
Host smart-96359fa1-7cc6-40a8-9454-072da5ac86c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383787619 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3383787619
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2983260144
Short name T175
Test name
Test status
Simulation time 78313017543 ps
CPU time 437.63 seconds
Started Apr 30 12:22:48 PM PDT 24
Finished Apr 30 12:30:07 PM PDT 24
Peak memory 199236 kb
Host smart-16962448-495f-47cd-b944-b96240bf6697
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983260144 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2983260144
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4175458693
Short name T419
Test name
Test status
Simulation time 6803616354 ps
CPU time 91.59 seconds
Started Apr 30 12:22:05 PM PDT 24
Finished Apr 30 12:23:38 PM PDT 24
Peak memory 198744 kb
Host smart-6a1c02bc-c72f-4f0f-ae65-0e3bf1086ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175458693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4175458693
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2829844700
Short name T334
Test name
Test status
Simulation time 37406229 ps
CPU time 0.61 seconds
Started Apr 30 12:21:21 PM PDT 24
Finished Apr 30 12:21:22 PM PDT 24
Peak memory 195296 kb
Host smart-d912f382-2021-4969-989d-d1a7c61ffa78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829844700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2829844700
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.602881246
Short name T195
Test name
Test status
Simulation time 3872913607 ps
CPU time 31.58 seconds
Started Apr 30 12:18:22 PM PDT 24
Finished Apr 30 12:18:53 PM PDT 24
Peak memory 215984 kb
Host smart-5805129e-c6f6-4b49-a74c-3d05dc846e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602881246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.602881246
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.320818171
Short name T453
Test name
Test status
Simulation time 1264808398 ps
CPU time 58.19 seconds
Started Apr 30 12:18:17 PM PDT 24
Finished Apr 30 12:19:16 PM PDT 24
Peak memory 198608 kb
Host smart-c267fc8b-0d7b-4298-be66-7b6b88ee6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320818171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.320818171
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2375502311
Short name T558
Test name
Test status
Simulation time 3065244813 ps
CPU time 86.16 seconds
Started Apr 30 12:18:19 PM PDT 24
Finished Apr 30 12:19:46 PM PDT 24
Peak memory 199188 kb
Host smart-93bd1d34-8c75-4e9b-8393-9efda7458bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375502311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2375502311
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.321308387
Short name T26
Test name
Test status
Simulation time 11927666827 ps
CPU time 77.18 seconds
Started Apr 30 12:18:27 PM PDT 24
Finished Apr 30 12:19:44 PM PDT 24
Peak memory 199560 kb
Host smart-33d12d80-d820-4fa2-ab2a-6b043d9d3e1d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321308387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.321308387
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2071532557
Short name T321
Test name
Test status
Simulation time 4519472484 ps
CPU time 53.68 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:23:07 PM PDT 24
Peak memory 199068 kb
Host smart-27251d25-99c3-4220-a93a-b76d22930d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071532557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2071532557
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.4235862426
Short name T346
Test name
Test status
Simulation time 22163356 ps
CPU time 0.88 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:14 PM PDT 24
Peak memory 197860 kb
Host smart-306816f1-4c3e-4521-9e7f-495c2a51c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235862426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4235862426
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2232549997
Short name T512
Test name
Test status
Simulation time 13111556168 ps
CPU time 184.81 seconds
Started Apr 30 12:21:20 PM PDT 24
Finished Apr 30 12:24:26 PM PDT 24
Peak memory 199716 kb
Host smart-22ac1763-4189-4619-8669-881f8fbd66ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232549997 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2232549997
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2054464088
Short name T81
Test name
Test status
Simulation time 32478070 ps
CPU time 1.18 seconds
Started Apr 30 12:17:32 PM PDT 24
Finished Apr 30 12:17:34 PM PDT 24
Peak memory 199408 kb
Host smart-90136eb7-85e7-4af5-a661-3cab211f46f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054464088 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2054464088
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2076867778
Short name T199
Test name
Test status
Simulation time 35142038825 ps
CPU time 435.57 seconds
Started Apr 30 12:18:18 PM PDT 24
Finished Apr 30 12:25:34 PM PDT 24
Peak memory 199052 kb
Host smart-481dad27-9200-498a-8f83-d99df441a5a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076867778 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2076867778
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2520091405
Short name T469
Test name
Test status
Simulation time 2464577748 ps
CPU time 43.09 seconds
Started Apr 30 12:18:43 PM PDT 24
Finished Apr 30 12:19:27 PM PDT 24
Peak memory 199712 kb
Host smart-4b51598a-f903-4ebe-8575-cfe86b983392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520091405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2520091405
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1986963900
Short name T216
Test name
Test status
Simulation time 14614015 ps
CPU time 0.65 seconds
Started Apr 30 12:26:01 PM PDT 24
Finished Apr 30 12:26:03 PM PDT 24
Peak memory 193124 kb
Host smart-eed0195f-bdfc-4d8b-80eb-e68d726741c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986963900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1986963900
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.305464112
Short name T368
Test name
Test status
Simulation time 134529324 ps
CPU time 5.21 seconds
Started Apr 30 12:24:37 PM PDT 24
Finished Apr 30 12:24:43 PM PDT 24
Peak memory 207696 kb
Host smart-7882f6f0-f633-461a-aa3c-b6c78e66fa1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305464112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.305464112
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1287467395
Short name T269
Test name
Test status
Simulation time 12377685688 ps
CPU time 48.28 seconds
Started Apr 30 12:26:04 PM PDT 24
Finished Apr 30 12:26:53 PM PDT 24
Peak memory 199488 kb
Host smart-bd979937-2e6e-4550-ae0e-f72aeaa07b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287467395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1287467395
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.93898002
Short name T594
Test name
Test status
Simulation time 943352113 ps
CPU time 54.01 seconds
Started Apr 30 12:24:49 PM PDT 24
Finished Apr 30 12:25:44 PM PDT 24
Peak memory 199384 kb
Host smart-d3444d2d-c80a-48ba-b4b5-f04ee19d389a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93898002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.93898002
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2835218994
Short name T190
Test name
Test status
Simulation time 1272787274 ps
CPU time 49.84 seconds
Started Apr 30 12:24:58 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199500 kb
Host smart-f7ade344-f5e4-4edf-aa44-07b8e9e7ea5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835218994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2835218994
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1987161527
Short name T378
Test name
Test status
Simulation time 6209277095 ps
CPU time 117.72 seconds
Started Apr 30 12:26:02 PM PDT 24
Finished Apr 30 12:28:01 PM PDT 24
Peak memory 199228 kb
Host smart-4b8da9af-1394-484a-b648-cb9c808419b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987161527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1987161527
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.865365382
Short name T486
Test name
Test status
Simulation time 239074776 ps
CPU time 1.33 seconds
Started Apr 30 12:24:33 PM PDT 24
Finished Apr 30 12:24:35 PM PDT 24
Peak memory 199512 kb
Host smart-888c1ecc-6492-40e1-85e8-2ec1b0cf428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865365382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.865365382
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2780629608
Short name T234
Test name
Test status
Simulation time 23677713844 ps
CPU time 1149.03 seconds
Started Apr 30 12:24:40 PM PDT 24
Finished Apr 30 12:43:49 PM PDT 24
Peak memory 199384 kb
Host smart-bcaa158e-c79a-473c-b480-b727ec83ddbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780629608 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2780629608
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1135996076
Short name T308
Test name
Test status
Simulation time 124896402 ps
CPU time 1.15 seconds
Started Apr 30 12:24:43 PM PDT 24
Finished Apr 30 12:24:45 PM PDT 24
Peak memory 199432 kb
Host smart-593a4ee0-5ff0-4125-96e5-f9de9f14e730
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135996076 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1135996076
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2631000273
Short name T521
Test name
Test status
Simulation time 96824221632 ps
CPU time 447.98 seconds
Started Apr 30 12:24:58 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 199440 kb
Host smart-9f041a18-e52e-4069-82e4-53d557591ec9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631000273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.2631000273
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3789489851
Short name T554
Test name
Test status
Simulation time 1449661376 ps
CPU time 73.55 seconds
Started Apr 30 12:26:01 PM PDT 24
Finished Apr 30 12:27:16 PM PDT 24
Peak memory 197224 kb
Host smart-8a7e853d-a790-4767-8519-c94627834f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789489851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3789489851
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.3265692140
Short name T12
Test name
Test status
Simulation time 29581046219 ps
CPU time 415.78 seconds
Started Apr 30 12:26:03 PM PDT 24
Finished Apr 30 12:33:00 PM PDT 24
Peak memory 238460 kb
Host smart-454518a5-5abf-4386-a1e2-3f05d7f358e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265692140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.3265692140
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3543767236
Short name T304
Test name
Test status
Simulation time 23893377 ps
CPU time 0.56 seconds
Started Apr 30 12:24:41 PM PDT 24
Finished Apr 30 12:24:42 PM PDT 24
Peak memory 194000 kb
Host smart-5dd2e786-1c65-45af-b6d9-1db99b7c4b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543767236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3543767236
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1471715924
Short name T369
Test name
Test status
Simulation time 1223132430 ps
CPU time 20.55 seconds
Started Apr 30 12:24:41 PM PDT 24
Finished Apr 30 12:25:03 PM PDT 24
Peak memory 207768 kb
Host smart-1b4589ff-5aa2-4916-9478-1a7ca6a558fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471715924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1471715924
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2409787360
Short name T513
Test name
Test status
Simulation time 879547989 ps
CPU time 10.71 seconds
Started Apr 30 12:24:58 PM PDT 24
Finished Apr 30 12:25:10 PM PDT 24
Peak memory 199428 kb
Host smart-9fb27986-1bd9-444d-8682-d3def9e5a522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409787360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2409787360
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.246768775
Short name T460
Test name
Test status
Simulation time 4482280449 ps
CPU time 65.97 seconds
Started Apr 30 12:24:40 PM PDT 24
Finished Apr 30 12:25:46 PM PDT 24
Peak memory 199528 kb
Host smart-b360647d-e022-45df-8cc1-5e633546badd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246768775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.246768775
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1941691578
Short name T16
Test name
Test status
Simulation time 13115637202 ps
CPU time 115.4 seconds
Started Apr 30 12:24:41 PM PDT 24
Finished Apr 30 12:26:37 PM PDT 24
Peak memory 199456 kb
Host smart-4186884b-d01f-4050-b87b-05f43298994f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941691578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1941691578
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3526673893
Short name T288
Test name
Test status
Simulation time 29752238577 ps
CPU time 102.93 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:26:32 PM PDT 24
Peak memory 199484 kb
Host smart-5c68603d-6ae0-45c2-8adf-3496cac52aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526673893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3526673893
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1462623843
Short name T140
Test name
Test status
Simulation time 96386727 ps
CPU time 3.18 seconds
Started Apr 30 12:24:39 PM PDT 24
Finished Apr 30 12:24:43 PM PDT 24
Peak memory 199432 kb
Host smart-9fe904bd-d255-42ab-bf66-c32a368f9f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462623843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1462623843
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3569955369
Short name T541
Test name
Test status
Simulation time 334378794 ps
CPU time 1.44 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:25:02 PM PDT 24
Peak memory 199492 kb
Host smart-43e0ba6a-5d49-40c0-8d15-ca927197c6bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569955369 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3569955369
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.2330137029
Short name T10
Test name
Test status
Simulation time 13413124154 ps
CPU time 390.03 seconds
Started Apr 30 12:24:53 PM PDT 24
Finished Apr 30 12:31:24 PM PDT 24
Peak memory 215928 kb
Host smart-db8ca1a3-1820-4ab7-9440-bb6e0c69d824
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330137029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.2330137029
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.890675952
Short name T316
Test name
Test status
Simulation time 103673559 ps
CPU time 1.02 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:25:02 PM PDT 24
Peak memory 198820 kb
Host smart-de956e16-0727-4a7a-a693-e80516de56d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890675952 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.890675952
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3495603543
Short name T475
Test name
Test status
Simulation time 36886643578 ps
CPU time 493.38 seconds
Started Apr 30 12:24:39 PM PDT 24
Finished Apr 30 12:32:53 PM PDT 24
Peak memory 199480 kb
Host smart-b6230294-ed03-4daf-8207-064dd277db1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495603543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3495603543
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2802660809
Short name T540
Test name
Test status
Simulation time 3818806791 ps
CPU time 64.83 seconds
Started Apr 30 12:24:40 PM PDT 24
Finished Apr 30 12:25:46 PM PDT 24
Peak memory 199524 kb
Host smart-650534f3-11f3-4849-93d0-ce6bef44e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802660809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2802660809
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.3356044989
Short name T9
Test name
Test status
Simulation time 23848071930 ps
CPU time 1200.12 seconds
Started Apr 30 12:26:12 PM PDT 24
Finished Apr 30 12:46:13 PM PDT 24
Peak memory 225476 kb
Host smart-a7751a8d-ac87-48f3-b684-c90d9b6a2d59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356044989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.3356044989
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.3253651727
Short name T426
Test name
Test status
Simulation time 243411847790 ps
CPU time 980.18 seconds
Started Apr 30 12:26:13 PM PDT 24
Finished Apr 30 12:42:34 PM PDT 24
Peak memory 247724 kb
Host smart-7ca26c6b-65a2-4266-93b2-90bc252bea96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253651727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.3253651727
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3670723242
Short name T328
Test name
Test status
Simulation time 42196340 ps
CPU time 0.58 seconds
Started Apr 30 12:24:53 PM PDT 24
Finished Apr 30 12:24:55 PM PDT 24
Peak memory 195280 kb
Host smart-d16abc1f-9b80-4347-8327-019d87cb009c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670723242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3670723242
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1843536862
Short name T606
Test name
Test status
Simulation time 1042338552 ps
CPU time 49.39 seconds
Started Apr 30 12:24:41 PM PDT 24
Finished Apr 30 12:25:31 PM PDT 24
Peak memory 232400 kb
Host smart-6c3ed7e9-1bb6-4d3d-ae61-be8ce41fcd9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843536862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1843536862
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1008651153
Short name T414
Test name
Test status
Simulation time 4661448044 ps
CPU time 14.83 seconds
Started Apr 30 12:24:40 PM PDT 24
Finished Apr 30 12:24:55 PM PDT 24
Peak memory 199524 kb
Host smart-ff724a1c-2b1f-478c-b90f-ce0927996129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008651153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1008651153
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1938587484
Short name T358
Test name
Test status
Simulation time 4306894230 ps
CPU time 128.3 seconds
Started Apr 30 12:24:43 PM PDT 24
Finished Apr 30 12:26:52 PM PDT 24
Peak memory 199536 kb
Host smart-01f42196-32e6-48c4-aa16-e49ea7eb6f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938587484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1938587484
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.100838454
Short name T550
Test name
Test status
Simulation time 10193888450 ps
CPU time 102.34 seconds
Started Apr 30 12:24:44 PM PDT 24
Finished Apr 30 12:26:27 PM PDT 24
Peak memory 199580 kb
Host smart-389cbc24-f51c-407a-b167-0b1f9501292f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100838454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.100838454
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3589924913
Short name T3
Test name
Test status
Simulation time 17082148522 ps
CPU time 115 seconds
Started Apr 30 12:24:45 PM PDT 24
Finished Apr 30 12:26:40 PM PDT 24
Peak memory 199456 kb
Host smart-e0f89874-9bbe-474b-8281-40437e5df5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589924913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3589924913
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3469063563
Short name T392
Test name
Test status
Simulation time 395968626 ps
CPU time 5.76 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:25:06 PM PDT 24
Peak memory 199416 kb
Host smart-443c0f34-2cc8-469a-b5df-d346f893f605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469063563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3469063563
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3101491002
Short name T529
Test name
Test status
Simulation time 123464323602 ps
CPU time 1550.81 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:50:40 PM PDT 24
Peak memory 236480 kb
Host smart-6afd4685-8996-4042-99e7-7bed087f9132
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101491002 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3101491002
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.163875691
Short name T226
Test name
Test status
Simulation time 62083389 ps
CPU time 1.3 seconds
Started Apr 30 12:24:39 PM PDT 24
Finished Apr 30 12:24:41 PM PDT 24
Peak memory 199416 kb
Host smart-95579db5-bef0-45b7-978c-e1555085eddb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163875691 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.163875691
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3874722903
Short name T361
Test name
Test status
Simulation time 140948698016 ps
CPU time 520.81 seconds
Started Apr 30 12:24:40 PM PDT 24
Finished Apr 30 12:33:21 PM PDT 24
Peak memory 199408 kb
Host smart-55b50713-7a97-4f4b-8eff-4b59f147e61f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874722903 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3874722903
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.634494029
Short name T277
Test name
Test status
Simulation time 3383772840 ps
CPU time 30.5 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:25:31 PM PDT 24
Peak memory 199588 kb
Host smart-b9fa9b14-abf6-48d3-86be-542a12a23440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634494029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.634494029
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.1113845955
Short name T13
Test name
Test status
Simulation time 353596778437 ps
CPU time 3602.33 seconds
Started Apr 30 12:26:14 PM PDT 24
Finished Apr 30 01:26:18 PM PDT 24
Peak memory 258984 kb
Host smart-1e09c25c-27ae-40c7-b24f-9849934e42bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113845955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.1113845955
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2712637975
Short name T273
Test name
Test status
Simulation time 59331770 ps
CPU time 0.57 seconds
Started Apr 30 12:24:50 PM PDT 24
Finished Apr 30 12:24:52 PM PDT 24
Peak memory 195244 kb
Host smart-1407fd43-f139-495a-9f6d-560e7df4e15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712637975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2712637975
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3129782673
Short name T518
Test name
Test status
Simulation time 1240191608 ps
CPU time 40.77 seconds
Started Apr 30 12:24:53 PM PDT 24
Finished Apr 30 12:25:35 PM PDT 24
Peak memory 207200 kb
Host smart-8f721d61-190f-41c6-9b6a-841fb7306975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129782673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3129782673
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1067424085
Short name T181
Test name
Test status
Simulation time 1243437375 ps
CPU time 10.1 seconds
Started Apr 30 12:24:49 PM PDT 24
Finished Apr 30 12:25:00 PM PDT 24
Peak memory 199440 kb
Host smart-fa13fa94-2022-42fc-b74c-83e69d6db147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067424085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1067424085
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2381626861
Short name T305
Test name
Test status
Simulation time 9713129047 ps
CPU time 138.9 seconds
Started Apr 30 12:24:50 PM PDT 24
Finished Apr 30 12:27:10 PM PDT 24
Peak memory 199556 kb
Host smart-3254e0dd-5727-45aa-ad6f-c34dae57cce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381626861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2381626861
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.4150605666
Short name T50
Test name
Test status
Simulation time 9885775648 ps
CPU time 43.18 seconds
Started Apr 30 12:25:05 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 199484 kb
Host smart-8b119325-c370-4736-9117-6e3ec955aa78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150605666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.4150605666
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.523186450
Short name T350
Test name
Test status
Simulation time 3147640447 ps
CPU time 41.77 seconds
Started Apr 30 12:25:05 PM PDT 24
Finished Apr 30 12:25:47 PM PDT 24
Peak memory 199528 kb
Host smart-6ff93f8b-95f2-4ed3-af8a-6b8627544f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523186450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.523186450
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2897288056
Short name T236
Test name
Test status
Simulation time 3733673683 ps
CPU time 6.81 seconds
Started Apr 30 12:25:05 PM PDT 24
Finished Apr 30 12:25:12 PM PDT 24
Peak memory 199504 kb
Host smart-2c9921bf-04f1-43c0-86cb-8e8dbc696945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897288056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2897288056
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3840169630
Short name T164
Test name
Test status
Simulation time 47070673814 ps
CPU time 178.81 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:27:48 PM PDT 24
Peak memory 199536 kb
Host smart-af1d8516-6786-433f-b29b-9d69b2755234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840169630 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3840169630
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2766665780
Short name T223
Test name
Test status
Simulation time 96488940 ps
CPU time 0.97 seconds
Started Apr 30 12:24:50 PM PDT 24
Finished Apr 30 12:24:52 PM PDT 24
Peak memory 199044 kb
Host smart-43f85d4a-88ca-431e-9952-9d735a73e6da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766665780 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2766665780
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1850370889
Short name T579
Test name
Test status
Simulation time 35810625270 ps
CPU time 444.79 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:32:14 PM PDT 24
Peak memory 199456 kb
Host smart-7efefe74-76ef-4a25-ad8c-505515ad1a00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850370889 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1850370889
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2566364522
Short name T391
Test name
Test status
Simulation time 16516599774 ps
CPU time 78.04 seconds
Started Apr 30 12:24:53 PM PDT 24
Finished Apr 30 12:26:11 PM PDT 24
Peak memory 199428 kb
Host smart-f944651d-fc5c-41e7-b671-d0e9a0fab492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566364522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2566364522
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.4209509163
Short name T11
Test name
Test status
Simulation time 20103120695 ps
CPU time 532.71 seconds
Started Apr 30 12:26:14 PM PDT 24
Finished Apr 30 12:35:08 PM PDT 24
Peak memory 207832 kb
Host smart-921ef838-3b73-4787-ae3d-01b19788e411
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209509163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.4209509163
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3506562455
Short name T251
Test name
Test status
Simulation time 47906936 ps
CPU time 0.59 seconds
Started Apr 30 12:24:57 PM PDT 24
Finished Apr 30 12:24:58 PM PDT 24
Peak memory 195084 kb
Host smart-8da5a6d1-3c3e-4ef1-bffa-307a2ad2fe6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506562455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3506562455
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3841987781
Short name T571
Test name
Test status
Simulation time 1184145104 ps
CPU time 39.43 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:25:28 PM PDT 24
Peak memory 215956 kb
Host smart-0fd08669-139f-4413-9372-23521718bbb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841987781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3841987781
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1314003229
Short name T298
Test name
Test status
Simulation time 11018990647 ps
CPU time 17.99 seconds
Started Apr 30 12:24:49 PM PDT 24
Finished Apr 30 12:25:08 PM PDT 24
Peak memory 199476 kb
Host smart-de80ca1b-2d38-41cd-931f-98d4bfd12fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314003229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1314003229
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1132300634
Short name T359
Test name
Test status
Simulation time 9172148629 ps
CPU time 130.3 seconds
Started Apr 30 12:24:51 PM PDT 24
Finished Apr 30 12:27:02 PM PDT 24
Peak memory 199524 kb
Host smart-07a8d951-80d3-44c6-bd3b-600a0b83f5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132300634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1132300634
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2317352654
Short name T533
Test name
Test status
Simulation time 3048896265 ps
CPU time 43.12 seconds
Started Apr 30 12:25:04 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199504 kb
Host smart-98ef06c5-e138-4c2d-bec4-109063110d53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317352654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2317352654
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1311894402
Short name T122
Test name
Test status
Simulation time 13068738567 ps
CPU time 85.4 seconds
Started Apr 30 12:24:52 PM PDT 24
Finished Apr 30 12:26:18 PM PDT 24
Peak memory 199524 kb
Host smart-3ff1ee95-f6d8-4e7c-98df-6614909e106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311894402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1311894402
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1435320375
Short name T479
Test name
Test status
Simulation time 2019214918 ps
CPU time 4.9 seconds
Started Apr 30 12:24:52 PM PDT 24
Finished Apr 30 12:24:58 PM PDT 24
Peak memory 199480 kb
Host smart-d2932feb-80e9-4044-9d52-02d5113806c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435320375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1435320375
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1243151701
Short name T68
Test name
Test status
Simulation time 123585324785 ps
CPU time 1624.19 seconds
Started Apr 30 12:24:55 PM PDT 24
Finished Apr 30 12:52:00 PM PDT 24
Peak memory 233532 kb
Host smart-e8292494-8218-4c18-99bc-62290adfefb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243151701 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1243151701
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3901968680
Short name T170
Test name
Test status
Simulation time 378906437 ps
CPU time 1.27 seconds
Started Apr 30 12:24:58 PM PDT 24
Finished Apr 30 12:25:00 PM PDT 24
Peak memory 199344 kb
Host smart-ae4e37c5-3892-41e8-85a6-e7d3b4024fd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901968680 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3901968680
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2362184416
Short name T548
Test name
Test status
Simulation time 35662886145 ps
CPU time 512.59 seconds
Started Apr 30 12:24:50 PM PDT 24
Finished Apr 30 12:33:23 PM PDT 24
Peak memory 199388 kb
Host smart-15d1d840-2e55-4f7f-945d-b3e1238ed81b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362184416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2362184416
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.726913791
Short name T509
Test name
Test status
Simulation time 11542719403 ps
CPU time 54.89 seconds
Started Apr 30 12:24:55 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 199676 kb
Host smart-dd918f62-78c7-4851-816b-4c2723074e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726913791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.726913791
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2981993915
Short name T375
Test name
Test status
Simulation time 45919310 ps
CPU time 0.6 seconds
Started Apr 30 12:24:52 PM PDT 24
Finished Apr 30 12:24:54 PM PDT 24
Peak memory 195260 kb
Host smart-46435f1d-4efe-4a5a-ad27-b9c208faff2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981993915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2981993915
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.246494532
Short name T444
Test name
Test status
Simulation time 2315116730 ps
CPU time 74.5 seconds
Started Apr 30 12:24:55 PM PDT 24
Finished Apr 30 12:26:10 PM PDT 24
Peak memory 234972 kb
Host smart-873ac972-c167-45c9-b431-f9e3d3b46c32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246494532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.246494532
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4231471872
Short name T604
Test name
Test status
Simulation time 1380701034 ps
CPU time 34.47 seconds
Started Apr 30 12:24:49 PM PDT 24
Finished Apr 30 12:25:25 PM PDT 24
Peak memory 199452 kb
Host smart-d9fdcbef-c316-438d-ac46-651006f075b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231471872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4231471872
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2973730346
Short name T535
Test name
Test status
Simulation time 2218085686 ps
CPU time 32.01 seconds
Started Apr 30 12:24:55 PM PDT 24
Finished Apr 30 12:25:28 PM PDT 24
Peak memory 199452 kb
Host smart-b4fd679f-8170-41b0-8434-1843dbc686e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973730346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2973730346
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2019518739
Short name T515
Test name
Test status
Simulation time 11709428342 ps
CPU time 155.75 seconds
Started Apr 30 12:24:55 PM PDT 24
Finished Apr 30 12:27:31 PM PDT 24
Peak memory 199680 kb
Host smart-93bcb883-a4e7-4f14-ab42-20d556491464
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019518739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2019518739
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4036590956
Short name T597
Test name
Test status
Simulation time 2029096573 ps
CPU time 39.77 seconds
Started Apr 30 12:24:53 PM PDT 24
Finished Apr 30 12:25:34 PM PDT 24
Peak memory 199452 kb
Host smart-adfc64cd-ca4f-4884-9d40-b28ecb2848bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036590956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4036590956
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3465259615
Short name T248
Test name
Test status
Simulation time 1841825617 ps
CPU time 2.52 seconds
Started Apr 30 12:24:50 PM PDT 24
Finished Apr 30 12:24:53 PM PDT 24
Peak memory 199468 kb
Host smart-6555d79a-9791-4a19-b3f6-b41f4bd5caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465259615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3465259615
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2376320659
Short name T69
Test name
Test status
Simulation time 86555443995 ps
CPU time 1162.75 seconds
Started Apr 30 12:24:49 PM PDT 24
Finished Apr 30 12:44:12 PM PDT 24
Peak memory 233324 kb
Host smart-a450a468-5936-455c-b87e-cd7870d0484b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376320659 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2376320659
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3771614335
Short name T120
Test name
Test status
Simulation time 134599688 ps
CPU time 1 seconds
Started Apr 30 12:24:53 PM PDT 24
Finished Apr 30 12:24:55 PM PDT 24
Peak memory 199564 kb
Host smart-3a0d2587-feaf-4db7-94c6-a7dc16f9b6e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771614335 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3771614335
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.806969664
Short name T18
Test name
Test status
Simulation time 57815151966 ps
CPU time 485.37 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:32:55 PM PDT 24
Peak memory 199504 kb
Host smart-b43d0f20-ce52-494b-8a51-45f0d8645282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806969664 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.806969664
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.684233461
Short name T481
Test name
Test status
Simulation time 10193236348 ps
CPU time 91.52 seconds
Started Apr 30 12:24:46 PM PDT 24
Finished Apr 30 12:26:18 PM PDT 24
Peak memory 199540 kb
Host smart-d1b472dd-254d-4e46-ae2c-b60f6362b7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684233461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.684233461
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.314788376
Short name T508
Test name
Test status
Simulation time 4385318878 ps
CPU time 37.47 seconds
Started Apr 30 12:24:51 PM PDT 24
Finished Apr 30 12:25:29 PM PDT 24
Peak memory 207752 kb
Host smart-66076e90-1c1d-4a23-b07a-2618e781186d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314788376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.314788376
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3749214923
Short name T235
Test name
Test status
Simulation time 752004028 ps
CPU time 3.83 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:25:04 PM PDT 24
Peak memory 199420 kb
Host smart-ebce22c0-412b-4592-84e1-33e42ec8af62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749214923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3749214923
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1223745024
Short name T411
Test name
Test status
Simulation time 5897125218 ps
CPU time 83.99 seconds
Started Apr 30 12:24:56 PM PDT 24
Finished Apr 30 12:26:21 PM PDT 24
Peak memory 199396 kb
Host smart-e5c10648-68ce-45a8-8694-9ce447c3499d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223745024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1223745024
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.550872310
Short name T472
Test name
Test status
Simulation time 4163977682 ps
CPU time 80.42 seconds
Started Apr 30 12:24:51 PM PDT 24
Finished Apr 30 12:26:12 PM PDT 24
Peak memory 199548 kb
Host smart-ee31bbe5-e545-47bf-b7a2-2068e199ac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550872310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.550872310
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4061069308
Short name T86
Test name
Test status
Simulation time 2592609228 ps
CPU time 7.75 seconds
Started Apr 30 12:25:04 PM PDT 24
Finished Apr 30 12:25:13 PM PDT 24
Peak memory 199456 kb
Host smart-ab967d39-0d57-4ba8-aa94-6477f4c69544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061069308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4061069308
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1830741401
Short name T267
Test name
Test status
Simulation time 43816147271 ps
CPU time 438.91 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:32:20 PM PDT 24
Peak memory 240580 kb
Host smart-170db77b-f9e6-4782-8d72-537ee998fc00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830741401 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1830741401
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1960293870
Short name T363
Test name
Test status
Simulation time 123349461 ps
CPU time 1.22 seconds
Started Apr 30 12:25:09 PM PDT 24
Finished Apr 30 12:25:11 PM PDT 24
Peak memory 199296 kb
Host smart-420f6850-af94-4688-b32c-f830b826ad98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960293870 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1960293870
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.855679128
Short name T589
Test name
Test status
Simulation time 172310226920 ps
CPU time 509.76 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:33:31 PM PDT 24
Peak memory 199476 kb
Host smart-31a7a0f5-2bee-4852-ad67-93637041c886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855679128 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.855679128
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3348368389
Short name T286
Test name
Test status
Simulation time 4571625584 ps
CPU time 89.02 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:26:28 PM PDT 24
Peak memory 199492 kb
Host smart-3b8cdd22-7b4a-4f0c-b68c-fb9b10df5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348368389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3348368389
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.2764426247
Short name T557
Test name
Test status
Simulation time 56324163591 ps
CPU time 182.79 seconds
Started Apr 30 12:26:21 PM PDT 24
Finished Apr 30 12:29:24 PM PDT 24
Peak memory 215932 kb
Host smart-8aac777b-22d7-4d41-abe6-7414da5e4239
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764426247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.2764426247
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2200690469
Short name T134
Test name
Test status
Simulation time 51940835 ps
CPU time 0.58 seconds
Started Apr 30 12:25:08 PM PDT 24
Finished Apr 30 12:25:09 PM PDT 24
Peak memory 195232 kb
Host smart-178dc828-686b-4fc0-974f-9d35ea0ee833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200690469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2200690469
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1611026348
Short name T575
Test name
Test status
Simulation time 9380300835 ps
CPU time 46.14 seconds
Started Apr 30 12:24:57 PM PDT 24
Finished Apr 30 12:25:44 PM PDT 24
Peak memory 217820 kb
Host smart-49242710-7662-4952-a6e9-572cef1d735e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611026348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1611026348
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.442196233
Short name T76
Test name
Test status
Simulation time 311695642 ps
CPU time 6.66 seconds
Started Apr 30 12:25:09 PM PDT 24
Finished Apr 30 12:25:16 PM PDT 24
Peak memory 199304 kb
Host smart-57726910-1792-4ae1-b5f8-4714ef4c079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442196233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.442196233
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2820378462
Short name T287
Test name
Test status
Simulation time 55780131 ps
CPU time 0.67 seconds
Started Apr 30 12:25:01 PM PDT 24
Finished Apr 30 12:25:02 PM PDT 24
Peak memory 196404 kb
Host smart-885eb067-40ba-4966-a09f-970ed90d3639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2820378462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2820378462
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.824100329
Short name T596
Test name
Test status
Simulation time 3582752025 ps
CPU time 187.55 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:28:09 PM PDT 24
Peak memory 199456 kb
Host smart-cf733d7c-bb94-4c71-a2d1-3f170877eed1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824100329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.824100329
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2734246522
Short name T429
Test name
Test status
Simulation time 3132253519 ps
CPU time 37.94 seconds
Started Apr 30 12:25:13 PM PDT 24
Finished Apr 30 12:25:52 PM PDT 24
Peak memory 199424 kb
Host smart-6a39ae61-16db-4d00-bccf-750dd751b84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734246522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2734246522
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1305476867
Short name T247
Test name
Test status
Simulation time 74571052 ps
CPU time 1.1 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:25:02 PM PDT 24
Peak memory 199468 kb
Host smart-41ca50cd-0e25-4618-bba5-621515c9f3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305476867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1305476867
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.348831475
Short name T15
Test name
Test status
Simulation time 130310251248 ps
CPU time 1562.81 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:51:20 PM PDT 24
Peak memory 240504 kb
Host smart-2f4fa637-4fa9-4c15-89b3-313c7dc241e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348831475 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.348831475
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1118134599
Short name T352
Test name
Test status
Simulation time 112110066 ps
CPU time 1.3 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:25:01 PM PDT 24
Peak memory 199348 kb
Host smart-e2244a09-1353-444c-9944-df66ebdcde8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118134599 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1118134599
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1284071463
Short name T410
Test name
Test status
Simulation time 8581038584 ps
CPU time 456.34 seconds
Started Apr 30 12:24:57 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 199436 kb
Host smart-d992d2d2-81eb-4f74-8597-6e7198633ab5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284071463 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1284071463
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1785488381
Short name T562
Test name
Test status
Simulation time 197823527 ps
CPU time 3.64 seconds
Started Apr 30 12:24:58 PM PDT 24
Finished Apr 30 12:25:02 PM PDT 24
Peak memory 199316 kb
Host smart-9916e5a6-36a3-46e6-b553-d7835119f60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785488381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1785488381
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.241241961
Short name T494
Test name
Test status
Simulation time 31107228896 ps
CPU time 795.67 seconds
Started Apr 30 12:26:19 PM PDT 24
Finished Apr 30 12:39:35 PM PDT 24
Peak memory 231184 kb
Host smart-c3f4f217-e90e-4ea7-bfad-5973bdb6452c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241241961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.241241961
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1328107142
Short name T351
Test name
Test status
Simulation time 18656627 ps
CPU time 0.59 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:25:00 PM PDT 24
Peak memory 195188 kb
Host smart-da50a1f4-36bd-4154-8bf9-c5a3228b1a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328107142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1328107142
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2157568391
Short name T292
Test name
Test status
Simulation time 6505510322 ps
CPU time 53.28 seconds
Started Apr 30 12:25:09 PM PDT 24
Finished Apr 30 12:26:03 PM PDT 24
Peak memory 232616 kb
Host smart-1c699f79-6142-40a6-909a-e85a32cdaa91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157568391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2157568391
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1839372308
Short name T510
Test name
Test status
Simulation time 482194605 ps
CPU time 24.72 seconds
Started Apr 30 12:24:57 PM PDT 24
Finished Apr 30 12:25:23 PM PDT 24
Peak memory 199328 kb
Host smart-748608f2-ce44-443b-a0c4-0d79d21537f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839372308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1839372308
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2484194007
Short name T488
Test name
Test status
Simulation time 3261749363 ps
CPU time 44.36 seconds
Started Apr 30 12:25:09 PM PDT 24
Finished Apr 30 12:25:54 PM PDT 24
Peak memory 199392 kb
Host smart-7f9634eb-1d5a-4cc6-aabb-1f4a77d52be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484194007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2484194007
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4010194732
Short name T189
Test name
Test status
Simulation time 9020536774 ps
CPU time 108.76 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:26:49 PM PDT 24
Peak memory 199484 kb
Host smart-b34de121-53e4-4098-ade1-60ba912202c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010194732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4010194732
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2735038683
Short name T75
Test name
Test status
Simulation time 4696621264 ps
CPU time 62.41 seconds
Started Apr 30 12:25:01 PM PDT 24
Finished Apr 30 12:26:04 PM PDT 24
Peak memory 199468 kb
Host smart-18c71374-d2d5-4111-a2cc-28bf5439aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735038683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2735038683
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1411934585
Short name T454
Test name
Test status
Simulation time 139741243 ps
CPU time 4.3 seconds
Started Apr 30 12:25:15 PM PDT 24
Finished Apr 30 12:25:20 PM PDT 24
Peak memory 199480 kb
Host smart-96748ed4-4fa1-4f02-88ab-2583bc861428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411934585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1411934585
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2725551686
Short name T365
Test name
Test status
Simulation time 3096270997 ps
CPU time 153.98 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:27:34 PM PDT 24
Peak memory 199644 kb
Host smart-d80a5dd5-1613-45f2-9141-fea8e8b51f4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725551686 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2725551686
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2464961642
Short name T428
Test name
Test status
Simulation time 48430968 ps
CPU time 1.06 seconds
Started Apr 30 12:24:59 PM PDT 24
Finished Apr 30 12:25:00 PM PDT 24
Peak memory 198936 kb
Host smart-5ce209b3-5d79-494a-91ac-49c2cd657cd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464961642 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2464961642
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3156767696
Short name T511
Test name
Test status
Simulation time 76481006541 ps
CPU time 399.53 seconds
Started Apr 30 12:25:01 PM PDT 24
Finished Apr 30 12:31:42 PM PDT 24
Peak memory 199864 kb
Host smart-7bcc70f6-9c1e-4fa1-bd65-c9dfae8e570e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156767696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3156767696
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.538967715
Short name T183
Test name
Test status
Simulation time 1376368035 ps
CPU time 42.16 seconds
Started Apr 30 12:25:05 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199272 kb
Host smart-07628d3e-bac2-4416-b79e-406f5659816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538967715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.538967715
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.2245411209
Short name T582
Test name
Test status
Simulation time 20761258982 ps
CPU time 1126.86 seconds
Started Apr 30 12:26:29 PM PDT 24
Finished Apr 30 12:45:16 PM PDT 24
Peak memory 240708 kb
Host smart-55df7922-2f3d-4388-9ce9-bad2ca4dc94c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245411209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.2245411209
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4233144243
Short name T495
Test name
Test status
Simulation time 13029784 ps
CPU time 0.56 seconds
Started Apr 30 12:24:57 PM PDT 24
Finished Apr 30 12:24:58 PM PDT 24
Peak memory 195068 kb
Host smart-116d2166-a4a9-4b24-a5ec-f22f54be8634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233144243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4233144243
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2881912749
Short name T252
Test name
Test status
Simulation time 2111669676 ps
CPU time 37.62 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 199556 kb
Host smart-e0dd9867-a1d5-4015-8322-fb5d387e42ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881912749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2881912749
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3376207404
Short name T337
Test name
Test status
Simulation time 472770984 ps
CPU time 9.61 seconds
Started Apr 30 12:25:09 PM PDT 24
Finished Apr 30 12:25:19 PM PDT 24
Peak memory 199308 kb
Host smart-1e42f086-20b9-4c4a-aecd-beda57f4f5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376207404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3376207404
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.42029354
Short name T588
Test name
Test status
Simulation time 2220495538 ps
CPU time 14.71 seconds
Started Apr 30 12:25:02 PM PDT 24
Finished Apr 30 12:25:18 PM PDT 24
Peak memory 199508 kb
Host smart-81bd5136-09a1-4626-9249-f471014bd120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42029354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.42029354
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3202768800
Short name T254
Test name
Test status
Simulation time 21534042748 ps
CPU time 202.91 seconds
Started Apr 30 12:25:01 PM PDT 24
Finished Apr 30 12:28:24 PM PDT 24
Peak memory 199936 kb
Host smart-9bc0a499-9b79-4239-aabf-67f05b064cfc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202768800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3202768800
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2112128687
Short name T563
Test name
Test status
Simulation time 33794165592 ps
CPU time 118.27 seconds
Started Apr 30 12:25:01 PM PDT 24
Finished Apr 30 12:27:00 PM PDT 24
Peak memory 199544 kb
Host smart-c1eb2b9d-c458-41a0-a943-a39368d435d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112128687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2112128687
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.4292521508
Short name T371
Test name
Test status
Simulation time 666327346 ps
CPU time 2.58 seconds
Started Apr 30 12:25:00 PM PDT 24
Finished Apr 30 12:25:03 PM PDT 24
Peak memory 199408 kb
Host smart-5931e422-13e6-4288-9da9-ed74abee0dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292521508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.4292521508
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.817807900
Short name T499
Test name
Test status
Simulation time 47191635 ps
CPU time 0.96 seconds
Started Apr 30 12:24:57 PM PDT 24
Finished Apr 30 12:24:59 PM PDT 24
Peak memory 199360 kb
Host smart-fa309297-5de7-49af-9b60-6d223b5dd55e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817807900 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.817807900
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2331591522
Short name T348
Test name
Test status
Simulation time 160930460668 ps
CPU time 519.27 seconds
Started Apr 30 12:25:09 PM PDT 24
Finished Apr 30 12:33:49 PM PDT 24
Peak memory 199320 kb
Host smart-fed2e37c-041d-4ba0-8e30-87706d45ff10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331591522 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2331591522
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.770772474
Short name T343
Test name
Test status
Simulation time 1412812773 ps
CPU time 4.18 seconds
Started Apr 30 12:25:13 PM PDT 24
Finished Apr 30 12:25:18 PM PDT 24
Peak memory 199368 kb
Host smart-51367f6f-de8d-46d5-bd54-51489d36e9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770772474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.770772474
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.2559078520
Short name T66
Test name
Test status
Simulation time 143448015784 ps
CPU time 1169.72 seconds
Started Apr 30 12:26:26 PM PDT 24
Finished Apr 30 12:45:57 PM PDT 24
Peak memory 259820 kb
Host smart-ff6b53d8-dbe1-4fbe-9b52-79659a34a008
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559078520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.2559078520
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.3709421134
Short name T525
Test name
Test status
Simulation time 45350586918 ps
CPU time 680.74 seconds
Started Apr 30 12:26:29 PM PDT 24
Finished Apr 30 12:37:50 PM PDT 24
Peak memory 233044 kb
Host smart-d2ed2a91-74e6-443d-be6b-1b87a922b5ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709421134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.3709421134
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1315977348
Short name T163
Test name
Test status
Simulation time 23137135 ps
CPU time 0.55 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 193872 kb
Host smart-7ae7bd6a-2313-413d-a610-a06dd6482fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315977348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1315977348
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.167232413
Short name T415
Test name
Test status
Simulation time 1466764459 ps
CPU time 54.92 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:23:11 PM PDT 24
Peak memory 239444 kb
Host smart-af5ced3f-2be0-4fa4-96b1-acb31ff8543d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167232413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.167232413
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.105707170
Short name T123
Test name
Test status
Simulation time 3209511265 ps
CPU time 65.9 seconds
Started Apr 30 12:19:23 PM PDT 24
Finished Apr 30 12:20:30 PM PDT 24
Peak memory 199684 kb
Host smart-b5d80925-586c-4800-999c-dd42defe8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105707170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.105707170
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1103999808
Short name T213
Test name
Test status
Simulation time 3551663920 ps
CPU time 53.38 seconds
Started Apr 30 12:21:45 PM PDT 24
Finished Apr 30 12:22:38 PM PDT 24
Peak memory 199452 kb
Host smart-9c316f97-50b9-4b53-b2f1-f1f76c0285d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103999808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1103999808
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3679843367
Short name T427
Test name
Test status
Simulation time 4507871850 ps
CPU time 57.64 seconds
Started Apr 30 12:23:16 PM PDT 24
Finished Apr 30 12:24:15 PM PDT 24
Peak memory 199448 kb
Host smart-fcb68f40-de1f-4f49-914e-fadbc7dfefd8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679843367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3679843367
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3429851223
Short name T240
Test name
Test status
Simulation time 11255716233 ps
CPU time 37.61 seconds
Started Apr 30 12:22:12 PM PDT 24
Finished Apr 30 12:22:51 PM PDT 24
Peak memory 199184 kb
Host smart-787c435d-a9b6-4143-aca3-1d22e8d0777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429851223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3429851223
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.135252915
Short name T32
Test name
Test status
Simulation time 395936728 ps
CPU time 0.88 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:22:17 PM PDT 24
Peak memory 217532 kb
Host smart-7ca2f32b-fded-4bc1-ab15-61c458a97f8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135252915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.135252915
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1788746441
Short name T534
Test name
Test status
Simulation time 1889278404 ps
CPU time 6.32 seconds
Started Apr 30 12:24:12 PM PDT 24
Finished Apr 30 12:24:20 PM PDT 24
Peak memory 198176 kb
Host smart-0c8a3ad1-c562-47ff-ba36-0ee0c111f696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788746441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1788746441
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.260222544
Short name T313
Test name
Test status
Simulation time 270331067522 ps
CPU time 168.11 seconds
Started Apr 30 12:22:14 PM PDT 24
Finished Apr 30 12:25:04 PM PDT 24
Peak memory 216588 kb
Host smart-62c7398c-45cd-40b9-8cfb-2ce0146b27ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260222544 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.260222544
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.594470813
Short name T121
Test name
Test status
Simulation time 39757065 ps
CPU time 0.99 seconds
Started Apr 30 12:22:23 PM PDT 24
Finished Apr 30 12:22:24 PM PDT 24
Peak memory 199044 kb
Host smart-e7f12170-e1d0-49f6-b27e-0e4ace2de264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594470813 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.594470813
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.770782587
Short name T133
Test name
Test status
Simulation time 39284664142 ps
CPU time 395.84 seconds
Started Apr 30 12:20:11 PM PDT 24
Finished Apr 30 12:26:47 PM PDT 24
Peak memory 199624 kb
Host smart-d0352a67-866d-4cd2-ba1f-6693910407e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770782587 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.770782587
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3160267152
Short name T451
Test name
Test status
Simulation time 30159775330 ps
CPU time 59.64 seconds
Started Apr 30 12:22:22 PM PDT 24
Finished Apr 30 12:23:23 PM PDT 24
Peak memory 199416 kb
Host smart-c7a5db59-6bb8-4e46-ad30-087d8956dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160267152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3160267152
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.933922545
Short name T457
Test name
Test status
Simulation time 33127389 ps
CPU time 0.55 seconds
Started Apr 30 12:25:06 PM PDT 24
Finished Apr 30 12:25:07 PM PDT 24
Peak memory 194032 kb
Host smart-1eee8802-6ea1-4068-8cd3-26c33c8f879d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933922545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.933922545
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4228160229
Short name T55
Test name
Test status
Simulation time 3271960555 ps
CPU time 54.92 seconds
Started Apr 30 12:25:03 PM PDT 24
Finished Apr 30 12:25:58 PM PDT 24
Peak memory 226084 kb
Host smart-380e29f9-ea51-479b-8d60-babb815b6065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228160229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4228160229
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1604015385
Short name T500
Test name
Test status
Simulation time 1312439606 ps
CPU time 29.76 seconds
Started Apr 30 12:25:03 PM PDT 24
Finished Apr 30 12:25:34 PM PDT 24
Peak memory 199440 kb
Host smart-934c0861-399d-4268-a81d-f3c4d84dfb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604015385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1604015385
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3477233960
Short name T497
Test name
Test status
Simulation time 20439147140 ps
CPU time 80.34 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:26:37 PM PDT 24
Peak memory 199548 kb
Host smart-0af98aa0-cc8c-4875-b318-f4103c345b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477233960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3477233960
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.512112499
Short name T424
Test name
Test status
Simulation time 58097876997 ps
CPU time 90.37 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:26:47 PM PDT 24
Peak memory 199556 kb
Host smart-0a4c0f21-5b36-4ce6-95d8-ead095338b22
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512112499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.512112499
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2327017091
Short name T355
Test name
Test status
Simulation time 15676282 ps
CPU time 0.84 seconds
Started Apr 30 12:25:05 PM PDT 24
Finished Apr 30 12:25:06 PM PDT 24
Peak memory 198024 kb
Host smart-584aa13a-a463-4496-9548-bae7e3875fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327017091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2327017091
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2492652518
Short name T387
Test name
Test status
Simulation time 27996327 ps
CPU time 0.72 seconds
Started Apr 30 12:25:02 PM PDT 24
Finished Apr 30 12:25:04 PM PDT 24
Peak memory 196636 kb
Host smart-38f9aa70-9e0a-4760-8920-62daf01b25e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492652518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2492652518
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.944800966
Short name T270
Test name
Test status
Simulation time 17855719232 ps
CPU time 880.62 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:39:57 PM PDT 24
Peak memory 221072 kb
Host smart-f27aa2c1-98a6-420b-885b-64e7c1a33b92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944800966 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.944800966
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3941147878
Short name T309
Test name
Test status
Simulation time 38963815 ps
CPU time 1.02 seconds
Started Apr 30 12:25:05 PM PDT 24
Finished Apr 30 12:25:07 PM PDT 24
Peak memory 198440 kb
Host smart-71be9bed-bebd-46d2-9f74-134f18fbff81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941147878 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3941147878
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1445661908
Short name T519
Test name
Test status
Simulation time 157656808126 ps
CPU time 469.09 seconds
Started Apr 30 12:25:03 PM PDT 24
Finished Apr 30 12:32:53 PM PDT 24
Peak memory 199472 kb
Host smart-f8c4d2c2-325c-4c6f-a1e3-3dfd9689e7a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445661908 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1445661908
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1830150060
Short name T243
Test name
Test status
Simulation time 2367125721 ps
CPU time 66.25 seconds
Started Apr 30 12:25:09 PM PDT 24
Finished Apr 30 12:26:16 PM PDT 24
Peak memory 199448 kb
Host smart-4d1f1de0-5eec-42da-8023-682ef40fcf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830150060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1830150060
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1393197286
Short name T208
Test name
Test status
Simulation time 36177403 ps
CPU time 0.62 seconds
Started Apr 30 12:25:12 PM PDT 24
Finished Apr 30 12:25:13 PM PDT 24
Peak memory 195204 kb
Host smart-1ce0d094-1c77-4460-bf63-68efb4e48a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393197286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1393197286
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4123956934
Short name T301
Test name
Test status
Simulation time 2585643712 ps
CPU time 16.65 seconds
Started Apr 30 12:25:13 PM PDT 24
Finished Apr 30 12:25:30 PM PDT 24
Peak memory 210788 kb
Host smart-a07712e0-27b2-468e-ae12-ef0ca433979a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123956934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4123956934
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1262758369
Short name T312
Test name
Test status
Simulation time 12813768678 ps
CPU time 25.33 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:25:42 PM PDT 24
Peak memory 199488 kb
Host smart-d3e76478-fd05-4b0a-9d1b-39059f8b7b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262758369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1262758369
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2472531460
Short name T30
Test name
Test status
Simulation time 1191358490 ps
CPU time 34.28 seconds
Started Apr 30 12:25:27 PM PDT 24
Finished Apr 30 12:26:02 PM PDT 24
Peak memory 199380 kb
Host smart-fee95e6c-f7e3-4145-8ce1-5b61eafe71e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472531460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2472531460
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3687765326
Short name T536
Test name
Test status
Simulation time 2480776179 ps
CPU time 33.2 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199504 kb
Host smart-37035066-bd42-4059-81a0-6dc2d9201b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687765326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3687765326
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2587172842
Short name T281
Test name
Test status
Simulation time 622196456 ps
CPU time 2.54 seconds
Started Apr 30 12:25:15 PM PDT 24
Finished Apr 30 12:25:19 PM PDT 24
Peak memory 199460 kb
Host smart-22f6d951-ac2c-4c78-a078-ef9003a0a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587172842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2587172842
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3491907271
Short name T584
Test name
Test status
Simulation time 35958553703 ps
CPU time 505.47 seconds
Started Apr 30 12:25:27 PM PDT 24
Finished Apr 30 12:33:53 PM PDT 24
Peak memory 199456 kb
Host smart-5f687ce7-916a-4b56-8807-80c4a12abbc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491907271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3491907271
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.46687700
Short name T221
Test name
Test status
Simulation time 186621994 ps
CPU time 1.06 seconds
Started Apr 30 12:25:13 PM PDT 24
Finished Apr 30 12:25:15 PM PDT 24
Peak memory 198584 kb
Host smart-937f080d-6b06-4efd-a341-63a9bbb193b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46687700 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.hmac_test_hmac_vectors.46687700
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.720248586
Short name T126
Test name
Test status
Simulation time 27385679984 ps
CPU time 470.72 seconds
Started Apr 30 12:25:20 PM PDT 24
Finished Apr 30 12:33:11 PM PDT 24
Peak memory 199500 kb
Host smart-a7c77b52-8df3-44b2-b718-11efefb9863b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720248586 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.720248586
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2841829461
Short name T161
Test name
Test status
Simulation time 2045804719 ps
CPU time 36.02 seconds
Started Apr 30 12:25:13 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 199504 kb
Host smart-79c04b76-c858-4e90-b2a1-eca074238e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841829461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2841829461
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1935532598
Short name T146
Test name
Test status
Simulation time 25443903 ps
CPU time 0.59 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:25:32 PM PDT 24
Peak memory 195136 kb
Host smart-d064280c-fcf4-4df1-b46b-bc4735a878f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935532598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1935532598
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3871036366
Short name T282
Test name
Test status
Simulation time 120753106 ps
CPU time 3.46 seconds
Started Apr 30 12:25:15 PM PDT 24
Finished Apr 30 12:25:19 PM PDT 24
Peak memory 207616 kb
Host smart-2b34a652-8f97-40c1-b22e-f5df22a5fadf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871036366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3871036366
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3147198377
Short name T149
Test name
Test status
Simulation time 744050731 ps
CPU time 35.03 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 199476 kb
Host smart-11bbefc7-f36f-4dce-92d6-769e8ea164d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147198377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3147198377
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.786780300
Short name T194
Test name
Test status
Simulation time 2439334743 ps
CPU time 34.32 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 199532 kb
Host smart-b6a537c2-3d31-4f63-802c-9f190476090e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786780300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.786780300
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1771669342
Short name T127
Test name
Test status
Simulation time 386346240 ps
CPU time 7.28 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:22 PM PDT 24
Peak memory 199412 kb
Host smart-39cb400b-dfa4-4fcc-ad48-f3a19f989632
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771669342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1771669342
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2316297946
Short name T202
Test name
Test status
Simulation time 17011704426 ps
CPU time 57.35 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:26:14 PM PDT 24
Peak memory 199492 kb
Host smart-854df837-5209-4b69-a94d-71e4055dda0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316297946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2316297946
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.389166179
Short name T74
Test name
Test status
Simulation time 212174595 ps
CPU time 2.67 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:25:20 PM PDT 24
Peak memory 199516 kb
Host smart-7eb1f1eb-404c-43df-8d71-5b4f97fdd90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389166179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.389166179
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4202360179
Short name T543
Test name
Test status
Simulation time 68375009870 ps
CPU time 1613.83 seconds
Started Apr 30 12:25:12 PM PDT 24
Finished Apr 30 12:52:07 PM PDT 24
Peak memory 240100 kb
Host smart-de319cf3-42f7-44ae-a91e-349234594f7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202360179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4202360179
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1991369457
Short name T257
Test name
Test status
Simulation time 67558867 ps
CPU time 1.13 seconds
Started Apr 30 12:25:12 PM PDT 24
Finished Apr 30 12:25:14 PM PDT 24
Peak memory 199096 kb
Host smart-7cd16cee-8e71-4a52-add9-bb3736b4b5ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991369457 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1991369457
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3696828712
Short name T142
Test name
Test status
Simulation time 103227071139 ps
CPU time 446.56 seconds
Started Apr 30 12:25:15 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 199448 kb
Host smart-d6789742-2b96-472d-a861-177ee51166f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696828712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.3696828712
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2917841352
Short name T302
Test name
Test status
Simulation time 6937990010 ps
CPU time 40.5 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:55 PM PDT 24
Peak memory 199496 kb
Host smart-96993991-a3da-4787-9a87-eed85fe5867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917841352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2917841352
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.406128667
Short name T507
Test name
Test status
Simulation time 39113213 ps
CPU time 0.59 seconds
Started Apr 30 12:25:25 PM PDT 24
Finished Apr 30 12:25:26 PM PDT 24
Peak memory 194104 kb
Host smart-7d8b164e-3e7c-443a-a2f8-b2cf3d413151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406128667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.406128667
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.584290945
Short name T564
Test name
Test status
Simulation time 3968054786 ps
CPU time 36.09 seconds
Started Apr 30 12:25:20 PM PDT 24
Finished Apr 30 12:25:57 PM PDT 24
Peak memory 215828 kb
Host smart-353731be-cb89-435c-91e5-0f8a383b8398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584290945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.584290945
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2842921222
Short name T447
Test name
Test status
Simulation time 379320392 ps
CPU time 3.71 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:19 PM PDT 24
Peak memory 199444 kb
Host smart-52c28cfc-a4ab-492e-acb5-31b9aaa33821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842921222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2842921222
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2049737454
Short name T184
Test name
Test status
Simulation time 1551975317 ps
CPU time 92.68 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:26:47 PM PDT 24
Peak memory 199384 kb
Host smart-7b22d80d-1234-46b1-9856-c47c81b12201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2049737454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2049737454
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2078065765
Short name T528
Test name
Test status
Simulation time 1091299954 ps
CPU time 19.1 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:25:36 PM PDT 24
Peak memory 199392 kb
Host smart-0daaa44f-c9b4-498e-81f6-8557970ccfb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078065765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2078065765
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.255534762
Short name T413
Test name
Test status
Simulation time 7346139694 ps
CPU time 101.95 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:26:59 PM PDT 24
Peak memory 199516 kb
Host smart-e8db48c7-adfd-4c9c-a9d2-71224843c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255534762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.255534762
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2374788267
Short name T465
Test name
Test status
Simulation time 369598653 ps
CPU time 5.72 seconds
Started Apr 30 12:25:13 PM PDT 24
Finished Apr 30 12:25:20 PM PDT 24
Peak memory 199472 kb
Host smart-2285bd50-de81-4fb1-8bb1-38e4a8fc0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374788267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2374788267
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3869175261
Short name T516
Test name
Test status
Simulation time 43210953926 ps
CPU time 2283.79 seconds
Started Apr 30 12:25:15 PM PDT 24
Finished Apr 30 01:03:19 PM PDT 24
Peak memory 236724 kb
Host smart-a90bd7b8-1456-4f50-843a-fa58e97cb338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869175261 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3869175261
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.2416027051
Short name T490
Test name
Test status
Simulation time 119810987283 ps
CPU time 981.95 seconds
Started Apr 30 12:25:18 PM PDT 24
Finished Apr 30 12:41:41 PM PDT 24
Peak memory 242228 kb
Host smart-951d3339-8a97-4383-9f5a-e8c5964cd91d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416027051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.2416027051
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.4024489505
Short name T307
Test name
Test status
Simulation time 293014188 ps
CPU time 1.21 seconds
Started Apr 30 12:25:15 PM PDT 24
Finished Apr 30 12:25:17 PM PDT 24
Peak memory 199272 kb
Host smart-eabf150a-3556-41a4-a446-0b11a1ecc8cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024489505 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.4024489505
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1661366175
Short name T275
Test name
Test status
Simulation time 35222901839 ps
CPU time 478.17 seconds
Started Apr 30 12:25:12 PM PDT 24
Finished Apr 30 12:33:10 PM PDT 24
Peak memory 199472 kb
Host smart-8386a2ab-e333-4dd6-9c62-6d37e9a68250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661366175 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1661366175
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1589359620
Short name T435
Test name
Test status
Simulation time 12260409501 ps
CPU time 57.52 seconds
Started Apr 30 12:25:18 PM PDT 24
Finished Apr 30 12:26:16 PM PDT 24
Peak memory 199896 kb
Host smart-60ac55fa-f434-4b1c-9a57-70c84de03edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589359620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1589359620
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2268573406
Short name T339
Test name
Test status
Simulation time 16246846 ps
CPU time 0.6 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:25:31 PM PDT 24
Peak memory 195080 kb
Host smart-332932d1-3063-4e09-9494-5ac62307ec66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268573406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2268573406
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2223175016
Short name T159
Test name
Test status
Simulation time 984357612 ps
CPU time 34.58 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 215388 kb
Host smart-3f22d2b3-e6d7-4c58-a4e7-87e754c8738f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223175016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2223175016
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2189966365
Short name T325
Test name
Test status
Simulation time 5416734335 ps
CPU time 40.45 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:56 PM PDT 24
Peak memory 199528 kb
Host smart-f40802de-4e9e-43f6-a11f-d43d4417b546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189966365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2189966365
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1852458866
Short name T330
Test name
Test status
Simulation time 5569110963 ps
CPU time 164.15 seconds
Started Apr 30 12:25:21 PM PDT 24
Finished Apr 30 12:28:05 PM PDT 24
Peak memory 199544 kb
Host smart-f832b9de-d57d-46b5-b460-3a87f63f1615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1852458866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1852458866
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2614073089
Short name T545
Test name
Test status
Simulation time 3293962258 ps
CPU time 43.77 seconds
Started Apr 30 12:25:15 PM PDT 24
Finished Apr 30 12:26:00 PM PDT 24
Peak memory 199456 kb
Host smart-317af6c2-a596-4f69-8c16-c415d5bf1232
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614073089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2614073089
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.78380726
Short name T229
Test name
Test status
Simulation time 2507021218 ps
CPU time 51.96 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:26:07 PM PDT 24
Peak memory 199548 kb
Host smart-ac006657-607c-4c22-87c2-844fa2b9c5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78380726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.78380726
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2153977225
Short name T285
Test name
Test status
Simulation time 200303656 ps
CPU time 1.04 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:25:32 PM PDT 24
Peak memory 199388 kb
Host smart-962ef3aa-752c-437a-a134-d9b2b6a47415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153977225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2153977225
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2528649459
Short name T372
Test name
Test status
Simulation time 2856332610389 ps
CPU time 2640.7 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 01:09:17 PM PDT 24
Peak memory 240428 kb
Host smart-3e612636-ba24-4409-a724-4e8b57499d0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528649459 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2528649459
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2473764358
Short name T404
Test name
Test status
Simulation time 52430011 ps
CPU time 1.05 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:16 PM PDT 24
Peak memory 198264 kb
Host smart-b1ac895f-2937-431b-9603-630f5b76755c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473764358 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2473764358
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2073398878
Short name T397
Test name
Test status
Simulation time 8274279363 ps
CPU time 452.33 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 199456 kb
Host smart-8b6b886c-9e66-4558-9de2-53186ab029be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073398878 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.2073398878
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3840488122
Short name T160
Test name
Test status
Simulation time 11808725409 ps
CPU time 52.06 seconds
Started Apr 30 12:25:22 PM PDT 24
Finished Apr 30 12:26:15 PM PDT 24
Peak memory 199520 kb
Host smart-f77f54fd-0812-4283-9675-0d9f2cc23beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840488122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3840488122
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2409501111
Short name T324
Test name
Test status
Simulation time 36381520 ps
CPU time 0.65 seconds
Started Apr 30 12:25:17 PM PDT 24
Finished Apr 30 12:25:18 PM PDT 24
Peak memory 195140 kb
Host smart-ce4efc63-a447-4175-af71-d8a850506d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409501111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2409501111
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.709146810
Short name T531
Test name
Test status
Simulation time 3886556187 ps
CPU time 38.69 seconds
Started Apr 30 12:25:19 PM PDT 24
Finished Apr 30 12:25:58 PM PDT 24
Peak memory 224488 kb
Host smart-ce2bc2d9-ef47-4aba-a297-4db5e54c8b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709146810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.709146810
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2383693896
Short name T502
Test name
Test status
Simulation time 252336557 ps
CPU time 12.81 seconds
Started Apr 30 12:25:20 PM PDT 24
Finished Apr 30 12:25:34 PM PDT 24
Peak memory 199336 kb
Host smart-ab558deb-8378-420f-8087-e677c02ae47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383693896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2383693896
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3962319724
Short name T225
Test name
Test status
Simulation time 94840584 ps
CPU time 1.76 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:25:18 PM PDT 24
Peak memory 199452 kb
Host smart-96af08ce-0afb-4f15-a8ee-22ab85132373
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962319724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3962319724
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.512010713
Short name T471
Test name
Test status
Simulation time 9058922693 ps
CPU time 181.09 seconds
Started Apr 30 12:25:18 PM PDT 24
Finished Apr 30 12:28:20 PM PDT 24
Peak memory 199692 kb
Host smart-65007d9f-e485-4b66-bc0d-1014fe19da68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512010713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.512010713
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.737900346
Short name T436
Test name
Test status
Simulation time 3051021178 ps
CPU time 46.85 seconds
Started Apr 30 12:25:17 PM PDT 24
Finished Apr 30 12:26:05 PM PDT 24
Peak memory 199500 kb
Host smart-c2ce7ab2-a510-41ce-99f2-c0957e9e878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737900346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.737900346
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4221153531
Short name T284
Test name
Test status
Simulation time 203510327 ps
CPU time 5 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:25:22 PM PDT 24
Peak memory 199452 kb
Host smart-d1745111-743a-4fb7-be00-5b42ff9c921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221153531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4221153531
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1174627796
Short name T230
Test name
Test status
Simulation time 1419497711 ps
CPU time 27.66 seconds
Started Apr 30 12:25:24 PM PDT 24
Finished Apr 30 12:25:52 PM PDT 24
Peak memory 199344 kb
Host smart-5d33a31a-c2aa-4478-ba2a-202868989839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174627796 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1174627796
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3324897006
Short name T551
Test name
Test status
Simulation time 44273687 ps
CPU time 0.95 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:25:18 PM PDT 24
Peak memory 197836 kb
Host smart-7eb848e2-241f-48af-911f-ef83585c0af4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324897006 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3324897006
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1475778520
Short name T256
Test name
Test status
Simulation time 42724615707 ps
CPU time 519.01 seconds
Started Apr 30 12:25:19 PM PDT 24
Finished Apr 30 12:33:59 PM PDT 24
Peak memory 199392 kb
Host smart-9bc90e19-19b6-4ab2-8be1-cc3133f09134
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475778520 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1475778520
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3649904224
Short name T329
Test name
Test status
Simulation time 21635574529 ps
CPU time 56.36 seconds
Started Apr 30 12:25:26 PM PDT 24
Finished Apr 30 12:26:23 PM PDT 24
Peak memory 199536 kb
Host smart-1d0397b2-6256-4ff3-a815-206772c93c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649904224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3649904224
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1163654115
Short name T574
Test name
Test status
Simulation time 23443051 ps
CPU time 0.59 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:25:31 PM PDT 24
Peak memory 195020 kb
Host smart-aeb9110b-2d94-4224-a6c5-7ec397c68b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163654115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1163654115
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1428714426
Short name T182
Test name
Test status
Simulation time 1324967208 ps
CPU time 26.71 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:26:01 PM PDT 24
Peak memory 215720 kb
Host smart-2ec258e8-bbb0-45d7-8b76-ffb9fffb859d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428714426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1428714426
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1679167881
Short name T590
Test name
Test status
Simulation time 3398928021 ps
CPU time 50.45 seconds
Started Apr 30 12:25:18 PM PDT 24
Finished Apr 30 12:26:09 PM PDT 24
Peak memory 199696 kb
Host smart-9296ba34-d855-4f4b-85bb-0e9b87db7780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679167881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1679167881
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2821146321
Short name T452
Test name
Test status
Simulation time 4959388756 ps
CPU time 31.6 seconds
Started Apr 30 12:25:14 PM PDT 24
Finished Apr 30 12:25:46 PM PDT 24
Peak memory 199500 kb
Host smart-975721f9-1b53-4600-bc49-c8397aa27bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821146321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2821146321
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2509954653
Short name T520
Test name
Test status
Simulation time 11835783904 ps
CPU time 59.21 seconds
Started Apr 30 12:25:12 PM PDT 24
Finished Apr 30 12:26:12 PM PDT 24
Peak memory 199540 kb
Host smart-026ad44a-e51f-417d-b3d7-77bb039be036
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509954653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2509954653
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2917089958
Short name T573
Test name
Test status
Simulation time 1501492752 ps
CPU time 44.13 seconds
Started Apr 30 12:25:27 PM PDT 24
Finished Apr 30 12:26:12 PM PDT 24
Peak memory 199364 kb
Host smart-778d7fce-bd49-4ab0-a7b0-bbcf3acf76d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917089958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2917089958
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.998581060
Short name T331
Test name
Test status
Simulation time 56415617 ps
CPU time 1.91 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:25:36 PM PDT 24
Peak memory 199352 kb
Host smart-ec9cf884-e59f-44cd-a0f6-c8ebc6ac75ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998581060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.998581060
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2446666139
Short name T211
Test name
Test status
Simulation time 181232254698 ps
CPU time 758.08 seconds
Started Apr 30 12:25:29 PM PDT 24
Finished Apr 30 12:38:08 PM PDT 24
Peak memory 231952 kb
Host smart-88c1951b-f040-4e35-aa55-50fac581c2d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446666139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2446666139
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1562369856
Short name T407
Test name
Test status
Simulation time 92118291 ps
CPU time 1.04 seconds
Started Apr 30 12:25:16 PM PDT 24
Finished Apr 30 12:25:18 PM PDT 24
Peak memory 199048 kb
Host smart-30390d39-beac-430d-9cc2-017eb856d86e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562369856 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1562369856
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.173782521
Short name T553
Test name
Test status
Simulation time 105352510049 ps
CPU time 437.76 seconds
Started Apr 30 12:25:24 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 199404 kb
Host smart-05d8fac1-a44e-4c1f-9bb3-abd77cf34192
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173782521 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.173782521
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.571648377
Short name T150
Test name
Test status
Simulation time 104764894 ps
CPU time 2.91 seconds
Started Apr 30 12:25:23 PM PDT 24
Finished Apr 30 12:25:27 PM PDT 24
Peak memory 199368 kb
Host smart-37e44242-9729-4ded-be96-e9db654f376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571648377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.571648377
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1747538897
Short name T205
Test name
Test status
Simulation time 28064519 ps
CPU time 0.58 seconds
Started Apr 30 12:25:35 PM PDT 24
Finished Apr 30 12:25:37 PM PDT 24
Peak memory 194768 kb
Host smart-ef087ed5-c0c1-4631-8d95-cd22e6698045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747538897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1747538897
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.580212698
Short name T357
Test name
Test status
Simulation time 7923311692 ps
CPU time 31.25 seconds
Started Apr 30 12:25:31 PM PDT 24
Finished Apr 30 12:26:03 PM PDT 24
Peak memory 199552 kb
Host smart-ed6887ec-bea2-4518-b971-fe5ba3e93a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580212698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.580212698
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3231627958
Short name T468
Test name
Test status
Simulation time 2239574593 ps
CPU time 129.82 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:27:38 PM PDT 24
Peak memory 199488 kb
Host smart-1cd0caba-fecb-4fe1-8435-0cd05fe3ebb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231627958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3231627958
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2890026071
Short name T377
Test name
Test status
Simulation time 159183418997 ps
CPU time 224.92 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:29:22 PM PDT 24
Peak memory 199476 kb
Host smart-739c9c81-250b-4eef-be4a-48aa9cee6207
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890026071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2890026071
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3534600246
Short name T434
Test name
Test status
Simulation time 1858912721 ps
CPU time 35.67 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:26:10 PM PDT 24
Peak memory 199448 kb
Host smart-ba943029-3b26-4f85-8825-3adde3a5881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534600246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3534600246
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.195303935
Short name T220
Test name
Test status
Simulation time 639153958 ps
CPU time 4.66 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 199428 kb
Host smart-85184d48-778d-4080-a3f8-62663fd000f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195303935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.195303935
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2478728484
Short name T19
Test name
Test status
Simulation time 2054294555 ps
CPU time 93.38 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:27:12 PM PDT 24
Peak memory 223948 kb
Host smart-42d7ce3d-2900-4398-8e4b-e6099383599f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478728484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2478728484
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.635512054
Short name T173
Test name
Test status
Simulation time 100490551 ps
CPU time 0.93 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:25:29 PM PDT 24
Peak memory 199144 kb
Host smart-fbdb280e-6db3-4fb8-8845-2ba79cad99c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635512054 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.635512054
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.364591757
Short name T327
Test name
Test status
Simulation time 38665441109 ps
CPU time 538.52 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 199456 kb
Host smart-f81ddcce-cc6f-4e78-bcd9-ed4e337918dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364591757 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.364591757
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2045874411
Short name T412
Test name
Test status
Simulation time 18678536612 ps
CPU time 87.6 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:27:01 PM PDT 24
Peak memory 199504 kb
Host smart-a43ea612-cc43-464f-9a85-e9b4ab6169a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045874411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2045874411
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3788082120
Short name T135
Test name
Test status
Simulation time 44354586 ps
CPU time 0.58 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:25:31 PM PDT 24
Peak memory 193780 kb
Host smart-f4f5ba61-4b80-46e2-ab7d-a16a0d69b76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788082120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3788082120
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3842904934
Short name T338
Test name
Test status
Simulation time 3766855133 ps
CPU time 38.29 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:26:13 PM PDT 24
Peak memory 224584 kb
Host smart-7d87bf8f-3201-405a-9122-dfb4145d413c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842904934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3842904934
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.501502659
Short name T249
Test name
Test status
Simulation time 4357950971 ps
CPU time 60.66 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:26:29 PM PDT 24
Peak memory 199520 kb
Host smart-88c371b0-0e77-4adb-a60e-de2aff5ea1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501502659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.501502659
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1916458980
Short name T131
Test name
Test status
Simulation time 11250178696 ps
CPU time 95.44 seconds
Started Apr 30 12:25:29 PM PDT 24
Finished Apr 30 12:27:05 PM PDT 24
Peak memory 199416 kb
Host smart-d438077b-2f84-4f68-9146-fcd6234de51f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916458980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1916458980
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3223199520
Short name T246
Test name
Test status
Simulation time 16702496917 ps
CPU time 151.19 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:28:09 PM PDT 24
Peak memory 199536 kb
Host smart-08b499e9-26e6-4964-8d3e-ef6c4018e1a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223199520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3223199520
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2011731454
Short name T601
Test name
Test status
Simulation time 2825377373 ps
CPU time 45.13 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:26:20 PM PDT 24
Peak memory 199496 kb
Host smart-0f3f3e92-47e7-4ff4-925c-4faceff7a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011731454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2011731454
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2346373420
Short name T400
Test name
Test status
Simulation time 207626019 ps
CPU time 2.84 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 199468 kb
Host smart-147a7351-2286-4381-bd61-d25bf4c8f293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346373420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2346373420
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3747759352
Short name T174
Test name
Test status
Simulation time 36532628262 ps
CPU time 641.88 seconds
Started Apr 30 12:25:35 PM PDT 24
Finished Apr 30 12:36:18 PM PDT 24
Peak memory 199304 kb
Host smart-44a37754-14b8-4eb7-a926-6485117ffad1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747759352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3747759352
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.538650135
Short name T63
Test name
Test status
Simulation time 30810929730 ps
CPU time 1674.17 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:53:29 PM PDT 24
Peak memory 248772 kb
Host smart-67f49f5a-2a75-4ef5-af8c-ea16d77ca03c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538650135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.538650135
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1817338266
Short name T420
Test name
Test status
Simulation time 55527030 ps
CPU time 0.95 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:25:32 PM PDT 24
Peak memory 198488 kb
Host smart-7335791b-a646-4554-b0a7-f79e5881a222
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817338266 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1817338266
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.371291313
Short name T233
Test name
Test status
Simulation time 32336433261 ps
CPU time 457.11 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:33:13 PM PDT 24
Peak memory 199480 kb
Host smart-e3bfcb34-7de8-4c23-ba18-186500c8f7d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371291313 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.371291313
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3445746454
Short name T599
Test name
Test status
Simulation time 3398325136 ps
CPU time 12.13 seconds
Started Apr 30 12:25:29 PM PDT 24
Finished Apr 30 12:25:42 PM PDT 24
Peak memory 199520 kb
Host smart-cbbdb0c1-9bfd-4f7f-846d-5b5a219bde4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445746454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3445746454
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1137218828
Short name T2
Test name
Test status
Simulation time 16095764 ps
CPU time 0.56 seconds
Started Apr 30 12:25:31 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 194116 kb
Host smart-b5eb6446-0f29-46be-ab40-57a9411b1377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137218828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1137218828
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3221369018
Short name T40
Test name
Test status
Simulation time 849723663 ps
CPU time 14.83 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 207596 kb
Host smart-a73dce05-1f3e-42dc-8a48-e491ece07ec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221369018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3221369018
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.347916954
Short name T504
Test name
Test status
Simulation time 1868824171 ps
CPU time 30.79 seconds
Started Apr 30 12:25:31 PM PDT 24
Finished Apr 30 12:26:03 PM PDT 24
Peak memory 199460 kb
Host smart-43058da8-1a92-465e-9613-fffdadcce9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347916954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.347916954
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3440729738
Short name T433
Test name
Test status
Simulation time 52238118 ps
CPU time 3.1 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:25:38 PM PDT 24
Peak memory 199380 kb
Host smart-0b65ea7a-27fd-41cc-aca4-b7dd72a81872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440729738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3440729738
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2724617914
Short name T114
Test name
Test status
Simulation time 5091153391 ps
CPU time 33.67 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:26:08 PM PDT 24
Peak memory 199504 kb
Host smart-8258ef1d-5fd5-4cb5-b567-18e3004459f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724617914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2724617914
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4001622509
Short name T128
Test name
Test status
Simulation time 60841471667 ps
CPU time 73.96 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:26:52 PM PDT 24
Peak memory 199536 kb
Host smart-89570cff-c04b-4487-bd09-ac1fc4e0b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001622509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4001622509
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2769332934
Short name T489
Test name
Test status
Simulation time 496573299 ps
CPU time 3.11 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:36 PM PDT 24
Peak memory 199372 kb
Host smart-e6e80479-88d1-4d5f-a6b7-886969fe6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769332934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2769332934
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.593143649
Short name T367
Test name
Test status
Simulation time 13486742450 ps
CPU time 192.64 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:28:47 PM PDT 24
Peak memory 232260 kb
Host smart-52bace2a-64a3-478a-b032-e332c531a150
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593143649 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.593143649
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.879567010
Short name T39
Test name
Test status
Simulation time 221944933 ps
CPU time 1.19 seconds
Started Apr 30 12:25:24 PM PDT 24
Finished Apr 30 12:25:26 PM PDT 24
Peak memory 199416 kb
Host smart-575f3a21-2bcc-4723-a043-7ffb0e8d589c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879567010 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.879567010
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.366958116
Short name T264
Test name
Test status
Simulation time 187030298549 ps
CPU time 446.01 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:33:00 PM PDT 24
Peak memory 199448 kb
Host smart-ec1c2584-58ca-492b-b9e4-192d09ecf82b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366958116 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.366958116
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3886959288
Short name T162
Test name
Test status
Simulation time 10362829634 ps
CPU time 58.9 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:26:28 PM PDT 24
Peak memory 199540 kb
Host smart-d1bf540f-1fc3-425c-8056-7f779090e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886959288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3886959288
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.4035054247
Short name T310
Test name
Test status
Simulation time 22134933 ps
CPU time 0.58 seconds
Started Apr 30 12:21:14 PM PDT 24
Finished Apr 30 12:21:15 PM PDT 24
Peak memory 195124 kb
Host smart-0c378343-ed6e-4fdf-b58f-e6a937046544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035054247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.4035054247
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.893624505
Short name T552
Test name
Test status
Simulation time 4575340126 ps
CPU time 33.45 seconds
Started Apr 30 12:21:44 PM PDT 24
Finished Apr 30 12:22:18 PM PDT 24
Peak memory 215144 kb
Host smart-65057f1e-949f-4ccc-b673-fb5a23d06a04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893624505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.893624505
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.191873368
Short name T25
Test name
Test status
Simulation time 618106165 ps
CPU time 28.78 seconds
Started Apr 30 12:20:43 PM PDT 24
Finished Apr 30 12:21:13 PM PDT 24
Peak memory 199396 kb
Host smart-90fb5f78-3f26-431d-86cd-de426503fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191873368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.191873368
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.4138398799
Short name T130
Test name
Test status
Simulation time 5860842149 ps
CPU time 83.26 seconds
Started Apr 30 12:20:41 PM PDT 24
Finished Apr 30 12:22:05 PM PDT 24
Peak memory 199476 kb
Host smart-f704a0ac-12b2-4e49-9c69-5c218a19f762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138398799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4138398799
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1548283394
Short name T46
Test name
Test status
Simulation time 13790193873 ps
CPU time 57.64 seconds
Started Apr 30 12:22:56 PM PDT 24
Finished Apr 30 12:23:55 PM PDT 24
Peak memory 199456 kb
Host smart-731b239f-6e89-4185-950b-d11f20f1c382
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548283394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1548283394
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1417026708
Short name T78
Test name
Test status
Simulation time 6913404588 ps
CPU time 101.08 seconds
Started Apr 30 12:21:42 PM PDT 24
Finished Apr 30 12:23:24 PM PDT 24
Peak memory 199456 kb
Host smart-9b51c2bc-d44f-4173-823b-bbaff3a15980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417026708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1417026708
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3602891221
Short name T33
Test name
Test status
Simulation time 59973102 ps
CPU time 0.93 seconds
Started Apr 30 12:23:05 PM PDT 24
Finished Apr 30 12:23:08 PM PDT 24
Peak memory 217828 kb
Host smart-80fb9b16-848b-47ec-972b-969dd10684df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602891221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3602891221
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.551280366
Short name T193
Test name
Test status
Simulation time 341037201 ps
CPU time 2.62 seconds
Started Apr 30 12:22:06 PM PDT 24
Finished Apr 30 12:22:10 PM PDT 24
Peak memory 198304 kb
Host smart-1951868f-3596-4960-9706-1caf05912753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551280366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.551280366
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2678952956
Short name T354
Test name
Test status
Simulation time 32710428125 ps
CPU time 378.47 seconds
Started Apr 30 12:22:53 PM PDT 24
Finished Apr 30 12:29:12 PM PDT 24
Peak memory 223572 kb
Host smart-09c13251-257e-4b29-8f76-83c1ea9bb1c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678952956 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2678952956
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2176461063
Short name T137
Test name
Test status
Simulation time 145618135 ps
CPU time 1.23 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:23:00 PM PDT 24
Peak memory 199312 kb
Host smart-97329d12-4cab-4660-a8c4-b2e2017b1995
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176461063 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2176461063
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3472868264
Short name T41
Test name
Test status
Simulation time 8073159654 ps
CPU time 403.43 seconds
Started Apr 30 12:22:58 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 199388 kb
Host smart-f9d84e6a-90dd-4a94-a766-f29665ac6410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472868264 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3472868264
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3298076795
Short name T602
Test name
Test status
Simulation time 9231108479 ps
CPU time 38.11 seconds
Started Apr 30 12:22:07 PM PDT 24
Finished Apr 30 12:22:46 PM PDT 24
Peak memory 199196 kb
Host smart-9df46ec0-0645-4443-944f-f6f7e1e3d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298076795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3298076795
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1189495913
Short name T409
Test name
Test status
Simulation time 16694642 ps
CPU time 0.62 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 195064 kb
Host smart-78fadad0-546d-4b32-8b4b-21315c462ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189495913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1189495913
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.325464969
Short name T438
Test name
Test status
Simulation time 831086476 ps
CPU time 28.82 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:25:59 PM PDT 24
Peak memory 215664 kb
Host smart-4911c6b4-b0ec-4383-80c7-80c9a7629d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325464969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.325464969
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.44874618
Short name T388
Test name
Test status
Simulation time 1680501078 ps
CPU time 3.69 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:37 PM PDT 24
Peak memory 199424 kb
Host smart-83108d1a-c23a-4c20-a4ee-93ee9d5ab363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44874618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.44874618
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.842867117
Short name T289
Test name
Test status
Simulation time 7339507255 ps
CPU time 101.13 seconds
Started Apr 30 12:25:25 PM PDT 24
Finished Apr 30 12:27:07 PM PDT 24
Peak memory 199588 kb
Host smart-2ffcad20-0e90-41e8-864f-ea6a72f2a5f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842867117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.842867117
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3406296270
Short name T390
Test name
Test status
Simulation time 50183387 ps
CPU time 0.66 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:25:29 PM PDT 24
Peak memory 196020 kb
Host smart-0130bae6-d70c-4e4f-9481-80c57e7c239c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406296270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3406296270
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3966042049
Short name T207
Test name
Test status
Simulation time 15316867308 ps
CPU time 54.59 seconds
Started Apr 30 12:25:31 PM PDT 24
Finished Apr 30 12:26:26 PM PDT 24
Peak memory 199528 kb
Host smart-d5ddfc24-2342-47d3-a882-92c9b9ae77a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966042049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3966042049
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1768060870
Short name T379
Test name
Test status
Simulation time 203982836 ps
CPU time 2.02 seconds
Started Apr 30 12:25:29 PM PDT 24
Finished Apr 30 12:25:32 PM PDT 24
Peak memory 199340 kb
Host smart-ea696dc6-f5dc-4364-a148-5a19cc62c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768060870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1768060870
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3876998584
Short name T335
Test name
Test status
Simulation time 7365570615 ps
CPU time 362.18 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:31:40 PM PDT 24
Peak memory 199544 kb
Host smart-599b6749-f7ee-414c-987d-8262829ddb7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876998584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3876998584
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3237921733
Short name T374
Test name
Test status
Simulation time 78728663 ps
CPU time 1.06 seconds
Started Apr 30 12:25:25 PM PDT 24
Finished Apr 30 12:25:27 PM PDT 24
Peak memory 198828 kb
Host smart-02a9b0b1-f2b5-4360-8213-253eb7e8e627
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237921733 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3237921733
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.174333273
Short name T204
Test name
Test status
Simulation time 40553847525 ps
CPU time 505.27 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:34:00 PM PDT 24
Peak memory 199624 kb
Host smart-e649132f-2f90-4fa0-a39f-7d349862f9d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174333273 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.174333273
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2720113762
Short name T527
Test name
Test status
Simulation time 2331283073 ps
CPU time 29.76 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:26:10 PM PDT 24
Peak memory 199592 kb
Host smart-635be691-d00a-413d-9c54-efc07b0158fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720113762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2720113762
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2041152747
Short name T523
Test name
Test status
Simulation time 13140400 ps
CPU time 0.57 seconds
Started Apr 30 12:25:24 PM PDT 24
Finished Apr 30 12:25:25 PM PDT 24
Peak memory 194220 kb
Host smart-730e4569-89cc-4ac2-a33e-61f7c4375266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041152747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2041152747
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.995369780
Short name T360
Test name
Test status
Simulation time 5849237197 ps
CPU time 52.97 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:26:26 PM PDT 24
Peak memory 233288 kb
Host smart-5cffe273-22df-4945-a2c3-4fc4e184388e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995369780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.995369780
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1108368384
Short name T566
Test name
Test status
Simulation time 1980331687 ps
CPU time 19.64 seconds
Started Apr 30 12:25:24 PM PDT 24
Finished Apr 30 12:25:45 PM PDT 24
Peak memory 199420 kb
Host smart-208db98a-8c9f-4caa-92e7-0ff484c26225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108368384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1108368384
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.739975047
Short name T544
Test name
Test status
Simulation time 2581111035 ps
CPU time 79.8 seconds
Started Apr 30 12:25:26 PM PDT 24
Finished Apr 30 12:26:46 PM PDT 24
Peak memory 199496 kb
Host smart-da2a403b-8e68-4b95-b8fb-35ebda7730d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739975047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.739975047
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1529769800
Short name T28
Test name
Test status
Simulation time 13566797568 ps
CPU time 197.87 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:28:48 PM PDT 24
Peak memory 199508 kb
Host smart-9f8b69c9-0cd2-4c88-89ee-0fb4a52f34ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529769800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1529769800
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1346881832
Short name T116
Test name
Test status
Simulation time 5862009152 ps
CPU time 82.47 seconds
Started Apr 30 12:25:27 PM PDT 24
Finished Apr 30 12:26:50 PM PDT 24
Peak memory 199516 kb
Host smart-ebd2e779-02ed-4f9d-9521-b858b47d2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346881832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1346881832
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.917281191
Short name T144
Test name
Test status
Simulation time 771661258 ps
CPU time 4.55 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 199488 kb
Host smart-6fa43029-d936-4341-840d-9d97ee0be97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917281191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.917281191
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2848785428
Short name T491
Test name
Test status
Simulation time 142667216410 ps
CPU time 651.86 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:36:27 PM PDT 24
Peak memory 215272 kb
Host smart-382ab43b-b767-4756-bb44-b809a1c72ca8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848785428 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2848785428
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.256078385
Short name T79
Test name
Test status
Simulation time 36689848511 ps
CPU time 949.9 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:41:23 PM PDT 24
Peak memory 236400 kb
Host smart-d3f97e6c-c611-4677-9a09-f60fb89f1084
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256078385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.256078385
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2047582304
Short name T450
Test name
Test status
Simulation time 150699079 ps
CPU time 1.35 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:25:30 PM PDT 24
Peak memory 199476 kb
Host smart-ea24972d-f429-440a-bffd-e150682107d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047582304 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2047582304
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2489494250
Short name T177
Test name
Test status
Simulation time 7901163926 ps
CPU time 405.48 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:32:14 PM PDT 24
Peak memory 199516 kb
Host smart-007f2483-4048-4428-bac2-008ee0846000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489494250 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2489494250
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1113830335
Short name T431
Test name
Test status
Simulation time 53370715926 ps
CPU time 48.97 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:26:26 PM PDT 24
Peak memory 199488 kb
Host smart-a2aee15f-c0a1-4c76-a6fe-f0262cac877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113830335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1113830335
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4036129175
Short name T141
Test name
Test status
Simulation time 13804275 ps
CPU time 0.6 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 195136 kb
Host smart-07745da7-07f1-4cea-af76-868ee39bf2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036129175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4036129175
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3483644296
Short name T222
Test name
Test status
Simulation time 869290239 ps
CPU time 8.62 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:42 PM PDT 24
Peak memory 207464 kb
Host smart-844b4e84-f90a-4b9e-a5e0-cb05c1f22456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483644296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3483644296
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.624939632
Short name T85
Test name
Test status
Simulation time 102487256 ps
CPU time 1.26 seconds
Started Apr 30 12:25:43 PM PDT 24
Finished Apr 30 12:25:44 PM PDT 24
Peak memory 199372 kb
Host smart-75f94ea7-b015-4669-85ed-40d39917c510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624939632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.624939632
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1066982002
Short name T522
Test name
Test status
Simulation time 3951416021 ps
CPU time 110.45 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:27:19 PM PDT 24
Peak memory 199532 kb
Host smart-bb357e31-4864-4908-bcfd-5b4dc1786e60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066982002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1066982002
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3668990554
Short name T274
Test name
Test status
Simulation time 1371771342 ps
CPU time 75.75 seconds
Started Apr 30 12:25:30 PM PDT 24
Finished Apr 30 12:26:47 PM PDT 24
Peak memory 199460 kb
Host smart-88125138-4cc5-4a60-b1ee-10582fb1ee99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668990554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3668990554
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3891247542
Short name T138
Test name
Test status
Simulation time 7209183776 ps
CPU time 106.88 seconds
Started Apr 30 12:25:27 PM PDT 24
Finished Apr 30 12:27:15 PM PDT 24
Peak memory 199480 kb
Host smart-376c001b-3eea-4891-9e48-263e6db81d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891247542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3891247542
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3044165794
Short name T476
Test name
Test status
Simulation time 262273053 ps
CPU time 3.44 seconds
Started Apr 30 12:25:29 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 199448 kb
Host smart-f1ca7a9a-f373-4266-8f6a-4d3c1b44e517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044165794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3044165794
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.867448787
Short name T70
Test name
Test status
Simulation time 232293566925 ps
CPU time 723.68 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:37:37 PM PDT 24
Peak memory 199516 kb
Host smart-06ecd510-6295-42ad-a59b-4b1d8ba851f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867448787 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.867448787
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1950410382
Short name T341
Test name
Test status
Simulation time 62534427 ps
CPU time 1.41 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:25:40 PM PDT 24
Peak memory 199464 kb
Host smart-2c6cce8d-0212-4891-8cc5-fc7b16bd7883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950410382 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1950410382
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1955773074
Short name T80
Test name
Test status
Simulation time 28711837137 ps
CPU time 540.95 seconds
Started Apr 30 12:25:31 PM PDT 24
Finished Apr 30 12:34:33 PM PDT 24
Peak memory 199456 kb
Host smart-7554657e-75cc-4e79-9b22-8a87430eda66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955773074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1955773074
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1173779084
Short name T265
Test name
Test status
Simulation time 6886865982 ps
CPU time 77.1 seconds
Started Apr 30 12:25:35 PM PDT 24
Finished Apr 30 12:26:53 PM PDT 24
Peak memory 199488 kb
Host smart-2ec2d403-04f7-4468-b59e-b8b85a603ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173779084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1173779084
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2608733146
Short name T188
Test name
Test status
Simulation time 12762803 ps
CPU time 0.57 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 194696 kb
Host smart-cd173a1a-50b9-49bf-be04-7ecab7cd4f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608733146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2608733146
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3853933648
Short name T473
Test name
Test status
Simulation time 6071442331 ps
CPU time 59.7 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:26:33 PM PDT 24
Peak memory 247900 kb
Host smart-383cbb61-cb2e-46a6-bcb8-2ec37a523251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853933648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3853933648
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3581760450
Short name T203
Test name
Test status
Simulation time 10477061490 ps
CPU time 44.01 seconds
Started Apr 30 12:25:29 PM PDT 24
Finished Apr 30 12:26:14 PM PDT 24
Peak memory 199524 kb
Host smart-da08c6ad-0b39-422c-a449-446ffa008323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581760450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3581760450
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3193279224
Short name T125
Test name
Test status
Simulation time 1241695770 ps
CPU time 64.01 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:26:37 PM PDT 24
Peak memory 199424 kb
Host smart-0d2c4945-73e3-4c46-bca4-5e3e05e85ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193279224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3193279224
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.669554026
Short name T294
Test name
Test status
Simulation time 11674296030 ps
CPU time 77.28 seconds
Started Apr 30 12:25:28 PM PDT 24
Finished Apr 30 12:26:46 PM PDT 24
Peak memory 199560 kb
Host smart-1c2d5e25-28a2-4325-89ab-711b752040cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669554026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.669554026
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.288429816
Short name T191
Test name
Test status
Simulation time 3772678328 ps
CPU time 34.7 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:26:07 PM PDT 24
Peak memory 199496 kb
Host smart-577dc716-3911-4f6d-89eb-b05fc438231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288429816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.288429816
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.401511651
Short name T37
Test name
Test status
Simulation time 499251804 ps
CPU time 4.42 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:37 PM PDT 24
Peak memory 199428 kb
Host smart-9c9f6033-44a7-4839-b5f8-7eb838d55171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401511651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.401511651
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.905060066
Short name T559
Test name
Test status
Simulation time 28668259721 ps
CPU time 1590.24 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:52:04 PM PDT 24
Peak memory 199476 kb
Host smart-70eb72b2-7382-4110-bb2b-9bb4a31e2e69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905060066 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.905060066
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.663325712
Short name T219
Test name
Test status
Simulation time 85277184 ps
CPU time 1.15 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:25:40 PM PDT 24
Peak memory 199292 kb
Host smart-8c955bff-099a-42e9-b51a-d84227941d11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663325712 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.663325712
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1285668458
Short name T167
Test name
Test status
Simulation time 7071848160 ps
CPU time 395.78 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:32:17 PM PDT 24
Peak memory 199412 kb
Host smart-c09f599e-09a5-4dc1-ac27-d3123aeb4f43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285668458 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1285668458
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.898378852
Short name T484
Test name
Test status
Simulation time 700710871 ps
CPU time 13.49 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:25:52 PM PDT 24
Peak memory 199220 kb
Host smart-418c7a1e-5518-49e2-bfd4-f3f05b1d5319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898378852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.898378852
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2209024636
Short name T389
Test name
Test status
Simulation time 16279042 ps
CPU time 0.62 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:25:42 PM PDT 24
Peak memory 195316 kb
Host smart-f3bf308a-2ebe-4d2a-a937-721b971f698a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209024636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2209024636
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.176828400
Short name T212
Test name
Test status
Simulation time 2012572952 ps
CPU time 13.24 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:25:53 PM PDT 24
Peak memory 207548 kb
Host smart-99192d51-2f78-4c01-87d0-3ee51c4b5784
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176828400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.176828400
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.75898566
Short name T187
Test name
Test status
Simulation time 442699883 ps
CPU time 22.44 seconds
Started Apr 30 12:25:27 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 199492 kb
Host smart-df54a0c6-c654-45b4-9de5-735456bd127b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75898566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.75898566
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.883767054
Short name T110
Test name
Test status
Simulation time 6789116259 ps
CPU time 94.82 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:27:14 PM PDT 24
Peak memory 199380 kb
Host smart-1bcb50ab-25b3-4b1c-b31a-8df60ea2042a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883767054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.883767054
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.288249434
Short name T592
Test name
Test status
Simulation time 35232038330 ps
CPU time 103 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:27:22 PM PDT 24
Peak memory 199404 kb
Host smart-dccbe127-cf14-44f2-8565-c9aa6cb344d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288249434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.288249434
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3848112761
Short name T259
Test name
Test status
Simulation time 3625740763 ps
CPU time 48.7 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:26:25 PM PDT 24
Peak memory 199408 kb
Host smart-0d1cfe24-e4a0-46d0-be45-8c40c2edff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848112761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3848112761
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3298444269
Short name T255
Test name
Test status
Simulation time 103656283 ps
CPU time 3.24 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:25:43 PM PDT 24
Peak memory 199328 kb
Host smart-2fd772fa-3562-4458-8d57-12bb69329dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298444269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3298444269
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.1583427361
Short name T65
Test name
Test status
Simulation time 88739700417 ps
CPU time 2158.94 seconds
Started Apr 30 12:25:31 PM PDT 24
Finished Apr 30 01:01:31 PM PDT 24
Peak memory 264292 kb
Host smart-6de3c6b5-b014-4182-b347-78bb80251c32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583427361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.1583427361
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1580953837
Short name T380
Test name
Test status
Simulation time 29221371 ps
CPU time 1.03 seconds
Started Apr 30 12:25:35 PM PDT 24
Finished Apr 30 12:25:36 PM PDT 24
Peak memory 199116 kb
Host smart-3fcf6235-8007-4cc9-bdcd-25ff374e0b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580953837 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1580953837
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3483950473
Short name T280
Test name
Test status
Simulation time 56080523479 ps
CPU time 451.39 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:33:04 PM PDT 24
Peak memory 199436 kb
Host smart-006b8606-1dd7-449a-b4dd-733b293ea244
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483950473 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3483950473
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3721308734
Short name T271
Test name
Test status
Simulation time 37362304 ps
CPU time 1.96 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:25:36 PM PDT 24
Peak memory 199452 kb
Host smart-23e46af0-d81d-4eca-8a3a-fbc7ec27f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721308734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3721308734
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.208017666
Short name T506
Test name
Test status
Simulation time 11520563 ps
CPU time 0.56 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:25:40 PM PDT 24
Peak memory 195068 kb
Host smart-390e53c8-c2ef-49fc-ab0d-506703091770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208017666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.208017666
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1822608956
Short name T322
Test name
Test status
Simulation time 544047574 ps
CPU time 19.46 seconds
Started Apr 30 12:25:32 PM PDT 24
Finished Apr 30 12:25:52 PM PDT 24
Peak memory 207584 kb
Host smart-38ed4059-cc2d-4041-bd46-ae61e2053487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822608956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1822608956
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.210330121
Short name T115
Test name
Test status
Simulation time 1762256663 ps
CPU time 59.28 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:26:36 PM PDT 24
Peak memory 199632 kb
Host smart-561d41f8-b167-404f-bc4f-9f87b6aac7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210330121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.210330121
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2180071857
Short name T152
Test name
Test status
Simulation time 9329943107 ps
CPU time 42.23 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:26:23 PM PDT 24
Peak memory 199452 kb
Host smart-a76f846e-c39c-49ef-83b7-d021b95bb215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180071857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2180071857
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1002611316
Short name T297
Test name
Test status
Simulation time 4772790520 ps
CPU time 143.55 seconds
Started Apr 30 12:25:33 PM PDT 24
Finished Apr 30 12:27:58 PM PDT 24
Peak memory 199548 kb
Host smart-b27068b4-2e5a-4473-b85f-779031fbd74f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002611316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1002611316
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3158485918
Short name T459
Test name
Test status
Simulation time 2407920992 ps
CPU time 70.86 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:26:51 PM PDT 24
Peak memory 199700 kb
Host smart-59de7722-19e6-4f55-8995-fbebcd2c736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158485918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3158485918
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.4236410516
Short name T394
Test name
Test status
Simulation time 148277072 ps
CPU time 4.71 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 199392 kb
Host smart-bd998c4d-6b14-4439-a23d-4217cb0dff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236410516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4236410516
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3465422914
Short name T29
Test name
Test status
Simulation time 20314564086 ps
CPU time 304.77 seconds
Started Apr 30 12:25:35 PM PDT 24
Finished Apr 30 12:30:40 PM PDT 24
Peak memory 234156 kb
Host smart-aa743c54-fa12-4f2a-b964-2e5af2325d40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465422914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3465422914
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1002809813
Short name T35
Test name
Test status
Simulation time 32590443 ps
CPU time 1.26 seconds
Started Apr 30 12:25:31 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 199460 kb
Host smart-b3a7d787-88c6-4fb5-bb9f-e287f4e5e7d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002809813 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1002809813
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1640155532
Short name T532
Test name
Test status
Simulation time 128161396841 ps
CPU time 490.04 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 199412 kb
Host smart-7b16028d-f35c-4dbb-aace-10640ec0e4cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640155532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1640155532
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3798023006
Short name T231
Test name
Test status
Simulation time 12493774240 ps
CPU time 24.99 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:26:02 PM PDT 24
Peak memory 199428 kb
Host smart-db928fd0-60c1-4663-831e-6e88325bc634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798023006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3798023006
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3494678372
Short name T570
Test name
Test status
Simulation time 38211023 ps
CPU time 0.64 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:25:37 PM PDT 24
Peak memory 195320 kb
Host smart-838c32d1-5156-44df-8b33-83a917e70d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494678372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3494678372
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2048225226
Short name T237
Test name
Test status
Simulation time 2473576841 ps
CPU time 26.88 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:26:08 PM PDT 24
Peak memory 214556 kb
Host smart-459b1e9d-98a2-4fb4-84a4-fee6d9b826a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048225226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2048225226
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.320633091
Short name T278
Test name
Test status
Simulation time 4363490869 ps
CPU time 50.33 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:26:36 PM PDT 24
Peak memory 199480 kb
Host smart-0295a43d-4740-4259-9374-ac92682026b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320633091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.320633091
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.278180915
Short name T315
Test name
Test status
Simulation time 1290270030 ps
CPU time 69.74 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:28:02 PM PDT 24
Peak memory 196624 kb
Host smart-0988b373-1562-48e0-b674-9af62423bad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278180915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.278180915
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2503479867
Short name T456
Test name
Test status
Simulation time 9032276937 ps
CPU time 145.26 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:28:11 PM PDT 24
Peak memory 199480 kb
Host smart-efa3ec2c-beed-484a-ac1a-358c97d1d010
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503479867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2503479867
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2497437254
Short name T117
Test name
Test status
Simulation time 5105265341 ps
CPU time 71.1 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:27:00 PM PDT 24
Peak memory 199436 kb
Host smart-6de87a30-d5a9-4aa6-8da4-3cb9ee544f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497437254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2497437254
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1645038442
Short name T132
Test name
Test status
Simulation time 121092744 ps
CPU time 3.33 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:25:41 PM PDT 24
Peak memory 199480 kb
Host smart-3fa02935-8eab-4816-b956-dd8f438817e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645038442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1645038442
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.576510782
Short name T45
Test name
Test status
Simulation time 522955317793 ps
CPU time 1601.64 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:52:21 PM PDT 24
Peak memory 215604 kb
Host smart-7ccff4d0-f197-4efd-b88d-c533a99b7857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576510782 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.576510782
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1611854617
Short name T176
Test name
Test status
Simulation time 79868329 ps
CPU time 1.01 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:25:41 PM PDT 24
Peak memory 198360 kb
Host smart-01199bfb-0766-4aa3-a31f-ca0d0a4342d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611854617 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1611854617
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3175339989
Short name T293
Test name
Test status
Simulation time 38024450395 ps
CPU time 510.56 seconds
Started Apr 30 12:25:47 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 199416 kb
Host smart-cca3d075-2708-4b16-840e-a3b02ebcfd36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175339989 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3175339989
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1451190179
Short name T227
Test name
Test status
Simulation time 1141295816 ps
CPU time 13.08 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:25:51 PM PDT 24
Peak memory 199492 kb
Host smart-21d4c5b6-46c8-4fe6-9e97-4b90bceada7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451190179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1451190179
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.673918523
Short name T299
Test name
Test status
Simulation time 33739908 ps
CPU time 0.57 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 195012 kb
Host smart-0a73d459-6459-4101-a049-8da7d445a3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673918523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.673918523
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1421359740
Short name T154
Test name
Test status
Simulation time 367563657 ps
CPU time 8.53 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 232152 kb
Host smart-bc9d3f59-9cc9-4f36-b5a9-b70b64307f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421359740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1421359740
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1957201497
Short name T442
Test name
Test status
Simulation time 13466294439 ps
CPU time 46.84 seconds
Started Apr 30 12:25:34 PM PDT 24
Finished Apr 30 12:26:22 PM PDT 24
Peak memory 199904 kb
Host smart-7e3d5bef-c301-4687-8bd4-1420e5f724e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957201497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1957201497
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2827879585
Short name T340
Test name
Test status
Simulation time 389928729 ps
CPU time 10.71 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:27:03 PM PDT 24
Peak memory 199088 kb
Host smart-15c1336b-da9a-475d-b19c-c4fa3d523943
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827879585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2827879585
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1741560070
Short name T370
Test name
Test status
Simulation time 19831303 ps
CPU time 0.95 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 197400 kb
Host smart-e1107acc-6627-405c-a9a8-293976d2613a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741560070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1741560070
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1475065559
Short name T600
Test name
Test status
Simulation time 40079575520 ps
CPU time 146.02 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:28:08 PM PDT 24
Peak memory 199468 kb
Host smart-fced769a-faec-4f82-8721-3d7972aacc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475065559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1475065559
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.764004519
Short name T171
Test name
Test status
Simulation time 1614616327 ps
CPU time 5.36 seconds
Started Apr 30 12:27:05 PM PDT 24
Finished Apr 30 12:27:10 PM PDT 24
Peak memory 199316 kb
Host smart-fc9de20b-94d8-4b7b-8e76-8bb1bcec6b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764004519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.764004519
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.282076300
Short name T17
Test name
Test status
Simulation time 116632316647 ps
CPU time 1046.87 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:43:05 PM PDT 24
Peak memory 199720 kb
Host smart-0d5719f6-3b49-42f7-bd5c-a115df22359a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282076300 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.282076300
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1359136625
Short name T591
Test name
Test status
Simulation time 162001299 ps
CPU time 1.1 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:26:53 PM PDT 24
Peak memory 196032 kb
Host smart-a61e2525-a8ff-45cd-99cd-615b844a0e2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359136625 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1359136625
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1487195220
Short name T440
Test name
Test status
Simulation time 108939763820 ps
CPU time 490.92 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:33:51 PM PDT 24
Peak memory 199344 kb
Host smart-6fbc2a4a-401f-4474-b46a-3070e926947d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487195220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1487195220
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3086393182
Short name T539
Test name
Test status
Simulation time 461215276 ps
CPU time 21.3 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:27:13 PM PDT 24
Peak memory 199116 kb
Host smart-3d41f9fc-ccaa-4026-a126-01d00addd6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086393182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3086393182
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2241502871
Short name T555
Test name
Test status
Simulation time 14383073 ps
CPU time 0.57 seconds
Started Apr 30 12:27:05 PM PDT 24
Finished Apr 30 12:27:06 PM PDT 24
Peak memory 193928 kb
Host smart-b3ff449f-3fd0-4a37-aa55-c4d5dde7be13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241502871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2241502871
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1433434202
Short name T344
Test name
Test status
Simulation time 4544149962 ps
CPU time 46.24 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:26:27 PM PDT 24
Peak memory 224064 kb
Host smart-00b1a82b-60b3-4133-aa11-46084facf9ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433434202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1433434202
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3917091468
Short name T569
Test name
Test status
Simulation time 2714766971 ps
CPU time 18.2 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:26:04 PM PDT 24
Peak memory 199456 kb
Host smart-ef8c6fb1-7140-499e-a1af-13751b47e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917091468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3917091468
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2312641757
Short name T526
Test name
Test status
Simulation time 1032713752 ps
CPU time 62.34 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:26:43 PM PDT 24
Peak memory 199440 kb
Host smart-20b45ca8-d889-45ee-8e82-9ee62520cf87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312641757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2312641757
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.335334745
Short name T228
Test name
Test status
Simulation time 256667545357 ps
CPU time 163.26 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:28:29 PM PDT 24
Peak memory 199504 kb
Host smart-4a593925-bc90-4a68-8a73-17c9748605ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335334745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.335334745
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3230686475
Short name T576
Test name
Test status
Simulation time 20165934283 ps
CPU time 120.11 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:27:42 PM PDT 24
Peak memory 199432 kb
Host smart-3a28fc3a-2cfe-417b-b1f9-cf2afbcbb1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230686475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3230686475
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.600087107
Short name T318
Test name
Test status
Simulation time 71479700 ps
CPU time 2.27 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199572 kb
Host smart-e09bb3a9-47cb-4b21-8259-053b0f5c43bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600087107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.600087107
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3820403245
Short name T49
Test name
Test status
Simulation time 259584369605 ps
CPU time 861.43 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:40:01 PM PDT 24
Peak memory 234828 kb
Host smart-d72ef70a-4843-469c-aab1-89b94e8165fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820403245 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3820403245
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1775765629
Short name T546
Test name
Test status
Simulation time 464562718 ps
CPU time 1.37 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:25:43 PM PDT 24
Peak memory 199416 kb
Host smart-e42fc69b-e42c-4e1c-938c-bdcb819cc622
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775765629 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1775765629
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.4171233002
Short name T244
Test name
Test status
Simulation time 31881169518 ps
CPU time 439.27 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:32:59 PM PDT 24
Peak memory 199488 kb
Host smart-861b7ecd-1325-4afa-921f-e715f3e2047e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171233002 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.4171233002
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.243065855
Short name T403
Test name
Test status
Simulation time 14433947716 ps
CPU time 51.89 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:26:38 PM PDT 24
Peak memory 199640 kb
Host smart-c5d3c033-e6b0-47d1-b339-f7c1b8bf535f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243065855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.243065855
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2629767721
Short name T215
Test name
Test status
Simulation time 13442148 ps
CPU time 0.59 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:25:47 PM PDT 24
Peak memory 194884 kb
Host smart-10c21432-d3f7-406d-9618-2b4673eb51d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629767721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2629767721
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3479248299
Short name T567
Test name
Test status
Simulation time 4911004453 ps
CPU time 45.9 seconds
Started Apr 30 12:25:42 PM PDT 24
Finished Apr 30 12:26:28 PM PDT 24
Peak memory 230496 kb
Host smart-3afb09c1-c10b-41c6-ba1e-c180d53fc542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479248299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3479248299
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2738790956
Short name T139
Test name
Test status
Simulation time 4773211234 ps
CPU time 55.67 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:26:42 PM PDT 24
Peak memory 199588 kb
Host smart-f87221b0-a145-4c89-972a-356a56c2ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738790956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2738790956
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3629807491
Short name T384
Test name
Test status
Simulation time 3604073591 ps
CPU time 49.88 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:27:42 PM PDT 24
Peak memory 197032 kb
Host smart-65da5485-f913-474e-b3a1-052b83995a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629807491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3629807491
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3430071117
Short name T245
Test name
Test status
Simulation time 5062986388 ps
CPU time 22.22 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:27:14 PM PDT 24
Peak memory 197944 kb
Host smart-199ab51c-1a64-4dcf-a4ea-91605f2bc23c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430071117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3430071117
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3133674888
Short name T290
Test name
Test status
Simulation time 3721012121 ps
CPU time 67.48 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:27:59 PM PDT 24
Peak memory 196620 kb
Host smart-40d35e0b-4f76-481b-89e9-6d6002f07c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133674888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3133674888
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2120382204
Short name T477
Test name
Test status
Simulation time 291857775 ps
CPU time 2.08 seconds
Started Apr 30 12:25:35 PM PDT 24
Finished Apr 30 12:25:38 PM PDT 24
Peak memory 199496 kb
Host smart-94e41a79-a703-471d-a04d-774799beec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120382204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2120382204
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2151566105
Short name T54
Test name
Test status
Simulation time 54136703342 ps
CPU time 702.17 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:37:23 PM PDT 24
Peak memory 238460 kb
Host smart-c39484dc-abe3-4959-b0a5-7d2d84219efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151566105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2151566105
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2464463278
Short name T449
Test name
Test status
Simulation time 106393254 ps
CPU time 1.01 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:26:53 PM PDT 24
Peak memory 198720 kb
Host smart-20afab9b-b1eb-49f9-87c7-a7ff49e8cefb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464463278 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2464463278
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3064923160
Short name T345
Test name
Test status
Simulation time 31870287148 ps
CPU time 467.34 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:33:29 PM PDT 24
Peak memory 199388 kb
Host smart-c1543af4-6140-4c90-a8f3-52d05381f83d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064923160 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3064923160
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2191504546
Short name T323
Test name
Test status
Simulation time 901759973 ps
CPU time 44.21 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:26:22 PM PDT 24
Peak memory 199472 kb
Host smart-f031b7ed-40d6-4bd6-8701-8d186ef7e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191504546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2191504546
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1685152775
Short name T342
Test name
Test status
Simulation time 22841894 ps
CPU time 0.55 seconds
Started Apr 30 12:25:56 PM PDT 24
Finished Apr 30 12:25:57 PM PDT 24
Peak memory 194592 kb
Host smart-d87499dd-85f2-44bb-b393-33c4625a43e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685152775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1685152775
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3191595489
Short name T266
Test name
Test status
Simulation time 4397027607 ps
CPU time 39.87 seconds
Started Apr 30 12:24:06 PM PDT 24
Finished Apr 30 12:24:47 PM PDT 24
Peak memory 224152 kb
Host smart-07e07262-c898-488c-b71b-c6420cce0e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191595489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3191595489
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1803266650
Short name T347
Test name
Test status
Simulation time 3078762509 ps
CPU time 22.38 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:24:50 PM PDT 24
Peak memory 199532 kb
Host smart-2fd0d222-3aad-42dd-a9d3-8cbb513e1d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803266650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1803266650
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2165716428
Short name T583
Test name
Test status
Simulation time 827662588 ps
CPU time 35.08 seconds
Started Apr 30 12:24:08 PM PDT 24
Finished Apr 30 12:24:44 PM PDT 24
Peak memory 199472 kb
Host smart-a54406cc-eb5b-4ada-b5c5-96fdb292d3ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165716428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2165716428
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.905265243
Short name T151
Test name
Test status
Simulation time 4597686384 ps
CPU time 59.07 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199468 kb
Host smart-285e1718-38a2-4ec6-b10f-a8a5946c6616
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905265243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.905265243
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.958065409
Short name T383
Test name
Test status
Simulation time 2277993582 ps
CPU time 61.4 seconds
Started Apr 30 12:24:36 PM PDT 24
Finished Apr 30 12:25:38 PM PDT 24
Peak memory 199496 kb
Host smart-b24b306d-4b8a-4cfc-919b-28c3acd5c5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958065409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.958065409
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3852756397
Short name T31
Test name
Test status
Simulation time 200582636 ps
CPU time 1.05 seconds
Started Apr 30 12:24:36 PM PDT 24
Finished Apr 30 12:24:38 PM PDT 24
Peak memory 218604 kb
Host smart-9a7029c4-a09c-435e-8fe8-334d110b48d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852756397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3852756397
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1149049095
Short name T198
Test name
Test status
Simulation time 391564385 ps
CPU time 2.91 seconds
Started Apr 30 12:19:57 PM PDT 24
Finished Apr 30 12:20:01 PM PDT 24
Peak memory 199856 kb
Host smart-a46775bb-a60b-465d-b167-6d41576a3ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149049095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1149049095
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.63770137
Short name T261
Test name
Test status
Simulation time 5212980828 ps
CPU time 139.78 seconds
Started Apr 30 12:24:11 PM PDT 24
Finished Apr 30 12:26:31 PM PDT 24
Peak memory 199504 kb
Host smart-fe3573b3-fdf5-429e-9cea-0967c375537c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63770137 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.63770137
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1682913179
Short name T376
Test name
Test status
Simulation time 143433964 ps
CPU time 1.14 seconds
Started Apr 30 12:24:08 PM PDT 24
Finished Apr 30 12:24:10 PM PDT 24
Peak memory 199436 kb
Host smart-d1d62376-7aa7-4249-ab57-19bf3b985cd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682913179 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1682913179
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1150593886
Short name T530
Test name
Test status
Simulation time 166288566413 ps
CPU time 471.56 seconds
Started Apr 30 12:24:10 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 199424 kb
Host smart-9bad4c55-4bca-4732-96a8-6f76d09e5b75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150593886 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.1150593886
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2778508556
Short name T560
Test name
Test status
Simulation time 3453846711 ps
CPU time 32.5 seconds
Started Apr 30 12:24:08 PM PDT 24
Finished Apr 30 12:24:42 PM PDT 24
Peak memory 199532 kb
Host smart-bc7aa19b-9293-42c5-a800-cb5982ae1205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778508556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2778508556
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1180422996
Short name T585
Test name
Test status
Simulation time 17743963 ps
CPU time 0.57 seconds
Started Apr 30 12:25:42 PM PDT 24
Finished Apr 30 12:25:43 PM PDT 24
Peak memory 194080 kb
Host smart-6ca314fc-4687-4dc1-b0ec-5fe87a475dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180422996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1180422996
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.419508670
Short name T577
Test name
Test status
Simulation time 2346264778 ps
CPU time 44.9 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:26:23 PM PDT 24
Peak memory 219008 kb
Host smart-53d1d364-9536-424b-b862-79fe1bb091ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419508670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.419508670
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3535702082
Short name T218
Test name
Test status
Simulation time 2600654131 ps
CPU time 29.46 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:26:09 PM PDT 24
Peak memory 199716 kb
Host smart-0ba58a75-ca75-49fa-a927-ec1294a31de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535702082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3535702082
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3718243350
Short name T461
Test name
Test status
Simulation time 1194752363 ps
CPU time 71.63 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:26:52 PM PDT 24
Peak memory 199472 kb
Host smart-1b03fab5-4867-427e-927e-61e4f1192d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718243350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3718243350
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1675278991
Short name T143
Test name
Test status
Simulation time 5232169760 ps
CPU time 222.84 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:29:23 PM PDT 24
Peak memory 199428 kb
Host smart-dd3daeb2-290b-4695-9ae2-3aa4b667f973
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675278991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1675278991
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.826383206
Short name T118
Test name
Test status
Simulation time 5219081867 ps
CPU time 45.94 seconds
Started Apr 30 12:25:45 PM PDT 24
Finished Apr 30 12:26:31 PM PDT 24
Peak memory 199612 kb
Host smart-7b8bc641-30bb-488f-9a60-eb8228fed0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826383206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.826383206
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2125262398
Short name T458
Test name
Test status
Simulation time 116218884 ps
CPU time 1.74 seconds
Started Apr 30 12:25:37 PM PDT 24
Finished Apr 30 12:25:40 PM PDT 24
Peak memory 199484 kb
Host smart-202cbc8f-5818-4e0e-9b90-5e21cefaa4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125262398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2125262398
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1029931484
Short name T296
Test name
Test status
Simulation time 119763885239 ps
CPU time 1510.63 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:50:52 PM PDT 24
Peak memory 230456 kb
Host smart-19abc9f5-833f-4c47-9937-9113455fce73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029931484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1029931484
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.26166086
Short name T398
Test name
Test status
Simulation time 363172391 ps
CPU time 1.36 seconds
Started Apr 30 12:25:36 PM PDT 24
Finished Apr 30 12:25:39 PM PDT 24
Peak memory 199512 kb
Host smart-b6c6979d-a911-45d1-8e51-76a923414637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26166086 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.hmac_test_hmac_vectors.26166086
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.485287624
Short name T165
Test name
Test status
Simulation time 34550142487 ps
CPU time 450.16 seconds
Started Apr 30 12:25:49 PM PDT 24
Finished Apr 30 12:33:20 PM PDT 24
Peak memory 199392 kb
Host smart-a399c8c0-4f7d-4e97-a3c8-777f107540d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485287624 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.485287624
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2158842932
Short name T303
Test name
Test status
Simulation time 1461072592 ps
CPU time 45.6 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:26:32 PM PDT 24
Peak memory 199400 kb
Host smart-13cafa5d-f10f-465c-89b8-d2b413186cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158842932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2158842932
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3542261425
Short name T23
Test name
Test status
Simulation time 12309976 ps
CPU time 0.58 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:25:42 PM PDT 24
Peak memory 194064 kb
Host smart-08acca9f-652f-4a6a-96ec-d84749013816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542261425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3542261425
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.693444407
Short name T196
Test name
Test status
Simulation time 541336651 ps
CPU time 20.69 seconds
Started Apr 30 12:25:42 PM PDT 24
Finished Apr 30 12:26:03 PM PDT 24
Peak memory 199440 kb
Host smart-5516f151-0a6c-4ce6-8eed-f20f762779c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693444407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.693444407
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2746517601
Short name T393
Test name
Test status
Simulation time 15024066434 ps
CPU time 29.45 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:26:09 PM PDT 24
Peak memory 199540 kb
Host smart-32873cc8-c127-4d6a-9aaf-a07aefe1e148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746517601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2746517601
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1946004855
Short name T332
Test name
Test status
Simulation time 10663328038 ps
CPU time 135.05 seconds
Started Apr 30 12:26:51 PM PDT 24
Finished Apr 30 12:29:07 PM PDT 24
Peak memory 196916 kb
Host smart-24f8ef8d-aca7-493c-9f1e-878019d8d87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946004855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1946004855
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2729285886
Short name T464
Test name
Test status
Simulation time 8557122339 ps
CPU time 112.04 seconds
Started Apr 30 12:25:43 PM PDT 24
Finished Apr 30 12:27:35 PM PDT 24
Peak memory 199516 kb
Host smart-6fca52af-eeae-4242-bc51-b4fcef89fb29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729285886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2729285886
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.205042058
Short name T279
Test name
Test status
Simulation time 5160364041 ps
CPU time 95.72 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:27:18 PM PDT 24
Peak memory 199524 kb
Host smart-e9fcef77-1ef2-451f-9cc7-9490f5942bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205042058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.205042058
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.50502513
Short name T448
Test name
Test status
Simulation time 73729764 ps
CPU time 1.37 seconds
Started Apr 30 12:25:42 PM PDT 24
Finished Apr 30 12:25:44 PM PDT 24
Peak memory 199344 kb
Host smart-c9804427-f964-4713-8e63-f9b8904f44f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50502513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.50502513
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1857100774
Short name T178
Test name
Test status
Simulation time 10305275634 ps
CPU time 111.12 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:27:33 PM PDT 24
Peak memory 207712 kb
Host smart-ada8ba6b-17e4-4de5-8b11-a9504327e451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857100774 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1857100774
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.347932923
Short name T478
Test name
Test status
Simulation time 187005327 ps
CPU time 1.19 seconds
Started Apr 30 12:25:42 PM PDT 24
Finished Apr 30 12:25:44 PM PDT 24
Peak memory 199388 kb
Host smart-9c351100-c82a-4b15-ad27-47c064c6ff79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347932923 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.347932923
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3803814825
Short name T82
Test name
Test status
Simulation time 41297209198 ps
CPU time 380.74 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 199456 kb
Host smart-3d3a9cee-f140-472d-a824-de310255ad3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803814825 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3803814825
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3643602025
Short name T432
Test name
Test status
Simulation time 133452783 ps
CPU time 3.67 seconds
Started Apr 30 12:25:41 PM PDT 24
Finished Apr 30 12:25:46 PM PDT 24
Peak memory 199432 kb
Host smart-2a249ace-fd58-4f85-8056-f73b1954c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643602025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3643602025
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.91888698
Short name T200
Test name
Test status
Simulation time 32990431 ps
CPU time 0.56 seconds
Started Apr 30 12:25:43 PM PDT 24
Finished Apr 30 12:25:44 PM PDT 24
Peak memory 195092 kb
Host smart-3e052a3e-b3a4-47d5-8cb5-71b91f4cb67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91888698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.91888698
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.276591755
Short name T517
Test name
Test status
Simulation time 619392152 ps
CPU time 11.49 seconds
Started Apr 30 12:25:47 PM PDT 24
Finished Apr 30 12:26:00 PM PDT 24
Peak memory 215756 kb
Host smart-b325687f-0b2f-43b8-a9c5-dc087f06f6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276591755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.276591755
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3881435002
Short name T192
Test name
Test status
Simulation time 145904616 ps
CPU time 7.14 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199476 kb
Host smart-d7e6ade9-2e56-4025-ae9f-a929b164ede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881435002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3881435002
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2318250314
Short name T5
Test name
Test status
Simulation time 13988487660 ps
CPU time 109.26 seconds
Started Apr 30 12:25:39 PM PDT 24
Finished Apr 30 12:27:29 PM PDT 24
Peak memory 199492 kb
Host smart-33454a03-f509-41b8-a512-fb0dc49f6051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318250314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2318250314
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2578364744
Short name T185
Test name
Test status
Simulation time 2372272418 ps
CPU time 46.73 seconds
Started Apr 30 12:25:44 PM PDT 24
Finished Apr 30 12:26:31 PM PDT 24
Peak memory 199536 kb
Host smart-c82a5d66-0cb4-4868-afa0-4bec1f1b9bc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578364744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2578364744
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3167986992
Short name T311
Test name
Test status
Simulation time 1494448275 ps
CPU time 85.35 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:27:12 PM PDT 24
Peak memory 199436 kb
Host smart-d6355732-e920-4c5d-9fa2-8368a98b876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167986992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3167986992
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1469637931
Short name T242
Test name
Test status
Simulation time 469166652 ps
CPU time 5.66 seconds
Started Apr 30 12:25:43 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 199452 kb
Host smart-f74a250a-3db5-438c-af23-dd12cc9f7ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469637931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1469637931
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3151357059
Short name T547
Test name
Test status
Simulation time 18099838827 ps
CPU time 947.26 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:41:28 PM PDT 24
Peak memory 207804 kb
Host smart-c74972b3-7fce-4418-93e9-be162886c07a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151357059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3151357059
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2258030820
Short name T43
Test name
Test status
Simulation time 26533299 ps
CPU time 0.97 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:25:42 PM PDT 24
Peak memory 198288 kb
Host smart-efbd8e2c-dd81-4ad2-9099-29cb9fe09335
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258030820 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2258030820
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.922018313
Short name T88
Test name
Test status
Simulation time 28727724913 ps
CPU time 441.18 seconds
Started Apr 30 12:25:42 PM PDT 24
Finished Apr 30 12:33:04 PM PDT 24
Peak memory 199396 kb
Host smart-816a1b16-1e54-4fb6-b766-f720fee9ab03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922018313 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.922018313
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2950602246
Short name T417
Test name
Test status
Simulation time 6919968492 ps
CPU time 25.27 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:26:12 PM PDT 24
Peak memory 199508 kb
Host smart-bf431f9f-c6f8-4dc5-adff-fd084f9a470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950602246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2950602246
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.88187821
Short name T470
Test name
Test status
Simulation time 13486599 ps
CPU time 0.57 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 195072 kb
Host smart-6b387731-a64d-4516-a180-f9442b84cc66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88187821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.88187821
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1482638415
Short name T568
Test name
Test status
Simulation time 391322657 ps
CPU time 15.96 seconds
Started Apr 30 12:25:42 PM PDT 24
Finished Apr 30 12:25:59 PM PDT 24
Peak memory 228080 kb
Host smart-ae9d4d7d-cd49-49d7-901d-0f9c22c9de8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482638415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1482638415
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1369271585
Short name T295
Test name
Test status
Simulation time 1099643835 ps
CPU time 53.31 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:26:34 PM PDT 24
Peak memory 199536 kb
Host smart-b01843e5-fef9-4c04-b34e-5de759dfdf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369271585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1369271585
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3358964548
Short name T206
Test name
Test status
Simulation time 9149896590 ps
CPU time 136.35 seconds
Started Apr 30 12:25:47 PM PDT 24
Finished Apr 30 12:28:04 PM PDT 24
Peak memory 199472 kb
Host smart-d0b21f8d-1439-4540-a019-faa858acbc1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358964548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3358964548
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1833340762
Short name T241
Test name
Test status
Simulation time 8526405015 ps
CPU time 114.81 seconds
Started Apr 30 12:25:38 PM PDT 24
Finished Apr 30 12:27:34 PM PDT 24
Peak memory 199508 kb
Host smart-f359997b-36d4-4bf7-8134-38f59c4c4bb8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833340762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1833340762
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.382878371
Short name T172
Test name
Test status
Simulation time 135462187 ps
CPU time 7.64 seconds
Started Apr 30 12:25:40 PM PDT 24
Finished Apr 30 12:25:48 PM PDT 24
Peak memory 199504 kb
Host smart-d7204e0c-9e5c-45c8-9572-d1c823033d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382878371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.382878371
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2679489023
Short name T217
Test name
Test status
Simulation time 1502076427 ps
CPU time 5.73 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:25:55 PM PDT 24
Peak memory 199424 kb
Host smart-06605dcb-4755-45d7-8786-153bc28e3997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679489023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2679489023
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4120698255
Short name T253
Test name
Test status
Simulation time 3081220768 ps
CPU time 156.44 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:28:25 PM PDT 24
Peak memory 199464 kb
Host smart-f7c3d45b-5864-49c2-b802-827d60f3d915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120698255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4120698255
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2650418339
Short name T498
Test name
Test status
Simulation time 145101046 ps
CPU time 1.35 seconds
Started Apr 30 12:25:53 PM PDT 24
Finished Apr 30 12:25:55 PM PDT 24
Peak memory 199192 kb
Host smart-8d5398db-d924-41e1-b3a3-8c9db84450ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650418339 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2650418339
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1542736242
Short name T514
Test name
Test status
Simulation time 29566990292 ps
CPU time 516.04 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 199412 kb
Host smart-3f6dd764-3b11-490c-b35b-1a92f2712efd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542736242 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1542736242
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1567613578
Short name T549
Test name
Test status
Simulation time 2188583323 ps
CPU time 26.62 seconds
Started Apr 30 12:25:44 PM PDT 24
Finished Apr 30 12:26:11 PM PDT 24
Peak memory 199476 kb
Host smart-3a62a608-10e6-46f4-99e2-8a6413aba25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567613578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1567613578
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3320743129
Short name T441
Test name
Test status
Simulation time 43686307 ps
CPU time 0.56 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:25:51 PM PDT 24
Peak memory 193984 kb
Host smart-79572c00-69e7-442b-8aa9-c619326dca10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320743129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3320743129
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2051278380
Short name T53
Test name
Test status
Simulation time 2256539840 ps
CPU time 43.47 seconds
Started Apr 30 12:25:55 PM PDT 24
Finished Apr 30 12:26:39 PM PDT 24
Peak memory 224252 kb
Host smart-7b6097f6-9c80-4073-878e-e84d881d308b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051278380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2051278380
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.958160819
Short name T462
Test name
Test status
Simulation time 4646362397 ps
CPU time 44.99 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:26:32 PM PDT 24
Peak memory 199548 kb
Host smart-680fa835-ec18-4d6c-8954-6d7e83c83951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958160819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.958160819
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3011057707
Short name T349
Test name
Test status
Simulation time 5659714600 ps
CPU time 164.16 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:28:31 PM PDT 24
Peak memory 199656 kb
Host smart-55f52438-0543-4d9a-b2d6-3593b2441aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011057707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3011057707
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2503537242
Short name T425
Test name
Test status
Simulation time 2081762688 ps
CPU time 116.4 seconds
Started Apr 30 12:25:47 PM PDT 24
Finished Apr 30 12:27:49 PM PDT 24
Peak memory 199856 kb
Host smart-a3adfc09-9847-4714-862e-b3dae9db0d7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503537242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2503537242
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4146236277
Short name T395
Test name
Test status
Simulation time 18510585250 ps
CPU time 119.33 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:27:48 PM PDT 24
Peak memory 199496 kb
Host smart-de9b5f32-a22c-4ce4-8895-c58b6d007680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146236277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4146236277
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2470404035
Short name T480
Test name
Test status
Simulation time 1216125358 ps
CPU time 3.87 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:25:53 PM PDT 24
Peak memory 199404 kb
Host smart-bdbcda2e-f740-4fb7-9cb1-39e4c7d1a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470404035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2470404035
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2999174025
Short name T67
Test name
Test status
Simulation time 45044788326 ps
CPU time 220.5 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:29:31 PM PDT 24
Peak memory 228056 kb
Host smart-c2b27978-b65d-46d6-b594-2b56fb20c914
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999174025 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2999174025
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1361822898
Short name T496
Test name
Test status
Simulation time 59485325 ps
CPU time 1.26 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 199620 kb
Host smart-bb9c051c-fd3f-411e-81c2-8ce861d5b39e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361822898 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1361822898
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.659345216
Short name T83
Test name
Test status
Simulation time 355059713289 ps
CPU time 497.3 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 199448 kb
Host smart-67abf60c-fce5-4673-a05b-d56afbecd79a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659345216 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.659345216
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4232021266
Short name T129
Test name
Test status
Simulation time 5560380596 ps
CPU time 24.5 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:26:15 PM PDT 24
Peak memory 199536 kb
Host smart-6fba0064-dc9d-4a3a-858a-e63254748987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232021266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4232021266
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2930305440
Short name T291
Test name
Test status
Simulation time 32903809 ps
CPU time 0.59 seconds
Started Apr 30 12:25:51 PM PDT 24
Finished Apr 30 12:25:52 PM PDT 24
Peak memory 193984 kb
Host smart-cba0ed36-6ca8-4b9c-be9f-9df2d4aad336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930305440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2930305440
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3692748312
Short name T224
Test name
Test status
Simulation time 16366987719 ps
CPU time 58.11 seconds
Started Apr 30 12:25:56 PM PDT 24
Finished Apr 30 12:26:55 PM PDT 24
Peak memory 199424 kb
Host smart-1cf62d47-3538-4770-9995-05b9eec2a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692748312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3692748312
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2147799278
Short name T401
Test name
Test status
Simulation time 16206943501 ps
CPU time 120.39 seconds
Started Apr 30 12:25:59 PM PDT 24
Finished Apr 30 12:28:05 PM PDT 24
Peak memory 199564 kb
Host smart-03457951-9972-4def-b67b-cd80d86b495b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2147799278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2147799278
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.553110215
Short name T27
Test name
Test status
Simulation time 8755802283 ps
CPU time 113.54 seconds
Started Apr 30 12:25:49 PM PDT 24
Finished Apr 30 12:27:43 PM PDT 24
Peak memory 199560 kb
Host smart-ba7d7375-fe2e-4b2e-96b0-62dbeb499b0d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553110215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.553110215
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3958015037
Short name T36
Test name
Test status
Simulation time 33054603983 ps
CPU time 99.47 seconds
Started Apr 30 12:25:52 PM PDT 24
Finished Apr 30 12:27:32 PM PDT 24
Peak memory 199496 kb
Host smart-5989430d-4777-432d-920e-fee36f234b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958015037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3958015037
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.769867014
Short name T524
Test name
Test status
Simulation time 771079158 ps
CPU time 3.11 seconds
Started Apr 30 12:25:56 PM PDT 24
Finished Apr 30 12:26:00 PM PDT 24
Peak memory 199332 kb
Host smart-f78525f7-fcd3-4da0-be27-21167ec5eb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769867014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.769867014
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.735576426
Short name T385
Test name
Test status
Simulation time 103246154203 ps
CPU time 1349.68 seconds
Started Apr 30 12:26:03 PM PDT 24
Finished Apr 30 12:48:34 PM PDT 24
Peak memory 239832 kb
Host smart-ff003df7-2d43-477b-ba01-101438f5b7e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735576426 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.735576426
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2373495691
Short name T84
Test name
Test status
Simulation time 386833500 ps
CPU time 1.14 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 199300 kb
Host smart-6bf45c29-6473-4880-8c9b-5965cfa085bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373495691 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2373495691
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.81711552
Short name T445
Test name
Test status
Simulation time 180872170143 ps
CPU time 467.19 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 199440 kb
Host smart-360faa94-c52d-4db1-a324-eadfc0657fbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81711552 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.81711552
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3781579040
Short name T578
Test name
Test status
Simulation time 344587489 ps
CPU time 5 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:25:56 PM PDT 24
Peak memory 199528 kb
Host smart-eacb81c0-d61c-481a-adbf-a8594f267a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781579040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3781579040
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.4157598812
Short name T155
Test name
Test status
Simulation time 48749606 ps
CPU time 0.58 seconds
Started Apr 30 12:25:52 PM PDT 24
Finished Apr 30 12:25:53 PM PDT 24
Peak memory 195132 kb
Host smart-2374ca39-17cf-4a37-89e1-82840f1eb252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157598812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.4157598812
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.57369911
Short name T306
Test name
Test status
Simulation time 10766990687 ps
CPU time 35.12 seconds
Started Apr 30 12:25:53 PM PDT 24
Finished Apr 30 12:26:29 PM PDT 24
Peak memory 215868 kb
Host smart-9ac4b73b-35bf-4655-aef7-05807db16423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57369911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.57369911
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4282892949
Short name T113
Test name
Test status
Simulation time 9279781538 ps
CPU time 43.8 seconds
Started Apr 30 12:26:00 PM PDT 24
Finished Apr 30 12:26:45 PM PDT 24
Peak memory 199412 kb
Host smart-a9c6c54a-1f8c-4ebc-8a76-9f7d504a1cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282892949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4282892949
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1825112253
Short name T262
Test name
Test status
Simulation time 1322513525 ps
CPU time 38.45 seconds
Started Apr 30 12:25:49 PM PDT 24
Finished Apr 30 12:26:29 PM PDT 24
Peak memory 199516 kb
Host smart-a83aa3b6-b3e4-419d-a9e1-20f96945d4bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825112253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1825112253
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2248443703
Short name T214
Test name
Test status
Simulation time 119864304247 ps
CPU time 123.98 seconds
Started Apr 30 12:25:54 PM PDT 24
Finished Apr 30 12:27:58 PM PDT 24
Peak memory 199536 kb
Host smart-93313b76-edbe-477c-b478-b0ffacf29616
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248443703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2248443703
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1769831425
Short name T487
Test name
Test status
Simulation time 4684012064 ps
CPU time 85.54 seconds
Started Apr 30 12:26:21 PM PDT 24
Finished Apr 30 12:27:47 PM PDT 24
Peak memory 199396 kb
Host smart-677f6cb4-9a9e-49ac-9cc4-b87266e10c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769831425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1769831425
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3359624632
Short name T399
Test name
Test status
Simulation time 399650535 ps
CPU time 6.53 seconds
Started Apr 30 12:26:09 PM PDT 24
Finished Apr 30 12:26:16 PM PDT 24
Peak memory 199416 kb
Host smart-4360934c-304c-44a6-830c-c452b5b9078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359624632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3359624632
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3869400795
Short name T333
Test name
Test status
Simulation time 5789957181 ps
CPU time 135.43 seconds
Started Apr 30 12:25:57 PM PDT 24
Finished Apr 30 12:28:13 PM PDT 24
Peak memory 240508 kb
Host smart-225a45a8-9137-43dc-a567-348b52a89444
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869400795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3869400795
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3384920729
Short name T603
Test name
Test status
Simulation time 64680933 ps
CPU time 1.24 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:25:50 PM PDT 24
Peak memory 199368 kb
Host smart-a9adcd92-45d4-4ea2-bc9c-f96d43c68dff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384920729 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3384920729
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2162847195
Short name T423
Test name
Test status
Simulation time 27245331958 ps
CPU time 454.48 seconds
Started Apr 30 12:26:23 PM PDT 24
Finished Apr 30 12:33:59 PM PDT 24
Peak memory 199352 kb
Host smart-7662ac14-2a8f-4f4f-b976-450fab51fa7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162847195 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2162847195
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1464052360
Short name T148
Test name
Test status
Simulation time 2047046152 ps
CPU time 25.51 seconds
Started Apr 30 12:26:04 PM PDT 24
Finished Apr 30 12:26:30 PM PDT 24
Peak memory 199440 kb
Host smart-6baf8502-6e36-41de-8714-0d9afebb970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464052360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1464052360
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3798954543
Short name T408
Test name
Test status
Simulation time 13232670 ps
CPU time 0.6 seconds
Started Apr 30 12:25:54 PM PDT 24
Finished Apr 30 12:25:55 PM PDT 24
Peak memory 195160 kb
Host smart-8096d6bf-c140-4eb6-b8cd-0521b6506538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798954543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3798954543
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1157888597
Short name T366
Test name
Test status
Simulation time 5130435706 ps
CPU time 43.02 seconds
Started Apr 30 12:26:11 PM PDT 24
Finished Apr 30 12:26:55 PM PDT 24
Peak memory 230476 kb
Host smart-8bf00ae3-ca7e-4154-8d26-23c4ba29409e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157888597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1157888597
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4023575288
Short name T586
Test name
Test status
Simulation time 1288166982 ps
CPU time 13.91 seconds
Started Apr 30 12:26:18 PM PDT 24
Finished Apr 30 12:26:33 PM PDT 24
Peak memory 199436 kb
Host smart-2b53bd3b-6bfb-4c7e-ae7f-82fa4a36e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023575288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4023575288
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3802963604
Short name T382
Test name
Test status
Simulation time 447175760 ps
CPU time 26.22 seconds
Started Apr 30 12:26:17 PM PDT 24
Finished Apr 30 12:26:44 PM PDT 24
Peak memory 199448 kb
Host smart-be1e1996-3fd9-4776-adfc-fb1bc3759c39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802963604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3802963604
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1649821583
Short name T505
Test name
Test status
Simulation time 3457254561 ps
CPU time 183.95 seconds
Started Apr 30 12:25:49 PM PDT 24
Finished Apr 30 12:28:54 PM PDT 24
Peak memory 199648 kb
Host smart-8b268c32-5eea-46df-a7d6-44c5243d279c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649821583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1649821583
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3529729569
Short name T537
Test name
Test status
Simulation time 5769034439 ps
CPU time 50.35 seconds
Started Apr 30 12:26:14 PM PDT 24
Finished Apr 30 12:27:05 PM PDT 24
Peak memory 199436 kb
Host smart-a98766d6-40e3-4fb4-83c2-20bc739ec3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529729569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3529729569
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3418947682
Short name T605
Test name
Test status
Simulation time 124469254 ps
CPU time 2.18 seconds
Started Apr 30 12:25:52 PM PDT 24
Finished Apr 30 12:25:55 PM PDT 24
Peak memory 199440 kb
Host smart-e64b195c-3926-4fa1-90a6-7fb5c0a7d34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418947682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3418947682
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3927848517
Short name T572
Test name
Test status
Simulation time 1356839255218 ps
CPU time 1528.99 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:51:20 PM PDT 24
Peak memory 247744 kb
Host smart-cf7c2a99-2181-4cfe-85fb-885a8d8dfe84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927848517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3927848517
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.396809589
Short name T405
Test name
Test status
Simulation time 145458789 ps
CPU time 1.03 seconds
Started Apr 30 12:25:51 PM PDT 24
Finished Apr 30 12:25:52 PM PDT 24
Peak memory 198892 kb
Host smart-0c2124aa-2293-42e4-90ba-8cd950c418d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396809589 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.396809589
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1081920724
Short name T485
Test name
Test status
Simulation time 83958597002 ps
CPU time 502.27 seconds
Started Apr 30 12:25:58 PM PDT 24
Finished Apr 30 12:34:21 PM PDT 24
Peak memory 199476 kb
Host smart-bd633425-7b8e-4d5f-bbe5-92fc082e5141
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081920724 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1081920724
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3513405306
Short name T272
Test name
Test status
Simulation time 11524511247 ps
CPU time 89.06 seconds
Started Apr 30 12:25:58 PM PDT 24
Finished Apr 30 12:27:27 PM PDT 24
Peak memory 199516 kb
Host smart-12c01f34-53c1-42c2-853f-09a92de921ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513405306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3513405306
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2069474596
Short name T581
Test name
Test status
Simulation time 47664246 ps
CPU time 0.58 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:25:51 PM PDT 24
Peak memory 194812 kb
Host smart-78861b3f-01d2-45ea-a6d4-f738535fb835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069474596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2069474596
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3257588112
Short name T232
Test name
Test status
Simulation time 1087324262 ps
CPU time 18.63 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:26:05 PM PDT 24
Peak memory 215344 kb
Host smart-be628e08-13ca-4d57-944e-7a1c4b23dce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257588112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3257588112
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2323197128
Short name T439
Test name
Test status
Simulation time 3278246091 ps
CPU time 36.78 seconds
Started Apr 30 12:25:48 PM PDT 24
Finished Apr 30 12:26:25 PM PDT 24
Peak memory 199500 kb
Host smart-cf8662a3-de69-4239-a724-dff3f39628ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323197128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2323197128
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.765944208
Short name T147
Test name
Test status
Simulation time 2665338249 ps
CPU time 69.28 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:26:56 PM PDT 24
Peak memory 199532 kb
Host smart-d807394f-e4c5-4a92-b454-1afc28fa9076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765944208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.765944208
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.285096866
Short name T239
Test name
Test status
Simulation time 45536805816 ps
CPU time 113.17 seconds
Started Apr 30 12:25:49 PM PDT 24
Finished Apr 30 12:27:43 PM PDT 24
Peak memory 199448 kb
Host smart-3e1e415f-42b0-4cd4-80d1-494af0aa5882
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285096866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.285096866
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2689264163
Short name T406
Test name
Test status
Simulation time 4078809296 ps
CPU time 56.58 seconds
Started Apr 30 12:25:47 PM PDT 24
Finished Apr 30 12:26:49 PM PDT 24
Peak memory 199544 kb
Host smart-22d87888-5135-4105-873b-31c8f90cde53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689264163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2689264163
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1637196590
Short name T474
Test name
Test status
Simulation time 359273706 ps
CPU time 4.05 seconds
Started Apr 30 12:25:46 PM PDT 24
Finished Apr 30 12:25:51 PM PDT 24
Peak memory 199452 kb
Host smart-1d54923a-dbc0-4c50-a619-9818f24db3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637196590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1637196590
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1901309796
Short name T153
Test name
Test status
Simulation time 365484709658 ps
CPU time 833.04 seconds
Started Apr 30 12:25:51 PM PDT 24
Finished Apr 30 12:39:45 PM PDT 24
Peak memory 235248 kb
Host smart-fff63c8e-1f4b-4337-b031-070898d7ad11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901309796 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1901309796
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.804378219
Short name T482
Test name
Test status
Simulation time 61857198 ps
CPU time 1.35 seconds
Started Apr 30 12:25:52 PM PDT 24
Finished Apr 30 12:25:54 PM PDT 24
Peak memory 199452 kb
Host smart-7f617b18-023c-4098-8be4-4fd004a17d9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804378219 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.804378219
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.4102772411
Short name T119
Test name
Test status
Simulation time 159163982689 ps
CPU time 497.42 seconds
Started Apr 30 12:25:50 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 199476 kb
Host smart-eaed04e9-2747-4bae-9a0e-8c01fc8c9318
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102772411 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.4102772411
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2379644697
Short name T353
Test name
Test status
Simulation time 1132158437 ps
CPU time 35.62 seconds
Started Apr 30 12:26:06 PM PDT 24
Finished Apr 30 12:26:43 PM PDT 24
Peak memory 199452 kb
Host smart-09c08c51-fcd8-4535-8af1-8764fa6386a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379644697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2379644697
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3593828851
Short name T22
Test name
Test status
Simulation time 115584677 ps
CPU time 0.58 seconds
Started Apr 30 12:26:05 PM PDT 24
Finished Apr 30 12:26:06 PM PDT 24
Peak memory 195144 kb
Host smart-18a564fc-481b-4421-ad1a-823b37a6fe7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593828851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3593828851
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4056868319
Short name T156
Test name
Test status
Simulation time 932267758 ps
CPU time 30.02 seconds
Started Apr 30 12:25:49 PM PDT 24
Finished Apr 30 12:26:20 PM PDT 24
Peak memory 207704 kb
Host smart-dc012353-8db6-4ef6-8b39-4ddffa316872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056868319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4056868319
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1287772568
Short name T430
Test name
Test status
Simulation time 1197878551 ps
CPU time 9.61 seconds
Started Apr 30 12:26:08 PM PDT 24
Finished Apr 30 12:26:19 PM PDT 24
Peak memory 199448 kb
Host smart-b5bdfacf-8c48-4d21-8ab3-5c99b2cb18f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287772568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1287772568
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1407217786
Short name T314
Test name
Test status
Simulation time 770266694 ps
CPU time 45.31 seconds
Started Apr 30 12:25:52 PM PDT 24
Finished Apr 30 12:26:38 PM PDT 24
Peak memory 199428 kb
Host smart-77b9283d-39c8-473c-b4fe-b08411944825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407217786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1407217786
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.736868033
Short name T593
Test name
Test status
Simulation time 10530210757 ps
CPU time 192.12 seconds
Started Apr 30 12:25:54 PM PDT 24
Finished Apr 30 12:29:07 PM PDT 24
Peak memory 199544 kb
Host smart-0ea5584a-c2f7-4cf8-94df-97e6d506a5ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736868033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.736868033
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4205159546
Short name T197
Test name
Test status
Simulation time 8507792641 ps
CPU time 121.42 seconds
Started Apr 30 12:25:49 PM PDT 24
Finished Apr 30 12:27:51 PM PDT 24
Peak memory 199500 kb
Host smart-4ea5d6f0-7416-45f5-96b0-3b428bf69cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205159546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4205159546
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1907205688
Short name T169
Test name
Test status
Simulation time 219305907 ps
CPU time 5.26 seconds
Started Apr 30 12:25:47 PM PDT 24
Finished Apr 30 12:25:53 PM PDT 24
Peak memory 199436 kb
Host smart-872b0239-767e-4c72-8d58-93bc3ef340ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907205688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1907205688
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1661385524
Short name T276
Test name
Test status
Simulation time 24915656537 ps
CPU time 1281.26 seconds
Started Apr 30 12:26:09 PM PDT 24
Finished Apr 30 12:47:31 PM PDT 24
Peak memory 236412 kb
Host smart-cbdc95c6-017b-4c8d-a120-a6ff5d611552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661385524 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1661385524
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.468117435
Short name T503
Test name
Test status
Simulation time 42987363 ps
CPU time 1.02 seconds
Started Apr 30 12:26:10 PM PDT 24
Finished Apr 30 12:26:12 PM PDT 24
Peak memory 198816 kb
Host smart-c506fa43-688d-4b81-8828-d9e26b1a74c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468117435 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.468117435
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.585755667
Short name T109
Test name
Test status
Simulation time 33575651444 ps
CPU time 459.11 seconds
Started Apr 30 12:26:05 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 199456 kb
Host smart-3dd1e593-1290-4244-a30c-6a5ea8596fcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585755667 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.585755667
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3036819087
Short name T268
Test name
Test status
Simulation time 347996541 ps
CPU time 10.77 seconds
Started Apr 30 12:26:23 PM PDT 24
Finished Apr 30 12:26:34 PM PDT 24
Peak memory 199360 kb
Host smart-c9280047-2169-4f9c-bd8e-45e85fd0f666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036819087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3036819087
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1141786170
Short name T418
Test name
Test status
Simulation time 19154244 ps
CPU time 0.56 seconds
Started Apr 30 12:24:20 PM PDT 24
Finished Apr 30 12:24:22 PM PDT 24
Peak memory 194048 kb
Host smart-c44c91ab-64a8-4058-9966-8ca9cb7adc04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141786170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1141786170
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.891149951
Short name T209
Test name
Test status
Simulation time 2360072592 ps
CPU time 21.38 seconds
Started Apr 30 12:24:11 PM PDT 24
Finished Apr 30 12:24:33 PM PDT 24
Peak memory 227160 kb
Host smart-47f46edf-e6cc-4615-9926-fb11598a88bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891149951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.891149951
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3752300777
Short name T595
Test name
Test status
Simulation time 7973328579 ps
CPU time 53.66 seconds
Started Apr 30 12:24:26 PM PDT 24
Finished Apr 30 12:25:20 PM PDT 24
Peak memory 199540 kb
Host smart-23cc733d-c764-430d-bbd7-72b40cee3b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752300777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3752300777
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1526654718
Short name T542
Test name
Test status
Simulation time 1367596972 ps
CPU time 17.15 seconds
Started Apr 30 12:24:28 PM PDT 24
Finished Apr 30 12:24:46 PM PDT 24
Peak memory 199464 kb
Host smart-c6821419-4afb-4233-8538-b5b879bdb28c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526654718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1526654718
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3031539849
Short name T168
Test name
Test status
Simulation time 608417469 ps
CPU time 16.11 seconds
Started Apr 30 12:26:01 PM PDT 24
Finished Apr 30 12:26:19 PM PDT 24
Peak memory 197528 kb
Host smart-103857e3-3ada-4ba9-8258-575fa464ddec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031539849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3031539849
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4217227738
Short name T319
Test name
Test status
Simulation time 251137936 ps
CPU time 13.78 seconds
Started Apr 30 12:25:57 PM PDT 24
Finished Apr 30 12:26:11 PM PDT 24
Peak memory 199232 kb
Host smart-4c567dc5-05b5-4d15-bbed-b1bc889fa3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217227738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4217227738
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1593742863
Short name T317
Test name
Test status
Simulation time 571977310 ps
CPU time 3.37 seconds
Started Apr 30 12:24:19 PM PDT 24
Finished Apr 30 12:24:23 PM PDT 24
Peak memory 199568 kb
Host smart-922059e3-df60-4746-bb19-3a98185a25df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593742863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1593742863
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.226716949
Short name T47
Test name
Test status
Simulation time 40859954646 ps
CPU time 270.14 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:28:59 PM PDT 24
Peak memory 199528 kb
Host smart-19907431-b663-46d4-b058-7009a5d31ca2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226716949 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.226716949
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3870606458
Short name T87
Test name
Test status
Simulation time 29129073 ps
CPU time 0.99 seconds
Started Apr 30 12:24:27 PM PDT 24
Finished Apr 30 12:24:29 PM PDT 24
Peak memory 199092 kb
Host smart-96ebf3f5-176b-46b8-98e4-e8b34e0b02a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870606458 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3870606458
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3790019745
Short name T250
Test name
Test status
Simulation time 45748231483 ps
CPU time 430.31 seconds
Started Apr 30 12:24:28 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 199464 kb
Host smart-1a6fcb6b-7267-45d2-9230-de09de053e36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790019745 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3790019745
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3529561072
Short name T396
Test name
Test status
Simulation time 18185717014 ps
CPU time 81.78 seconds
Started Apr 30 12:24:20 PM PDT 24
Finished Apr 30 12:25:43 PM PDT 24
Peak memory 199472 kb
Host smart-84968559-593a-432d-9096-72693aab43c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529561072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3529561072
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.1766418755
Short name T64
Test name
Test status
Simulation time 39237670006 ps
CPU time 203.82 seconds
Started Apr 30 12:26:14 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 230288 kb
Host smart-5941005f-9b91-43a3-98a3-7d90d4714130
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1766418755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.1766418755
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.950109813
Short name T538
Test name
Test status
Simulation time 11183326 ps
CPU time 0.62 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:24:31 PM PDT 24
Peak memory 195160 kb
Host smart-f9f390aa-cd3a-4af0-9349-cc6f01b6f295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950109813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.950109813
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1166194326
Short name T201
Test name
Test status
Simulation time 937253796 ps
CPU time 37.07 seconds
Started Apr 30 12:24:21 PM PDT 24
Finished Apr 30 12:24:59 PM PDT 24
Peak memory 222980 kb
Host smart-39c87526-8df2-4725-b758-7fb9b1146182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166194326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1166194326
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2815992209
Short name T356
Test name
Test status
Simulation time 1365735738 ps
CPU time 11.17 seconds
Started Apr 30 12:24:21 PM PDT 24
Finished Apr 30 12:24:33 PM PDT 24
Peak memory 199404 kb
Host smart-02f3eb09-9ae9-4912-b593-81a0eaae27a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815992209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2815992209
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3412000777
Short name T437
Test name
Test status
Simulation time 19376221772 ps
CPU time 80.44 seconds
Started Apr 30 12:26:01 PM PDT 24
Finished Apr 30 12:27:23 PM PDT 24
Peak memory 197432 kb
Host smart-f21f754b-918d-4363-bce0-6b898e93db81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412000777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3412000777
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2136078849
Short name T386
Test name
Test status
Simulation time 5223090346 ps
CPU time 142.68 seconds
Started Apr 30 12:24:21 PM PDT 24
Finished Apr 30 12:26:45 PM PDT 24
Peak memory 199508 kb
Host smart-74b5262c-b9e6-4cbd-96b8-260bc8050fda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136078849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2136078849
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1891564637
Short name T210
Test name
Test status
Simulation time 7423204762 ps
CPU time 107.2 seconds
Started Apr 30 12:24:43 PM PDT 24
Finished Apr 30 12:26:31 PM PDT 24
Peak memory 199480 kb
Host smart-43e44517-3a4b-4d3e-9684-d5b80b2deaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891564637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1891564637
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2130361274
Short name T422
Test name
Test status
Simulation time 569706862 ps
CPU time 4.28 seconds
Started Apr 30 12:26:02 PM PDT 24
Finished Apr 30 12:26:07 PM PDT 24
Peak memory 197880 kb
Host smart-81e55c8e-524e-4a60-b69e-156d85520bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130361274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2130361274
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.529597209
Short name T179
Test name
Test status
Simulation time 122354211091 ps
CPU time 1681.33 seconds
Started Apr 30 12:24:26 PM PDT 24
Finished Apr 30 12:52:29 PM PDT 24
Peak memory 248840 kb
Host smart-0cf538d6-52e4-4e7d-8a22-ad2eb3c66f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529597209 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.529597209
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.831097158
Short name T501
Test name
Test status
Simulation time 322344174 ps
CPU time 1.14 seconds
Started Apr 30 12:24:44 PM PDT 24
Finished Apr 30 12:24:45 PM PDT 24
Peak memory 199008 kb
Host smart-cebc27c2-a149-4bf7-90bf-eb3bc460471f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831097158 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.831097158
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3586135619
Short name T467
Test name
Test status
Simulation time 272072194145 ps
CPU time 480.19 seconds
Started Apr 30 12:24:26 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 199564 kb
Host smart-e38e8653-b71c-4d8e-a579-6512d7c608b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586135619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3586135619
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3071470659
Short name T186
Test name
Test status
Simulation time 542765491 ps
CPU time 13.52 seconds
Started Apr 30 12:24:32 PM PDT 24
Finished Apr 30 12:24:46 PM PDT 24
Peak memory 199448 kb
Host smart-044bb59a-4528-43d0-90e2-e2f162f23446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071470659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3071470659
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.1403434642
Short name T493
Test name
Test status
Simulation time 262427048238 ps
CPU time 572.02 seconds
Started Apr 30 12:26:06 PM PDT 24
Finished Apr 30 12:35:39 PM PDT 24
Peak memory 208828 kb
Host smart-56cad55c-045c-496f-8e31-0f41a322b7d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403434642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.1403434642
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1946835422
Short name T565
Test name
Test status
Simulation time 37490951 ps
CPU time 0.58 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:24:31 PM PDT 24
Peak memory 194212 kb
Host smart-e5c715b0-2427-4e17-8838-df7d742d8bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946835422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1946835422
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4160997351
Short name T52
Test name
Test status
Simulation time 4063995544 ps
CPU time 37.96 seconds
Started Apr 30 12:24:28 PM PDT 24
Finished Apr 30 12:25:07 PM PDT 24
Peak memory 227296 kb
Host smart-77889057-edfa-439b-91a0-8937cfde8b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160997351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4160997351
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3773552996
Short name T38
Test name
Test status
Simulation time 924284759 ps
CPU time 21.68 seconds
Started Apr 30 12:24:24 PM PDT 24
Finished Apr 30 12:24:47 PM PDT 24
Peak memory 199496 kb
Host smart-d1707488-88d3-4b0a-b2d2-9a2b9fa30fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773552996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3773552996
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1152380275
Short name T260
Test name
Test status
Simulation time 1567693968 ps
CPU time 42.57 seconds
Started Apr 30 12:24:25 PM PDT 24
Finished Apr 30 12:25:08 PM PDT 24
Peak memory 199432 kb
Host smart-72bbe305-d4c5-44f2-a4c1-16e236993310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152380275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1152380275
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.12899573
Short name T598
Test name
Test status
Simulation time 11147093034 ps
CPU time 144.65 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:26:55 PM PDT 24
Peak memory 199552 kb
Host smart-5fa8e0ee-63f7-4bc3-9759-ecddc5379d11
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.12899573
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3168289130
Short name T373
Test name
Test status
Simulation time 21844243612 ps
CPU time 105.67 seconds
Started Apr 30 12:24:48 PM PDT 24
Finished Apr 30 12:26:35 PM PDT 24
Peak memory 199484 kb
Host smart-f0c8cdce-cf42-417f-9f96-34fa64eba0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168289130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3168289130
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1987754677
Short name T77
Test name
Test status
Simulation time 86707189 ps
CPU time 2.92 seconds
Started Apr 30 12:26:04 PM PDT 24
Finished Apr 30 12:26:07 PM PDT 24
Peak memory 199424 kb
Host smart-b42816b6-adfa-4722-9c70-1a0559315904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987754677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1987754677
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2177785338
Short name T455
Test name
Test status
Simulation time 104703079146 ps
CPU time 456.23 seconds
Started Apr 30 12:24:28 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 207728 kb
Host smart-e21cefb8-c57d-441c-a641-273e4fa427a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177785338 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2177785338
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1893208412
Short name T463
Test name
Test status
Simulation time 76551651 ps
CPU time 1.29 seconds
Started Apr 30 12:24:30 PM PDT 24
Finished Apr 30 12:24:33 PM PDT 24
Peak memory 199468 kb
Host smart-e8a43471-af58-4c24-896f-63d2d1945a28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893208412 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1893208412
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.867245927
Short name T556
Test name
Test status
Simulation time 101416710736 ps
CPU time 477.92 seconds
Started Apr 30 12:24:25 PM PDT 24
Finished Apr 30 12:32:24 PM PDT 24
Peak memory 199468 kb
Host smart-d0d94518-1bd6-43d8-b7b9-8b870cdb0938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867245927 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.867245927
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2037317579
Short name T258
Test name
Test status
Simulation time 4963938350 ps
CPU time 22.51 seconds
Started Apr 30 12:24:23 PM PDT 24
Finished Apr 30 12:24:46 PM PDT 24
Peak memory 199536 kb
Host smart-3cdc8127-37ac-42fa-893d-fa48bb04b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037317579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2037317579
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.3423908507
Short name T561
Test name
Test status
Simulation time 36949553360 ps
CPU time 1721.91 seconds
Started Apr 30 12:26:34 PM PDT 24
Finished Apr 30 12:55:17 PM PDT 24
Peak memory 241368 kb
Host smart-8229d7df-b89a-4552-9a9b-45db04031a9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423908507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.3423908507
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1835750062
Short name T180
Test name
Test status
Simulation time 40148673 ps
CPU time 0.57 seconds
Started Apr 30 12:24:35 PM PDT 24
Finished Apr 30 12:24:36 PM PDT 24
Peak memory 194108 kb
Host smart-f0b85887-6b72-4f58-ae0e-ac7aecf391fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835750062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1835750062
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2284838899
Short name T402
Test name
Test status
Simulation time 1175102086 ps
CPU time 35.82 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:25:06 PM PDT 24
Peak memory 239984 kb
Host smart-e6da105c-b365-43e9-b244-0b3d98832360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284838899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2284838899
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.98652375
Short name T320
Test name
Test status
Simulation time 10887024987 ps
CPU time 65.83 seconds
Started Apr 30 12:24:28 PM PDT 24
Finished Apr 30 12:25:35 PM PDT 24
Peak memory 199548 kb
Host smart-d1b7d5bc-520e-4d05-b3d4-1535bac910b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98652375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.98652375
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.558573195
Short name T326
Test name
Test status
Simulation time 1926268980 ps
CPU time 27.24 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:24:58 PM PDT 24
Peak memory 199364 kb
Host smart-424f591a-e55b-4c76-b1f4-3c9fd4d4f194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558573195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.558573195
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3666985632
Short name T446
Test name
Test status
Simulation time 5780323170 ps
CPU time 78.61 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:25:49 PM PDT 24
Peak memory 199548 kb
Host smart-c0047f90-a3f5-4def-bb76-33c6727a5add
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666985632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3666985632
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3102024726
Short name T492
Test name
Test status
Simulation time 9563869419 ps
CPU time 140.25 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:26:51 PM PDT 24
Peak memory 199544 kb
Host smart-753edcc9-d876-4f2e-bcf6-86181bd48b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102024726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3102024726
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4024701558
Short name T381
Test name
Test status
Simulation time 3109788514 ps
CPU time 4.17 seconds
Started Apr 30 12:24:29 PM PDT 24
Finished Apr 30 12:24:34 PM PDT 24
Peak memory 199564 kb
Host smart-2275c93b-0ae8-4ee6-8404-a61bd10fed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024701558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4024701558
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2010346076
Short name T364
Test name
Test status
Simulation time 21325509883 ps
CPU time 286.42 seconds
Started Apr 30 12:24:36 PM PDT 24
Finished Apr 30 12:29:23 PM PDT 24
Peak memory 230948 kb
Host smart-7f52ca03-fdc3-49b2-859b-72c043f63395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010346076 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2010346076
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3118774875
Short name T587
Test name
Test status
Simulation time 185923767 ps
CPU time 1.1 seconds
Started Apr 30 12:26:02 PM PDT 24
Finished Apr 30 12:26:04 PM PDT 24
Peak memory 199012 kb
Host smart-8a996e27-e306-49c9-a2dc-397e8a6dbeaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118774875 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3118774875
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1766555301
Short name T111
Test name
Test status
Simulation time 8167371970 ps
CPU time 452.45 seconds
Started Apr 30 12:24:22 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 199404 kb
Host smart-d4a245fe-8d97-4e24-806a-5e59fbd8f70c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766555301 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1766555301
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.658780044
Short name T124
Test name
Test status
Simulation time 25430864206 ps
CPU time 85.65 seconds
Started Apr 30 12:24:24 PM PDT 24
Finished Apr 30 12:25:51 PM PDT 24
Peak memory 199568 kb
Host smart-ddfcbe3b-f270-41c6-ae0f-1ec4e90ac81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658780044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.658780044
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2397013522
Short name T145
Test name
Test status
Simulation time 10830624 ps
CPU time 0.57 seconds
Started Apr 30 12:24:33 PM PDT 24
Finished Apr 30 12:24:34 PM PDT 24
Peak memory 194124 kb
Host smart-3f7bcfcc-c4ce-4599-a01c-ed97d40e170d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397013522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2397013522
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.890753213
Short name T158
Test name
Test status
Simulation time 987955444 ps
CPU time 38.45 seconds
Started Apr 30 12:24:35 PM PDT 24
Finished Apr 30 12:25:14 PM PDT 24
Peak memory 229860 kb
Host smart-17e378ae-cb3f-4fd7-9f78-f65051b967bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890753213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.890753213
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.200560504
Short name T157
Test name
Test status
Simulation time 2677913014 ps
CPU time 54.79 seconds
Started Apr 30 12:24:38 PM PDT 24
Finished Apr 30 12:25:33 PM PDT 24
Peak memory 199448 kb
Host smart-be3cea59-4105-461a-9924-d24a72e9475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200560504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.200560504
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3987662772
Short name T42
Test name
Test status
Simulation time 3734043506 ps
CPU time 126.72 seconds
Started Apr 30 12:24:35 PM PDT 24
Finished Apr 30 12:26:42 PM PDT 24
Peak memory 199620 kb
Host smart-b1ca1207-596f-4ff3-99ce-d722c8980b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987662772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3987662772
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.376320149
Short name T466
Test name
Test status
Simulation time 62262118554 ps
CPU time 190.28 seconds
Started Apr 30 12:26:04 PM PDT 24
Finished Apr 30 12:29:15 PM PDT 24
Peak memory 199512 kb
Host smart-d70f9eee-a3d2-4ab7-989c-893223f8c2f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376320149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.376320149
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.634296276
Short name T336
Test name
Test status
Simulation time 8202266813 ps
CPU time 50.97 seconds
Started Apr 30 12:24:36 PM PDT 24
Finished Apr 30 12:25:28 PM PDT 24
Peak memory 199540 kb
Host smart-ea3002b9-73d2-445c-9166-91b7060c6825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634296276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.634296276
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3486654873
Short name T580
Test name
Test status
Simulation time 121389644 ps
CPU time 2.85 seconds
Started Apr 30 12:24:34 PM PDT 24
Finished Apr 30 12:24:38 PM PDT 24
Peak memory 199648 kb
Host smart-7fc878fa-cc91-4a3f-bb9e-842a4d4028d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486654873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3486654873
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1862431023
Short name T416
Test name
Test status
Simulation time 68585447596 ps
CPU time 1599.4 seconds
Started Apr 30 12:24:34 PM PDT 24
Finished Apr 30 12:51:14 PM PDT 24
Peak memory 240528 kb
Host smart-b1e8d962-5170-42bd-b02c-fc09a9d89763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862431023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1862431023
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2588552066
Short name T238
Test name
Test status
Simulation time 216045992 ps
CPU time 0.94 seconds
Started Apr 30 12:24:40 PM PDT 24
Finished Apr 30 12:24:42 PM PDT 24
Peak memory 197740 kb
Host smart-d5f9e9b1-94cc-4d88-b310-65f2e482003f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588552066 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2588552066
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3665429487
Short name T112
Test name
Test status
Simulation time 761081903587 ps
CPU time 567.85 seconds
Started Apr 30 12:24:40 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 199328 kb
Host smart-a2184226-1dbc-4399-a46b-9aac8ad15b51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665429487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3665429487
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4129025269
Short name T483
Test name
Test status
Simulation time 427685850 ps
CPU time 19.01 seconds
Started Apr 30 12:24:35 PM PDT 24
Finished Apr 30 12:24:55 PM PDT 24
Peak memory 199500 kb
Host smart-1021462f-96f1-48e0-b61d-d0fbd75dc7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129025269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4129025269
Directory /workspace/9.hmac_wipe_secret/latest
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