Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14334956	1			T2	216		T3	84209		T4	81
all_values[1]	14334956	1			T2	216		T3	84209		T4	81
all_values[2]	14334956	1			T2	216		T3	84209		T4	81

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123593

1

T2

4

T5

2

T20

4141

auto[1]

42881275

1

T2

644

T3

252627

T4

243

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40462190

1

T2

632

T3

240808

T4

226

auto[1]

2542678

1

T2

16

T3

11819

T4

17

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	46519	1			T20	3762		T7	164		T35	1
all_values[0]	auto[0]	auto[1]	450	1			T7	4		T35	2		T39	2
all_values[0]	auto[1]	auto[0]	14239906	1			T2	200		T3	84015		T4	77
all_values[0]	auto[1]	auto[1]	48081	1			T2	16		T3	194		T4	4
all_values[1]	auto[0]	auto[0]	35168	1			T35	3		T26	1051		T49	85
all_values[1]	auto[0]	auto[1]	214	1			T26	3		T54	1		T17	4
all_values[1]	auto[1]	auto[0]	14299079	1			T2	216		T3	84209		T4	81
all_values[1]	auto[1]	auto[1]	495	1			T29	2		T26	1		T54	2
all_values[2]	auto[0]	auto[0]	33340	1			T2	4		T5	2		T20	1
all_values[2]	auto[0]	auto[1]	7902	1			T20	378		T26	1		T54	2
all_values[2]	auto[1]	auto[0]	11808178	1			T2	212		T3	72584		T4	68
all_values[2]	auto[1]	auto[1]	2485536	1			T3	11625		T4	13		T6	14822