Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
2.17	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	78	75	3	3.85
Crosses	152	150	2	1.32

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len	76	75	1	1.32	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_cross	152	150	2	1.32	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70077

1

T2

7

T3

97

T6

19

auto[1]

68377

1

T2

8

T6

18

T5

19

---

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	76	75	1	1.32

User Defined Bins for msg_len

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto_lens[0]	0	1	1
auto_lens[1]	0	1	1
auto_lens[2]	0	1	1
auto_lens[3]	0	1	1
auto_lens[4]	0	1	1
auto_lens[5]	0	1	1
auto_lens[6]	0	1	1
auto_lens[7]	0	1	1
auto_lens[8]	0	1	1
auto_lens[9]	0	1	1
auto_lens[10]	0	1	1
auto_lens[11]	0	1	1
auto_lens[12]	0	1	1
auto_lens[13]	0	1	1
auto_lens[14]	0	1	1
auto_lens[15]	0	1	1
auto_lens[16]	0	1	1
auto_lens[17]	0	1	1
auto_lens[18]	0	1	1
auto_lens[19]	0	1	1
auto_lens[20]	0	1	1
auto_lens[21]	0	1	1
auto_lens[22]	0	1	1
auto_lens[23]	0	1	1
auto_lens[24]	0	1	1
auto_lens[25]	0	1	1
auto_lens[26]	0	1	1
auto_lens[27]	0	1	1
auto_lens[28]	0	1	1
auto_lens[29]	0	1	1
auto_lens[30]	0	1	1
auto_lens[31]	0	1	1
auto_lens[32]	0	1	1
auto_lens[33]	0	1	1
auto_lens[34]	0	1	1
auto_lens[35]	0	1	1
auto_lens[36]	0	1	1
auto_lens[37]	0	1	1
auto_lens[38]	0	1	1
auto_lens[39]	0	1	1
auto_lens[40]	0	1	1
auto_lens[41]	0	1	1
auto_lens[42]	0	1	1
auto_lens[43]	0	1	1
auto_lens[44]	0	1	1
auto_lens[45]	0	1	1
auto_lens[46]	0	1	1
auto_lens[47]	0	1	1
auto_lens[48]	0	1	1
auto_lens[49]	0	1	1
len_3073	0	1	1
len_3072	0	1	1
len_2817	0	1	1
len_2816	0	1	1
len_2561	0	1	1
len_2560	0	1	1
len_2305	0	1	1
len_2304	0	1	1
len_2049	0	1	1
len_2048	0	1	1
len_1793	0	1	1
len_1792	0	1	1
len_1537	0	1	1
len_1536	0	1	1
len_1281	0	1	1
len_1280	0	1	1
len_1025	0	1	1
len_1024	0	1	1
len_769	0	1	1
len_768	0	1	1
len_513	0	1	1
len_512	0	1	1
len_257	0	1	1
len_256	0	1	1
len_1	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_0

138454

1

T2

15

T3

97

T6

37

---

Summary for Cross msg_len_cross

Samples crossed: hmac_en msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	152	150	2	1.32	150

Automatically Generated Cross Bins for msg_len_cross

Element holes

hmac_en	msg_len	COUNT	AT LEAST	NUMBER	STATUS
*	[auto_lens[0] , auto_lens[1] , auto_lens[2] , auto_lens[3] , auto_lens[4] , auto_lens[5] , auto_lens[6] , auto_lens[7] , auto_lens[8] , auto_lens[9] , auto_lens[10] , auto_lens[11] , auto_lens[12] , auto_lens[13] , auto_lens[14] , auto_lens[15] , auto_lens[16] , auto_lens[17] , auto_lens[18] , auto_lens[19] , auto_lens[20] , auto_lens[21] , auto_lens[22] , auto_lens[23] , auto_lens[24] , auto_lens[25] , auto_lens[26] , auto_lens[27] , auto_lens[28] , auto_lens[29] , auto_lens[30] , auto_lens[31] , auto_lens[32] , auto_lens[33] , auto_lens[34] , auto_lens[35] , auto_lens[36] , auto_lens[37] , auto_lens[38] , auto_lens[39] , auto_lens[40] , auto_lens[41] , auto_lens[42] , auto_lens[43] , auto_lens[44] , auto_lens[45] , auto_lens[46] , auto_lens[47] , auto_lens[48] , auto_lens[49] , len_3073 , len_3072 , len_2817 , len_2816 , len_2561 , len_2560 , len_2305 , len_2304 , len_2049 , len_2048 , len_1793 , len_1792 , len_1537 , len_1536 , len_1281 , len_1280 , len_1025 , len_1024 , len_769 , len_768 , len_513 , len_512 , len_257 , len_256 , len_1]	--	--	150

Covered bins

hmac_en

msg_len

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_0

70077

1

T2

7

T3

97

T6

19

auto[1]

len_0

68377

1

T2

8

T6

18

T5

19