Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6851945

1

T2

4

T3

37459

T4

32

auto[1]

2813846

1

T2

9

T6

2321

T5

21

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2823840

1

T2

5

T6

2173

T5

11

auto[1]

6841951

1

T2

8

T3

37459

T4

32

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6017536

1

T2

6

T3

37459

T6

1788

auto[1]

3648255

1

T2

7

T4

32

T6

2189

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6184018	1			T2	1		T3	26468		T4	30
fifo_depth[1]	456755	1			T3	2473		T4	2		T6	66
fifo_depth[2]	376145	1			T3	2369		T6	16		T20	114
fifo_depth[3]	304860	1			T3	1850		T6	6		T20	40
fifo_depth[4]	265867	1			T3	1239		T6	1		T20	12
fifo_depth[5]	237069	1			T3	941		T20	3		T7	682
fifo_depth[6]	226901	1			T3	737		T7	670		T39	1447
fifo_depth[7]	201231	1			T3	519		T7	652		T39	1406
fifo_depth[8]	183496	1			T3	361		T7	543		T39	1145
fifo_depth[9]	126668	1			T3	241		T7	405		T39	843
fifo_depth[10]	99221	1			T3	128		T7	271		T39	556
fifo_depth[11]	61772	1			T3	72		T7	151		T39	349
fifo_depth[12]	63201	1			T3	35		T7	62		T39	165
fifo_depth[13]	33167	1			T3	20		T7	34		T39	69
fifo_depth[14]	42590	1			T3	5		T7	5		T39	25
fifo_depth[15]	27367	1			T3	1		T7	4		T39	10
fifo_depth[16]	108064	1			T7	1		T39	6		T21	91

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3621904

1

T2

13

T3

10991

T4

2

auto[1]

6043887

1

T3

26468

T4

30

T6

3888

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9525660

1

T2

12

T3

37459

T4

32

auto[1]

140131

1

T2

1

T5

4

T21

284

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

251442

1

T2

1

T5

2

T20

28

auto[0]

auto[0]

auto[0]

auto[1]

249211

1

T2

2

T6

32

T5

5

auto[0]

auto[0]

auto[1]

auto[0]

979428

1

T2

2

T3

10991

T6

8

auto[0]

auto[0]

auto[1]

auto[1]

253607

1

T2

1

T6

5

T5

6

auto[0]

auto[1]

auto[0]

auto[0]

477539

1

T2

1

T5

3

T20

106

auto[0]

auto[1]

auto[0]

auto[1]

463881

1

T2

1

T6

43

T5

1

auto[0]

auto[1]

auto[1]

auto[0]

486245

1

T4

2

T6

1

T5

3

auto[0]

auto[1]

auto[1]

auto[1]

460551

1

T2

5

T5

9

T7

991

auto[1]

auto[0]

auto[0]

auto[0]

240217

1

T6

77

T20

778

T18

357

auto[1]

auto[0]

auto[0]

auto[1]

267886

1

T6

513

T20

836

T18

2694

auto[1]

auto[0]

auto[1]

auto[0]

3517757

1

T3

26468

T6

507

T20

1034

auto[1]

auto[0]

auto[1]

auto[1]

257988

1

T6

646

T20

1637

T35

36

auto[1]

auto[1]

auto[0]

auto[0]

438195

1

T6

948

T20

3400

T7

1086

auto[1]

auto[1]

auto[0]

auto[1]

435469

1

T6

560

T20

1411

T7

514

auto[1]

auto[1]

auto[1]

auto[0]

461122

1

T4

30

T6

115

T20

310

auto[1]

auto[1]

auto[1]

auto[1]

425253

1

T6

522

T20

26

T7

499

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

476522

1

T2

1

T6

77

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

503223

1

T2

2

T6

545

T5

5

auto[0]

auto[0]

auto[1]

auto[0]

4482177

1

T2

2

T3

37459

T6

515

auto[0]

auto[0]

auto[1]

auto[1]

495749

1

T2

1

T6

651

T5

6

auto[0]

auto[1]

auto[0]

auto[0]

896500

1

T2

1

T6

948

T5

2

auto[0]

auto[1]

auto[0]

auto[1]

876874

1

T2

1

T6

603

T20

1527

auto[0]

auto[1]

auto[1]

auto[0]

930758

1

T4

32

T6

116

T5

3

auto[0]

auto[1]

auto[1]

auto[1]

863857

1

T2

4

T6

522

T5

9

auto[1]

auto[0]

auto[0]

auto[0]

15137

1

T5

1

T22

1

T28

16

auto[1]

auto[0]

auto[0]

auto[1]

13874

1

T45

1

T47

1

T29

43

auto[1]

auto[0]

auto[1]

auto[0]

15008

1

T5

1

T21

14

T45

3

auto[1]

auto[0]

auto[1]

auto[1]

15846

1

T21

1

T22

1

T45

1

auto[1]

auto[1]

auto[0]

auto[0]

19234

1

T5

1

T46

1

T47

3

auto[1]

auto[1]

auto[0]

auto[1]

22476

1

T5

1

T46

1

T47

2

auto[1]

auto[1]

auto[1]

auto[0]

16609

1

T21

155

T28

13

T47

1

auto[1]

auto[1]

auto[1]

auto[1]

21947

1

T2

1

T21

114

T22

2

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	255354	1			T6	77		T5	1		T20	778
fifo_depth[0]	auto[0]	auto[0]	auto[1]	281760	1			T6	513		T20	836		T18	2694
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3532765	1			T3	26468		T6	507		T5	1
fifo_depth[0]	auto[0]	auto[1]	auto[1]	273834	1			T6	646		T20	1637		T35	36
fifo_depth[0]	auto[1]	auto[0]	auto[0]	457429	1			T6	948		T5	1		T20	3400
fifo_depth[0]	auto[1]	auto[0]	auto[1]	457945	1			T6	560		T5	1		T20	1411
fifo_depth[0]	auto[1]	auto[1]	auto[0]	477731	1			T4	30		T6	115		T20	310
fifo_depth[0]	auto[1]	auto[1]	auto[1]	447200	1			T2	1		T6	522		T20	26
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19478	1			T20	19		T18	13		T19	46
fifo_depth[1]	auto[0]	auto[0]	auto[1]	20309	1			T6	22		T20	37		T18	53
fifo_depth[1]	auto[0]	auto[1]	auto[0]	208742	1			T3	2473		T6	8		T20	14
fifo_depth[1]	auto[0]	auto[1]	auto[1]	20151	1			T6	5		T20	57		T21	22
fifo_depth[1]	auto[1]	auto[0]	auto[0]	47632	1			T20	67		T7	205		T18	24
fifo_depth[1]	auto[1]	auto[0]	auto[1]	46832	1			T6	30		T20	70		T7	111
fifo_depth[1]	auto[1]	auto[1]	auto[0]	49111	1			T4	2		T6	1		T20	3
fifo_depth[1]	auto[1]	auto[1]	auto[1]	44500	1			T7	102		T35	6		T39	440
fifo_depth[2]	auto[0]	auto[0]	auto[0]	16887	1			T20	7		T18	9		T19	22
fifo_depth[2]	auto[0]	auto[0]	auto[1]	17421	1			T6	6		T20	11		T18	29
fifo_depth[2]	auto[0]	auto[1]	auto[0]	156947	1			T3	2369		T21	1		T122	591
fifo_depth[2]	auto[0]	auto[1]	auto[1]	17174	1			T20	38		T21	123		T28	1
fifo_depth[2]	auto[1]	auto[0]	auto[0]	42165	1			T20	25		T7	219		T18	9
fifo_depth[2]	auto[1]	auto[0]	auto[1]	41847	1			T6	10		T20	33		T7	98
fifo_depth[2]	auto[1]	auto[1]	auto[0]	43895	1			T7	252		T35	5		T39	378
fifo_depth[2]	auto[1]	auto[1]	auto[1]	39809	1			T7	102		T35	7		T39	403
fifo_depth[3]	auto[0]	auto[0]	auto[0]	13667	1			T20	2		T18	6		T19	6
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13742	1			T6	4		T20	7		T18	6
fifo_depth[3]	auto[0]	auto[1]	auto[0]	116318	1			T3	1850		T122	220		T124	21
fifo_depth[3]	auto[0]	auto[1]	auto[1]	14052	1			T20	11		T21	119		T125	21
fifo_depth[3]	auto[1]	auto[0]	auto[0]	37580	1			T20	11		T7	209		T18	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	36885	1			T6	2		T20	9		T7	103
fifo_depth[3]	auto[1]	auto[1]	auto[0]	38279	1			T7	281		T39	361		T19	38
fifo_depth[3]	auto[1]	auto[1]	auto[1]	34337	1			T7	115		T35	4		T39	404
fifo_depth[4]	auto[0]	auto[0]	auto[0]	13794	1			T19	2		T21	1		T126	9
fifo_depth[4]	auto[0]	auto[0]	auto[1]	12808	1			T20	1		T18	3		T126	86
fifo_depth[4]	auto[0]	auto[1]	auto[0]	85327	1			T3	1239		T122	69		T124	4
fifo_depth[4]	auto[0]	auto[1]	auto[1]	13304	1			T20	4		T21	122		T125	12
fifo_depth[4]	auto[1]	auto[0]	auto[0]	36079	1			T20	3		T7	230		T35	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	34779	1			T6	1		T20	4		T7	102
fifo_depth[4]	auto[1]	auto[1]	auto[0]	36968	1			T7	269		T39	379		T19	10
fifo_depth[4]	auto[1]	auto[1]	auto[1]	32808	1			T7	118		T35	1		T39	417
fifo_depth[5]	auto[0]	auto[0]	auto[0]	12068	1			T21	2		T126	1		T28	19
fifo_depth[5]	auto[0]	auto[0]	auto[1]	11072	1			T20	1		T18	1		T126	95
fifo_depth[5]	auto[0]	auto[1]	auto[0]	70433	1			T3	941		T122	14		T124	2
fifo_depth[5]	auto[0]	auto[1]	auto[1]	11916	1			T20	2		T21	121		T28	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	33438	1			T7	210		T39	386		T85	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	33092	1			T7	100		T39	307		T19	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	34186	1			T7	258		T35	1		T39	390
fifo_depth[5]	auto[1]	auto[1]	auto[1]	30864	1			T7	114		T39	433		T19	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	12107	1			T126	4		T28	7		T125	2
fifo_depth[6]	auto[0]	auto[0]	auto[1]	11250	1			T126	95		T125	56		T32	23
fifo_depth[6]	auto[0]	auto[1]	auto[0]	61947	1			T3	737		T122	3		T124	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	11784	1			T21	122		T125	7		T29	79
fifo_depth[6]	auto[1]	auto[0]	auto[0]	33300	1			T7	214		T39	388		T109	82
fifo_depth[6]	auto[1]	auto[0]	auto[1]	32506	1			T7	91		T39	311		T84	151
fifo_depth[6]	auto[1]	auto[1]	auto[0]	33705	1			T7	262		T39	355		T109	92
fifo_depth[6]	auto[1]	auto[1]	auto[1]	30302	1			T7	103		T39	393		T109	206
fifo_depth[7]	auto[0]	auto[0]	auto[0]	10998	1			T21	2		T126	1		T28	19
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10161	1			T126	76		T125	55		T32	10
fifo_depth[7]	auto[0]	auto[1]	auto[0]	49950	1			T3	519		T28	39		T32	98
fifo_depth[7]	auto[0]	auto[1]	auto[1]	10789	1			T21	120		T125	12		T29	41
fifo_depth[7]	auto[1]	auto[0]	auto[0]	30415	1			T7	199		T39	378		T85	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	30189	1			T7	109		T39	281		T84	123
fifo_depth[7]	auto[1]	auto[1]	auto[0]	31114	1			T7	251		T39	362		T109	80
fifo_depth[7]	auto[1]	auto[1]	auto[1]	27615	1			T7	93		T39	385		T109	193
fifo_depth[8]	auto[0]	auto[0]	auto[0]	11717	1			T126	3		T28	231		T125	1
fifo_depth[8]	auto[0]	auto[0]	auto[1]	10846	1			T126	67		T125	31		T32	5
fifo_depth[8]	auto[0]	auto[1]	auto[0]	40644	1			T3	361		T21	1		T28	41
fifo_depth[8]	auto[0]	auto[1]	auto[1]	11489	1			T21	125		T28	2		T125	17
fifo_depth[8]	auto[1]	auto[0]	auto[0]	28194	1			T7	169		T39	302		T109	44
fifo_depth[8]	auto[1]	auto[0]	auto[1]	27119	1			T7	79		T39	229		T84	94
fifo_depth[8]	auto[1]	auto[1]	auto[0]	27905	1			T7	199		T39	286		T109	70
fifo_depth[8]	auto[1]	auto[1]	auto[1]	25582	1			T7	96		T39	328		T109	157
fifo_depth[9]	auto[0]	auto[0]	auto[0]	7499	1			T126	2		T28	26		T125	4
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7204	1			T126	39		T125	25		T29	1
fifo_depth[9]	auto[0]	auto[1]	auto[0]	26641	1			T3	241		T28	39		T32	78
fifo_depth[9]	auto[0]	auto[1]	auto[1]	7568	1			T21	120		T125	12		T29	43
fifo_depth[9]	auto[1]	auto[0]	auto[0]	19691	1			T7	128		T39	230		T109	41
fifo_depth[9]	auto[1]	auto[0]	auto[1]	19275	1			T7	54		T39	176		T84	93
fifo_depth[9]	auto[1]	auto[1]	auto[0]	20432	1			T7	160		T39	201		T109	63
fifo_depth[9]	auto[1]	auto[1]	auto[1]	18358	1			T7	63		T39	236		T109	119
fifo_depth[10]	auto[0]	auto[0]	auto[0]	6999	1			T126	2		T125	1		T29	81
fifo_depth[10]	auto[0]	auto[0]	auto[1]	6947	1			T126	35		T125	17		T31	23
fifo_depth[10]	auto[0]	auto[1]	auto[0]	18408	1			T3	128		T28	41		T32	41
fifo_depth[10]	auto[0]	auto[1]	auto[1]	7054	1			T21	122		T28	1		T125	6
fifo_depth[10]	auto[1]	auto[0]	auto[0]	15482	1			T7	94		T39	143		T109	36
fifo_depth[10]	auto[1]	auto[0]	auto[1]	14443	1			T7	39		T39	123		T84	67
fifo_depth[10]	auto[1]	auto[1]	auto[0]	15491	1			T7	100		T39	142		T109	35
fifo_depth[10]	auto[1]	auto[1]	auto[1]	14397	1			T7	38		T39	148		T109	94
fifo_depth[11]	auto[0]	auto[0]	auto[0]	4657	1			T126	5		T28	26		T29	13
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4728	1			T126	17		T125	14		T29	1
fifo_depth[11]	auto[0]	auto[1]	auto[0]	11032	1			T3	72		T28	40		T32	21
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4445	1			T21	120		T28	1		T125	3
fifo_depth[11]	auto[1]	auto[0]	auto[0]	9313	1			T7	51		T39	89		T109	16
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9017	1			T7	17		T39	71		T84	40
fifo_depth[11]	auto[1]	auto[1]	auto[0]	9879	1			T7	60		T39	91		T21	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8701	1			T7	23		T39	98		T109	52
fifo_depth[12]	auto[0]	auto[0]	auto[0]	6671	1			T28	217		T29	112		T26	108
fifo_depth[12]	auto[0]	auto[0]	auto[1]	5794	1			T126	3		T125	2		T29	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10348	1			T3	35		T28	41		T32	8
fifo_depth[12]	auto[0]	auto[1]	auto[1]	6432	1			T21	123		T125	1		T29	38
fifo_depth[12]	auto[1]	auto[0]	auto[0]	8410	1			T7	22		T39	49		T109	8
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7990	1			T7	9		T39	27		T84	14
fifo_depth[12]	auto[1]	auto[1]	auto[0]	8931	1			T7	18		T39	46		T109	10
fifo_depth[12]	auto[1]	auto[1]	auto[1]	8625	1			T7	13		T39	43		T21	1
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3530	1			T126	1		T28	19		T29	46
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3706	1			T126	2		T31	1		T26	78
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4656	1			T3	20		T28	39		T32	4
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2788	1			T21	119		T28	1		T125	1
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4545	1			T7	7		T39	19		T109	3
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4390	1			T7	6		T39	8		T84	5
fifo_depth[13]	auto[1]	auto[1]	auto[0]	4886	1			T7	12		T39	17		T109	3
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4666	1			T7	9		T39	25		T21	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	5156	1			T28	6		T29	97		T26	118
fifo_depth[14]	auto[0]	auto[0]	auto[1]	5030	1			T126	2		T29	2		T26	150
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5353	1			T3	5		T21	1		T28	41
fifo_depth[14]	auto[0]	auto[1]	auto[1]	5159	1			T21	122		T28	1		T29	36
fifo_depth[14]	auto[1]	auto[0]	auto[0]	5347	1			T7	2		T39	6		T109	4
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4641	1			T39	5		T84	6		T109	3
fifo_depth[14]	auto[1]	auto[1]	auto[0]	6096	1			T7	2		T39	7		T21	2
fifo_depth[14]	auto[1]	auto[1]	auto[1]	5808	1			T7	1		T39	7		T109	3
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3547	1			T28	19		T29	45		T26	147
fifo_depth[15]	auto[0]	auto[0]	auto[1]	3988	1			T29	1		T26	72		T127	40
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3344	1			T3	1		T28	23		T29	18
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2543	1			T21	105		T29	47		T26	11
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3279	1			T7	2		T39	2		T109	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3095	1			T39	3		T109	3		T28	40
fifo_depth[15]	auto[1]	auto[1]	auto[0]	4021	1			T7	1		T110	3		T28	42
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3550	1			T7	1		T39	5		T21	1
fifo_depth[16]	auto[0]	auto[0]	auto[0]	14007	1			T28	204		T29	80		T26	1087
fifo_depth[16]	auto[0]	auto[0]	auto[1]	10974	1			T26	739		T127	43		T16	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	12565	1			T21	2		T28	7		T29	71
fifo_depth[16]	auto[0]	auto[1]	auto[1]	12540	1			T21	85		T28	1		T29	56
fifo_depth[16]	auto[1]	auto[0]	auto[0]	12763	1			T7	1		T39	1		T125	2
fifo_depth[16]	auto[1]	auto[0]	auto[1]	15246	1			T28	6		T29	1		T31	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	14566	1			T39	2		T21	3		T110	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	15403	1			T39	3		T21	1		T26	170