Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14334956	1			T2	216		T3	84209		T4	81
all_pins[1]	14334956	1			T2	216		T3	84209		T4	81
all_pins[2]	14334956	1			T2	216		T3	84209		T4	81

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	40469373	1			T2	629		T3	240808		T4	226
values[0x1]	2535495	1			T2	19		T3	11819		T4	17
transitions[0x0=>0x1]	2535322	1			T2	19		T3	11819		T4	17
transitions[0x1=>0x0]	2535338	1			T2	19		T3	11819		T4	17

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14285527	1			T2	197		T3	84015		T4	77
all_pins[0]	values[0x1]	49429	1			T2	19		T3	194		T4	4
all_pins[0]	transitions[0x0=>0x1]	49357	1			T2	19		T3	194		T4	4
all_pins[0]	transitions[0x1=>0x0]	2485480	1			T3	11625		T4	13		T6	14822
all_pins[1]	values[0x0]	14334426	1			T2	216		T3	84209		T4	81
all_pins[1]	values[0x1]	530	1			T29	2		T26	2		T54	2
all_pins[1]	transitions[0x0=>0x1]	474	1			T29	2		T26	2		T54	2
all_pins[1]	transitions[0x1=>0x0]	49373	1			T2	19		T3	194		T4	4
all_pins[2]	values[0x0]	11849420	1			T2	216		T3	72584		T4	68
all_pins[2]	values[0x1]	2485536	1			T3	11625		T4	13		T6	14822
all_pins[2]	transitions[0x0=>0x1]	2485491	1			T3	11625		T4	13		T6	14822
all_pins[2]	transitions[0x1=>0x0]	485	1			T29	2		T26	2		T54	2