Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 994 1 T26 7 T54 7 T17 17
all_values[1] 994 1 T26 7 T54 7 T17 17
all_values[2] 994 1 T26 7 T54 7 T17 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1479 1 T26 17 T54 6 T17 24
auto[1] 1503 1 T26 4 T54 15 T17 27


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1050 1 T26 11 T54 9 T17 18
auto[1] 1932 1 T26 10 T54 12 T17 33


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1683 1 T26 12 T54 13 T17 28
auto[1] 1299 1 T26 9 T54 8 T17 23


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 166 1 T26 5 T17 4 T44 1
all_values[0] auto[0] auto[0] auto[1] 74 1 T17 1 T44 1 T111 1
all_values[0] auto[0] auto[1] auto[0] 193 1 T54 5 T17 1 T44 3
all_values[0] auto[0] auto[1] auto[1] 113 1 T17 1 T44 1 T112 2
all_values[0] auto[1] auto[0] auto[1] 209 1 T26 2 T17 5 T44 2
all_values[0] auto[1] auto[1] auto[1] 239 1 T54 2 T17 5 T112 3
all_values[1] auto[0] auto[0] auto[0] 148 1 T54 1 T17 3 T44 3
all_values[1] auto[0] auto[0] auto[1] 125 1 T26 1 T17 2 T44 1
all_values[1] auto[0] auto[1] auto[0] 166 1 T26 2 T54 2 T17 3
all_values[1] auto[0] auto[1] auto[1] 131 1 T54 1 T17 2 T44 1
all_values[1] auto[1] auto[0] auto[1] 213 1 T26 3 T17 5 T44 2
all_values[1] auto[1] auto[1] auto[1] 211 1 T26 1 T54 3 T17 2
all_values[2] auto[0] auto[0] auto[0] 214 1 T26 4 T54 1 T17 4
all_values[2] auto[0] auto[0] auto[1] 97 1 T54 2 T44 2 T112 3
all_values[2] auto[0] auto[1] auto[0] 163 1 T17 3 T44 2 T111 1
all_values[2] auto[0] auto[1] auto[1] 93 1 T54 1 T17 4 T65 3
all_values[2] auto[1] auto[0] auto[1] 233 1 T26 2 T54 2 T44 1
all_values[2] auto[1] auto[1] auto[1] 194 1 T26 1 T54 1 T17 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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