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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.93 92.47 85.16 100.00 76.32 85.98 99.49 69.08


Total test records in report: 737
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T531 /workspace/coverage/default/49.hmac_wipe_secret.3126847807 May 02 02:47:35 PM PDT 24 May 02 02:48:36 PM PDT 24 12921770878 ps
T532 /workspace/coverage/default/9.hmac_burst_wr.457552695 May 02 02:44:39 PM PDT 24 May 02 02:45:01 PM PDT 24 1030757999 ps
T533 /workspace/coverage/default/48.hmac_long_msg.1981283365 May 02 02:47:30 PM PDT 24 May 02 02:48:11 PM PDT 24 2709418933 ps
T534 /workspace/coverage/default/24.hmac_burst_wr.1804775158 May 02 02:45:54 PM PDT 24 May 02 02:46:42 PM PDT 24 13034838942 ps
T535 /workspace/coverage/default/7.hmac_wipe_secret.2245426878 May 02 02:44:31 PM PDT 24 May 02 02:45:07 PM PDT 24 10360856917 ps
T536 /workspace/coverage/default/36.hmac_wipe_secret.33924979 May 02 02:46:40 PM PDT 24 May 02 02:47:18 PM PDT 24 10790487259 ps
T537 /workspace/coverage/default/4.hmac_long_msg.4136175037 May 02 02:44:08 PM PDT 24 May 02 02:44:16 PM PDT 24 1270057784 ps
T538 /workspace/coverage/default/17.hmac_stress_all.3386435993 May 02 02:45:15 PM PDT 24 May 02 02:48:23 PM PDT 24 13567592878 ps
T539 /workspace/coverage/default/48.hmac_back_pressure.1829523752 May 02 02:47:28 PM PDT 24 May 02 02:48:07 PM PDT 24 3849470577 ps
T540 /workspace/coverage/default/47.hmac_stress_all.2078712012 May 02 02:47:30 PM PDT 24 May 02 02:48:18 PM PDT 24 8048514892 ps
T541 /workspace/coverage/default/43.hmac_alert_test.100358673 May 02 02:47:17 PM PDT 24 May 02 02:47:19 PM PDT 24 12943727 ps
T542 /workspace/coverage/default/43.hmac_wipe_secret.1345523164 May 02 02:47:11 PM PDT 24 May 02 02:48:33 PM PDT 24 15688692199 ps
T543 /workspace/coverage/default/26.hmac_burst_wr.22493568 May 02 02:45:57 PM PDT 24 May 02 02:46:20 PM PDT 24 3958788623 ps
T95 /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.2623754938 May 02 02:45:54 PM PDT 24 May 02 03:22:21 PM PDT 24 153610378582 ps
T544 /workspace/coverage/default/35.hmac_alert_test.1842637590 May 02 02:46:36 PM PDT 24 May 02 02:46:37 PM PDT 24 12203688 ps
T545 /workspace/coverage/default/41.hmac_test_hmac_vectors.1735069479 May 02 02:47:03 PM PDT 24 May 02 02:47:06 PM PDT 24 28937003 ps
T546 /workspace/coverage/default/45.hmac_test_hmac_vectors.3163825317 May 02 02:47:22 PM PDT 24 May 02 02:47:24 PM PDT 24 30723882 ps
T547 /workspace/coverage/default/35.hmac_smoke.2769674438 May 02 02:46:31 PM PDT 24 May 02 02:46:38 PM PDT 24 187443705 ps
T548 /workspace/coverage/default/43.hmac_datapath_stress.3983969711 May 02 02:47:22 PM PDT 24 May 02 02:48:57 PM PDT 24 12369228798 ps
T549 /workspace/coverage/default/3.hmac_long_msg.1193210437 May 02 02:44:03 PM PDT 24 May 02 02:44:15 PM PDT 24 676789617 ps
T550 /workspace/coverage/default/0.hmac_stress_all.3555339314 May 02 02:43:49 PM PDT 24 May 02 03:05:24 PM PDT 24 299153977908 ps
T551 /workspace/coverage/default/48.hmac_error.777712416 May 02 02:47:31 PM PDT 24 May 02 02:50:20 PM PDT 24 19666562894 ps
T552 /workspace/coverage/default/13.hmac_test_sha_vectors.2197166829 May 02 02:44:56 PM PDT 24 May 02 02:51:23 PM PDT 24 75957934499 ps
T553 /workspace/coverage/default/12.hmac_stress_all.4186075682 May 02 02:44:51 PM PDT 24 May 02 03:19:30 PM PDT 24 141894339711 ps
T554 /workspace/coverage/default/0.hmac_alert_test.222653781 May 02 02:43:55 PM PDT 24 May 02 02:43:57 PM PDT 24 30842250 ps
T555 /workspace/coverage/default/32.hmac_wipe_secret.3067764161 May 02 02:46:18 PM PDT 24 May 02 02:46:53 PM PDT 24 718157100 ps
T556 /workspace/coverage/default/7.hmac_error.814470455 May 02 02:44:33 PM PDT 24 May 02 02:45:04 PM PDT 24 1722756844 ps
T557 /workspace/coverage/default/21.hmac_burst_wr.3521515842 May 02 02:45:33 PM PDT 24 May 02 02:46:23 PM PDT 24 3898176186 ps
T558 /workspace/coverage/default/27.hmac_test_hmac_vectors.3394105528 May 02 02:46:03 PM PDT 24 May 02 02:46:15 PM PDT 24 269663162 ps
T559 /workspace/coverage/default/36.hmac_stress_all.1972967906 May 02 02:46:43 PM PDT 24 May 02 02:46:51 PM PDT 24 4283104999 ps
T560 /workspace/coverage/default/28.hmac_burst_wr.3613002413 May 02 02:46:03 PM PDT 24 May 02 02:46:38 PM PDT 24 4704363222 ps
T561 /workspace/coverage/default/4.hmac_test_hmac_vectors.1537337561 May 02 02:44:18 PM PDT 24 May 02 02:44:20 PM PDT 24 258446320 ps
T562 /workspace/coverage/default/0.hmac_error.2395336807 May 02 02:43:50 PM PDT 24 May 02 02:45:57 PM PDT 24 8604747229 ps
T563 /workspace/coverage/default/8.hmac_test_hmac_vectors.3401500834 May 02 02:44:36 PM PDT 24 May 02 02:44:38 PM PDT 24 36416012 ps
T564 /workspace/coverage/default/11.hmac_stress_all.3346439313 May 02 02:44:45 PM PDT 24 May 02 02:55:57 PM PDT 24 53449612180 ps
T565 /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2221162652 May 02 02:44:54 PM PDT 24 May 02 03:03:50 PM PDT 24 52431253283 ps
T566 /workspace/coverage/default/37.hmac_error.2003101594 May 02 02:46:44 PM PDT 24 May 02 02:48:51 PM PDT 24 16960674673 ps
T567 /workspace/coverage/default/21.hmac_smoke.4000381490 May 02 02:45:37 PM PDT 24 May 02 02:45:46 PM PDT 24 444349271 ps
T568 /workspace/coverage/default/2.hmac_datapath_stress.1109956318 May 02 02:44:00 PM PDT 24 May 02 02:44:39 PM PDT 24 1414580553 ps
T569 /workspace/coverage/default/40.hmac_stress_all.159164013 May 02 02:46:58 PM PDT 24 May 02 02:57:48 PM PDT 24 34622508282 ps
T570 /workspace/coverage/default/24.hmac_datapath_stress.2783785286 May 02 02:45:53 PM PDT 24 May 02 02:46:38 PM PDT 24 866893607 ps
T571 /workspace/coverage/default/26.hmac_back_pressure.615615403 May 02 02:45:57 PM PDT 24 May 02 02:46:49 PM PDT 24 8666768895 ps
T572 /workspace/coverage/default/12.hmac_back_pressure.2670318739 May 02 02:44:52 PM PDT 24 May 02 02:46:01 PM PDT 24 21735479957 ps
T573 /workspace/coverage/default/4.hmac_stress_all.1627654308 May 02 02:44:19 PM PDT 24 May 02 02:45:48 PM PDT 24 1465442715 ps
T574 /workspace/coverage/default/38.hmac_back_pressure.2591834101 May 02 02:46:51 PM PDT 24 May 02 02:47:31 PM PDT 24 9500681372 ps
T575 /workspace/coverage/default/27.hmac_back_pressure.3551923450 May 02 02:46:08 PM PDT 24 May 02 02:47:07 PM PDT 24 17534669080 ps
T576 /workspace/coverage/default/44.hmac_burst_wr.1193959734 May 02 02:47:15 PM PDT 24 May 02 02:47:51 PM PDT 24 11678423099 ps
T577 /workspace/coverage/default/47.hmac_smoke.1176115520 May 02 02:47:33 PM PDT 24 May 02 02:47:36 PM PDT 24 478357523 ps
T578 /workspace/coverage/default/12.hmac_test_sha_vectors.2762179500 May 02 02:44:51 PM PDT 24 May 02 02:53:36 PM PDT 24 47168507512 ps
T579 /workspace/coverage/default/40.hmac_burst_wr.3255799153 May 02 02:46:59 PM PDT 24 May 02 02:47:40 PM PDT 24 806818364 ps
T580 /workspace/coverage/default/28.hmac_back_pressure.538226351 May 02 02:46:02 PM PDT 24 May 02 02:46:50 PM PDT 24 1020591662 ps
T581 /workspace/coverage/default/19.hmac_wipe_secret.3154981514 May 02 02:45:24 PM PDT 24 May 02 02:47:09 PM PDT 24 7974533707 ps
T582 /workspace/coverage/default/13.hmac_long_msg.1997072373 May 02 02:44:53 PM PDT 24 May 02 02:45:00 PM PDT 24 84660359 ps
T583 /workspace/coverage/default/47.hmac_back_pressure.1172397456 May 02 02:47:28 PM PDT 24 May 02 02:48:28 PM PDT 24 15587870679 ps
T584 /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.3264592755 May 02 02:48:30 PM PDT 24 May 02 02:55:31 PM PDT 24 33120313736 ps
T585 /workspace/coverage/default/18.hmac_stress_all.3109405232 May 02 02:45:23 PM PDT 24 May 02 03:07:20 PM PDT 24 404479091514 ps
T586 /workspace/coverage/default/8.hmac_stress_all.497518691 May 02 02:44:42 PM PDT 24 May 02 02:47:35 PM PDT 24 18964819318 ps
T587 /workspace/coverage/default/1.hmac_test_hmac_vectors.2682135276 May 02 02:44:00 PM PDT 24 May 02 02:44:02 PM PDT 24 283206655 ps
T588 /workspace/coverage/default/19.hmac_back_pressure.987449295 May 02 02:45:22 PM PDT 24 May 02 02:46:06 PM PDT 24 3548958752 ps
T589 /workspace/coverage/default/12.hmac_wipe_secret.36458687 May 02 02:44:54 PM PDT 24 May 02 02:45:09 PM PDT 24 918610121 ps
T590 /workspace/coverage/default/22.hmac_smoke.3353895866 May 02 02:46:10 PM PDT 24 May 02 02:46:23 PM PDT 24 282043647 ps
T591 /workspace/coverage/default/6.hmac_wipe_secret.2883177769 May 02 02:44:27 PM PDT 24 May 02 02:45:54 PM PDT 24 8503996871 ps
T592 /workspace/coverage/default/38.hmac_burst_wr.2071623912 May 02 02:46:49 PM PDT 24 May 02 02:47:42 PM PDT 24 2103092210 ps
T593 /workspace/coverage/default/38.hmac_test_sha_vectors.2592261376 May 02 02:46:51 PM PDT 24 May 02 02:53:36 PM PDT 24 9917130010 ps
T594 /workspace/coverage/default/42.hmac_back_pressure.3139909371 May 02 02:47:05 PM PDT 24 May 02 02:47:42 PM PDT 24 3404156186 ps
T595 /workspace/coverage/default/18.hmac_test_sha_vectors.1264658445 May 02 02:45:15 PM PDT 24 May 02 02:53:47 PM PDT 24 100162345036 ps
T596 /workspace/coverage/default/33.hmac_datapath_stress.2928775821 May 02 02:46:24 PM PDT 24 May 02 02:47:27 PM PDT 24 1076038852 ps
T597 /workspace/coverage/default/16.hmac_back_pressure.4168587562 May 02 02:45:04 PM PDT 24 May 02 02:45:24 PM PDT 24 1984462853 ps
T598 /workspace/coverage/default/35.hmac_error.2792596750 May 02 02:46:28 PM PDT 24 May 02 02:49:50 PM PDT 24 14290551141 ps
T599 /workspace/coverage/default/48.hmac_burst_wr.2081788628 May 02 02:47:29 PM PDT 24 May 02 02:48:36 PM PDT 24 5551549679 ps
T600 /workspace/coverage/default/37.hmac_back_pressure.1400369298 May 02 02:46:42 PM PDT 24 May 02 02:47:22 PM PDT 24 4676911469 ps
T601 /workspace/coverage/default/3.hmac_error.3313478153 May 02 02:44:09 PM PDT 24 May 02 02:46:04 PM PDT 24 16472603613 ps
T55 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2075006090 May 02 02:34:10 PM PDT 24 May 02 02:34:12 PM PDT 24 45782229 ps
T602 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2523622278 May 02 02:34:18 PM PDT 24 May 02 02:34:20 PM PDT 24 37966888 ps
T603 /workspace/coverage/cover_reg_top/49.hmac_intr_test.914995254 May 02 02:35:14 PM PDT 24 May 02 02:35:17 PM PDT 24 26318733 ps
T56 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2426929730 May 02 02:35:09 PM PDT 24 May 02 02:35:12 PM PDT 24 27581727 ps
T604 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3286867811 May 02 02:35:21 PM PDT 24 May 02 02:35:24 PM PDT 24 36552475 ps
T605 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1547689626 May 02 02:34:33 PM PDT 24 May 02 02:34:34 PM PDT 24 45388110 ps
T606 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1894918172 May 02 02:35:15 PM PDT 24 May 02 02:35:18 PM PDT 24 18577997 ps
T57 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2807949755 May 02 02:34:33 PM PDT 24 May 02 02:34:38 PM PDT 24 103997628 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3484669648 May 02 02:34:03 PM PDT 24 May 02 02:34:05 PM PDT 24 85146805 ps
T607 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2638755359 May 02 02:34:09 PM PDT 24 May 02 02:34:11 PM PDT 24 77023915 ps
T608 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1042289050 May 02 02:35:19 PM PDT 24 May 02 02:35:22 PM PDT 24 13213307 ps
T609 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2010725450 May 02 02:34:26 PM PDT 24 May 02 02:34:28 PM PDT 24 39384094 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1292981455 May 02 02:34:17 PM PDT 24 May 02 02:34:26 PM PDT 24 300252675 ps
T610 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1887843781 May 02 02:34:50 PM PDT 24 May 02 02:34:53 PM PDT 24 84618886 ps
T611 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.690207597 May 02 02:34:18 PM PDT 24 May 02 02:34:30 PM PDT 24 727954664 ps
T612 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4059456532 May 02 02:34:48 PM PDT 24 May 02 02:34:50 PM PDT 24 157372407 ps
T613 /workspace/coverage/cover_reg_top/25.hmac_intr_test.192323459 May 02 02:35:17 PM PDT 24 May 02 02:35:20 PM PDT 24 32496579 ps
T614 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3083736730 May 02 02:35:15 PM PDT 24 May 02 02:35:19 PM PDT 24 43957702 ps
T51 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4121008485 May 02 02:34:18 PM PDT 24 May 02 02:34:21 PM PDT 24 87693440 ps
T52 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2316314365 May 02 02:34:55 PM PDT 24 May 02 02:34:59 PM PDT 24 309818241 ps
T615 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1418906849 May 02 02:34:39 PM PDT 24 May 02 02:34:42 PM PDT 24 237425765 ps
T616 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3566375965 May 02 02:34:09 PM PDT 24 May 02 02:34:12 PM PDT 24 179869719 ps
T617 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2981960199 May 02 02:34:33 PM PDT 24 May 02 02:34:38 PM PDT 24 321744476 ps
T53 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1500623525 May 02 02:34:31 PM PDT 24 May 02 02:34:35 PM PDT 24 411455089 ps
T618 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.778170051 May 02 02:34:48 PM PDT 24 May 02 02:46:35 PM PDT 24 64745986296 ps
T619 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.104540090 May 02 02:34:24 PM PDT 24 May 02 02:34:27 PM PDT 24 104641801 ps
T620 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.591605235 May 02 02:34:43 PM PDT 24 May 02 02:34:46 PM PDT 24 104950208 ps
T621 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3996372846 May 02 02:34:57 PM PDT 24 May 02 02:35:02 PM PDT 24 286041121 ps
T98 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3146793462 May 02 02:34:51 PM PDT 24 May 02 02:34:53 PM PDT 24 45698181 ps
T622 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2833602744 May 02 02:34:13 PM PDT 24 May 02 02:34:14 PM PDT 24 17043987 ps
T116 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.326435414 May 02 02:34:03 PM PDT 24 May 02 02:34:08 PM PDT 24 1543878114 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2002936335 May 02 02:34:25 PM PDT 24 May 02 02:34:34 PM PDT 24 2210077556 ps
T623 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2731133751 May 02 02:34:58 PM PDT 24 May 02 02:35:03 PM PDT 24 400819602 ps
T624 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2763797133 May 02 02:34:25 PM PDT 24 May 02 02:34:32 PM PDT 24 2222730558 ps
T625 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3829342412 May 02 02:35:05 PM PDT 24 May 02 02:35:09 PM PDT 24 107579241 ps
T626 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2063170109 May 02 02:34:13 PM PDT 24 May 02 02:34:15 PM PDT 24 14388177 ps
T627 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1668401060 May 02 02:34:49 PM PDT 24 May 02 02:34:53 PM PDT 24 100217065 ps
T628 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3255643699 May 02 02:35:19 PM PDT 24 May 02 02:35:22 PM PDT 24 45755925 ps
T629 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.411167921 May 02 02:34:16 PM PDT 24 May 02 02:34:18 PM PDT 24 18613289 ps
T630 /workspace/coverage/cover_reg_top/44.hmac_intr_test.144107787 May 02 02:35:15 PM PDT 24 May 02 02:35:18 PM PDT 24 17597236 ps
T631 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1397112562 May 02 02:34:56 PM PDT 24 May 02 02:34:59 PM PDT 24 42662589 ps
T632 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3877495526 May 02 02:35:13 PM PDT 24 May 02 02:35:16 PM PDT 24 25176698 ps
T633 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1807226118 May 02 02:34:33 PM PDT 24 May 02 02:34:49 PM PDT 24 1055451893 ps
T100 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2579570916 May 02 02:34:43 PM PDT 24 May 02 02:34:45 PM PDT 24 36543835 ps
T634 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1753606970 May 02 02:35:13 PM PDT 24 May 02 02:35:16 PM PDT 24 23213374 ps
T635 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.310092939 May 02 02:34:09 PM PDT 24 May 02 02:34:13 PM PDT 24 228411109 ps
T636 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1961093449 May 02 02:35:06 PM PDT 24 May 02 02:35:11 PM PDT 24 87794384 ps
T637 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2555211797 May 02 02:34:40 PM PDT 24 May 02 02:34:44 PM PDT 24 42754355 ps
T638 /workspace/coverage/cover_reg_top/10.hmac_intr_test.746838359 May 02 02:34:49 PM PDT 24 May 02 02:34:52 PM PDT 24 11806578 ps
T113 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3355159638 May 02 02:34:40 PM PDT 24 May 02 02:34:46 PM PDT 24 3369306814 ps
T114 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3139609152 May 02 02:34:10 PM PDT 24 May 02 02:34:15 PM PDT 24 835021578 ps
T639 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2306486737 May 02 02:35:05 PM PDT 24 May 02 02:35:08 PM PDT 24 18634784 ps
T117 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2053257965 May 02 02:34:48 PM PDT 24 May 02 02:34:54 PM PDT 24 1083035021 ps
T101 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4019183646 May 02 02:34:19 PM PDT 24 May 02 02:34:21 PM PDT 24 33035770 ps
T640 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.969702287 May 02 02:34:18 PM PDT 24 May 02 02:34:30 PM PDT 24 1076246430 ps
T58 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2939640894 May 02 02:34:46 PM PDT 24 May 02 02:34:50 PM PDT 24 190252008 ps
T641 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1181356116 May 02 02:34:47 PM PDT 24 May 02 02:34:49 PM PDT 24 20265397 ps
T642 /workspace/coverage/cover_reg_top/8.hmac_intr_test.4218510357 May 02 02:34:40 PM PDT 24 May 02 02:34:42 PM PDT 24 110953998 ps
T643 /workspace/coverage/cover_reg_top/12.hmac_intr_test.199494477 May 02 02:34:48 PM PDT 24 May 02 02:34:50 PM PDT 24 14450910 ps
T644 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.271651223 May 02 02:34:18 PM PDT 24 May 02 02:34:20 PM PDT 24 112556535 ps
T645 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2446766949 May 02 02:34:32 PM PDT 24 May 02 02:34:33 PM PDT 24 64582849 ps
T102 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4001578233 May 02 02:35:05 PM PDT 24 May 02 02:35:09 PM PDT 24 19488524 ps
T646 /workspace/coverage/cover_reg_top/27.hmac_intr_test.812544222 May 02 02:35:12 PM PDT 24 May 02 02:35:15 PM PDT 24 95950284 ps
T118 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2082865819 May 02 02:35:06 PM PDT 24 May 02 02:35:13 PM PDT 24 248290595 ps
T647 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3752427248 May 02 02:35:09 PM PDT 24 May 02 02:35:13 PM PDT 24 305424034 ps
T648 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.620669894 May 02 02:34:56 PM PDT 24 May 02 02:35:00 PM PDT 24 83509218 ps
T649 /workspace/coverage/cover_reg_top/16.hmac_intr_test.595136994 May 02 02:34:58 PM PDT 24 May 02 02:35:01 PM PDT 24 12079786 ps
T650 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1685279222 May 02 02:35:07 PM PDT 24 May 02 02:35:10 PM PDT 24 29544866 ps
T651 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1250120397 May 02 02:35:06 PM PDT 24 May 02 02:35:09 PM PDT 24 40338215 ps
T652 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2157619260 May 02 02:34:58 PM PDT 24 May 02 02:35:01 PM PDT 24 68586631 ps
T653 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.281747097 May 02 02:34:57 PM PDT 24 May 02 02:35:00 PM PDT 24 30810313 ps
T654 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1848518588 May 02 02:35:16 PM PDT 24 May 02 02:35:19 PM PDT 24 11421147 ps
T655 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4229200892 May 02 02:34:47 PM PDT 24 May 02 02:34:52 PM PDT 24 729002542 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4142839266 May 02 02:34:40 PM PDT 24 May 02 02:34:44 PM PDT 24 1150650523 ps
T657 /workspace/coverage/cover_reg_top/39.hmac_intr_test.170219681 May 02 02:35:16 PM PDT 24 May 02 02:35:19 PM PDT 24 19880423 ps
T658 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3436645953 May 02 02:34:49 PM PDT 24 May 02 02:34:54 PM PDT 24 1204886888 ps
T659 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2924438652 May 02 02:34:51 PM PDT 24 May 02 02:39:30 PM PDT 24 50617315953 ps
T121 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1398668761 May 02 02:34:51 PM PDT 24 May 02 02:34:55 PM PDT 24 395441111 ps
T660 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.65069441 May 02 02:34:56 PM PDT 24 May 02 02:34:59 PM PDT 24 174839349 ps
T661 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.75904234 May 02 02:34:10 PM PDT 24 May 02 02:34:14 PM PDT 24 363406575 ps
T662 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1099719817 May 02 02:34:40 PM PDT 24 May 02 02:34:46 PM PDT 24 209818525 ps
T120 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2491867304 May 02 02:34:57 PM PDT 24 May 02 02:35:02 PM PDT 24 417495090 ps
T663 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1490793819 May 02 02:34:50 PM PDT 24 May 02 02:34:56 PM PDT 24 73480901 ps
T664 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1302751718 May 02 02:35:16 PM PDT 24 May 02 02:35:19 PM PDT 24 27352055 ps
T665 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1168666925 May 02 02:34:31 PM PDT 24 May 02 02:34:34 PM PDT 24 260908384 ps
T115 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.353477897 May 02 02:34:56 PM PDT 24 May 02 02:35:03 PM PDT 24 271812249 ps
T666 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2756191552 May 02 02:35:05 PM PDT 24 May 02 02:35:10 PM PDT 24 455160801 ps
T119 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1575875074 May 02 02:34:50 PM PDT 24 May 02 02:34:54 PM PDT 24 661397557 ps
T667 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3778720399 May 02 02:34:26 PM PDT 24 May 02 02:34:27 PM PDT 24 74566323 ps
T668 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1741939651 May 02 02:34:32 PM PDT 24 May 02 02:34:36 PM PDT 24 560383484 ps
T669 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1841371425 May 02 02:34:26 PM PDT 24 May 02 02:34:30 PM PDT 24 77888718 ps
T670 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.706188364 May 02 02:35:04 PM PDT 24 May 02 02:35:10 PM PDT 24 236673268 ps
T671 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4230942399 May 02 02:35:18 PM PDT 24 May 02 02:35:21 PM PDT 24 15861741 ps
T672 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1856819007 May 02 02:34:41 PM PDT 24 May 02 02:34:45 PM PDT 24 96236462 ps
T673 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.191305185 May 02 02:34:55 PM PDT 24 May 02 02:35:00 PM PDT 24 194728779 ps
T674 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3039088950 May 02 02:35:13 PM PDT 24 May 02 02:35:16 PM PDT 24 14775383 ps
T675 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1931237764 May 02 02:34:17 PM PDT 24 May 02 02:34:20 PM PDT 24 24849757 ps
T103 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1558229036 May 02 02:34:17 PM PDT 24 May 02 02:34:21 PM PDT 24 231292939 ps
T104 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1352336602 May 02 02:34:47 PM PDT 24 May 02 02:34:50 PM PDT 24 34103255 ps
T676 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.516453752 May 02 02:34:48 PM PDT 24 May 02 02:34:50 PM PDT 24 33865085 ps
T677 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1766561504 May 02 02:35:15 PM PDT 24 May 02 02:35:18 PM PDT 24 51219575 ps
T678 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1873259719 May 02 02:35:06 PM PDT 24 May 02 02:35:12 PM PDT 24 75839100 ps
T105 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2657678950 May 02 02:34:33 PM PDT 24 May 02 02:34:35 PM PDT 24 17829398 ps
T679 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4054467867 May 02 02:34:43 PM PDT 24 May 02 02:34:45 PM PDT 24 38945869 ps
T680 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3355477825 May 02 02:34:08 PM PDT 24 May 02 02:34:24 PM PDT 24 2063630006 ps
T681 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2510341575 May 02 02:34:56 PM PDT 24 May 02 02:34:59 PM PDT 24 32320436 ps
T682 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2674723981 May 02 02:34:34 PM PDT 24 May 02 02:34:37 PM PDT 24 28371951 ps
T683 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.877749355 May 02 02:34:51 PM PDT 24 May 02 02:34:57 PM PDT 24 229798190 ps
T684 /workspace/coverage/cover_reg_top/30.hmac_intr_test.336828939 May 02 02:35:14 PM PDT 24 May 02 02:35:18 PM PDT 24 55823229 ps
T685 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2888869033 May 02 02:34:19 PM PDT 24 May 02 02:44:31 PM PDT 24 271286187078 ps
T686 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3561052464 May 02 02:34:48 PM PDT 24 May 02 02:34:52 PM PDT 24 737632302 ps
T687 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3650772859 May 02 02:35:07 PM PDT 24 May 02 02:35:10 PM PDT 24 18704399 ps
T688 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2423037479 May 02 02:34:04 PM PDT 24 May 02 02:34:07 PM PDT 24 152989294 ps
T689 /workspace/coverage/cover_reg_top/22.hmac_intr_test.901882618 May 02 02:35:05 PM PDT 24 May 02 02:35:08 PM PDT 24 64933906 ps
T690 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3452768540 May 02 02:35:07 PM PDT 24 May 02 02:35:10 PM PDT 24 35218370 ps
T691 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3845078295 May 02 02:34:35 PM PDT 24 May 02 02:34:38 PM PDT 24 130077143 ps
T692 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1262974938 May 02 02:34:49 PM PDT 24 May 02 02:34:54 PM PDT 24 1973422617 ps
T693 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1594928462 May 02 02:34:46 PM PDT 24 May 02 02:34:49 PM PDT 24 145121077 ps
T694 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1031213521 May 02 02:34:31 PM PDT 24 May 02 02:34:32 PM PDT 24 59367832 ps
T695 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.615950054 May 02 02:34:34 PM PDT 24 May 02 02:34:37 PM PDT 24 38726716 ps
T696 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1203027864 May 02 02:35:14 PM PDT 24 May 02 02:35:17 PM PDT 24 151682313 ps
T106 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2818008895 May 02 02:34:32 PM PDT 24 May 02 02:34:34 PM PDT 24 77155015 ps
T697 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3108851874 May 02 02:34:51 PM PDT 24 May 02 02:34:53 PM PDT 24 22258973 ps
T698 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2454640754 May 02 02:35:13 PM PDT 24 May 02 02:35:16 PM PDT 24 26097903 ps
T107 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.93116918 May 02 02:34:56 PM PDT 24 May 02 02:34:59 PM PDT 24 68576015 ps
T699 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3920579780 May 02 02:34:55 PM PDT 24 May 02 02:34:59 PM PDT 24 155574395 ps
T700 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.745432734 May 02 02:35:06 PM PDT 24 May 02 02:35:09 PM PDT 24 204329851 ps
T701 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3980738315 May 02 02:34:46 PM PDT 24 May 02 02:34:50 PM PDT 24 154089833 ps
T702 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3181215885 May 02 02:35:05 PM PDT 24 May 02 02:35:09 PM PDT 24 59699779 ps
T703 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1506554880 May 02 02:34:56 PM PDT 24 May 02 02:34:58 PM PDT 24 20007388 ps
T704 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3295395061 May 02 02:35:05 PM PDT 24 May 02 02:35:11 PM PDT 24 154554030 ps
T705 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4228275930 May 02 02:34:56 PM PDT 24 May 02 02:35:00 PM PDT 24 32195662 ps
T706 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.39134464 May 02 02:35:10 PM PDT 24 May 02 02:35:14 PM PDT 24 86784932 ps
T707 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2040654005 May 02 02:35:17 PM PDT 24 May 02 02:35:21 PM PDT 24 34762753 ps
T708 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1092237995 May 02 02:34:41 PM PDT 24 May 02 02:34:45 PM PDT 24 92993706 ps
T709 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2999572352 May 02 02:35:16 PM PDT 24 May 02 02:35:20 PM PDT 24 14053592 ps
T710 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2227839936 May 02 02:34:50 PM PDT 24 May 02 02:34:53 PM PDT 24 13025841 ps
T711 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.689816522 May 02 02:34:50 PM PDT 24 May 02 02:34:53 PM PDT 24 20080050 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3716565557 May 02 02:34:35 PM PDT 24 May 02 02:34:42 PM PDT 24 423300317 ps
T712 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4602213 May 02 02:34:33 PM PDT 24 May 02 02:34:36 PM PDT 24 340564902 ps
T713 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4163391285 May 02 02:34:25 PM PDT 24 May 02 02:34:29 PM PDT 24 156796750 ps
T714 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3009538599 May 02 02:34:29 PM PDT 24 May 02 02:34:31 PM PDT 24 45829706 ps
T715 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3364527728 May 02 02:34:56 PM PDT 24 May 02 02:35:01 PM PDT 24 188730446 ps
T716 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3965717007 May 02 02:34:18 PM PDT 24 May 02 02:34:21 PM PDT 24 32248731 ps
T717 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1634116890 May 02 02:34:47 PM PDT 24 May 02 02:34:49 PM PDT 24 35862279 ps
T718 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.237736390 May 02 02:34:33 PM PDT 24 May 02 02:34:36 PM PDT 24 110434645 ps
T719 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3587455161 May 02 02:35:06 PM PDT 24 May 02 02:35:12 PM PDT 24 491654025 ps
T720 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.851826761 May 02 02:34:41 PM PDT 24 May 02 02:34:43 PM PDT 24 25690094 ps
T721 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1984889382 May 02 02:35:14 PM PDT 24 May 02 02:35:17 PM PDT 24 10853709 ps
T722 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1522986309 May 02 02:34:43 PM PDT 24 May 02 02:34:45 PM PDT 24 47879831 ps
T723 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2251094972 May 02 02:35:09 PM PDT 24 May 02 02:35:12 PM PDT 24 57744352 ps
T724 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.297068763 May 02 02:35:05 PM PDT 24 May 02 02:48:47 PM PDT 24 55141490640 ps
T725 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2839318423 May 02 02:34:39 PM PDT 24 May 02 02:34:42 PM PDT 24 325595257 ps
T726 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3028681117 May 02 02:35:09 PM PDT 24 May 02 02:35:12 PM PDT 24 127021090 ps
T727 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2028628826 May 02 02:35:13 PM PDT 24 May 02 02:35:16 PM PDT 24 24897203 ps
T728 /workspace/coverage/cover_reg_top/0.hmac_intr_test.11515757 May 02 02:34:01 PM PDT 24 May 02 02:34:04 PM PDT 24 22161273 ps
T729 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2458738797 May 02 02:35:07 PM PDT 24 May 02 02:35:10 PM PDT 24 13543411 ps
T730 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3387411610 May 02 02:34:32 PM PDT 24 May 02 02:34:34 PM PDT 24 22849583 ps
T731 /workspace/coverage/cover_reg_top/3.hmac_intr_test.414500781 May 02 02:34:28 PM PDT 24 May 02 02:34:30 PM PDT 24 165080804 ps
T732 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2784444134 May 02 02:34:09 PM PDT 24 May 02 02:34:10 PM PDT 24 16088534 ps
T733 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.84601915 May 02 02:34:46 PM PDT 24 May 02 02:34:48 PM PDT 24 21486157 ps
T734 /workspace/coverage/cover_reg_top/31.hmac_intr_test.636896684 May 02 02:35:12 PM PDT 24 May 02 02:35:15 PM PDT 24 16291513 ps
T735 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1615798278 May 02 02:35:09 PM PDT 24 May 02 02:35:12 PM PDT 24 14936696 ps
T736 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3155538001 May 02 02:34:47 PM PDT 24 May 02 02:34:51 PM PDT 24 46629879 ps
T737 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2729813113 May 02 02:34:31 PM PDT 24 May 02 02:34:36 PM PDT 24 1798743492 ps

Test location /workspace/coverage/default/33.hmac_error.160394423
Short name T20
Test name
Test status
Simulation time 35313260189 ps
CPU time 236.16 seconds
Started May 02 02:46:22 PM PDT 24
Finished May 02 02:50:19 PM PDT 24
Peak memory 199752 kb
Host smart-e78b384f-0a39-4f38-a0f4-23a5a0098a3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160394423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.160394423
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.2520407734
Short name T11
Test name
Test status
Simulation time 50098806344 ps
CPU time 1911.67 seconds
Started May 02 02:47:56 PM PDT 24
Finished May 02 03:19:50 PM PDT 24
Peak memory 248912 kb
Host smart-acc400b6-5c48-447e-a8f0-df3d3cb10f39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520407734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.2520407734
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3846745146
Short name T26
Test name
Test status
Simulation time 5023220326 ps
CPU time 305.27 seconds
Started May 02 02:46:37 PM PDT 24
Finished May 02 02:51:44 PM PDT 24
Peak memory 199720 kb
Host smart-be392f08-a29d-424a-8f9c-137759ebe9ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846745146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3846745146
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2798946301
Short name T27
Test name
Test status
Simulation time 132566014 ps
CPU time 0.88 seconds
Started May 02 02:43:54 PM PDT 24
Finished May 02 02:43:55 PM PDT 24
Peak memory 218088 kb
Host smart-393715ff-682d-4c83-a023-5ed660b528b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798946301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2798946301
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.335982729
Short name T5
Test name
Test status
Simulation time 12188726272 ps
CPU time 50.94 seconds
Started May 02 02:46:59 PM PDT 24
Finished May 02 02:47:53 PM PDT 24
Peak memory 218868 kb
Host smart-26132c28-9dd6-467c-8dad-3c6124eef2d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335982729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.335982729
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2030424062
Short name T16
Test name
Test status
Simulation time 48222040427 ps
CPU time 1198.03 seconds
Started May 02 02:47:03 PM PDT 24
Finished May 02 03:07:04 PM PDT 24
Peak memory 241724 kb
Host smart-7bdee6fc-85b2-489e-99d2-7ca0848656f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030424062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2030424062
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4121008485
Short name T51
Test name
Test status
Simulation time 87693440 ps
CPU time 1.69 seconds
Started May 02 02:34:18 PM PDT 24
Finished May 02 02:34:21 PM PDT 24
Peak memory 199340 kb
Host smart-1a2b2715-fa56-4175-913a-3b53564db26d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121008485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4121008485
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.304188275
Short name T110
Test name
Test status
Simulation time 1381878646 ps
CPU time 77.53 seconds
Started May 02 02:45:21 PM PDT 24
Finished May 02 02:46:40 PM PDT 24
Peak memory 199612 kb
Host smart-455e54e1-dbc2-4a2e-9011-122e24ebeb2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304188275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.304188275
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2653636172
Short name T9
Test name
Test status
Simulation time 11878937521 ps
CPU time 614.65 seconds
Started May 02 02:44:23 PM PDT 24
Finished May 02 02:54:39 PM PDT 24
Peak memory 224372 kb
Host smart-bde12ef7-6f56-4391-9162-405df3867723
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653636172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2653636172
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_error.3461389897
Short name T32
Test name
Test status
Simulation time 3119819424 ps
CPU time 175.94 seconds
Started May 02 02:44:04 PM PDT 24
Finished May 02 02:47:01 PM PDT 24
Peak memory 199512 kb
Host smart-ef5229d1-9808-479f-8506-11d8a300e687
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461389897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3461389897
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2082865819
Short name T118
Test name
Test status
Simulation time 248290595 ps
CPU time 4.02 seconds
Started May 02 02:35:06 PM PDT 24
Finished May 02 02:35:13 PM PDT 24
Peak memory 199284 kb
Host smart-087f1cc9-8d3c-43f2-b4a1-9e17ff4288b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082865819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2082865819
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3793170408
Short name T41
Test name
Test status
Simulation time 777249417220 ps
CPU time 2573.91 seconds
Started May 02 02:45:58 PM PDT 24
Finished May 02 03:28:59 PM PDT 24
Peak memory 213736 kb
Host smart-dc79f896-f3f4-4e91-b6ac-edf920ca6ee7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793170408 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3793170408
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_alert_test.210954353
Short name T179
Test name
Test status
Simulation time 162961204 ps
CPU time 0.56 seconds
Started May 02 02:45:18 PM PDT 24
Finished May 02 02:45:20 PM PDT 24
Peak memory 195032 kb
Host smart-13f4f8b0-5136-45f0-beab-2322b6ce2164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210954353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.210954353
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.353477897
Short name T115
Test name
Test status
Simulation time 271812249 ps
CPU time 4.56 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:35:03 PM PDT 24
Peak memory 199316 kb
Host smart-f030da59-80a1-4c6c-b9b9-971c36d72eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353477897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.353477897
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3484669648
Short name T96
Test name
Test status
Simulation time 85146805 ps
CPU time 0.77 seconds
Started May 02 02:34:03 PM PDT 24
Finished May 02 02:34:05 PM PDT 24
Peak memory 197144 kb
Host smart-db5c9044-fd23-4427-9494-397284b5b442
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484669648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3484669648
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/0.hmac_error.2395336807
Short name T562
Test name
Test status
Simulation time 8604747229 ps
CPU time 125.26 seconds
Started May 02 02:43:50 PM PDT 24
Finished May 02 02:45:57 PM PDT 24
Peak memory 199636 kb
Host smart-76c0c5c1-c7c7-4f81-b14a-71b9a460870a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395336807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2395336807
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2939640894
Short name T58
Test name
Test status
Simulation time 190252008 ps
CPU time 3.15 seconds
Started May 02 02:34:46 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 199296 kb
Host smart-3d472b79-4f5b-4214-8d45-b51c07f29fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939640894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2939640894
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.4116172334
Short name T40
Test name
Test status
Simulation time 60045273488 ps
CPU time 156.54 seconds
Started May 02 02:44:46 PM PDT 24
Finished May 02 02:47:25 PM PDT 24
Peak memory 216212 kb
Host smart-6e99b00d-a484-40f5-863e-217bef8992dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116172334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.4116172334
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.310092939
Short name T635
Test name
Test status
Simulation time 228411109 ps
CPU time 3.08 seconds
Started May 02 02:34:09 PM PDT 24
Finished May 02 02:34:13 PM PDT 24
Peak memory 198140 kb
Host smart-45c480f8-0a02-41da-a51e-d4ab1e07db0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310092939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.310092939
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3355477825
Short name T680
Test name
Test status
Simulation time 2063630006 ps
CPU time 15.42 seconds
Started May 02 02:34:08 PM PDT 24
Finished May 02 02:34:24 PM PDT 24
Peak memory 199204 kb
Host smart-28433b21-531e-4d66-b02a-7ac04ef0ecb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355477825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3355477825
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2075006090
Short name T55
Test name
Test status
Simulation time 45782229 ps
CPU time 1.24 seconds
Started May 02 02:34:10 PM PDT 24
Finished May 02 02:34:12 PM PDT 24
Peak memory 199256 kb
Host smart-79c94b9a-ac23-48d7-902c-2c1e8ce89c9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075006090 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2075006090
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2063170109
Short name T626
Test name
Test status
Simulation time 14388177 ps
CPU time 0.8 seconds
Started May 02 02:34:13 PM PDT 24
Finished May 02 02:34:15 PM PDT 24
Peak memory 198440 kb
Host smart-81d0f14f-efcb-4e6c-b2a8-f3e9e3d1d985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063170109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2063170109
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.11515757
Short name T728
Test name
Test status
Simulation time 22161273 ps
CPU time 0.57 seconds
Started May 02 02:34:01 PM PDT 24
Finished May 02 02:34:04 PM PDT 24
Peak memory 194080 kb
Host smart-71b2e877-dd01-49bf-9bdc-c21784683a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11515757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.11515757
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3566375965
Short name T616
Test name
Test status
Simulation time 179869719 ps
CPU time 1.62 seconds
Started May 02 02:34:09 PM PDT 24
Finished May 02 02:34:12 PM PDT 24
Peak memory 199336 kb
Host smart-69610d93-4a73-44a4-82d3-814572a6255e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566375965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3566375965
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2423037479
Short name T688
Test name
Test status
Simulation time 152989294 ps
CPU time 1.59 seconds
Started May 02 02:34:04 PM PDT 24
Finished May 02 02:34:07 PM PDT 24
Peak memory 199400 kb
Host smart-d6b62b25-a81a-426c-933f-cfb80204814b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423037479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2423037479
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.326435414
Short name T116
Test name
Test status
Simulation time 1543878114 ps
CPU time 2.95 seconds
Started May 02 02:34:03 PM PDT 24
Finished May 02 02:34:08 PM PDT 24
Peak memory 199316 kb
Host smart-e049efc9-d731-493f-996d-835a8c7a9ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326435414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.326435414
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1292981455
Short name T97
Test name
Test status
Simulation time 300252675 ps
CPU time 7.79 seconds
Started May 02 02:34:17 PM PDT 24
Finished May 02 02:34:26 PM PDT 24
Peak memory 199144 kb
Host smart-8884f0fb-2322-4384-80fc-c48cd19f2f91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292981455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1292981455
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.969702287
Short name T640
Test name
Test status
Simulation time 1076246430 ps
CPU time 10.94 seconds
Started May 02 02:34:18 PM PDT 24
Finished May 02 02:34:30 PM PDT 24
Peak memory 199168 kb
Host smart-20963a5b-1263-4958-b13b-8fd86b087781
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969702287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.969702287
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2833602744
Short name T622
Test name
Test status
Simulation time 17043987 ps
CPU time 0.75 seconds
Started May 02 02:34:13 PM PDT 24
Finished May 02 02:34:14 PM PDT 24
Peak memory 197148 kb
Host smart-010ab82b-817f-4da5-95ee-b7f8275c204e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833602744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2833602744
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2888869033
Short name T685
Test name
Test status
Simulation time 271286187078 ps
CPU time 611.51 seconds
Started May 02 02:34:19 PM PDT 24
Finished May 02 02:44:31 PM PDT 24
Peak memory 215768 kb
Host smart-902b6d0d-b80c-46f6-826a-015307d7eb93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888869033 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2888869033
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2784444134
Short name T732
Test name
Test status
Simulation time 16088534 ps
CPU time 0.8 seconds
Started May 02 02:34:09 PM PDT 24
Finished May 02 02:34:10 PM PDT 24
Peak memory 199080 kb
Host smart-c61b3940-1c3f-4637-91f0-d813d1b6382f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784444134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2784444134
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2638755359
Short name T607
Test name
Test status
Simulation time 77023915 ps
CPU time 0.59 seconds
Started May 02 02:34:09 PM PDT 24
Finished May 02 02:34:11 PM PDT 24
Peak memory 193980 kb
Host smart-ef127e9d-eeb2-4db6-97b0-9ae294ddaa67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638755359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2638755359
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.271651223
Short name T644
Test name
Test status
Simulation time 112556535 ps
CPU time 1.13 seconds
Started May 02 02:34:18 PM PDT 24
Finished May 02 02:34:20 PM PDT 24
Peak memory 199356 kb
Host smart-418548ef-5460-41bb-bd68-9f5ac5e2668d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271651223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.271651223
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.75904234
Short name T661
Test name
Test status
Simulation time 363406575 ps
CPU time 3.63 seconds
Started May 02 02:34:10 PM PDT 24
Finished May 02 02:34:14 PM PDT 24
Peak memory 199364 kb
Host smart-c9fb58a9-897e-4a98-9017-6e859008c02f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75904234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.75904234
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3139609152
Short name T114
Test name
Test status
Simulation time 835021578 ps
CPU time 3.98 seconds
Started May 02 02:34:10 PM PDT 24
Finished May 02 02:34:15 PM PDT 24
Peak memory 199340 kb
Host smart-6479ead4-3ebf-4a21-a5b6-d9e6ecc5f57e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139609152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3139609152
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.778170051
Short name T618
Test name
Test status
Simulation time 64745986296 ps
CPU time 705.7 seconds
Started May 02 02:34:48 PM PDT 24
Finished May 02 02:46:35 PM PDT 24
Peak memory 215828 kb
Host smart-b11d6e45-f30a-4f79-b276-156ddf72cc6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778170051 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.778170051
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1352336602
Short name T104
Test name
Test status
Simulation time 34103255 ps
CPU time 0.66 seconds
Started May 02 02:34:47 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 197264 kb
Host smart-9c07d05b-0817-4f8b-8bfa-77ccacbe9e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352336602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1352336602
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.746838359
Short name T638
Test name
Test status
Simulation time 11806578 ps
CPU time 0.62 seconds
Started May 02 02:34:49 PM PDT 24
Finished May 02 02:34:52 PM PDT 24
Peak memory 194104 kb
Host smart-d68a58f7-862c-450f-a44a-bc7b49d5a0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746838359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.746838359
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3155538001
Short name T736
Test name
Test status
Simulation time 46629879 ps
CPU time 1.99 seconds
Started May 02 02:34:47 PM PDT 24
Finished May 02 02:34:51 PM PDT 24
Peak memory 199260 kb
Host smart-dc044087-cbc6-4e52-b750-56f5f1f4f617
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155538001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3155538001
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1490793819
Short name T663
Test name
Test status
Simulation time 73480901 ps
CPU time 3.71 seconds
Started May 02 02:34:50 PM PDT 24
Finished May 02 02:34:56 PM PDT 24
Peak memory 199384 kb
Host smart-34402da7-81b5-47fd-ab84-5a8aa2395725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490793819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1490793819
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1398668761
Short name T121
Test name
Test status
Simulation time 395441111 ps
CPU time 2.93 seconds
Started May 02 02:34:51 PM PDT 24
Finished May 02 02:34:55 PM PDT 24
Peak memory 199268 kb
Host smart-29ab8c0d-56c7-43a7-baf4-75f9dc56452b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398668761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1398668761
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3561052464
Short name T686
Test name
Test status
Simulation time 737632302 ps
CPU time 1.85 seconds
Started May 02 02:34:48 PM PDT 24
Finished May 02 02:34:52 PM PDT 24
Peak memory 199376 kb
Host smart-5bdcc203-fb5a-4984-9251-f4a89725f1e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561052464 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3561052464
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1634116890
Short name T717
Test name
Test status
Simulation time 35862279 ps
CPU time 0.68 seconds
Started May 02 02:34:47 PM PDT 24
Finished May 02 02:34:49 PM PDT 24
Peak memory 197028 kb
Host smart-2398ab4c-2c07-453c-b47d-146419ed9017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634116890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1634116890
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2227839936
Short name T710
Test name
Test status
Simulation time 13025841 ps
CPU time 0.62 seconds
Started May 02 02:34:50 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 194028 kb
Host smart-54b7002e-6116-47fe-a897-889f34a408d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227839936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2227839936
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1887843781
Short name T610
Test name
Test status
Simulation time 84618886 ps
CPU time 1.15 seconds
Started May 02 02:34:50 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 198800 kb
Host smart-023235a1-4c19-41d2-97f6-1c7e8d544d15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887843781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1887843781
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4229200892
Short name T655
Test name
Test status
Simulation time 729002542 ps
CPU time 3.23 seconds
Started May 02 02:34:47 PM PDT 24
Finished May 02 02:34:52 PM PDT 24
Peak memory 199324 kb
Host smart-7e2c49f1-608f-4c74-993c-00e555d4ec9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229200892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4229200892
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3980738315
Short name T701
Test name
Test status
Simulation time 154089833 ps
CPU time 3.08 seconds
Started May 02 02:34:46 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 199240 kb
Host smart-65bfde53-74e2-421f-9f9d-498e1fdee100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980738315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3980738315
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4059456532
Short name T612
Test name
Test status
Simulation time 157372407 ps
CPU time 1.14 seconds
Started May 02 02:34:48 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 199252 kb
Host smart-4d235a01-a28d-4642-8c13-6044bffa5acb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059456532 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4059456532
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.516453752
Short name T676
Test name
Test status
Simulation time 33865085 ps
CPU time 0.92 seconds
Started May 02 02:34:48 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 199168 kb
Host smart-ef0b559f-7f30-4335-8d20-03e0b888c84c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516453752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.516453752
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.199494477
Short name T643
Test name
Test status
Simulation time 14450910 ps
CPU time 0.61 seconds
Started May 02 02:34:48 PM PDT 24
Finished May 02 02:34:50 PM PDT 24
Peak memory 194060 kb
Host smart-b34fbf6a-d254-4504-a353-79b68d4bfed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199494477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.199494477
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3436645953
Short name T658
Test name
Test status
Simulation time 1204886888 ps
CPU time 2.45 seconds
Started May 02 02:34:49 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 199132 kb
Host smart-4ff4057c-4d36-4048-9ecb-661c28a3a02d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436645953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3436645953
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.877749355
Short name T683
Test name
Test status
Simulation time 229798190 ps
CPU time 4.03 seconds
Started May 02 02:34:51 PM PDT 24
Finished May 02 02:34:57 PM PDT 24
Peak memory 199380 kb
Host smart-2fabacef-dbdc-4e4e-a812-26cf655041d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877749355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.877749355
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2053257965
Short name T117
Test name
Test status
Simulation time 1083035021 ps
CPU time 4.62 seconds
Started May 02 02:34:48 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 199336 kb
Host smart-6f154260-7807-4e0b-835b-7ac100c3ea88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053257965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2053257965
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3920579780
Short name T699
Test name
Test status
Simulation time 155574395 ps
CPU time 1.2 seconds
Started May 02 02:34:55 PM PDT 24
Finished May 02 02:34:59 PM PDT 24
Peak memory 199256 kb
Host smart-dbb12bee-4754-4822-a332-6e199c6f0ca7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920579780 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3920579780
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.84601915
Short name T733
Test name
Test status
Simulation time 21486157 ps
CPU time 0.65 seconds
Started May 02 02:34:46 PM PDT 24
Finished May 02 02:34:48 PM PDT 24
Peak memory 197352 kb
Host smart-afa98507-9db5-4c1b-b444-1d0a0b3abca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84601915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.84601915
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1181356116
Short name T641
Test name
Test status
Simulation time 20265397 ps
CPU time 0.56 seconds
Started May 02 02:34:47 PM PDT 24
Finished May 02 02:34:49 PM PDT 24
Peak memory 194080 kb
Host smart-0a4e4885-472a-4104-8379-8bdb92e47775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181356116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1181356116
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2157619260
Short name T652
Test name
Test status
Simulation time 68586631 ps
CPU time 1.7 seconds
Started May 02 02:34:58 PM PDT 24
Finished May 02 02:35:01 PM PDT 24
Peak memory 198960 kb
Host smart-9110b253-4020-4184-af2a-da406ca22933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157619260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2157619260
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1262974938
Short name T692
Test name
Test status
Simulation time 1973422617 ps
CPU time 3.74 seconds
Started May 02 02:34:49 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 199384 kb
Host smart-cabf7012-97c2-4e97-997c-6cc3e58681a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262974938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1262974938
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2731133751
Short name T623
Test name
Test status
Simulation time 400819602 ps
CPU time 2.96 seconds
Started May 02 02:34:58 PM PDT 24
Finished May 02 02:35:03 PM PDT 24
Peak memory 207544 kb
Host smart-e57772cf-74b0-4a26-b1da-e893d4431177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731133751 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2731133751
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1506554880
Short name T703
Test name
Test status
Simulation time 20007388 ps
CPU time 0.67 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:34:58 PM PDT 24
Peak memory 196648 kb
Host smart-300ef330-df29-4a7e-acb8-cc8fe61df086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506554880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1506554880
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1397112562
Short name T631
Test name
Test status
Simulation time 42662589 ps
CPU time 0.59 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:34:59 PM PDT 24
Peak memory 194196 kb
Host smart-d9ad538c-084e-495b-9688-3f9c8fff5c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397112562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1397112562
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.65069441
Short name T660
Test name
Test status
Simulation time 174839349 ps
CPU time 1.19 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:34:59 PM PDT 24
Peak memory 199180 kb
Host smart-4fbfc962-73f3-4243-a277-79f09e61d9d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65069441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_
outstanding.65069441
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.191305185
Short name T673
Test name
Test status
Simulation time 194728779 ps
CPU time 3.4 seconds
Started May 02 02:34:55 PM PDT 24
Finished May 02 02:35:00 PM PDT 24
Peak memory 199340 kb
Host smart-07a281c0-0d5e-48a7-8946-d9c9b466b16a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191305185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.191305185
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4228275930
Short name T705
Test name
Test status
Simulation time 32195662 ps
CPU time 1.83 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:35:00 PM PDT 24
Peak memory 199336 kb
Host smart-2e0c86a7-1a03-4c91-89b9-1fb161c6bfbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228275930 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4228275930
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.281747097
Short name T653
Test name
Test status
Simulation time 30810313 ps
CPU time 0.89 seconds
Started May 02 02:34:57 PM PDT 24
Finished May 02 02:35:00 PM PDT 24
Peak memory 198628 kb
Host smart-5da36991-58c8-454c-9732-f9201da6184e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281747097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.281747097
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2510341575
Short name T681
Test name
Test status
Simulation time 32320436 ps
CPU time 0.55 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:34:59 PM PDT 24
Peak memory 194040 kb
Host smart-d6dc7c72-70d3-4b03-b31a-ef5f6e0caf9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510341575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2510341575
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.620669894
Short name T648
Test name
Test status
Simulation time 83509218 ps
CPU time 1.67 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:35:00 PM PDT 24
Peak memory 199316 kb
Host smart-5ece7d53-38c0-446a-93d3-2f3d5058f1e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620669894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.620669894
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3364527728
Short name T715
Test name
Test status
Simulation time 188730446 ps
CPU time 3.6 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:35:01 PM PDT 24
Peak memory 199348 kb
Host smart-ea308f8d-bf77-45d4-81c9-4fd22e74bed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364527728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3364527728
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2491867304
Short name T120
Test name
Test status
Simulation time 417495090 ps
CPU time 2.83 seconds
Started May 02 02:34:57 PM PDT 24
Finished May 02 02:35:02 PM PDT 24
Peak memory 199288 kb
Host smart-90dab973-0172-45f6-a63a-643cfe79b4a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491867304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2491867304
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.745432734
Short name T700
Test name
Test status
Simulation time 204329851 ps
CPU time 1.05 seconds
Started May 02 02:35:06 PM PDT 24
Finished May 02 02:35:09 PM PDT 24
Peak memory 199296 kb
Host smart-ac5bcc0e-f60e-49c5-abb7-8e6001c70633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745432734 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.745432734
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.93116918
Short name T107
Test name
Test status
Simulation time 68576015 ps
CPU time 0.94 seconds
Started May 02 02:34:56 PM PDT 24
Finished May 02 02:34:59 PM PDT 24
Peak memory 198708 kb
Host smart-24a140f0-80c8-424e-82c8-05a95899952e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93116918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.93116918
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.595136994
Short name T649
Test name
Test status
Simulation time 12079786 ps
CPU time 0.57 seconds
Started May 02 02:34:58 PM PDT 24
Finished May 02 02:35:01 PM PDT 24
Peak memory 194104 kb
Host smart-6983ce80-88b5-4eb0-970a-26a4b5d6f3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595136994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.595136994
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3829342412
Short name T625
Test name
Test status
Simulation time 107579241 ps
CPU time 1.75 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:35:09 PM PDT 24
Peak memory 199252 kb
Host smart-5bfe6ac4-9982-4c23-89fc-f1ee9d429b9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829342412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3829342412
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3996372846
Short name T621
Test name
Test status
Simulation time 286041121 ps
CPU time 2.86 seconds
Started May 02 02:34:57 PM PDT 24
Finished May 02 02:35:02 PM PDT 24
Peak memory 199440 kb
Host smart-0f6a22b0-3990-42f1-a1e2-54818d7038f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996372846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3996372846
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2316314365
Short name T52
Test name
Test status
Simulation time 309818241 ps
CPU time 1.74 seconds
Started May 02 02:34:55 PM PDT 24
Finished May 02 02:34:59 PM PDT 24
Peak memory 199308 kb
Host smart-9d374533-db2a-4b0b-bb9f-6fecffdcb31b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316314365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2316314365
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1250120397
Short name T651
Test name
Test status
Simulation time 40338215 ps
CPU time 1.22 seconds
Started May 02 02:35:06 PM PDT 24
Finished May 02 02:35:09 PM PDT 24
Peak memory 199260 kb
Host smart-d651f522-dc0f-4909-a6bf-bc68274f3265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250120397 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1250120397
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1685279222
Short name T650
Test name
Test status
Simulation time 29544866 ps
CPU time 0.96 seconds
Started May 02 02:35:07 PM PDT 24
Finished May 02 02:35:10 PM PDT 24
Peak memory 198828 kb
Host smart-57c21dd4-e22d-48fb-a550-e1958fdcc8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685279222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1685279222
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3650772859
Short name T687
Test name
Test status
Simulation time 18704399 ps
CPU time 0.6 seconds
Started May 02 02:35:07 PM PDT 24
Finished May 02 02:35:10 PM PDT 24
Peak memory 194064 kb
Host smart-d803e541-12fc-4fb9-9e28-d7354b7725f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650772859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3650772859
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3752427248
Short name T647
Test name
Test status
Simulation time 305424034 ps
CPU time 1.68 seconds
Started May 02 02:35:09 PM PDT 24
Finished May 02 02:35:13 PM PDT 24
Peak memory 199076 kb
Host smart-57b0052a-c75d-492b-8741-d1ebe606c361
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752427248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3752427248
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1873259719
Short name T678
Test name
Test status
Simulation time 75839100 ps
CPU time 3.95 seconds
Started May 02 02:35:06 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 199376 kb
Host smart-623005da-7d20-4176-8b9f-d68e95843d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873259719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1873259719
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.39134464
Short name T706
Test name
Test status
Simulation time 86784932 ps
CPU time 1.83 seconds
Started May 02 02:35:10 PM PDT 24
Finished May 02 02:35:14 PM PDT 24
Peak memory 199288 kb
Host smart-3ccae5e8-b6d9-473f-9542-96c47dc5b725
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.39134464
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.297068763
Short name T724
Test name
Test status
Simulation time 55141490640 ps
CPU time 819.31 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:48:47 PM PDT 24
Peak memory 224032 kb
Host smart-cc0156da-63e6-4027-8064-7d3715533742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297068763 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.297068763
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4001578233
Short name T102
Test name
Test status
Simulation time 19488524 ps
CPU time 0.97 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:35:09 PM PDT 24
Peak memory 198920 kb
Host smart-5d33e1b6-bf7c-443b-afe9-26a4fdaad368
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001578233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4001578233
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2306486737
Short name T639
Test name
Test status
Simulation time 18634784 ps
CPU time 0.57 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:35:08 PM PDT 24
Peak memory 194060 kb
Host smart-eed14a01-a759-4514-9afa-544e2b41d218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306486737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2306486737
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3181215885
Short name T702
Test name
Test status
Simulation time 59699779 ps
CPU time 1.15 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:35:09 PM PDT 24
Peak memory 198900 kb
Host smart-a1cc93b6-30b2-47a4-8d38-6e1f5cc0ee84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181215885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3181215885
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.706188364
Short name T670
Test name
Test status
Simulation time 236673268 ps
CPU time 4.01 seconds
Started May 02 02:35:04 PM PDT 24
Finished May 02 02:35:10 PM PDT 24
Peak memory 199264 kb
Host smart-d95dc090-dee7-4d73-8917-4fbfc0abfa5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706188364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.706188364
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1961093449
Short name T636
Test name
Test status
Simulation time 87794384 ps
CPU time 2.37 seconds
Started May 02 02:35:06 PM PDT 24
Finished May 02 02:35:11 PM PDT 24
Peak memory 199312 kb
Host smart-2c46d070-4daa-4346-b560-396d7d8b6a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961093449 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1961093449
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2426929730
Short name T56
Test name
Test status
Simulation time 27581727 ps
CPU time 0.84 seconds
Started May 02 02:35:09 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 198524 kb
Host smart-a00a7ec4-f1d3-48ba-acec-9dea332153dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426929730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2426929730
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2458738797
Short name T729
Test name
Test status
Simulation time 13543411 ps
CPU time 0.6 seconds
Started May 02 02:35:07 PM PDT 24
Finished May 02 02:35:10 PM PDT 24
Peak memory 194192 kb
Host smart-c0b21fa2-5327-4ee6-b4bb-0c0f8e6365e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458738797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2458738797
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2756191552
Short name T666
Test name
Test status
Simulation time 455160801 ps
CPU time 2.32 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:35:10 PM PDT 24
Peak memory 198428 kb
Host smart-4ebbeb96-8029-44ff-b2ee-34762f39dccf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756191552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2756191552
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3587455161
Short name T719
Test name
Test status
Simulation time 491654025 ps
CPU time 4 seconds
Started May 02 02:35:06 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 199332 kb
Host smart-650385fe-a443-43bb-93a6-6f85ea77bc62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587455161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3587455161
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3295395061
Short name T704
Test name
Test status
Simulation time 154554030 ps
CPU time 3.08 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:35:11 PM PDT 24
Peak memory 199328 kb
Host smart-e6d7b67b-cd76-48f9-aac3-e161d4c5627b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295395061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3295395061
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1558229036
Short name T103
Test name
Test status
Simulation time 231292939 ps
CPU time 3.09 seconds
Started May 02 02:34:17 PM PDT 24
Finished May 02 02:34:21 PM PDT 24
Peak memory 199248 kb
Host smart-9b507e37-7dc7-49da-b992-8a7d073fa174
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558229036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1558229036
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.690207597
Short name T611
Test name
Test status
Simulation time 727954664 ps
CPU time 10.7 seconds
Started May 02 02:34:18 PM PDT 24
Finished May 02 02:34:30 PM PDT 24
Peak memory 199168 kb
Host smart-af543534-40e2-4b6d-99a6-6d1b87b46f2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690207597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.690207597
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4019183646
Short name T101
Test name
Test status
Simulation time 33035770 ps
CPU time 0.86 seconds
Started May 02 02:34:19 PM PDT 24
Finished May 02 02:34:21 PM PDT 24
Peak memory 198168 kb
Host smart-2d6e71b2-38fe-4b03-9b15-71927a30487d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019183646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.4019183646
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1931237764
Short name T675
Test name
Test status
Simulation time 24849757 ps
CPU time 1.42 seconds
Started May 02 02:34:17 PM PDT 24
Finished May 02 02:34:20 PM PDT 24
Peak memory 199316 kb
Host smart-b2fcfdd5-6c73-43c1-92b8-718f75262212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931237764 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1931237764
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.411167921
Short name T629
Test name
Test status
Simulation time 18613289 ps
CPU time 0.68 seconds
Started May 02 02:34:16 PM PDT 24
Finished May 02 02:34:18 PM PDT 24
Peak memory 197308 kb
Host smart-d8ef90a1-eeb1-45ac-a0ca-9eac73fee0bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411167921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.411167921
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2523622278
Short name T602
Test name
Test status
Simulation time 37966888 ps
CPU time 0.59 seconds
Started May 02 02:34:18 PM PDT 24
Finished May 02 02:34:20 PM PDT 24
Peak memory 194144 kb
Host smart-e77b98b1-38a1-4ecc-8fdc-cb7832a59781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523622278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2523622278
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3965717007
Short name T716
Test name
Test status
Simulation time 32248731 ps
CPU time 1.58 seconds
Started May 02 02:34:18 PM PDT 24
Finished May 02 02:34:21 PM PDT 24
Peak memory 199180 kb
Host smart-88ecdb80-2cf4-457a-a8f0-3210e1362f86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965717007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3965717007
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.104540090
Short name T619
Test name
Test status
Simulation time 104641801 ps
CPU time 2.14 seconds
Started May 02 02:34:24 PM PDT 24
Finished May 02 02:34:27 PM PDT 24
Peak memory 199396 kb
Host smart-68aff946-1f5a-43a8-842e-8d58a06d03f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104540090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.104540090
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3452768540
Short name T690
Test name
Test status
Simulation time 35218370 ps
CPU time 0.6 seconds
Started May 02 02:35:07 PM PDT 24
Finished May 02 02:35:10 PM PDT 24
Peak memory 194104 kb
Host smart-96bbeccc-2274-4594-8ca2-119baccb1531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452768540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3452768540
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2251094972
Short name T723
Test name
Test status
Simulation time 57744352 ps
CPU time 0.59 seconds
Started May 02 02:35:09 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 194032 kb
Host smart-7732c503-1bfd-45e7-bb2e-4dbfd037bb7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251094972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2251094972
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.901882618
Short name T689
Test name
Test status
Simulation time 64933906 ps
CPU time 0.59 seconds
Started May 02 02:35:05 PM PDT 24
Finished May 02 02:35:08 PM PDT 24
Peak memory 194096 kb
Host smart-52113479-1f7c-4e0c-9b63-dbed00394816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901882618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.901882618
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1615798278
Short name T735
Test name
Test status
Simulation time 14936696 ps
CPU time 0.56 seconds
Started May 02 02:35:09 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 193980 kb
Host smart-372182d5-0fb3-4ed2-98dc-be75782600a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615798278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1615798278
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3028681117
Short name T726
Test name
Test status
Simulation time 127021090 ps
CPU time 0.57 seconds
Started May 02 02:35:09 PM PDT 24
Finished May 02 02:35:12 PM PDT 24
Peak memory 194152 kb
Host smart-3fa65726-4c24-4e23-85b3-f54cc21bd164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028681117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3028681117
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.192323459
Short name T613
Test name
Test status
Simulation time 32496579 ps
CPU time 0.63 seconds
Started May 02 02:35:17 PM PDT 24
Finished May 02 02:35:20 PM PDT 24
Peak memory 194104 kb
Host smart-5e62a623-85b3-4bee-ad77-c89133313c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192323459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.192323459
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1894918172
Short name T606
Test name
Test status
Simulation time 18577997 ps
CPU time 0.61 seconds
Started May 02 02:35:15 PM PDT 24
Finished May 02 02:35:18 PM PDT 24
Peak memory 194124 kb
Host smart-ae187b05-f140-4de9-868d-570b7917ad8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894918172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1894918172
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.812544222
Short name T646
Test name
Test status
Simulation time 95950284 ps
CPU time 0.57 seconds
Started May 02 02:35:12 PM PDT 24
Finished May 02 02:35:15 PM PDT 24
Peak memory 194080 kb
Host smart-682b7384-a99d-4ed9-9e32-58d4d1cbd528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812544222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.812544222
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1753606970
Short name T634
Test name
Test status
Simulation time 23213374 ps
CPU time 0.56 seconds
Started May 02 02:35:13 PM PDT 24
Finished May 02 02:35:16 PM PDT 24
Peak memory 194056 kb
Host smart-9abadac1-b5db-45f6-9b79-e7bb29b6931c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753606970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1753606970
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2028628826
Short name T727
Test name
Test status
Simulation time 24897203 ps
CPU time 0.62 seconds
Started May 02 02:35:13 PM PDT 24
Finished May 02 02:35:16 PM PDT 24
Peak memory 194016 kb
Host smart-732c10cd-90fd-4186-85d5-b27234a9d745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028628826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2028628826
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2002936335
Short name T99
Test name
Test status
Simulation time 2210077556 ps
CPU time 8.51 seconds
Started May 02 02:34:25 PM PDT 24
Finished May 02 02:34:34 PM PDT 24
Peak memory 199284 kb
Host smart-2ce77ddd-10c7-4ef3-a034-6abd4c29b0ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002936335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2002936335
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2763797133
Short name T624
Test name
Test status
Simulation time 2222730558 ps
CPU time 5.83 seconds
Started May 02 02:34:25 PM PDT 24
Finished May 02 02:34:32 PM PDT 24
Peak memory 199248 kb
Host smart-818e37d9-574e-4c1c-b175-57ca99e5b16d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763797133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2763797133
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3778720399
Short name T667
Test name
Test status
Simulation time 74566323 ps
CPU time 0.74 seconds
Started May 02 02:34:26 PM PDT 24
Finished May 02 02:34:27 PM PDT 24
Peak memory 197172 kb
Host smart-83126585-e9da-4464-8e97-5dd5531685e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778720399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3778720399
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2807949755
Short name T57
Test name
Test status
Simulation time 103997628 ps
CPU time 3.11 seconds
Started May 02 02:34:33 PM PDT 24
Finished May 02 02:34:38 PM PDT 24
Peak memory 199372 kb
Host smart-289284ba-7d00-4c5c-b319-202b745b16cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807949755 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2807949755
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3009538599
Short name T714
Test name
Test status
Simulation time 45829706 ps
CPU time 0.7 seconds
Started May 02 02:34:29 PM PDT 24
Finished May 02 02:34:31 PM PDT 24
Peak memory 196848 kb
Host smart-9e230d25-26d0-4186-85d1-083505714a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009538599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3009538599
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.414500781
Short name T731
Test name
Test status
Simulation time 165080804 ps
CPU time 0.59 seconds
Started May 02 02:34:28 PM PDT 24
Finished May 02 02:34:30 PM PDT 24
Peak memory 194132 kb
Host smart-7d03c60e-5d92-4cb3-bee1-ef3915863238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414500781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.414500781
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2010725450
Short name T609
Test name
Test status
Simulation time 39384094 ps
CPU time 1.05 seconds
Started May 02 02:34:26 PM PDT 24
Finished May 02 02:34:28 PM PDT 24
Peak memory 198820 kb
Host smart-192ca115-0c34-4c98-ad27-51142fec467f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010725450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2010725450
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1841371425
Short name T669
Test name
Test status
Simulation time 77888718 ps
CPU time 3.01 seconds
Started May 02 02:34:26 PM PDT 24
Finished May 02 02:34:30 PM PDT 24
Peak memory 199328 kb
Host smart-30f7e6a9-e2a3-4b38-b2f2-8ce12ec69487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841371425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1841371425
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4163391285
Short name T713
Test name
Test status
Simulation time 156796750 ps
CPU time 3.12 seconds
Started May 02 02:34:25 PM PDT 24
Finished May 02 02:34:29 PM PDT 24
Peak memory 199244 kb
Host smart-96bd51f2-ac69-42cb-a841-13701d342acf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163391285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4163391285
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.336828939
Short name T684
Test name
Test status
Simulation time 55823229 ps
CPU time 0.61 seconds
Started May 02 02:35:14 PM PDT 24
Finished May 02 02:35:18 PM PDT 24
Peak memory 194080 kb
Host smart-26078ce1-9592-4781-8dd7-12d555d3fa8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336828939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.336828939
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.636896684
Short name T734
Test name
Test status
Simulation time 16291513 ps
CPU time 0.57 seconds
Started May 02 02:35:12 PM PDT 24
Finished May 02 02:35:15 PM PDT 24
Peak memory 194100 kb
Host smart-1186f044-73e7-4e70-98af-2c2346859049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636896684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.636896684
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3039088950
Short name T674
Test name
Test status
Simulation time 14775383 ps
CPU time 0.6 seconds
Started May 02 02:35:13 PM PDT 24
Finished May 02 02:35:16 PM PDT 24
Peak memory 194100 kb
Host smart-aeaafd85-b37b-47f6-8742-1ab098c0719f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039088950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3039088950
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3877495526
Short name T632
Test name
Test status
Simulation time 25176698 ps
CPU time 0.6 seconds
Started May 02 02:35:13 PM PDT 24
Finished May 02 02:35:16 PM PDT 24
Peak memory 194076 kb
Host smart-6e2b073d-ead7-4101-8483-d8ed0557d91c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877495526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3877495526
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1302751718
Short name T664
Test name
Test status
Simulation time 27352055 ps
CPU time 0.55 seconds
Started May 02 02:35:16 PM PDT 24
Finished May 02 02:35:19 PM PDT 24
Peak memory 193992 kb
Host smart-7d8ba062-25e1-4008-8d73-df23ba2f443c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302751718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1302751718
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1848518588
Short name T654
Test name
Test status
Simulation time 11421147 ps
CPU time 0.57 seconds
Started May 02 02:35:16 PM PDT 24
Finished May 02 02:35:19 PM PDT 24
Peak memory 194124 kb
Host smart-4e98a249-bcf6-4534-948c-48bd8fec4376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848518588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1848518588
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2999572352
Short name T709
Test name
Test status
Simulation time 14053592 ps
CPU time 0.61 seconds
Started May 02 02:35:16 PM PDT 24
Finished May 02 02:35:20 PM PDT 24
Peak memory 194164 kb
Host smart-f4fa45ae-16df-454a-b3ec-d2ae6791eef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999572352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2999572352
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3255643699
Short name T628
Test name
Test status
Simulation time 45755925 ps
CPU time 0.57 seconds
Started May 02 02:35:19 PM PDT 24
Finished May 02 02:35:22 PM PDT 24
Peak memory 193916 kb
Host smart-034dfd84-d62a-4f3e-ac21-73105bf7eb09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255643699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3255643699
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3286867811
Short name T604
Test name
Test status
Simulation time 36552475 ps
CPU time 0.57 seconds
Started May 02 02:35:21 PM PDT 24
Finished May 02 02:35:24 PM PDT 24
Peak memory 193912 kb
Host smart-50227e94-8201-4a73-bdc7-767485cde9a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286867811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3286867811
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.170219681
Short name T657
Test name
Test status
Simulation time 19880423 ps
CPU time 0.57 seconds
Started May 02 02:35:16 PM PDT 24
Finished May 02 02:35:19 PM PDT 24
Peak memory 194104 kb
Host smart-eeddf85c-85cc-4c73-aef5-513c609f4701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170219681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.170219681
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3716565557
Short name T108
Test name
Test status
Simulation time 423300317 ps
CPU time 5.6 seconds
Started May 02 02:34:35 PM PDT 24
Finished May 02 02:34:42 PM PDT 24
Peak memory 199164 kb
Host smart-85ceca36-ca7d-4974-9a13-57502b2fa3a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716565557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3716565557
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1807226118
Short name T633
Test name
Test status
Simulation time 1055451893 ps
CPU time 15.05 seconds
Started May 02 02:34:33 PM PDT 24
Finished May 02 02:34:49 PM PDT 24
Peak memory 198072 kb
Host smart-6907b2c4-4ba6-4702-9556-3581cf80158b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807226118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1807226118
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2818008895
Short name T106
Test name
Test status
Simulation time 77155015 ps
CPU time 0.98 seconds
Started May 02 02:34:32 PM PDT 24
Finished May 02 02:34:34 PM PDT 24
Peak memory 199096 kb
Host smart-75185fd4-8e3d-4b5b-bd71-9b74d7be959d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818008895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2818008895
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2674723981
Short name T682
Test name
Test status
Simulation time 28371951 ps
CPU time 1.74 seconds
Started May 02 02:34:34 PM PDT 24
Finished May 02 02:34:37 PM PDT 24
Peak memory 199364 kb
Host smart-1d1f3344-2212-47c8-abbe-57d1691b2747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674723981 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2674723981
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2657678950
Short name T105
Test name
Test status
Simulation time 17829398 ps
CPU time 0.96 seconds
Started May 02 02:34:33 PM PDT 24
Finished May 02 02:34:35 PM PDT 24
Peak memory 198896 kb
Host smart-ec6a4f69-98be-4434-95f1-42b7f5b29fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657678950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2657678950
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1547689626
Short name T605
Test name
Test status
Simulation time 45388110 ps
CPU time 0.6 seconds
Started May 02 02:34:33 PM PDT 24
Finished May 02 02:34:34 PM PDT 24
Peak memory 194060 kb
Host smart-c1355837-eb5b-4bf3-9171-b16ae92b73a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547689626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1547689626
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1168666925
Short name T665
Test name
Test status
Simulation time 260908384 ps
CPU time 2.05 seconds
Started May 02 02:34:31 PM PDT 24
Finished May 02 02:34:34 PM PDT 24
Peak memory 199048 kb
Host smart-d79f9460-0989-4809-a59d-4218c6f15c0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168666925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1168666925
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.237736390
Short name T718
Test name
Test status
Simulation time 110434645 ps
CPU time 1.54 seconds
Started May 02 02:34:33 PM PDT 24
Finished May 02 02:34:36 PM PDT 24
Peak memory 199348 kb
Host smart-4db23c1c-c6dc-4efe-bbd1-d161726f461c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237736390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.237736390
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4602213
Short name T712
Test name
Test status
Simulation time 340564902 ps
CPU time 1.79 seconds
Started May 02 02:34:33 PM PDT 24
Finished May 02 02:34:36 PM PDT 24
Peak memory 199328 kb
Host smart-d9ab5990-4355-4271-9949-4f469d7a8abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4602213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4602213
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2040654005
Short name T707
Test name
Test status
Simulation time 34762753 ps
CPU time 0.56 seconds
Started May 02 02:35:17 PM PDT 24
Finished May 02 02:35:21 PM PDT 24
Peak memory 193988 kb
Host smart-b7b94a94-2712-43b3-ae49-c747e093cba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040654005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2040654005
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1042289050
Short name T608
Test name
Test status
Simulation time 13213307 ps
CPU time 0.58 seconds
Started May 02 02:35:19 PM PDT 24
Finished May 02 02:35:22 PM PDT 24
Peak memory 194036 kb
Host smart-4a7284c8-1adb-4cb7-bfaa-f8fbb886fda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042289050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1042289050
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1766561504
Short name T677
Test name
Test status
Simulation time 51219575 ps
CPU time 0.58 seconds
Started May 02 02:35:15 PM PDT 24
Finished May 02 02:35:18 PM PDT 24
Peak memory 194164 kb
Host smart-36654217-fffc-4996-9c19-ecafaaec5086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766561504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1766561504
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1984889382
Short name T721
Test name
Test status
Simulation time 10853709 ps
CPU time 0.56 seconds
Started May 02 02:35:14 PM PDT 24
Finished May 02 02:35:17 PM PDT 24
Peak memory 193968 kb
Host smart-bbd6deb0-ea93-4800-9cd3-b32160d4c544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984889382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1984889382
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.144107787
Short name T630
Test name
Test status
Simulation time 17597236 ps
CPU time 0.6 seconds
Started May 02 02:35:15 PM PDT 24
Finished May 02 02:35:18 PM PDT 24
Peak memory 194100 kb
Host smart-baef0f1c-fedc-4113-b110-75679fd0d3b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144107787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.144107787
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2454640754
Short name T698
Test name
Test status
Simulation time 26097903 ps
CPU time 0.62 seconds
Started May 02 02:35:13 PM PDT 24
Finished May 02 02:35:16 PM PDT 24
Peak memory 194100 kb
Host smart-5bdedf9c-75e2-4bfe-b5cd-5e59610ae697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454640754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2454640754
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1203027864
Short name T696
Test name
Test status
Simulation time 151682313 ps
CPU time 0.58 seconds
Started May 02 02:35:14 PM PDT 24
Finished May 02 02:35:17 PM PDT 24
Peak memory 194052 kb
Host smart-314d693e-62f0-4744-86c6-1deb19dd1951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203027864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1203027864
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4230942399
Short name T671
Test name
Test status
Simulation time 15861741 ps
CPU time 0.56 seconds
Started May 02 02:35:18 PM PDT 24
Finished May 02 02:35:21 PM PDT 24
Peak memory 193944 kb
Host smart-0bfae9fd-7839-44b1-ad2b-c3d70543e829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230942399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4230942399
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3083736730
Short name T614
Test name
Test status
Simulation time 43957702 ps
CPU time 0.65 seconds
Started May 02 02:35:15 PM PDT 24
Finished May 02 02:35:19 PM PDT 24
Peak memory 194060 kb
Host smart-0720caf0-73c1-4764-b04f-6ab6176966ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083736730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3083736730
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.914995254
Short name T603
Test name
Test status
Simulation time 26318733 ps
CPU time 0.62 seconds
Started May 02 02:35:14 PM PDT 24
Finished May 02 02:35:17 PM PDT 24
Peak memory 194080 kb
Host smart-af41b63a-754e-4ad5-afa5-752ecf761231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914995254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.914995254
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3845078295
Short name T691
Test name
Test status
Simulation time 130077143 ps
CPU time 1.72 seconds
Started May 02 02:34:35 PM PDT 24
Finished May 02 02:34:38 PM PDT 24
Peak memory 199328 kb
Host smart-a171dc5d-2a6a-444d-89ac-34e3ae1770fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845078295 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3845078295
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3387411610
Short name T730
Test name
Test status
Simulation time 22849583 ps
CPU time 0.69 seconds
Started May 02 02:34:32 PM PDT 24
Finished May 02 02:34:34 PM PDT 24
Peak memory 196696 kb
Host smart-b1a6cfb3-ac16-4dd0-9321-1a307f054dd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387411610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3387411610
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1031213521
Short name T694
Test name
Test status
Simulation time 59367832 ps
CPU time 0.58 seconds
Started May 02 02:34:31 PM PDT 24
Finished May 02 02:34:32 PM PDT 24
Peak memory 194204 kb
Host smart-6f6d8614-1f52-40ca-a9d4-fe0569c36e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031213521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1031213521
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.615950054
Short name T695
Test name
Test status
Simulation time 38726716 ps
CPU time 1.73 seconds
Started May 02 02:34:34 PM PDT 24
Finished May 02 02:34:37 PM PDT 24
Peak memory 199180 kb
Host smart-c121c579-ef75-4d16-a145-762b3fdcfac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615950054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.615950054
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2981960199
Short name T617
Test name
Test status
Simulation time 321744476 ps
CPU time 3.72 seconds
Started May 02 02:34:33 PM PDT 24
Finished May 02 02:34:38 PM PDT 24
Peak memory 199352 kb
Host smart-ec128405-74ac-499f-9923-ce7bea14ac34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981960199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2981960199
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2729813113
Short name T737
Test name
Test status
Simulation time 1798743492 ps
CPU time 3.15 seconds
Started May 02 02:34:31 PM PDT 24
Finished May 02 02:34:36 PM PDT 24
Peak memory 199312 kb
Host smart-b9691f38-aab0-4d1f-8b85-9a2a29415be8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729813113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2729813113
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4142839266
Short name T656
Test name
Test status
Simulation time 1150650523 ps
CPU time 1.8 seconds
Started May 02 02:34:40 PM PDT 24
Finished May 02 02:34:44 PM PDT 24
Peak memory 199292 kb
Host smart-f67f0776-504b-43d5-b556-b1151556a961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142839266 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4142839266
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2579570916
Short name T100
Test name
Test status
Simulation time 36543835 ps
CPU time 0.71 seconds
Started May 02 02:34:43 PM PDT 24
Finished May 02 02:34:45 PM PDT 24
Peak memory 197268 kb
Host smart-3e04d573-fb59-4d1d-9d63-4c58c05675ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579570916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2579570916
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2446766949
Short name T645
Test name
Test status
Simulation time 64582849 ps
CPU time 0.61 seconds
Started May 02 02:34:32 PM PDT 24
Finished May 02 02:34:33 PM PDT 24
Peak memory 194216 kb
Host smart-d59f4655-91dd-425e-b508-d9ddb01d053f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446766949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2446766949
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1418906849
Short name T615
Test name
Test status
Simulation time 237425765 ps
CPU time 2.34 seconds
Started May 02 02:34:39 PM PDT 24
Finished May 02 02:34:42 PM PDT 24
Peak memory 199100 kb
Host smart-8a999cfa-3911-4622-9e2b-cdd6b320d848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418906849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1418906849
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1741939651
Short name T668
Test name
Test status
Simulation time 560383484 ps
CPU time 2.76 seconds
Started May 02 02:34:32 PM PDT 24
Finished May 02 02:34:36 PM PDT 24
Peak memory 199388 kb
Host smart-0da8cd47-8ea6-45af-981d-7f980ad9fad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741939651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1741939651
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1500623525
Short name T53
Test name
Test status
Simulation time 411455089 ps
CPU time 2.81 seconds
Started May 02 02:34:31 PM PDT 24
Finished May 02 02:34:35 PM PDT 24
Peak memory 199308 kb
Host smart-974b09ce-0b20-4cac-b617-0da6defc2e86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500623525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1500623525
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.591605235
Short name T620
Test name
Test status
Simulation time 104950208 ps
CPU time 1.57 seconds
Started May 02 02:34:43 PM PDT 24
Finished May 02 02:34:46 PM PDT 24
Peak memory 199320 kb
Host smart-56bbe7e2-473c-4bf5-8657-e9e97f47daaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591605235 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.591605235
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.851826761
Short name T720
Test name
Test status
Simulation time 25690094 ps
CPU time 0.82 seconds
Started May 02 02:34:41 PM PDT 24
Finished May 02 02:34:43 PM PDT 24
Peak memory 198032 kb
Host smart-1a2cb203-ffcf-4b8f-93a2-fe6eaf6f0a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851826761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.851826761
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4054467867
Short name T679
Test name
Test status
Simulation time 38945869 ps
CPU time 0.57 seconds
Started May 02 02:34:43 PM PDT 24
Finished May 02 02:34:45 PM PDT 24
Peak memory 194136 kb
Host smart-76cf1dbc-849d-4740-aff2-c580cb68f485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054467867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4054467867
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2839318423
Short name T725
Test name
Test status
Simulation time 325595257 ps
CPU time 1.54 seconds
Started May 02 02:34:39 PM PDT 24
Finished May 02 02:34:42 PM PDT 24
Peak memory 199276 kb
Host smart-deb8876a-7944-4405-ab02-9245dbaa70e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839318423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2839318423
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1099719817
Short name T662
Test name
Test status
Simulation time 209818525 ps
CPU time 4.05 seconds
Started May 02 02:34:40 PM PDT 24
Finished May 02 02:34:46 PM PDT 24
Peak memory 199376 kb
Host smart-b7e5a8a3-32fa-4c2f-9da9-e7f7fc556358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099719817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1099719817
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1092237995
Short name T708
Test name
Test status
Simulation time 92993706 ps
CPU time 1.74 seconds
Started May 02 02:34:41 PM PDT 24
Finished May 02 02:34:45 PM PDT 24
Peak memory 199324 kb
Host smart-f25349a5-4a48-41f7-a674-f57d35818722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092237995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1092237995
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.689816522
Short name T711
Test name
Test status
Simulation time 20080050 ps
CPU time 1.2 seconds
Started May 02 02:34:50 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 199240 kb
Host smart-16e14279-11d2-422e-9407-61c985397fd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689816522 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.689816522
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1522986309
Short name T722
Test name
Test status
Simulation time 47879831 ps
CPU time 0.81 seconds
Started May 02 02:34:43 PM PDT 24
Finished May 02 02:34:45 PM PDT 24
Peak memory 199076 kb
Host smart-ba891666-9a10-47b2-841e-8a1084eb712d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522986309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1522986309
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.4218510357
Short name T642
Test name
Test status
Simulation time 110953998 ps
CPU time 0.58 seconds
Started May 02 02:34:40 PM PDT 24
Finished May 02 02:34:42 PM PDT 24
Peak memory 194036 kb
Host smart-fb404ad2-a365-4b31-b98d-a3e74e661a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218510357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4218510357
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2555211797
Short name T637
Test name
Test status
Simulation time 42754355 ps
CPU time 1.97 seconds
Started May 02 02:34:40 PM PDT 24
Finished May 02 02:34:44 PM PDT 24
Peak memory 199312 kb
Host smart-8f99fa6c-f11f-4eae-bf04-5b729b862ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555211797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2555211797
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1856819007
Short name T672
Test name
Test status
Simulation time 96236462 ps
CPU time 1.78 seconds
Started May 02 02:34:41 PM PDT 24
Finished May 02 02:34:45 PM PDT 24
Peak memory 199380 kb
Host smart-3f67bd93-e029-4ac8-b61a-eb93bd035527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856819007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1856819007
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3355159638
Short name T113
Test name
Test status
Simulation time 3369306814 ps
CPU time 4.01 seconds
Started May 02 02:34:40 PM PDT 24
Finished May 02 02:34:46 PM PDT 24
Peak memory 199400 kb
Host smart-b6589f18-508c-403d-b145-d62d5573e671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355159638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3355159638
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2924438652
Short name T659
Test name
Test status
Simulation time 50617315953 ps
CPU time 276.99 seconds
Started May 02 02:34:51 PM PDT 24
Finished May 02 02:39:30 PM PDT 24
Peak memory 215748 kb
Host smart-6a1628fe-d26d-48db-b696-7502cf35a255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924438652 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2924438652
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3146793462
Short name T98
Test name
Test status
Simulation time 45698181 ps
CPU time 0.84 seconds
Started May 02 02:34:51 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 199092 kb
Host smart-5bb5fb2b-a9df-47d4-b941-42c61022a4cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146793462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3146793462
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3108851874
Short name T697
Test name
Test status
Simulation time 22258973 ps
CPU time 0.61 seconds
Started May 02 02:34:51 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 194116 kb
Host smart-68457cff-03c5-4817-ac93-d376d1281972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108851874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3108851874
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1668401060
Short name T627
Test name
Test status
Simulation time 100217065 ps
CPU time 1.99 seconds
Started May 02 02:34:49 PM PDT 24
Finished May 02 02:34:53 PM PDT 24
Peak memory 199264 kb
Host smart-2cd2ba90-60a2-409a-86f3-fd994b9de865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668401060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1668401060
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1594928462
Short name T693
Test name
Test status
Simulation time 145121077 ps
CPU time 1.52 seconds
Started May 02 02:34:46 PM PDT 24
Finished May 02 02:34:49 PM PDT 24
Peak memory 199380 kb
Host smart-d7b90db2-ebca-4b8d-bfcd-b537f2a8f8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594928462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1594928462
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1575875074
Short name T119
Test name
Test status
Simulation time 661397557 ps
CPU time 3.04 seconds
Started May 02 02:34:50 PM PDT 24
Finished May 02 02:34:54 PM PDT 24
Peak memory 199280 kb
Host smart-c052a2c4-5d11-4402-abd1-de9f85e7149d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575875074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1575875074
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.222653781
Short name T554
Test name
Test status
Simulation time 30842250 ps
CPU time 0.56 seconds
Started May 02 02:43:55 PM PDT 24
Finished May 02 02:43:57 PM PDT 24
Peak memory 195240 kb
Host smart-960e775e-f86f-471e-8f8c-1985683bc281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222653781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.222653781
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1146854653
Short name T516
Test name
Test status
Simulation time 6891558080 ps
CPU time 47.65 seconds
Started May 02 02:43:49 PM PDT 24
Finished May 02 02:44:38 PM PDT 24
Peak memory 207980 kb
Host smart-ce5d8f9f-dea6-4350-aa5c-354ad92c34d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146854653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1146854653
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.4043251372
Short name T77
Test name
Test status
Simulation time 529553282 ps
CPU time 6.86 seconds
Started May 02 02:43:56 PM PDT 24
Finished May 02 02:44:04 PM PDT 24
Peak memory 199636 kb
Host smart-b9cc5683-d256-4d4e-9185-eae06d83f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043251372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.4043251372
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3706159487
Short name T455
Test name
Test status
Simulation time 2240245049 ps
CPU time 26.03 seconds
Started May 02 02:43:49 PM PDT 24
Finished May 02 02:44:16 PM PDT 24
Peak memory 199792 kb
Host smart-94e4047b-89b3-4188-8cdd-b02c4f1a02c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706159487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3706159487
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.615585251
Short name T384
Test name
Test status
Simulation time 802708888 ps
CPU time 8.23 seconds
Started May 02 02:43:56 PM PDT 24
Finished May 02 02:44:05 PM PDT 24
Peak memory 199596 kb
Host smart-ade661de-d980-4916-9624-b6d5363db5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615585251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.615585251
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1849894763
Short name T38
Test name
Test status
Simulation time 195508295 ps
CPU time 0.89 seconds
Started May 02 02:43:55 PM PDT 24
Finished May 02 02:43:57 PM PDT 24
Peak memory 218092 kb
Host smart-25a86be7-46e1-48d8-9973-4787073086fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849894763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1849894763
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2329546092
Short name T476
Test name
Test status
Simulation time 291278225 ps
CPU time 4.63 seconds
Started May 02 02:43:56 PM PDT 24
Finished May 02 02:44:01 PM PDT 24
Peak memory 199652 kb
Host smart-3dd94769-0ca2-45cd-99e3-bb77b033f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329546092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2329546092
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3555339314
Short name T550
Test name
Test status
Simulation time 299153977908 ps
CPU time 1293.71 seconds
Started May 02 02:43:49 PM PDT 24
Finished May 02 03:05:24 PM PDT 24
Peak memory 199724 kb
Host smart-5e6477ba-8cdb-4a34-b944-b542735f2bcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555339314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3555339314
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.791194075
Short name T14
Test name
Test status
Simulation time 58284100914 ps
CPU time 2946.96 seconds
Started May 02 02:43:48 PM PDT 24
Finished May 02 03:32:56 PM PDT 24
Peak memory 248936 kb
Host smart-ea62202f-4963-45d2-a4d8-d2bd16483f87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791194075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.791194075
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3385689819
Short name T411
Test name
Test status
Simulation time 49212239 ps
CPU time 1.02 seconds
Started May 02 02:43:49 PM PDT 24
Finished May 02 02:43:51 PM PDT 24
Peak memory 198124 kb
Host smart-709a5743-85ca-448b-ae3e-2899e9b018d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385689819 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3385689819
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.337826213
Short name T67
Test name
Test status
Simulation time 7449073052 ps
CPU time 399.3 seconds
Started May 02 02:43:49 PM PDT 24
Finished May 02 02:50:30 PM PDT 24
Peak memory 199644 kb
Host smart-908fb45f-dd35-40d7-990a-48edd99c47c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337826213 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.337826213
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1830883182
Short name T274
Test name
Test status
Simulation time 966441198 ps
CPU time 34.93 seconds
Started May 02 02:43:48 PM PDT 24
Finished May 02 02:44:24 PM PDT 24
Peak memory 199628 kb
Host smart-76b82be7-751a-4426-9e9c-e8a20b71b278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830883182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1830883182
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3186391904
Short name T272
Test name
Test status
Simulation time 15281929 ps
CPU time 0.63 seconds
Started May 02 02:43:55 PM PDT 24
Finished May 02 02:43:56 PM PDT 24
Peak memory 195492 kb
Host smart-a5a7de26-854f-45c3-87be-52d59a5d8a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186391904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3186391904
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3153106122
Short name T356
Test name
Test status
Simulation time 4978492052 ps
CPU time 46.28 seconds
Started May 02 02:43:55 PM PDT 24
Finished May 02 02:44:42 PM PDT 24
Peak memory 248344 kb
Host smart-99405c61-aba1-415a-aa2e-4f33415e4615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153106122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3153106122
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2829868888
Short name T362
Test name
Test status
Simulation time 3885672063 ps
CPU time 39.68 seconds
Started May 02 02:43:59 PM PDT 24
Finished May 02 02:44:39 PM PDT 24
Peak memory 199488 kb
Host smart-2b0784b9-2016-4741-8f2f-93841074377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829868888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2829868888
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.551588517
Short name T383
Test name
Test status
Simulation time 3794721714 ps
CPU time 57.63 seconds
Started May 02 02:43:58 PM PDT 24
Finished May 02 02:44:57 PM PDT 24
Peak memory 199484 kb
Host smart-ceefc1b4-1611-4b44-9bc2-c68d26de97ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551588517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.551588517
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.457963266
Short name T42
Test name
Test status
Simulation time 10044673122 ps
CPU time 171.97 seconds
Started May 02 02:43:56 PM PDT 24
Finished May 02 02:46:49 PM PDT 24
Peak memory 199732 kb
Host smart-2d67c159-19d0-4ceb-ab0a-e00035cd67ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457963266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.457963266
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1396407534
Short name T353
Test name
Test status
Simulation time 2008092756 ps
CPU time 36.55 seconds
Started May 02 02:43:55 PM PDT 24
Finished May 02 02:44:32 PM PDT 24
Peak memory 199676 kb
Host smart-38294882-3375-4dfe-bd67-7eebfc9a3f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396407534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1396407534
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.1848640693
Short name T85
Test name
Test status
Simulation time 1837436174 ps
CPU time 6.68 seconds
Started May 02 02:43:55 PM PDT 24
Finished May 02 02:44:03 PM PDT 24
Peak memory 199636 kb
Host smart-e26be3d3-82ff-4986-819a-97f6dc04b1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848640693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1848640693
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2501695918
Short name T264
Test name
Test status
Simulation time 108129872415 ps
CPU time 448.33 seconds
Started May 02 02:43:56 PM PDT 24
Finished May 02 02:51:25 PM PDT 24
Peak memory 199716 kb
Host smart-e7048617-42b1-4369-855d-002947c3dad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501695918 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2501695918
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2682135276
Short name T587
Test name
Test status
Simulation time 283206655 ps
CPU time 1.23 seconds
Started May 02 02:44:00 PM PDT 24
Finished May 02 02:44:02 PM PDT 24
Peak memory 199632 kb
Host smart-118ed31d-072c-4fb5-b360-cdd234b4fbd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682135276 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2682135276
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.497373721
Short name T327
Test name
Test status
Simulation time 189528539949 ps
CPU time 486.74 seconds
Started May 02 02:43:54 PM PDT 24
Finished May 02 02:52:01 PM PDT 24
Peak memory 199696 kb
Host smart-bb365ff1-de2c-47ca-a75b-078f85607dcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497373721 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.497373721
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.177135945
Short name T469
Test name
Test status
Simulation time 640644338 ps
CPU time 12.73 seconds
Started May 02 02:43:54 PM PDT 24
Finished May 02 02:44:07 PM PDT 24
Peak memory 199592 kb
Host smart-fc978f9a-cdde-4feb-8428-dc0efdae480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177135945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.177135945
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2218671965
Short name T406
Test name
Test status
Simulation time 11409715 ps
CPU time 0.58 seconds
Started May 02 02:44:43 PM PDT 24
Finished May 02 02:44:45 PM PDT 24
Peak memory 195308 kb
Host smart-6dec3b00-3ed4-46b3-8e1d-3d32e85c5210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218671965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2218671965
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2841194113
Short name T445
Test name
Test status
Simulation time 1557812883 ps
CPU time 34.48 seconds
Started May 02 02:44:38 PM PDT 24
Finished May 02 02:45:13 PM PDT 24
Peak memory 207888 kb
Host smart-67b0f08c-83a8-44f7-96d0-4040265577e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841194113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2841194113
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4058838437
Short name T229
Test name
Test status
Simulation time 3025133683 ps
CPU time 44 seconds
Started May 02 02:44:45 PM PDT 24
Finished May 02 02:45:31 PM PDT 24
Peak memory 199660 kb
Host smart-112ba700-5faa-4f67-8842-6bcd1cbd35e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058838437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4058838437
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3750143152
Short name T336
Test name
Test status
Simulation time 873540795 ps
CPU time 49.74 seconds
Started May 02 02:44:36 PM PDT 24
Finished May 02 02:45:26 PM PDT 24
Peak memory 199700 kb
Host smart-39088c0a-e470-4dc9-ab0d-71d9eeb54194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750143152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3750143152
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3199068564
Short name T371
Test name
Test status
Simulation time 12371138785 ps
CPU time 213.64 seconds
Started May 02 02:44:46 PM PDT 24
Finished May 02 02:48:21 PM PDT 24
Peak memory 199776 kb
Host smart-8b982e8f-4de5-412d-99d1-1dfed4af1836
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199068564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3199068564
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3133620285
Short name T210
Test name
Test status
Simulation time 853268890 ps
CPU time 48.24 seconds
Started May 02 02:44:38 PM PDT 24
Finished May 02 02:45:27 PM PDT 24
Peak memory 199744 kb
Host smart-7c8df85a-b96f-4cd9-94be-4bdedecfc50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133620285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3133620285
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.378709697
Short name T250
Test name
Test status
Simulation time 525948549 ps
CPU time 6.27 seconds
Started May 02 02:44:40 PM PDT 24
Finished May 02 02:44:47 PM PDT 24
Peak memory 199624 kb
Host smart-339d1113-1f96-46d7-bb38-0634931aad90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378709697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.378709697
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2846506028
Short name T173
Test name
Test status
Simulation time 108781791170 ps
CPU time 478.78 seconds
Started May 02 02:44:43 PM PDT 24
Finished May 02 02:52:43 PM PDT 24
Peak memory 199720 kb
Host smart-925cbbd4-b18e-4fb5-8e03-7588740ba95c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846506028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2846506028
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3509126126
Short name T322
Test name
Test status
Simulation time 327071433 ps
CPU time 1 seconds
Started May 02 02:44:46 PM PDT 24
Finished May 02 02:44:48 PM PDT 24
Peak memory 199216 kb
Host smart-044f362d-103b-4d70-991f-afc5c3ac7337
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509126126 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3509126126
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3462038188
Short name T320
Test name
Test status
Simulation time 7765738808 ps
CPU time 444.49 seconds
Started May 02 02:44:45 PM PDT 24
Finished May 02 02:52:11 PM PDT 24
Peak memory 199428 kb
Host smart-d3f54dc2-6db3-48b2-93a5-b79e95509e83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462038188 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3462038188
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3781748089
Short name T493
Test name
Test status
Simulation time 5081416208 ps
CPU time 42.7 seconds
Started May 02 02:44:44 PM PDT 24
Finished May 02 02:45:28 PM PDT 24
Peak memory 199692 kb
Host smart-0d13ed0b-5410-44e4-b2f0-d398c3978d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781748089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3781748089
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.2255327508
Short name T524
Test name
Test status
Simulation time 129100514310 ps
CPU time 966.46 seconds
Started May 02 02:48:05 PM PDT 24
Finished May 02 03:04:13 PM PDT 24
Peak memory 230424 kb
Host smart-cb10d91a-dd83-4f4c-ae6b-9e59792e4694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255327508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.2255327508
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1473531826
Short name T310
Test name
Test status
Simulation time 47004429 ps
CPU time 0.53 seconds
Started May 02 02:44:45 PM PDT 24
Finished May 02 02:44:47 PM PDT 24
Peak memory 194164 kb
Host smart-8874666f-d015-494d-9ee3-be8387cba815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473531826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1473531826
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.4159814599
Short name T273
Test name
Test status
Simulation time 6379091287 ps
CPU time 52.78 seconds
Started May 02 02:44:49 PM PDT 24
Finished May 02 02:45:43 PM PDT 24
Peak memory 224024 kb
Host smart-1bf5981a-16b4-4926-92df-6eac16a30171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159814599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.4159814599
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3223968368
Short name T211
Test name
Test status
Simulation time 161491676 ps
CPU time 7.08 seconds
Started May 02 02:44:42 PM PDT 24
Finished May 02 02:44:50 PM PDT 24
Peak memory 199696 kb
Host smart-1a77fa18-c25f-4ebf-ba3e-3ba907036b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223968368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3223968368
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1796426547
Short name T80
Test name
Test status
Simulation time 10276700427 ps
CPU time 137.93 seconds
Started May 02 02:44:42 PM PDT 24
Finished May 02 02:47:01 PM PDT 24
Peak memory 199728 kb
Host smart-a4d47820-fc76-48f9-bb28-8c57c4e0b807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796426547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1796426547
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1203497300
Short name T153
Test name
Test status
Simulation time 138232408472 ps
CPU time 118.34 seconds
Started May 02 02:44:43 PM PDT 24
Finished May 02 02:46:43 PM PDT 24
Peak memory 199728 kb
Host smart-d9737463-ad34-4066-9784-77a7eef9b8e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203497300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1203497300
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2938844975
Short name T82
Test name
Test status
Simulation time 24114530797 ps
CPU time 68.81 seconds
Started May 02 02:44:44 PM PDT 24
Finished May 02 02:45:54 PM PDT 24
Peak memory 199544 kb
Host smart-10581141-51c3-41ab-bbec-9bfd9499359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938844975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2938844975
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1298577951
Short name T517
Test name
Test status
Simulation time 419714940 ps
CPU time 5.07 seconds
Started May 02 02:44:44 PM PDT 24
Finished May 02 02:44:51 PM PDT 24
Peak memory 199648 kb
Host smart-691c4659-7182-457b-9dbb-cd58d48039ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298577951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1298577951
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3346439313
Short name T564
Test name
Test status
Simulation time 53449612180 ps
CPU time 670.92 seconds
Started May 02 02:44:45 PM PDT 24
Finished May 02 02:55:57 PM PDT 24
Peak memory 199560 kb
Host smart-36a56289-1b1e-4e4e-9478-3271484e20dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346439313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3346439313
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.58840409
Short name T206
Test name
Test status
Simulation time 114922339 ps
CPU time 1.24 seconds
Started May 02 02:44:44 PM PDT 24
Finished May 02 02:44:47 PM PDT 24
Peak memory 199580 kb
Host smart-70d00a59-3cb6-4b5f-9d6d-d3cacc4a3fa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58840409 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.hmac_test_hmac_vectors.58840409
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1317805145
Short name T278
Test name
Test status
Simulation time 25925993791 ps
CPU time 480.42 seconds
Started May 02 02:44:44 PM PDT 24
Finished May 02 02:52:46 PM PDT 24
Peak memory 199688 kb
Host smart-36c5df46-2ade-4687-b3da-8bc7b4bebed3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317805145 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1317805145
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2085314921
Short name T444
Test name
Test status
Simulation time 6026726141 ps
CPU time 55.45 seconds
Started May 02 02:44:42 PM PDT 24
Finished May 02 02:45:39 PM PDT 24
Peak memory 199748 kb
Host smart-d9a145e3-a2f7-43de-9dfd-2aefe9070cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085314921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2085314921
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.1030443402
Short name T12
Test name
Test status
Simulation time 69602553262 ps
CPU time 1375.17 seconds
Started May 02 02:48:02 PM PDT 24
Finished May 02 03:10:59 PM PDT 24
Peak memory 216848 kb
Host smart-61dda26b-d6a6-4463-af73-3a75aa23c72f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030443402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.1030443402
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1945124868
Short name T188
Test name
Test status
Simulation time 16294723 ps
CPU time 0.56 seconds
Started May 02 02:44:55 PM PDT 24
Finished May 02 02:44:57 PM PDT 24
Peak memory 195256 kb
Host smart-4314cd45-027c-455b-b6a4-2b03a72499f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945124868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1945124868
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2670318739
Short name T572
Test name
Test status
Simulation time 21735479957 ps
CPU time 66.83 seconds
Started May 02 02:44:52 PM PDT 24
Finished May 02 02:46:01 PM PDT 24
Peak memory 247960 kb
Host smart-47ef42b0-cdda-47cd-bf23-9fb18cde4ec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670318739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2670318739
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1634150614
Short name T286
Test name
Test status
Simulation time 1954350631 ps
CPU time 25.43 seconds
Started May 02 02:44:53 PM PDT 24
Finished May 02 02:45:20 PM PDT 24
Peak memory 199692 kb
Host smart-b0cdfa3a-1d61-406f-a654-58ddb36a76c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634150614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1634150614
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.584071394
Short name T339
Test name
Test status
Simulation time 120194474 ps
CPU time 8.18 seconds
Started May 02 02:44:53 PM PDT 24
Finished May 02 02:45:03 PM PDT 24
Peak memory 199616 kb
Host smart-99908deb-4fb8-4599-8feb-a93d98f0c992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584071394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.584071394
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2591943031
Short name T18
Test name
Test status
Simulation time 39509920685 ps
CPU time 121.56 seconds
Started May 02 02:44:51 PM PDT 24
Finished May 02 02:46:54 PM PDT 24
Peak memory 199696 kb
Host smart-e98ab47e-f654-4f8b-b4c0-996cb9c8fdb6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591943031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2591943031
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1921872623
Short name T239
Test name
Test status
Simulation time 5123243978 ps
CPU time 93.45 seconds
Started May 02 02:44:44 PM PDT 24
Finished May 02 02:46:19 PM PDT 24
Peak memory 199732 kb
Host smart-81d483b4-69fa-4210-85c5-d565497cdb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921872623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1921872623
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3584623619
Short name T277
Test name
Test status
Simulation time 244397740 ps
CPU time 3.83 seconds
Started May 02 02:44:45 PM PDT 24
Finished May 02 02:44:50 PM PDT 24
Peak memory 199640 kb
Host smart-0f65ff9f-0c43-4832-93d1-c23f298d8a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584623619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3584623619
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.4186075682
Short name T553
Test name
Test status
Simulation time 141894339711 ps
CPU time 2076.93 seconds
Started May 02 02:44:51 PM PDT 24
Finished May 02 03:19:30 PM PDT 24
Peak memory 207900 kb
Host smart-5e51ecfa-5e93-4a92-9593-891ef5d73d97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186075682 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4186075682
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2221162652
Short name T565
Test name
Test status
Simulation time 52431253283 ps
CPU time 1134.03 seconds
Started May 02 02:44:54 PM PDT 24
Finished May 02 03:03:50 PM PDT 24
Peak memory 248996 kb
Host smart-a2fd4053-2b1f-4536-965a-24ba848c8ffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221162652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.2221162652
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.129584644
Short name T315
Test name
Test status
Simulation time 194287185 ps
CPU time 1.05 seconds
Started May 02 02:44:55 PM PDT 24
Finished May 02 02:44:57 PM PDT 24
Peak memory 199116 kb
Host smart-a71d0bfc-944b-441f-a129-3d733d2d1cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129584644 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.129584644
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2762179500
Short name T578
Test name
Test status
Simulation time 47168507512 ps
CPU time 523.45 seconds
Started May 02 02:44:51 PM PDT 24
Finished May 02 02:53:36 PM PDT 24
Peak memory 199704 kb
Host smart-88b1197c-adf8-4f6f-8d57-e8c14441316b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762179500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2762179500
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.36458687
Short name T589
Test name
Test status
Simulation time 918610121 ps
CPU time 12.88 seconds
Started May 02 02:44:54 PM PDT 24
Finished May 02 02:45:09 PM PDT 24
Peak memory 199676 kb
Host smart-d4a1cbc5-9111-4435-bd28-ffaffd69b781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36458687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.36458687
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1280575302
Short name T293
Test name
Test status
Simulation time 11640808 ps
CPU time 0.55 seconds
Started May 02 02:44:56 PM PDT 24
Finished May 02 02:44:58 PM PDT 24
Peak memory 195248 kb
Host smart-33d06ecf-dabc-4d95-bca5-dd37c1c79121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280575302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1280575302
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2159631564
Short name T205
Test name
Test status
Simulation time 366391382 ps
CPU time 11.33 seconds
Started May 02 02:44:50 PM PDT 24
Finished May 02 02:45:03 PM PDT 24
Peak memory 207892 kb
Host smart-69a553d0-ef76-4128-a1c7-8987d4ad1755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159631564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2159631564
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4282700386
Short name T255
Test name
Test status
Simulation time 315333316 ps
CPU time 16.36 seconds
Started May 02 02:44:52 PM PDT 24
Finished May 02 02:45:10 PM PDT 24
Peak memory 199656 kb
Host smart-700f9859-4cde-4544-8dea-de387c960cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282700386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4282700386
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3288628768
Short name T483
Test name
Test status
Simulation time 4365183104 ps
CPU time 97.01 seconds
Started May 02 02:44:55 PM PDT 24
Finished May 02 02:46:33 PM PDT 24
Peak memory 199736 kb
Host smart-3dfdc426-09ae-47f8-8ad8-87374dbaedbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288628768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3288628768
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2032568182
Short name T495
Test name
Test status
Simulation time 7250465782 ps
CPU time 195.74 seconds
Started May 02 02:44:52 PM PDT 24
Finished May 02 02:48:10 PM PDT 24
Peak memory 199792 kb
Host smart-a2ce418a-7514-4b03-ac46-3cb554d03190
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032568182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2032568182
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1997072373
Short name T582
Test name
Test status
Simulation time 84660359 ps
CPU time 4.98 seconds
Started May 02 02:44:53 PM PDT 24
Finished May 02 02:45:00 PM PDT 24
Peak memory 199596 kb
Host smart-7fb0c8b6-dab2-4f5c-b77b-8d280457df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997072373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1997072373
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3780741285
Short name T177
Test name
Test status
Simulation time 25828478 ps
CPU time 0.78 seconds
Started May 02 02:44:54 PM PDT 24
Finished May 02 02:44:56 PM PDT 24
Peak memory 197008 kb
Host smart-210d356a-1cd4-4424-b229-87f3e22c5afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780741285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3780741285
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3524353483
Short name T167
Test name
Test status
Simulation time 96277503156 ps
CPU time 1248.28 seconds
Started May 02 02:44:55 PM PDT 24
Finished May 02 03:05:45 PM PDT 24
Peak memory 199728 kb
Host smart-92a76a63-581e-4abd-a306-d4fcf326605d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524353483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3524353483
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3437456826
Short name T76
Test name
Test status
Simulation time 34116319 ps
CPU time 0.98 seconds
Started May 02 02:44:57 PM PDT 24
Finished May 02 02:44:59 PM PDT 24
Peak memory 199096 kb
Host smart-bb073d08-0d02-470b-bcd8-cb9789f221fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437456826 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3437456826
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2197166829
Short name T552
Test name
Test status
Simulation time 75957934499 ps
CPU time 385.17 seconds
Started May 02 02:44:56 PM PDT 24
Finished May 02 02:51:23 PM PDT 24
Peak memory 199688 kb
Host smart-6c27097c-82f0-4a8f-914c-8feefced588a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197166829 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.2197166829
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2119275678
Short name T280
Test name
Test status
Simulation time 6636958175 ps
CPU time 65.39 seconds
Started May 02 02:44:50 PM PDT 24
Finished May 02 02:45:57 PM PDT 24
Peak memory 199752 kb
Host smart-cebdfdf4-b9cb-4788-86c4-b02530b80407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119275678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2119275678
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3456642095
Short name T407
Test name
Test status
Simulation time 19148353 ps
CPU time 0.59 seconds
Started May 02 02:45:03 PM PDT 24
Finished May 02 02:45:05 PM PDT 24
Peak memory 195364 kb
Host smart-28dc3ed1-e974-4fb1-8d0d-ca6b55e31c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456642095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3456642095
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2979633639
Short name T258
Test name
Test status
Simulation time 4134166718 ps
CPU time 41.21 seconds
Started May 02 02:44:58 PM PDT 24
Finished May 02 02:45:41 PM PDT 24
Peak memory 240720 kb
Host smart-74d6e6f9-881e-485c-98e0-c9e14385d9f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979633639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2979633639
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3655115178
Short name T453
Test name
Test status
Simulation time 2905045684 ps
CPU time 40.96 seconds
Started May 02 02:44:56 PM PDT 24
Finished May 02 02:45:39 PM PDT 24
Peak memory 199728 kb
Host smart-7f201621-0f42-41d1-9a94-268746ccff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655115178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3655115178
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1649068315
Short name T501
Test name
Test status
Simulation time 1558697142 ps
CPU time 22.6 seconds
Started May 02 02:45:00 PM PDT 24
Finished May 02 02:45:23 PM PDT 24
Peak memory 199696 kb
Host smart-954240e2-073e-4011-8977-219577f5aa12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649068315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1649068315
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4232119740
Short name T341
Test name
Test status
Simulation time 3351921634 ps
CPU time 183.96 seconds
Started May 02 02:44:57 PM PDT 24
Finished May 02 02:48:03 PM PDT 24
Peak memory 199756 kb
Host smart-609f7bf4-0778-4f98-a437-ed2cfdc95d1d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232119740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4232119740
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2303081680
Short name T309
Test name
Test status
Simulation time 17221197938 ps
CPU time 39.88 seconds
Started May 02 02:44:56 PM PDT 24
Finished May 02 02:45:37 PM PDT 24
Peak memory 199760 kb
Host smart-f26e4ce1-31fe-4359-8b86-08c6b3be6f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303081680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2303081680
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1069093352
Short name T86
Test name
Test status
Simulation time 370548033 ps
CPU time 5.68 seconds
Started May 02 02:44:55 PM PDT 24
Finished May 02 02:45:02 PM PDT 24
Peak memory 199688 kb
Host smart-9ba9a4d4-924d-443d-83ec-ecc10522321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069093352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1069093352
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3047746772
Short name T374
Test name
Test status
Simulation time 28988079911 ps
CPU time 117.28 seconds
Started May 02 02:44:56 PM PDT 24
Finished May 02 02:46:55 PM PDT 24
Peak memory 199744 kb
Host smart-e5e72c82-6868-4eea-82ea-8112da83b968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047746772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3047746772
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1491585449
Short name T4
Test name
Test status
Simulation time 212269326 ps
CPU time 1.18 seconds
Started May 02 02:44:59 PM PDT 24
Finished May 02 02:45:01 PM PDT 24
Peak memory 199488 kb
Host smart-1bcea72f-e1ae-4380-9701-6428b9f832a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491585449 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1491585449
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3868220513
Short name T474
Test name
Test status
Simulation time 35418539985 ps
CPU time 471.12 seconds
Started May 02 02:44:59 PM PDT 24
Finished May 02 02:52:52 PM PDT 24
Peak memory 199676 kb
Host smart-ee44211f-a67d-45b3-8733-5f7fce4fbf7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868220513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3868220513
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.253095053
Short name T70
Test name
Test status
Simulation time 2138679322 ps
CPU time 82.7 seconds
Started May 02 02:44:57 PM PDT 24
Finished May 02 02:46:22 PM PDT 24
Peak memory 199752 kb
Host smart-4701f815-4708-4194-a671-b009dabd655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253095053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.253095053
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2408543042
Short name T477
Test name
Test status
Simulation time 45764759 ps
CPU time 0.6 seconds
Started May 02 02:45:02 PM PDT 24
Finished May 02 02:45:04 PM PDT 24
Peak memory 195312 kb
Host smart-1a14ac73-22a4-4f68-951a-6ac9ce57e374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408543042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2408543042
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.677087085
Short name T432
Test name
Test status
Simulation time 5113563211 ps
CPU time 9.12 seconds
Started May 02 02:45:04 PM PDT 24
Finished May 02 02:45:15 PM PDT 24
Peak memory 199720 kb
Host smart-6915bad8-3343-4124-8506-29ab8d959609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677087085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.677087085
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1390933270
Short name T78
Test name
Test status
Simulation time 530675511 ps
CPU time 6.45 seconds
Started May 02 02:45:06 PM PDT 24
Finished May 02 02:45:13 PM PDT 24
Peak memory 199648 kb
Host smart-c47aafcc-0765-4524-89aa-eff337e71c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390933270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1390933270
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2432319660
Short name T245
Test name
Test status
Simulation time 2712625963 ps
CPU time 73.65 seconds
Started May 02 02:45:01 PM PDT 24
Finished May 02 02:46:16 PM PDT 24
Peak memory 199744 kb
Host smart-8ab75c68-d522-4d80-9b19-6f23410495d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432319660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2432319660
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.420649152
Short name T345
Test name
Test status
Simulation time 7299232977 ps
CPU time 89.47 seconds
Started May 02 02:45:01 PM PDT 24
Finished May 02 02:46:32 PM PDT 24
Peak memory 199716 kb
Host smart-36438d4d-f4a2-4be2-9469-fac486d3aaf7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420649152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.420649152
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3619911324
Short name T124
Test name
Test status
Simulation time 10572635264 ps
CPU time 12.66 seconds
Started May 02 02:45:01 PM PDT 24
Finished May 02 02:45:15 PM PDT 24
Peak memory 199772 kb
Host smart-7a645d85-7a0b-4ec7-82a4-3655e0d7427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619911324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3619911324
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1518489376
Short name T192
Test name
Test status
Simulation time 242927174 ps
CPU time 2.78 seconds
Started May 02 02:45:03 PM PDT 24
Finished May 02 02:45:07 PM PDT 24
Peak memory 199664 kb
Host smart-cdb40244-da3f-4035-a2b6-7db4fd52f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518489376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1518489376
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1607719213
Short name T233
Test name
Test status
Simulation time 186921154427 ps
CPU time 446.83 seconds
Started May 02 02:45:04 PM PDT 24
Finished May 02 02:52:32 PM PDT 24
Peak memory 233512 kb
Host smart-fd3b05dc-bfbc-4784-8202-2b55933071d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607719213 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1607719213
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.4025450393
Short name T225
Test name
Test status
Simulation time 111699889 ps
CPU time 1.15 seconds
Started May 02 02:45:04 PM PDT 24
Finished May 02 02:45:07 PM PDT 24
Peak memory 198688 kb
Host smart-97b720e5-e70c-45b5-9077-40ab0be68271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025450393 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.4025450393
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1760544550
Short name T166
Test name
Test status
Simulation time 71183243833 ps
CPU time 430.68 seconds
Started May 02 02:45:02 PM PDT 24
Finished May 02 02:52:14 PM PDT 24
Peak memory 199644 kb
Host smart-d80f4a9f-c781-4b9c-9b81-2526af348350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760544550 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1760544550
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.208869204
Short name T226
Test name
Test status
Simulation time 565189303 ps
CPU time 8.13 seconds
Started May 02 02:45:01 PM PDT 24
Finished May 02 02:45:11 PM PDT 24
Peak memory 199668 kb
Host smart-1d699b39-323d-4601-8525-878d78cb621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208869204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.208869204
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.2643596009
Short name T13
Test name
Test status
Simulation time 218289039296 ps
CPU time 2386.02 seconds
Started May 02 02:48:18 PM PDT 24
Finished May 02 03:28:06 PM PDT 24
Peak memory 256836 kb
Host smart-c432ef01-338b-4a37-b93e-10253a1c9716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643596009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.2643596009
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.3264592755
Short name T584
Test name
Test status
Simulation time 33120313736 ps
CPU time 420.07 seconds
Started May 02 02:48:30 PM PDT 24
Finished May 02 02:55:31 PM PDT 24
Peak memory 248368 kb
Host smart-5a677430-01cb-4725-a186-221ecabc45d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264592755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.3264592755
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2237149298
Short name T510
Test name
Test status
Simulation time 12530888 ps
CPU time 0.54 seconds
Started May 02 02:45:07 PM PDT 24
Finished May 02 02:45:09 PM PDT 24
Peak memory 194376 kb
Host smart-0e050402-ce6d-4332-b1dc-506c944561be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237149298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2237149298
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4168587562
Short name T597
Test name
Test status
Simulation time 1984462853 ps
CPU time 18.61 seconds
Started May 02 02:45:04 PM PDT 24
Finished May 02 02:45:24 PM PDT 24
Peak memory 207864 kb
Host smart-41be325d-9bf4-4947-95d5-664689f37420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168587562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4168587562
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2299655421
Short name T21
Test name
Test status
Simulation time 1071645714 ps
CPU time 13.64 seconds
Started May 02 02:45:10 PM PDT 24
Finished May 02 02:45:25 PM PDT 24
Peak memory 199688 kb
Host smart-bc507096-bdc3-4036-ac41-849e696a6d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299655421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2299655421
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2921262320
Short name T279
Test name
Test status
Simulation time 5997681926 ps
CPU time 74.01 seconds
Started May 02 02:45:08 PM PDT 24
Finished May 02 02:46:23 PM PDT 24
Peak memory 199748 kb
Host smart-2c1f2a06-c872-439c-8dcc-174c37846f09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2921262320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2921262320
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.792642465
Short name T66
Test name
Test status
Simulation time 76143082619 ps
CPU time 287.02 seconds
Started May 02 02:45:07 PM PDT 24
Finished May 02 02:49:56 PM PDT 24
Peak memory 199764 kb
Host smart-3a53083d-56a0-46f6-bc8b-a0fddc5564fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792642465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.792642465
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2730759420
Short name T360
Test name
Test status
Simulation time 5735512817 ps
CPU time 86.62 seconds
Started May 02 02:45:04 PM PDT 24
Finished May 02 02:46:32 PM PDT 24
Peak memory 199696 kb
Host smart-797eb7f5-f5ff-4107-bac8-2138c26f57b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730759420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2730759420
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2777188547
Short name T314
Test name
Test status
Simulation time 36616473 ps
CPU time 1.36 seconds
Started May 02 02:45:05 PM PDT 24
Finished May 02 02:45:08 PM PDT 24
Peak memory 199604 kb
Host smart-5e045f6e-4888-4eb6-a3a8-bccbf7a348df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777188547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2777188547
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.418589956
Short name T378
Test name
Test status
Simulation time 144298459255 ps
CPU time 1308.75 seconds
Started May 02 02:45:09 PM PDT 24
Finished May 02 03:06:59 PM PDT 24
Peak memory 215960 kb
Host smart-a655dfc9-a783-4094-8d00-583fb761b9c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418589956 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.418589956
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3938444142
Short name T296
Test name
Test status
Simulation time 112533280 ps
CPU time 1.02 seconds
Started May 02 02:45:07 PM PDT 24
Finished May 02 02:45:10 PM PDT 24
Peak memory 199272 kb
Host smart-17a26818-1635-41a6-b674-96d601018a34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938444142 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3938444142
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2919751511
Short name T439
Test name
Test status
Simulation time 104883237034 ps
CPU time 455.18 seconds
Started May 02 02:45:08 PM PDT 24
Finished May 02 02:52:45 PM PDT 24
Peak memory 199684 kb
Host smart-3186fa58-add8-4997-b2b0-0015c77ffa19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919751511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2919751511
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2378628291
Short name T347
Test name
Test status
Simulation time 16246129294 ps
CPU time 72.64 seconds
Started May 02 02:45:11 PM PDT 24
Finished May 02 02:46:25 PM PDT 24
Peak memory 199700 kb
Host smart-a634bd88-0098-400e-86a0-4c8739fd5ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378628291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2378628291
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3136279205
Short name T45
Test name
Test status
Simulation time 1266734914 ps
CPU time 11.82 seconds
Started May 02 02:45:09 PM PDT 24
Finished May 02 02:45:22 PM PDT 24
Peak memory 207816 kb
Host smart-08a5dd0c-ff81-41f1-b8c3-c9ef652ef8fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136279205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3136279205
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3003111306
Short name T190
Test name
Test status
Simulation time 90979266 ps
CPU time 2.13 seconds
Started May 02 02:45:08 PM PDT 24
Finished May 02 02:45:11 PM PDT 24
Peak memory 199608 kb
Host smart-547d7e1b-3a7c-40bf-83bd-5bebf41bec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003111306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3003111306
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2033327459
Short name T88
Test name
Test status
Simulation time 1566906388 ps
CPU time 50.99 seconds
Started May 02 02:45:09 PM PDT 24
Finished May 02 02:46:02 PM PDT 24
Peak memory 199664 kb
Host smart-78710f5d-c3a1-4ff2-aa40-8d8e5ec0753c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033327459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2033327459
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.142560692
Short name T199
Test name
Test status
Simulation time 5144404014 ps
CPU time 168.67 seconds
Started May 02 02:45:08 PM PDT 24
Finished May 02 02:47:58 PM PDT 24
Peak memory 199704 kb
Host smart-b89bca97-eb31-478e-9b57-02631909649d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142560692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.142560692
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.690976045
Short name T144
Test name
Test status
Simulation time 5483276745 ps
CPU time 114.63 seconds
Started May 02 02:45:10 PM PDT 24
Finished May 02 02:47:06 PM PDT 24
Peak memory 199724 kb
Host smart-00a9534a-52c4-4df4-bc27-8ea66b6869d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690976045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.690976045
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3022812768
Short name T196
Test name
Test status
Simulation time 360666101 ps
CPU time 1.34 seconds
Started May 02 02:45:10 PM PDT 24
Finished May 02 02:45:12 PM PDT 24
Peak memory 199672 kb
Host smart-953b2888-9bc7-4602-a204-bfe966a581c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022812768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3022812768
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3386435993
Short name T538
Test name
Test status
Simulation time 13567592878 ps
CPU time 186.33 seconds
Started May 02 02:45:15 PM PDT 24
Finished May 02 02:48:23 PM PDT 24
Peak memory 199732 kb
Host smart-34ab59e2-431b-441d-84a3-23bb91edc2cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386435993 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3386435993
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.362316839
Short name T131
Test name
Test status
Simulation time 54388784 ps
CPU time 1.25 seconds
Started May 02 02:45:14 PM PDT 24
Finished May 02 02:45:17 PM PDT 24
Peak memory 198556 kb
Host smart-eb16c412-883b-4b90-9f06-a53f811d4ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362316839 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.362316839
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2541821961
Short name T257
Test name
Test status
Simulation time 34541174739 ps
CPU time 450.82 seconds
Started May 02 02:45:10 PM PDT 24
Finished May 02 02:52:42 PM PDT 24
Peak memory 199652 kb
Host smart-cc266120-6ec3-4f82-a73c-39b515e40c43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541821961 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2541821961
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3935240951
Short name T305
Test name
Test status
Simulation time 1839743517 ps
CPU time 35.25 seconds
Started May 02 02:45:08 PM PDT 24
Finished May 02 02:45:45 PM PDT 24
Peak memory 199748 kb
Host smart-840f22c4-c326-47b2-9c00-95ae19258c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935240951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3935240951
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.3125113223
Short name T60
Test name
Test status
Simulation time 88029685872 ps
CPU time 1343.12 seconds
Started May 02 02:48:29 PM PDT 24
Finished May 02 03:10:53 PM PDT 24
Peak memory 214192 kb
Host smart-bd4b2f8d-9a13-4895-9d8a-ad0f765dfb17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125113223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.3125113223
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3129932998
Short name T209
Test name
Test status
Simulation time 12830638 ps
CPU time 0.6 seconds
Started May 02 02:45:23 PM PDT 24
Finished May 02 02:45:25 PM PDT 24
Peak memory 195236 kb
Host smart-e676c13c-4610-4922-9dc7-3d6bd9dd3070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129932998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3129932998
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2022072806
Short name T46
Test name
Test status
Simulation time 245554369 ps
CPU time 9.18 seconds
Started May 02 02:45:17 PM PDT 24
Finished May 02 02:45:27 PM PDT 24
Peak memory 215120 kb
Host smart-d2bb69c5-7043-40b2-a538-158cef1d7352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022072806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2022072806
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.815065811
Short name T459
Test name
Test status
Simulation time 1845181405 ps
CPU time 90.62 seconds
Started May 02 02:45:18 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199648 kb
Host smart-b831be8b-84f6-48e0-8d6b-85669a462933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815065811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.815065811
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3705416339
Short name T451
Test name
Test status
Simulation time 5746494278 ps
CPU time 117.53 seconds
Started May 02 02:45:17 PM PDT 24
Finished May 02 02:47:16 PM PDT 24
Peak memory 199700 kb
Host smart-0eb1d283-d0e2-4921-b9e2-c29f2acbcc09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705416339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3705416339
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3732891263
Short name T291
Test name
Test status
Simulation time 15249946157 ps
CPU time 162.24 seconds
Started May 02 02:45:17 PM PDT 24
Finished May 02 02:48:00 PM PDT 24
Peak memory 199756 kb
Host smart-172c0027-7b70-468c-8ac9-dd4a37d80a7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732891263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3732891263
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3617928453
Short name T308
Test name
Test status
Simulation time 51236988684 ps
CPU time 117.7 seconds
Started May 02 02:45:16 PM PDT 24
Finished May 02 02:47:15 PM PDT 24
Peak memory 199780 kb
Host smart-3b82f5ee-5a41-4c73-ae31-4d72fc5a8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617928453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3617928453
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2691021544
Short name T252
Test name
Test status
Simulation time 113967502 ps
CPU time 1.83 seconds
Started May 02 02:45:18 PM PDT 24
Finished May 02 02:45:22 PM PDT 24
Peak memory 199652 kb
Host smart-3ed2ce58-3192-4f3a-a49a-7e2f57b4352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691021544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2691021544
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3109405232
Short name T585
Test name
Test status
Simulation time 404479091514 ps
CPU time 1315.83 seconds
Started May 02 02:45:23 PM PDT 24
Finished May 02 03:07:20 PM PDT 24
Peak memory 244800 kb
Host smart-8e776d0b-ff9e-43dd-ada9-c0a7b94b141c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109405232 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3109405232
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.713848642
Short name T208
Test name
Test status
Simulation time 105657620 ps
CPU time 1.04 seconds
Started May 02 02:45:21 PM PDT 24
Finished May 02 02:45:23 PM PDT 24
Peak memory 199124 kb
Host smart-f7c89dd7-0848-489c-876f-8bf54a230f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713848642 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.713848642
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1264658445
Short name T595
Test name
Test status
Simulation time 100162345036 ps
CPU time 510.4 seconds
Started May 02 02:45:15 PM PDT 24
Finished May 02 02:53:47 PM PDT 24
Peak memory 199668 kb
Host smart-8214e66b-f57f-46de-9fe5-fd02bc7e4463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264658445 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.1264658445
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.344433372
Short name T299
Test name
Test status
Simulation time 1109740098 ps
CPU time 8.08 seconds
Started May 02 02:45:14 PM PDT 24
Finished May 02 02:45:23 PM PDT 24
Peak memory 199588 kb
Host smart-73c4a16a-b90a-48a6-9296-491daca26909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344433372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.344433372
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3393597905
Short name T367
Test name
Test status
Simulation time 34035576 ps
CPU time 0.56 seconds
Started May 02 02:45:29 PM PDT 24
Finished May 02 02:45:30 PM PDT 24
Peak memory 195004 kb
Host smart-848659c9-5f95-47aa-bba4-58985c201057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393597905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3393597905
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.987449295
Short name T588
Test name
Test status
Simulation time 3548958752 ps
CPU time 42.56 seconds
Started May 02 02:45:22 PM PDT 24
Finished May 02 02:46:06 PM PDT 24
Peak memory 232148 kb
Host smart-e5550098-a030-4c9d-a0f2-b1889525c555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987449295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.987449295
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1749452164
Short name T150
Test name
Test status
Simulation time 1573485844 ps
CPU time 21.73 seconds
Started May 02 02:45:20 PM PDT 24
Finished May 02 02:45:43 PM PDT 24
Peak memory 199672 kb
Host smart-9abcaf1d-67d0-43f4-b5e9-144e44cc3382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749452164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1749452164
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_error.846120732
Short name T251
Test name
Test status
Simulation time 37210729095 ps
CPU time 165.53 seconds
Started May 02 02:45:22 PM PDT 24
Finished May 02 02:48:08 PM PDT 24
Peak memory 199776 kb
Host smart-aba90d03-4f25-4918-8d2d-6ae568e95c5f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846120732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.846120732
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.22731305
Short name T164
Test name
Test status
Simulation time 3415798808 ps
CPU time 99.42 seconds
Started May 02 02:45:22 PM PDT 24
Finished May 02 02:47:03 PM PDT 24
Peak memory 199728 kb
Host smart-6d05e9c6-e681-4e27-9f6a-345af035b9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22731305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.22731305
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3820241569
Short name T417
Test name
Test status
Simulation time 1352266889 ps
CPU time 2.91 seconds
Started May 02 02:45:22 PM PDT 24
Finished May 02 02:45:26 PM PDT 24
Peak memory 199648 kb
Host smart-7d23880f-69f5-4d8c-87d0-66a90790d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820241569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3820241569
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.990688858
Short name T168
Test name
Test status
Simulation time 171143556611 ps
CPU time 799.82 seconds
Started May 02 02:45:27 PM PDT 24
Finished May 02 02:58:48 PM PDT 24
Peak memory 212000 kb
Host smart-a8bfc528-4f89-4449-bd96-102a42faa52c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990688858 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.990688858
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1925276070
Short name T157
Test name
Test status
Simulation time 33173197 ps
CPU time 1.2 seconds
Started May 02 02:45:28 PM PDT 24
Finished May 02 02:45:30 PM PDT 24
Peak memory 199604 kb
Host smart-e9c2487a-4ec8-4926-b9c9-71f3f5512865
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925276070 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1925276070
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3288554353
Short name T227
Test name
Test status
Simulation time 13300045939 ps
CPU time 453.39 seconds
Started May 02 02:45:22 PM PDT 24
Finished May 02 02:52:57 PM PDT 24
Peak memory 199644 kb
Host smart-4d56de72-bf53-4f08-858c-a963549e0f44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288554353 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3288554353
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3154981514
Short name T581
Test name
Test status
Simulation time 7974533707 ps
CPU time 103.55 seconds
Started May 02 02:45:24 PM PDT 24
Finished May 02 02:47:09 PM PDT 24
Peak memory 199704 kb
Host smart-8224a8fb-377f-49e3-ac60-e98cf00907e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154981514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3154981514
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4054832350
Short name T419
Test name
Test status
Simulation time 23749495 ps
CPU time 0.59 seconds
Started May 02 02:44:02 PM PDT 24
Finished May 02 02:44:03 PM PDT 24
Peak memory 194284 kb
Host smart-668dbd8b-82a4-4a4f-913b-11308f6bf8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054832350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4054832350
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.415041588
Short name T187
Test name
Test status
Simulation time 6090049550 ps
CPU time 35.96 seconds
Started May 02 02:43:53 PM PDT 24
Finished May 02 02:44:30 PM PDT 24
Peak memory 207924 kb
Host smart-b267b10b-7f27-4538-bc48-17f2212288d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415041588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.415041588
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3450435682
Short name T475
Test name
Test status
Simulation time 1116458512 ps
CPU time 15.78 seconds
Started May 02 02:44:04 PM PDT 24
Finished May 02 02:44:20 PM PDT 24
Peak memory 199652 kb
Host smart-ba40a226-f6fe-4b5f-8509-9e09329f633a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450435682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3450435682
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1109956318
Short name T568
Test name
Test status
Simulation time 1414580553 ps
CPU time 37.73 seconds
Started May 02 02:44:00 PM PDT 24
Finished May 02 02:44:39 PM PDT 24
Peak memory 199492 kb
Host smart-57a05664-fe5c-4357-9f99-30d5175113e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109956318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1109956318
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1103432826
Short name T302
Test name
Test status
Simulation time 4175111739 ps
CPU time 48.53 seconds
Started May 02 02:43:55 PM PDT 24
Finished May 02 02:44:45 PM PDT 24
Peak memory 199740 kb
Host smart-20a09590-ba6d-4f87-b47f-722e6fd87637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103432826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1103432826
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2576517622
Short name T36
Test name
Test status
Simulation time 267052703 ps
CPU time 0.87 seconds
Started May 02 02:44:02 PM PDT 24
Finished May 02 02:44:03 PM PDT 24
Peak memory 218088 kb
Host smart-1d2d5334-06b9-4de5-af2a-ebcc7754b213
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576517622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2576517622
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2444879503
Short name T35
Test name
Test status
Simulation time 1633560918 ps
CPU time 6.25 seconds
Started May 02 02:43:59 PM PDT 24
Finished May 02 02:44:06 PM PDT 24
Peak memory 199424 kb
Host smart-7ccd1971-d4d7-4560-8da4-22c56d2fc7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444879503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2444879503
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4097714421
Short name T527
Test name
Test status
Simulation time 341377909746 ps
CPU time 1533.53 seconds
Started May 02 02:44:02 PM PDT 24
Finished May 02 03:09:37 PM PDT 24
Peak memory 216104 kb
Host smart-7e6eb96e-69ac-4ec0-a432-9c5f1984103c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097714421 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4097714421
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1249721384
Short name T346
Test name
Test status
Simulation time 115155519 ps
CPU time 1.24 seconds
Started May 02 02:44:02 PM PDT 24
Finished May 02 02:44:04 PM PDT 24
Peak memory 199580 kb
Host smart-6ed8ab87-5bd5-466f-aed0-d0ff62dc7ab7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249721384 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1249721384
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.341443400
Short name T468
Test name
Test status
Simulation time 160529842067 ps
CPU time 490.95 seconds
Started May 02 02:44:01 PM PDT 24
Finished May 02 02:52:13 PM PDT 24
Peak memory 199660 kb
Host smart-bb2b78c2-6902-4934-9abb-f8c8488a8ffa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341443400 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.341443400
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.179912794
Short name T30
Test name
Test status
Simulation time 513215908 ps
CPU time 9.28 seconds
Started May 02 02:44:03 PM PDT 24
Finished May 02 02:44:14 PM PDT 24
Peak memory 199652 kb
Host smart-78528b7d-2436-492e-ac85-d84f0722cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179912794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.179912794
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2506208766
Short name T242
Test name
Test status
Simulation time 48580692 ps
CPU time 0.59 seconds
Started May 02 02:45:37 PM PDT 24
Finished May 02 02:45:40 PM PDT 24
Peak memory 195324 kb
Host smart-d5e6d66a-c717-4530-9955-535430f87d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506208766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2506208766
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.712154562
Short name T243
Test name
Test status
Simulation time 1302766010 ps
CPU time 21.64 seconds
Started May 02 02:45:28 PM PDT 24
Finished May 02 02:45:51 PM PDT 24
Peak memory 207864 kb
Host smart-0033b1c9-292b-4b4b-81fa-c486b06b402d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712154562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.712154562
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.15587013
Short name T401
Test name
Test status
Simulation time 953376119 ps
CPU time 19.47 seconds
Started May 02 02:45:27 PM PDT 24
Finished May 02 02:45:47 PM PDT 24
Peak memory 199684 kb
Host smart-c7a55811-fbcc-40dd-95a7-1641f24d8d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15587013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.15587013
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3892433146
Short name T456
Test name
Test status
Simulation time 3561954315 ps
CPU time 96.89 seconds
Started May 02 02:45:28 PM PDT 24
Finished May 02 02:47:06 PM PDT 24
Peak memory 199652 kb
Host smart-905a42ff-3623-4ad0-9b8e-70c5702b6ac8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892433146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3892433146
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3602749670
Short name T522
Test name
Test status
Simulation time 2387671418 ps
CPU time 5.66 seconds
Started May 02 02:45:27 PM PDT 24
Finished May 02 02:45:34 PM PDT 24
Peak memory 199740 kb
Host smart-2ce5da62-2eef-4516-a41f-d9b18103a696
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602749670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3602749670
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2033590207
Short name T440
Test name
Test status
Simulation time 10562870415 ps
CPU time 72.85 seconds
Started May 02 02:45:28 PM PDT 24
Finished May 02 02:46:42 PM PDT 24
Peak memory 199752 kb
Host smart-acb151df-a6c7-48aa-a4e1-2e4bf3004d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033590207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2033590207
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2048378926
Short name T334
Test name
Test status
Simulation time 140645334 ps
CPU time 4.49 seconds
Started May 02 02:45:27 PM PDT 24
Finished May 02 02:45:32 PM PDT 24
Peak memory 199636 kb
Host smart-5899b42a-51ef-4c91-bfbc-4065e77dfb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048378926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2048378926
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2008982548
Short name T72
Test name
Test status
Simulation time 170148858268 ps
CPU time 1081.59 seconds
Started May 02 02:45:28 PM PDT 24
Finished May 02 03:03:31 PM PDT 24
Peak memory 215264 kb
Host smart-83d0e9be-99aa-49f1-bfb7-807088d6dbfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008982548 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2008982548
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.318621387
Short name T472
Test name
Test status
Simulation time 95947443 ps
CPU time 0.96 seconds
Started May 02 02:45:26 PM PDT 24
Finished May 02 02:45:29 PM PDT 24
Peak memory 199580 kb
Host smart-e49d37bd-a32d-4217-b686-3ce7331492eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318621387 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.318621387
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1762994199
Short name T361
Test name
Test status
Simulation time 30050679705 ps
CPU time 431.88 seconds
Started May 02 02:45:29 PM PDT 24
Finished May 02 02:52:42 PM PDT 24
Peak memory 199664 kb
Host smart-21371aac-57e1-42e7-ae8c-e26580b8c56b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762994199 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1762994199
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1638619315
Short name T413
Test name
Test status
Simulation time 3352171992 ps
CPU time 48.14 seconds
Started May 02 02:45:28 PM PDT 24
Finished May 02 02:46:17 PM PDT 24
Peak memory 199732 kb
Host smart-82e8ea09-5439-4040-a4b1-515d0177e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638619315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1638619315
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3672170006
Short name T195
Test name
Test status
Simulation time 33267621 ps
CPU time 0.59 seconds
Started May 02 02:45:40 PM PDT 24
Finished May 02 02:45:43 PM PDT 24
Peak memory 195368 kb
Host smart-35493bbe-dfed-4ed9-af39-59f0a7e84c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672170006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3672170006
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1434584100
Short name T414
Test name
Test status
Simulation time 2477666772 ps
CPU time 46.79 seconds
Started May 02 02:45:34 PM PDT 24
Finished May 02 02:46:23 PM PDT 24
Peak memory 232468 kb
Host smart-c9a4615e-7f81-4ffb-871c-9f992aff1f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434584100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1434584100
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3521515842
Short name T557
Test name
Test status
Simulation time 3898176186 ps
CPU time 48.58 seconds
Started May 02 02:45:33 PM PDT 24
Finished May 02 02:46:23 PM PDT 24
Peak memory 199736 kb
Host smart-dcd21fec-399a-4628-a95b-77b97285b98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521515842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3521515842
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3035991380
Short name T396
Test name
Test status
Simulation time 4027253563 ps
CPU time 118.72 seconds
Started May 02 02:45:35 PM PDT 24
Finished May 02 02:47:36 PM PDT 24
Peak memory 199720 kb
Host smart-cf397faa-d2cc-41ff-899b-ac90ad4c3911
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035991380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3035991380
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3634510294
Short name T87
Test name
Test status
Simulation time 6059717541 ps
CPU time 26.97 seconds
Started May 02 02:45:36 PM PDT 24
Finished May 02 02:46:05 PM PDT 24
Peak memory 199660 kb
Host smart-64931b32-7d4c-4e1e-9cba-8ab25b79d186
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634510294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3634510294
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2215685420
Short name T389
Test name
Test status
Simulation time 7933630383 ps
CPU time 82.9 seconds
Started May 02 02:45:37 PM PDT 24
Finished May 02 02:47:02 PM PDT 24
Peak memory 199708 kb
Host smart-65511532-0d76-49e2-944b-1dbcc48544e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215685420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2215685420
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4000381490
Short name T567
Test name
Test status
Simulation time 444349271 ps
CPU time 6.33 seconds
Started May 02 02:45:37 PM PDT 24
Finished May 02 02:45:46 PM PDT 24
Peak memory 199660 kb
Host smart-116ad97d-8984-420c-a039-db24ecbd8969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000381490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4000381490
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3853951675
Short name T19
Test name
Test status
Simulation time 21387409081 ps
CPU time 205.64 seconds
Started May 02 02:45:36 PM PDT 24
Finished May 02 02:49:04 PM PDT 24
Peak memory 199748 kb
Host smart-7998ebca-6829-4abc-b15d-167ddf18e11b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853951675 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3853951675
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.727228955
Short name T143
Test name
Test status
Simulation time 27709833 ps
CPU time 0.95 seconds
Started May 02 02:45:36 PM PDT 24
Finished May 02 02:45:38 PM PDT 24
Peak memory 198676 kb
Host smart-7c10474f-324f-4186-990b-34e390eba9cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727228955 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.727228955
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1923741047
Short name T397
Test name
Test status
Simulation time 38541566388 ps
CPU time 372.74 seconds
Started May 02 02:45:33 PM PDT 24
Finished May 02 02:51:47 PM PDT 24
Peak memory 199712 kb
Host smart-1e856607-da3b-44bf-b427-f9b5ad574925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923741047 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1923741047
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.379339693
Short name T509
Test name
Test status
Simulation time 1524705361 ps
CPU time 66.01 seconds
Started May 02 02:45:35 PM PDT 24
Finished May 02 02:46:42 PM PDT 24
Peak memory 199644 kb
Host smart-c6e8fced-a427-4675-9536-18d3de871ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379339693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.379339693
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1428631299
Short name T287
Test name
Test status
Simulation time 14489651 ps
CPU time 0.57 seconds
Started May 02 02:45:53 PM PDT 24
Finished May 02 02:45:58 PM PDT 24
Peak memory 195272 kb
Host smart-8524ad8d-d9a9-403b-b485-38327f500ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428631299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1428631299
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.4054015277
Short name T448
Test name
Test status
Simulation time 1673694029 ps
CPU time 19.37 seconds
Started May 02 02:45:41 PM PDT 24
Finished May 02 02:46:02 PM PDT 24
Peak memory 223780 kb
Host smart-be790695-f5f3-4720-bfd9-fd3cb4402293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054015277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4054015277
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1444738046
Short name T174
Test name
Test status
Simulation time 1715353987 ps
CPU time 16.93 seconds
Started May 02 02:45:52 PM PDT 24
Finished May 02 02:46:12 PM PDT 24
Peak memory 199644 kb
Host smart-0b15edd0-d7f2-47b0-9c9a-2fbb75af77fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444738046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1444738046
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.4259192158
Short name T387
Test name
Test status
Simulation time 8554679128 ps
CPU time 113.9 seconds
Started May 02 02:45:42 PM PDT 24
Finished May 02 02:47:38 PM PDT 24
Peak memory 199704 kb
Host smart-efff8a77-ce7f-4115-a085-73886b2fa249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259192158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.4259192158
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.683370200
Short name T15
Test name
Test status
Simulation time 18622454456 ps
CPU time 176.7 seconds
Started May 02 02:45:42 PM PDT 24
Finished May 02 02:48:40 PM PDT 24
Peak memory 199720 kb
Host smart-1789597b-cd36-4492-b5f2-cd8199953a0a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683370200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.683370200
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.489011150
Short name T390
Test name
Test status
Simulation time 2235286471 ps
CPU time 31.45 seconds
Started May 02 02:45:51 PM PDT 24
Finished May 02 02:46:24 PM PDT 24
Peak memory 199724 kb
Host smart-bc16fb10-1f02-4ffc-81fd-73e20980adaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489011150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.489011150
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3353895866
Short name T590
Test name
Test status
Simulation time 282043647 ps
CPU time 4.62 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 02:46:23 PM PDT 24
Peak memory 199664 kb
Host smart-28e52858-0440-4b3c-a10a-5e43a9a5a596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353895866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3353895866
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2358221424
Short name T369
Test name
Test status
Simulation time 42900919056 ps
CPU time 1116.25 seconds
Started May 02 02:45:41 PM PDT 24
Finished May 02 03:04:19 PM PDT 24
Peak memory 238596 kb
Host smart-65ad1e1e-1198-498e-8611-0fe4b778c112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358221424 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2358221424
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.785252875
Short name T235
Test name
Test status
Simulation time 280492600 ps
CPU time 1.33 seconds
Started May 02 02:45:42 PM PDT 24
Finished May 02 02:45:45 PM PDT 24
Peak memory 199636 kb
Host smart-846fdc7b-9507-44c4-ab0b-77bf0da659bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785252875 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.785252875
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3599964794
Short name T220
Test name
Test status
Simulation time 7380700378 ps
CPU time 423.07 seconds
Started May 02 02:45:42 PM PDT 24
Finished May 02 02:52:47 PM PDT 24
Peak memory 199704 kb
Host smart-4ec0b6c1-880d-4190-a545-5caa70d47be9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599964794 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.3599964794
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4216705119
Short name T262
Test name
Test status
Simulation time 8518780284 ps
CPU time 81.96 seconds
Started May 02 02:45:56 PM PDT 24
Finished May 02 02:47:22 PM PDT 24
Peak memory 199728 kb
Host smart-e7fca84b-443a-4ce6-8eb7-641ec482e0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216705119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4216705119
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2627002775
Short name T357
Test name
Test status
Simulation time 49899816 ps
CPU time 0.58 seconds
Started May 02 02:45:55 PM PDT 24
Finished May 02 02:45:59 PM PDT 24
Peak memory 195340 kb
Host smart-b9a9dfb2-c06b-4ce0-8f93-fa5d06863c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627002775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2627002775
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3190722800
Short name T479
Test name
Test status
Simulation time 1299066241 ps
CPU time 46.57 seconds
Started May 02 02:45:54 PM PDT 24
Finished May 02 02:46:44 PM PDT 24
Peak memory 224048 kb
Host smart-187dea2c-faa5-4a9a-ad4a-972bd1bc4e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190722800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3190722800
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.641524974
Short name T127
Test name
Test status
Simulation time 17516800812 ps
CPU time 41.4 seconds
Started May 02 02:45:42 PM PDT 24
Finished May 02 02:46:25 PM PDT 24
Peak memory 199704 kb
Host smart-4d7dbf0f-8138-4adc-a3b9-175f226e0dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641524974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.641524974
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2058991103
Short name T290
Test name
Test status
Simulation time 23816268083 ps
CPU time 72.94 seconds
Started May 02 02:45:43 PM PDT 24
Finished May 02 02:46:58 PM PDT 24
Peak memory 199712 kb
Host smart-1f4e7e2e-5135-4a10-93f6-7c5aa2d07059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058991103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2058991103
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.685172144
Short name T433
Test name
Test status
Simulation time 11788076920 ps
CPU time 27.31 seconds
Started May 02 02:45:51 PM PDT 24
Finished May 02 02:46:21 PM PDT 24
Peak memory 199708 kb
Host smart-0753d5a6-4348-4e58-a5a2-78cced8f5408
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685172144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.685172144
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1933283693
Short name T214
Test name
Test status
Simulation time 2487575605 ps
CPU time 61.1 seconds
Started May 02 02:45:52 PM PDT 24
Finished May 02 02:46:56 PM PDT 24
Peak memory 199760 kb
Host smart-7c568565-c2e1-4a26-9432-91d283e1d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933283693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1933283693
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.442015697
Short name T81
Test name
Test status
Simulation time 490105503 ps
CPU time 2.69 seconds
Started May 02 02:45:56 PM PDT 24
Finished May 02 02:46:02 PM PDT 24
Peak memory 199672 kb
Host smart-24be3922-1ce6-4e4d-97bd-edffacb921c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442015697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.442015697
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1030281084
Short name T343
Test name
Test status
Simulation time 208532876 ps
CPU time 1.21 seconds
Started May 02 02:45:53 PM PDT 24
Finished May 02 02:45:58 PM PDT 24
Peak memory 199612 kb
Host smart-ac6943e1-8e66-477c-bb22-fc353923628c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030281084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1030281084
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3105752909
Short name T452
Test name
Test status
Simulation time 107057831687 ps
CPU time 511.46 seconds
Started May 02 02:45:51 PM PDT 24
Finished May 02 02:54:25 PM PDT 24
Peak memory 199632 kb
Host smart-6cd3b24b-a490-48e6-8798-383976b81033
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105752909 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3105752909
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2907704907
Short name T31
Test name
Test status
Simulation time 590933782 ps
CPU time 24.95 seconds
Started May 02 02:45:56 PM PDT 24
Finished May 02 02:46:26 PM PDT 24
Peak memory 199684 kb
Host smart-e8aca6d2-5cf3-43fd-ba40-684364c08045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907704907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2907704907
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1924332525
Short name T24
Test name
Test status
Simulation time 77486680 ps
CPU time 0.59 seconds
Started May 02 02:45:53 PM PDT 24
Finished May 02 02:45:57 PM PDT 24
Peak memory 195320 kb
Host smart-d163dd27-e173-4071-8475-68de2ad62ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924332525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1924332525
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2809426125
Short name T49
Test name
Test status
Simulation time 1511315314 ps
CPU time 12.02 seconds
Started May 02 02:45:54 PM PDT 24
Finished May 02 02:46:10 PM PDT 24
Peak memory 199696 kb
Host smart-f8769360-59d9-4cc7-80f7-59d85d21119c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809426125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2809426125
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1804775158
Short name T534
Test name
Test status
Simulation time 13034838942 ps
CPU time 44.6 seconds
Started May 02 02:45:54 PM PDT 24
Finished May 02 02:46:42 PM PDT 24
Peak memory 199780 kb
Host smart-6fe8a52a-9e4e-46ca-afb2-965402fe66ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804775158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1804775158
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2783785286
Short name T570
Test name
Test status
Simulation time 866893607 ps
CPU time 41.85 seconds
Started May 02 02:45:53 PM PDT 24
Finished May 02 02:46:38 PM PDT 24
Peak memory 199660 kb
Host smart-b4624407-9235-412c-9850-f6de24bb9411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783785286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2783785286
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1530889186
Short name T184
Test name
Test status
Simulation time 30579743131 ps
CPU time 51.53 seconds
Started May 02 02:45:56 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199712 kb
Host smart-8500b78d-44d0-44cb-b820-22258d405688
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530889186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1530889186
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3940193364
Short name T148
Test name
Test status
Simulation time 5565276956 ps
CPU time 78.88 seconds
Started May 02 02:45:55 PM PDT 24
Finished May 02 02:47:17 PM PDT 24
Peak memory 199744 kb
Host smart-908c5a2c-371b-4218-8f68-49eaffec1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940193364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3940193364
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.299332250
Short name T133
Test name
Test status
Simulation time 857722972 ps
CPU time 6.7 seconds
Started May 02 02:45:52 PM PDT 24
Finished May 02 02:46:02 PM PDT 24
Peak memory 199572 kb
Host smart-d3007986-79fd-497e-b725-9883c93ce77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299332250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.299332250
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1480529518
Short name T185
Test name
Test status
Simulation time 32224457900 ps
CPU time 843.01 seconds
Started May 02 02:45:57 PM PDT 24
Finished May 02 03:00:04 PM PDT 24
Peak memory 199332 kb
Host smart-032c87bd-bc18-4631-bd4c-44be27d8409c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480529518 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1480529518
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2433044781
Short name T496
Test name
Test status
Simulation time 55419947 ps
CPU time 1.26 seconds
Started May 02 02:45:58 PM PDT 24
Finished May 02 02:46:06 PM PDT 24
Peak memory 199588 kb
Host smart-6c137412-dcb4-4980-99cd-17e1ec6df336
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433044781 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2433044781
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1460525904
Short name T64
Test name
Test status
Simulation time 32816391338 ps
CPU time 409.53 seconds
Started May 02 02:45:53 PM PDT 24
Finished May 02 02:52:47 PM PDT 24
Peak memory 199680 kb
Host smart-9684631f-cd37-4901-b819-7d69ea02a327
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460525904 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1460525904
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.311992087
Short name T386
Test name
Test status
Simulation time 2034690161 ps
CPU time 39.46 seconds
Started May 02 02:45:59 PM PDT 24
Finished May 02 02:46:46 PM PDT 24
Peak memory 199624 kb
Host smart-5da2ce70-91c4-4fc4-b34a-05953122c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311992087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.311992087
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.233250628
Short name T403
Test name
Test status
Simulation time 11840779 ps
CPU time 0.59 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:46:14 PM PDT 24
Peak memory 195208 kb
Host smart-0430f55c-686c-4eeb-8e47-b4df341a7701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233250628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.233250628
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3400810095
Short name T370
Test name
Test status
Simulation time 1446230813 ps
CPU time 26.37 seconds
Started May 02 02:45:57 PM PDT 24
Finished May 02 02:46:28 PM PDT 24
Peak memory 215992 kb
Host smart-d9ff507f-012d-4613-aea0-61b9ad024972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400810095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3400810095
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2342073615
Short name T497
Test name
Test status
Simulation time 2417842453 ps
CPU time 44.37 seconds
Started May 02 02:45:53 PM PDT 24
Finished May 02 02:46:41 PM PDT 24
Peak memory 199720 kb
Host smart-12613f68-5fab-47b7-9073-43e7791e227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342073615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2342073615
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1184840375
Short name T232
Test name
Test status
Simulation time 2262851755 ps
CPU time 65.79 seconds
Started May 02 02:45:58 PM PDT 24
Finished May 02 02:47:10 PM PDT 24
Peak memory 199684 kb
Host smart-30d463b8-714b-468e-a304-1d9442f000f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184840375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1184840375
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.78278062
Short name T34
Test name
Test status
Simulation time 6471439515 ps
CPU time 56.62 seconds
Started May 02 02:45:59 PM PDT 24
Finished May 02 02:47:04 PM PDT 24
Peak memory 199728 kb
Host smart-20430d22-a604-4412-add8-f8a28247f3d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78278062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.78278062
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2332580854
Short name T83
Test name
Test status
Simulation time 13849935873 ps
CPU time 78.49 seconds
Started May 02 02:45:59 PM PDT 24
Finished May 02 02:47:25 PM PDT 24
Peak memory 199696 kb
Host smart-f52dc627-dd45-4d5b-ae61-11d973f73d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332580854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2332580854
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2091207437
Short name T498
Test name
Test status
Simulation time 184681846 ps
CPU time 2.37 seconds
Started May 02 02:45:59 PM PDT 24
Finished May 02 02:46:10 PM PDT 24
Peak memory 199664 kb
Host smart-4ed76cce-acef-4293-9797-737321337b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091207437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2091207437
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1075872292
Short name T400
Test name
Test status
Simulation time 10180919345 ps
CPU time 160.49 seconds
Started May 02 02:45:55 PM PDT 24
Finished May 02 02:48:40 PM PDT 24
Peak memory 199740 kb
Host smart-12df69ba-b8d0-40dd-b69a-ed391c9ac2bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075872292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1075872292
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1246462005
Short name T404
Test name
Test status
Simulation time 60548918 ps
CPU time 1.21 seconds
Started May 02 02:45:55 PM PDT 24
Finished May 02 02:46:00 PM PDT 24
Peak memory 199512 kb
Host smart-25dc12b4-2fa0-4317-a3f5-b717c9868516
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246462005 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1246462005
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3488891438
Short name T136
Test name
Test status
Simulation time 169600293532 ps
CPU time 526.48 seconds
Started May 02 02:45:55 PM PDT 24
Finished May 02 02:54:46 PM PDT 24
Peak memory 199596 kb
Host smart-04f44119-1218-4b5e-b5e6-c171a4afa996
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488891438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3488891438
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.22738311
Short name T494
Test name
Test status
Simulation time 15837196389 ps
CPU time 99.45 seconds
Started May 02 02:45:55 PM PDT 24
Finished May 02 02:47:39 PM PDT 24
Peak memory 199712 kb
Host smart-f6bb3f32-4763-442d-85df-ca6b495eb042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22738311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.22738311
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1839343482
Short name T464
Test name
Test status
Simulation time 11776489 ps
CPU time 0.61 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:46:14 PM PDT 24
Peak memory 195308 kb
Host smart-28fdf6c5-cbcd-48ce-8b7c-97264b464717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839343482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1839343482
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.615615403
Short name T571
Test name
Test status
Simulation time 8666768895 ps
CPU time 46.43 seconds
Started May 02 02:45:57 PM PDT 24
Finished May 02 02:46:49 PM PDT 24
Peak memory 226528 kb
Host smart-2832751e-d4d0-4cfc-b5be-e3348b84c316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615615403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.615615403
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.22493568
Short name T543
Test name
Test status
Simulation time 3958788623 ps
CPU time 18.78 seconds
Started May 02 02:45:57 PM PDT 24
Finished May 02 02:46:20 PM PDT 24
Peak memory 199460 kb
Host smart-ee9ac173-dc80-41a0-bc7b-58e85a9e50c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22493568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.22493568
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3055034801
Short name T513
Test name
Test status
Simulation time 444397361 ps
CPU time 11.49 seconds
Started May 02 02:45:58 PM PDT 24
Finished May 02 02:46:17 PM PDT 24
Peak memory 199496 kb
Host smart-808eb1ef-2930-4f88-9aa0-03e2cbb4d123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055034801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3055034801
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2251632969
Short name T514
Test name
Test status
Simulation time 23825655137 ps
CPU time 50.52 seconds
Started May 02 02:45:56 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199728 kb
Host smart-3ecc77f0-6270-4060-a37b-aa5dbb5c4c7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251632969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2251632969
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.263375891
Short name T171
Test name
Test status
Simulation time 2619240670 ps
CPU time 26.42 seconds
Started May 02 02:45:57 PM PDT 24
Finished May 02 02:46:28 PM PDT 24
Peak memory 199708 kb
Host smart-5151a4b8-2772-408d-9791-ec8a26c5397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263375891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.263375891
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3763457714
Short name T393
Test name
Test status
Simulation time 805749380 ps
CPU time 6.22 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:46:19 PM PDT 24
Peak memory 199640 kb
Host smart-8f3e880a-f42b-42dc-ad09-ff59e9175c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763457714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3763457714
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1644555744
Short name T481
Test name
Test status
Simulation time 296643039387 ps
CPU time 3023.69 seconds
Started May 02 02:45:55 PM PDT 24
Finished May 02 03:36:23 PM PDT 24
Peak memory 199508 kb
Host smart-15c07109-bfdc-4fcc-866c-af9aec32e33c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644555744 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1644555744
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.2623754938
Short name T95
Test name
Test status
Simulation time 153610378582 ps
CPU time 2182.4 seconds
Started May 02 02:45:54 PM PDT 24
Finished May 02 03:22:21 PM PDT 24
Peak memory 256928 kb
Host smart-21b0f635-0d8e-4e94-bea8-6de6485259d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623754938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.2623754938
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2210275633
Short name T292
Test name
Test status
Simulation time 125036811 ps
CPU time 1.04 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:46:15 PM PDT 24
Peak memory 199208 kb
Host smart-6c67fc67-00ff-4588-a7b7-39cd4c1f38e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210275633 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2210275633
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1471522110
Short name T281
Test name
Test status
Simulation time 34327223060 ps
CPU time 454.1 seconds
Started May 02 02:45:58 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 199504 kb
Host smart-1f5d5763-e9c5-4da2-a652-e0a8cb060ef1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471522110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1471522110
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2568511199
Short name T266
Test name
Test status
Simulation time 1586161908 ps
CPU time 21.99 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:46:35 PM PDT 24
Peak memory 199620 kb
Host smart-da38144f-572d-486b-8389-9f075c72b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568511199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2568511199
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3831824771
Short name T330
Test name
Test status
Simulation time 27166673 ps
CPU time 0.59 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:46:13 PM PDT 24
Peak memory 195332 kb
Host smart-cd030bcc-30c4-4f37-b2d9-ef32b03a2272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831824771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3831824771
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3551923450
Short name T575
Test name
Test status
Simulation time 17534669080 ps
CPU time 50.04 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:47:07 PM PDT 24
Peak memory 226100 kb
Host smart-d4316c9f-3a76-4975-8163-c2a3b99a8d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551923450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3551923450
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3067553874
Short name T63
Test name
Test status
Simulation time 3723233423 ps
CPU time 43.61 seconds
Started May 02 02:46:04 PM PDT 24
Finished May 02 02:46:58 PM PDT 24
Peak memory 199660 kb
Host smart-09abbaf6-b26f-4358-8890-cc470f69db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067553874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3067553874
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.4250634391
Short name T241
Test name
Test status
Simulation time 2171746035 ps
CPU time 30.53 seconds
Started May 02 02:46:04 PM PDT 24
Finished May 02 02:46:45 PM PDT 24
Peak memory 199740 kb
Host smart-f9332c15-1605-4c43-9bb2-d907fb3bfefe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250634391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.4250634391
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3419132978
Short name T297
Test name
Test status
Simulation time 686155843 ps
CPU time 37.42 seconds
Started May 02 02:46:04 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199668 kb
Host smart-52994054-7533-4beb-ab83-9d84e3353dca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419132978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3419132978
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1895446842
Short name T203
Test name
Test status
Simulation time 4019832001 ps
CPU time 73.14 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:47:25 PM PDT 24
Peak memory 199720 kb
Host smart-6b465a84-1d3a-4211-bb16-26a0e7acf0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895446842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1895446842
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1451531916
Short name T129
Test name
Test status
Simulation time 434492264 ps
CPU time 6.23 seconds
Started May 02 02:46:01 PM PDT 24
Finished May 02 02:46:17 PM PDT 24
Peak memory 199668 kb
Host smart-ce19f6e0-9088-4d46-9410-98e0e8186ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451531916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1451531916
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2082323237
Short name T421
Test name
Test status
Simulation time 16432482215 ps
CPU time 854.75 seconds
Started May 02 02:46:01 PM PDT 24
Finished May 02 03:00:26 PM PDT 24
Peak memory 228304 kb
Host smart-7939a26c-75c7-4b3e-af4a-04568ed17cec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082323237 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2082323237
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3394105528
Short name T558
Test name
Test status
Simulation time 269663162 ps
CPU time 1 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:46:15 PM PDT 24
Peak memory 198296 kb
Host smart-dba7dbce-f00d-4dbd-a965-22933c57f414
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394105528 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3394105528
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3219587364
Short name T201
Test name
Test status
Simulation time 127083540203 ps
CPU time 340.01 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:51:57 PM PDT 24
Peak memory 199500 kb
Host smart-cc352a39-5faf-4c57-8109-719eb80bf1b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219587364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.3219587364
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2509775300
Short name T263
Test name
Test status
Simulation time 1724019150 ps
CPU time 28.09 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:46:40 PM PDT 24
Peak memory 199688 kb
Host smart-8a140c54-bf98-4f24-b907-cbc63e369120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509775300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2509775300
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.885793572
Short name T181
Test name
Test status
Simulation time 12751749 ps
CPU time 0.57 seconds
Started May 02 02:46:04 PM PDT 24
Finished May 02 02:46:15 PM PDT 24
Peak memory 194300 kb
Host smart-bf78cf59-1c6d-4ea9-a2bd-b8e621035b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885793572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.885793572
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.538226351
Short name T580
Test name
Test status
Simulation time 1020591662 ps
CPU time 37.38 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:46:50 PM PDT 24
Peak memory 207836 kb
Host smart-817e4e2b-60ea-4976-a298-53bd873ccc4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538226351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.538226351
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3613002413
Short name T560
Test name
Test status
Simulation time 4704363222 ps
CPU time 23.91 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:46:38 PM PDT 24
Peak memory 199728 kb
Host smart-f736f466-6150-4dc8-959e-ce0b11c4eab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613002413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3613002413
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3255792563
Short name T489
Test name
Test status
Simulation time 4849368949 ps
CPU time 144.81 seconds
Started May 02 02:46:06 PM PDT 24
Finished May 02 02:48:41 PM PDT 24
Peak memory 199708 kb
Host smart-00a903f4-c3e5-4064-8964-08266d15e077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255792563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3255792563
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.380214068
Short name T492
Test name
Test status
Simulation time 11025976085 ps
CPU time 50.24 seconds
Started May 02 02:46:03 PM PDT 24
Finished May 02 02:47:03 PM PDT 24
Peak memory 199776 kb
Host smart-ef2e2d39-f7c0-471a-aadf-ce03a45b0656
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380214068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.380214068
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1539283237
Short name T221
Test name
Test status
Simulation time 514460749 ps
CPU time 29.29 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:46:41 PM PDT 24
Peak memory 199660 kb
Host smart-1135e11e-287e-49e6-9591-6e886bb9ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539283237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1539283237
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.436262281
Short name T228
Test name
Test status
Simulation time 102055765 ps
CPU time 1.66 seconds
Started May 02 02:46:04 PM PDT 24
Finished May 02 02:46:16 PM PDT 24
Peak memory 199592 kb
Host smart-2b1757f6-60b9-4c42-b1db-fc7e3057192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436262281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.436262281
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3355136031
Short name T54
Test name
Test status
Simulation time 260125757953 ps
CPU time 1258.73 seconds
Started May 02 02:46:01 PM PDT 24
Finished May 02 03:07:10 PM PDT 24
Peak memory 237508 kb
Host smart-26c88874-bca0-4ee0-8b8c-1caad7eef215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355136031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3355136031
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3093306093
Short name T518
Test name
Test status
Simulation time 114115631 ps
CPU time 1 seconds
Started May 02 02:46:01 PM PDT 24
Finished May 02 02:46:11 PM PDT 24
Peak memory 199312 kb
Host smart-fa2bc567-24a0-4ceb-9f5e-41097065f65d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093306093 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3093306093
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1378111569
Short name T399
Test name
Test status
Simulation time 87797041044 ps
CPU time 536.19 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:55:09 PM PDT 24
Peak memory 199708 kb
Host smart-9a94e073-9f9f-4fb2-ab7a-80ea7d10b5cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378111569 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1378111569
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2488773393
Short name T382
Test name
Test status
Simulation time 13842822502 ps
CPU time 97.11 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:47:49 PM PDT 24
Peak memory 199708 kb
Host smart-6937fba0-a2bc-4eae-a81e-4a27f7a435ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488773393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2488773393
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.797803350
Short name T426
Test name
Test status
Simulation time 45263124 ps
CPU time 0.59 seconds
Started May 02 02:46:12 PM PDT 24
Finished May 02 02:46:19 PM PDT 24
Peak memory 195172 kb
Host smart-d32b7149-d0fc-45b0-a269-b6d1df197ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797803350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.797803350
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3827970733
Short name T521
Test name
Test status
Simulation time 4585447071 ps
CPU time 39.95 seconds
Started May 02 02:46:21 PM PDT 24
Finished May 02 02:47:02 PM PDT 24
Peak memory 227312 kb
Host smart-d4a7e7c2-04aa-41f3-9b7b-2dc0b2c34d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827970733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3827970733
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3188278804
Short name T430
Test name
Test status
Simulation time 14585785368 ps
CPU time 49.47 seconds
Started May 02 02:46:11 PM PDT 24
Finished May 02 02:47:08 PM PDT 24
Peak memory 199728 kb
Host smart-d957f4e2-5d6b-48e4-ae49-6d9c0a7ed392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188278804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3188278804
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3290722474
Short name T149
Test name
Test status
Simulation time 1266247418 ps
CPU time 33.64 seconds
Started May 02 02:46:12 PM PDT 24
Finished May 02 02:46:52 PM PDT 24
Peak memory 199684 kb
Host smart-07ba8e41-136f-427d-b5bc-4a92227b959d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290722474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3290722474
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.494909540
Short name T224
Test name
Test status
Simulation time 10301616074 ps
CPU time 142.43 seconds
Started May 02 02:46:09 PM PDT 24
Finished May 02 02:48:40 PM PDT 24
Peak memory 199724 kb
Host smart-138537ff-e782-446a-8501-62aeb8ecd832
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494909540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.494909540
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4017121250
Short name T151
Test name
Test status
Simulation time 1815849603 ps
CPU time 9.74 seconds
Started May 02 02:46:04 PM PDT 24
Finished May 02 02:46:24 PM PDT 24
Peak memory 199584 kb
Host smart-a9bfb7f7-4167-4fe4-a293-ea1f8c4a734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017121250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4017121250
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1277980173
Short name T159
Test name
Test status
Simulation time 614619871 ps
CPU time 4.93 seconds
Started May 02 02:46:02 PM PDT 24
Finished May 02 02:46:16 PM PDT 24
Peak memory 199664 kb
Host smart-cdb6051e-6d78-4af5-bd18-a9e2247fc517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277980173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1277980173
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3260121479
Short name T511
Test name
Test status
Simulation time 85759054505 ps
CPU time 1172.73 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 03:05:51 PM PDT 24
Peak memory 248748 kb
Host smart-326df857-3af5-4ff6-8f46-af5494414a2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260121479 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3260121479
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3745490872
Short name T261
Test name
Test status
Simulation time 114566495 ps
CPU time 1.3 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 02:46:19 PM PDT 24
Peak memory 199608 kb
Host smart-3256ff3b-e25e-425c-a3dd-787fd87be300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745490872 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3745490872
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.165382293
Short name T93
Test name
Test status
Simulation time 45349720945 ps
CPU time 413.38 seconds
Started May 02 02:46:09 PM PDT 24
Finished May 02 02:53:10 PM PDT 24
Peak memory 199708 kb
Host smart-e4f6484d-5d9b-47f8-a191-4ab5aed0f907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165382293 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.165382293
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1877260930
Short name T425
Test name
Test status
Simulation time 8663935585 ps
CPU time 79.08 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:47:36 PM PDT 24
Peak memory 199740 kb
Host smart-e7d07a73-ab82-4357-9e7b-93410449f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877260930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1877260930
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2896335334
Short name T172
Test name
Test status
Simulation time 17087770 ps
CPU time 0.59 seconds
Started May 02 02:44:08 PM PDT 24
Finished May 02 02:44:10 PM PDT 24
Peak memory 195340 kb
Host smart-b5ea3e55-5645-452f-bf2d-c0a572f095c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896335334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2896335334
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.335009982
Short name T520
Test name
Test status
Simulation time 467931819 ps
CPU time 15.79 seconds
Started May 02 02:44:03 PM PDT 24
Finished May 02 02:44:20 PM PDT 24
Peak memory 215484 kb
Host smart-71fbd7f0-3832-475f-b1eb-c8407e283f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335009982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.335009982
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3805826988
Short name T467
Test name
Test status
Simulation time 660461874 ps
CPU time 32.18 seconds
Started May 02 02:44:09 PM PDT 24
Finished May 02 02:44:42 PM PDT 24
Peak memory 199620 kb
Host smart-b6ac3fb7-0ba1-4b14-877f-58052a3268a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805826988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3805826988
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.948806566
Short name T109
Test name
Test status
Simulation time 12726750941 ps
CPU time 47.11 seconds
Started May 02 02:44:07 PM PDT 24
Finished May 02 02:44:55 PM PDT 24
Peak memory 199752 kb
Host smart-21b696a9-aeda-45c1-bd37-45bbf7dd3126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948806566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.948806566
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3313478153
Short name T601
Test name
Test status
Simulation time 16472603613 ps
CPU time 113.44 seconds
Started May 02 02:44:09 PM PDT 24
Finished May 02 02:46:04 PM PDT 24
Peak memory 199736 kb
Host smart-783b4a3d-da0b-4ec8-b219-96dc0a99bb56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313478153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3313478153
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1193210437
Short name T549
Test name
Test status
Simulation time 676789617 ps
CPU time 10.42 seconds
Started May 02 02:44:03 PM PDT 24
Finished May 02 02:44:15 PM PDT 24
Peak memory 199644 kb
Host smart-e4cd7e33-1630-4a84-83c3-59521a164b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193210437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1193210437
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2489750960
Short name T37
Test name
Test status
Simulation time 169839728 ps
CPU time 1 seconds
Started May 02 02:44:10 PM PDT 24
Finished May 02 02:44:12 PM PDT 24
Peak memory 219132 kb
Host smart-be0286b5-3f3b-4cd6-b0e2-099b9bba96bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489750960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2489750960
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2762189768
Short name T424
Test name
Test status
Simulation time 192512710 ps
CPU time 3.28 seconds
Started May 02 02:44:02 PM PDT 24
Finished May 02 02:44:06 PM PDT 24
Peak memory 199648 kb
Host smart-62fa5e72-2c28-4a18-8bb5-5b05784bfbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762189768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2762189768
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3659726613
Short name T75
Test name
Test status
Simulation time 142592294239 ps
CPU time 549.98 seconds
Started May 02 02:44:09 PM PDT 24
Finished May 02 02:53:20 PM PDT 24
Peak memory 228448 kb
Host smart-4a808b27-3b91-429a-afb5-995d2a56a7c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659726613 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3659726613
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.304888701
Short name T275
Test name
Test status
Simulation time 30389841 ps
CPU time 0.94 seconds
Started May 02 02:44:08 PM PDT 24
Finished May 02 02:44:11 PM PDT 24
Peak memory 198396 kb
Host smart-8e22854c-e125-4341-b3b3-45caef32b46a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304888701 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.304888701
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1910454098
Short name T355
Test name
Test status
Simulation time 8086438104 ps
CPU time 438.31 seconds
Started May 02 02:44:10 PM PDT 24
Finished May 02 02:51:29 PM PDT 24
Peak memory 199660 kb
Host smart-2711ca12-999f-4e71-9892-6933671f32fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910454098 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1910454098
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2819850573
Short name T249
Test name
Test status
Simulation time 1824270925 ps
CPU time 56.74 seconds
Started May 02 02:44:07 PM PDT 24
Finished May 02 02:45:04 PM PDT 24
Peak memory 199676 kb
Host smart-8e2f032b-76ca-4bd6-a4f6-a9d642bcd76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819850573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2819850573
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3749781540
Short name T265
Test name
Test status
Simulation time 15416030 ps
CPU time 0.55 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 02:46:18 PM PDT 24
Peak memory 195108 kb
Host smart-90c3f537-7557-4a34-9d3a-44dd5ead6bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749781540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3749781540
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.581909008
Short name T298
Test name
Test status
Simulation time 2373461606 ps
CPU time 52.06 seconds
Started May 02 02:46:09 PM PDT 24
Finished May 02 02:47:09 PM PDT 24
Peak memory 232536 kb
Host smart-9e19f0fd-dc6d-4e62-a34c-d354076619f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581909008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.581909008
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3384541429
Short name T215
Test name
Test status
Simulation time 5081762426 ps
CPU time 34.1 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199692 kb
Host smart-57a800da-0d3e-485f-beb8-ae4e67bf5db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384541429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3384541429
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3637594503
Short name T478
Test name
Test status
Simulation time 2331098428 ps
CPU time 133.94 seconds
Started May 02 02:46:07 PM PDT 24
Finished May 02 02:48:30 PM PDT 24
Peak memory 199776 kb
Host smart-4d26adfa-93ac-425d-94e3-0f4935aecc06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3637594503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3637594503
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2046465738
Short name T416
Test name
Test status
Simulation time 47607462490 ps
CPU time 140.05 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:48:37 PM PDT 24
Peak memory 199664 kb
Host smart-f263038d-e77a-4181-afa1-6495c8d46db5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046465738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2046465738
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1364397198
Short name T152
Test name
Test status
Simulation time 23662238176 ps
CPU time 81.49 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 02:47:39 PM PDT 24
Peak memory 199740 kb
Host smart-10a94004-4e0c-43a6-bfbf-c6ec7ef89e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364397198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1364397198
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1059063702
Short name T329
Test name
Test status
Simulation time 254248945 ps
CPU time 2.11 seconds
Started May 02 02:46:11 PM PDT 24
Finished May 02 02:46:20 PM PDT 24
Peak memory 199684 kb
Host smart-74b69968-06eb-4806-bfe4-97d85a8a2396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059063702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1059063702
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.254323621
Short name T368
Test name
Test status
Simulation time 3143100845 ps
CPU time 33.46 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:46:50 PM PDT 24
Peak memory 227332 kb
Host smart-cc4bff8f-7c5b-45e4-bb86-9d21a1e2c09c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254323621 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.254323621
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.531541490
Short name T145
Test name
Test status
Simulation time 294136140 ps
CPU time 1.22 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 02:46:19 PM PDT 24
Peak memory 199648 kb
Host smart-bae0066e-87fb-432a-bf7a-4dc6f765c5ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531541490 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_hmac_vectors.531541490
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2335468220
Short name T528
Test name
Test status
Simulation time 44481057163 ps
CPU time 539.9 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:55:17 PM PDT 24
Peak memory 199704 kb
Host smart-53bf0d60-c00a-4400-afbc-f00112f675ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335468220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2335468220
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3402051501
Short name T160
Test name
Test status
Simulation time 7409066496 ps
CPU time 44.64 seconds
Started May 02 02:46:11 PM PDT 24
Finished May 02 02:47:03 PM PDT 24
Peak memory 199540 kb
Host smart-95d7ab87-7750-464f-b41e-e2ec170355c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402051501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3402051501
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4038350854
Short name T134
Test name
Test status
Simulation time 17017044 ps
CPU time 0.54 seconds
Started May 02 02:46:20 PM PDT 24
Finished May 02 02:46:22 PM PDT 24
Peak memory 194248 kb
Host smart-89e09d43-5dda-446a-a0e5-085f4a81a518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038350854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4038350854
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3857692046
Short name T482
Test name
Test status
Simulation time 6130727584 ps
CPU time 34.39 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 220560 kb
Host smart-9c957441-ff06-4349-b623-1d9c5f614b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857692046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3857692046
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2809944666
Short name T28
Test name
Test status
Simulation time 735492321 ps
CPU time 9.62 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:46:27 PM PDT 24
Peak memory 199652 kb
Host smart-1541cc8c-a329-4c58-98e5-4d643c23d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809944666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2809944666
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.541475933
Short name T427
Test name
Test status
Simulation time 4605093307 ps
CPU time 127.59 seconds
Started May 02 02:46:11 PM PDT 24
Finished May 02 02:48:26 PM PDT 24
Peak memory 199692 kb
Host smart-f955cbae-cd52-47f3-aae7-6036376fd315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541475933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.541475933
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3106539878
Short name T311
Test name
Test status
Simulation time 3310747528 ps
CPU time 48 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 02:47:06 PM PDT 24
Peak memory 199640 kb
Host smart-5a865fbe-b42f-4796-8697-7b52c68927c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106539878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3106539878
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.344710653
Short name T154
Test name
Test status
Simulation time 364468180 ps
CPU time 20.55 seconds
Started May 02 02:46:09 PM PDT 24
Finished May 02 02:46:38 PM PDT 24
Peak memory 199636 kb
Host smart-b6db5f56-70d9-4599-8992-dc5b07ec811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344710653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.344710653
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2621497910
Short name T137
Test name
Test status
Simulation time 361700841 ps
CPU time 5.96 seconds
Started May 02 02:46:08 PM PDT 24
Finished May 02 02:46:23 PM PDT 24
Peak memory 199668 kb
Host smart-2dfcd23f-e0d4-4d83-af70-a3cb7d7544ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621497910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2621497910
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2386966922
Short name T17
Test name
Test status
Simulation time 1267841866884 ps
CPU time 780.58 seconds
Started May 02 02:46:16 PM PDT 24
Finished May 02 02:59:20 PM PDT 24
Peak memory 207332 kb
Host smart-7e9d2209-1820-48cd-8fe6-5d70b31a6bc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386966922 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2386966922
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3333967285
Short name T372
Test name
Test status
Simulation time 339604503 ps
CPU time 1.21 seconds
Started May 02 02:46:16 PM PDT 24
Finished May 02 02:46:21 PM PDT 24
Peak memory 199620 kb
Host smart-a77c5edb-b556-4611-a34e-bb4812e4c7c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333967285 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3333967285
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.494267810
Short name T202
Test name
Test status
Simulation time 71067240669 ps
CPU time 467.73 seconds
Started May 02 02:46:20 PM PDT 24
Finished May 02 02:54:09 PM PDT 24
Peak memory 199536 kb
Host smart-50717cea-2367-4190-b437-ba03a5659798
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494267810 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.494267810
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4170016939
Short name T271
Test name
Test status
Simulation time 237133789 ps
CPU time 2.06 seconds
Started May 02 02:46:10 PM PDT 24
Finished May 02 02:46:20 PM PDT 24
Peak memory 199584 kb
Host smart-551cfdad-3a6f-43d0-ae2d-90183ce8cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170016939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4170016939
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.299502199
Short name T246
Test name
Test status
Simulation time 14783666 ps
CPU time 0.6 seconds
Started May 02 02:46:23 PM PDT 24
Finished May 02 02:46:25 PM PDT 24
Peak memory 195412 kb
Host smart-85cb938a-c163-4855-a83d-3ed7bb98ee74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299502199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.299502199
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2100990718
Short name T438
Test name
Test status
Simulation time 10684717893 ps
CPU time 29.93 seconds
Started May 02 02:46:18 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 228232 kb
Host smart-73af60fc-c28d-43c6-a37d-9a820edd7bf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100990718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2100990718
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.39012633
Short name T385
Test name
Test status
Simulation time 443829662 ps
CPU time 20.44 seconds
Started May 02 02:46:18 PM PDT 24
Finished May 02 02:46:41 PM PDT 24
Peak memory 199668 kb
Host smart-ffbf51e3-1ca9-4db3-8a19-2c8fc3d48504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39012633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.39012633
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3417899923
Short name T247
Test name
Test status
Simulation time 4992267295 ps
CPU time 20.37 seconds
Started May 02 02:46:17 PM PDT 24
Finished May 02 02:46:41 PM PDT 24
Peak memory 199724 kb
Host smart-2d900c67-494c-4a27-94ce-1ac46787e8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417899923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3417899923
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3697514750
Short name T62
Test name
Test status
Simulation time 2338668646 ps
CPU time 29.48 seconds
Started May 02 02:46:19 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199708 kb
Host smart-16cbbd32-0293-43e7-8e7a-a2d3df7e7d22
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697514750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3697514750
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3641628783
Short name T395
Test name
Test status
Simulation time 10142565588 ps
CPU time 102.95 seconds
Started May 02 02:46:17 PM PDT 24
Finished May 02 02:48:03 PM PDT 24
Peak memory 199776 kb
Host smart-16b2ed16-428c-4a19-babd-dcf396533bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641628783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3641628783
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2526424569
Short name T165
Test name
Test status
Simulation time 45526676 ps
CPU time 1.55 seconds
Started May 02 02:46:33 PM PDT 24
Finished May 02 02:46:36 PM PDT 24
Peak memory 199636 kb
Host smart-de88bd8b-a1a3-4558-a089-92197871039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526424569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2526424569
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1750493032
Short name T112
Test name
Test status
Simulation time 36616803616 ps
CPU time 1977.55 seconds
Started May 02 02:46:20 PM PDT 24
Finished May 02 03:19:19 PM PDT 24
Peak memory 199568 kb
Host smart-acbdc3e8-533f-48bf-b45e-82057831a905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750493032 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1750493032
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1462151481
Short name T123
Test name
Test status
Simulation time 217199404 ps
CPU time 1.32 seconds
Started May 02 02:46:14 PM PDT 24
Finished May 02 02:46:20 PM PDT 24
Peak memory 199628 kb
Host smart-99bbfa12-2525-4ad1-8b24-3072bf4cba27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462151481 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1462151481
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2411190167
Short name T321
Test name
Test status
Simulation time 65343504486 ps
CPU time 397.01 seconds
Started May 02 02:46:16 PM PDT 24
Finished May 02 02:52:57 PM PDT 24
Peak memory 199656 kb
Host smart-63469290-169a-4690-9b15-c7728064fb74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411190167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2411190167
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3067764161
Short name T555
Test name
Test status
Simulation time 718157100 ps
CPU time 32.57 seconds
Started May 02 02:46:18 PM PDT 24
Finished May 02 02:46:53 PM PDT 24
Peak memory 199648 kb
Host smart-fcdaea4e-d003-4c21-8a9a-3bd9e85fd14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067764161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3067764161
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2940262611
Short name T333
Test name
Test status
Simulation time 16960521 ps
CPU time 0.58 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:46:28 PM PDT 24
Peak memory 195376 kb
Host smart-5aeda9ad-c065-4382-a605-6de32d894cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940262611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2940262611
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3483137281
Short name T376
Test name
Test status
Simulation time 3347036944 ps
CPU time 14.67 seconds
Started May 02 02:46:23 PM PDT 24
Finished May 02 02:46:39 PM PDT 24
Peak memory 214396 kb
Host smart-90427213-9a97-403c-aaa7-8f3acfc0320a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483137281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3483137281
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.737061463
Short name T218
Test name
Test status
Simulation time 1858977021 ps
CPU time 35.93 seconds
Started May 02 02:46:24 PM PDT 24
Finished May 02 02:47:02 PM PDT 24
Peak memory 199676 kb
Host smart-f09bd5c2-8df5-4549-ba48-26cf9d8594b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737061463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.737061463
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2928775821
Short name T596
Test name
Test status
Simulation time 1076038852 ps
CPU time 62.06 seconds
Started May 02 02:46:24 PM PDT 24
Finished May 02 02:47:27 PM PDT 24
Peak memory 199684 kb
Host smart-903ce938-34b4-432b-8b64-bed2ee3374d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928775821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2928775821
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.161495709
Short name T466
Test name
Test status
Simulation time 2079043466 ps
CPU time 60.46 seconds
Started May 02 02:46:24 PM PDT 24
Finished May 02 02:47:26 PM PDT 24
Peak memory 199560 kb
Host smart-57d01337-54dc-4405-b9f2-26377a80b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161495709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.161495709
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4204495788
Short name T377
Test name
Test status
Simulation time 552591538 ps
CPU time 4.03 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:46:31 PM PDT 24
Peak memory 199692 kb
Host smart-c6160626-401e-46f7-81a6-de5b87b7b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204495788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4204495788
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3133911604
Short name T90
Test name
Test status
Simulation time 68206414550 ps
CPU time 918.78 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 03:01:46 PM PDT 24
Peak memory 224312 kb
Host smart-90437e19-47a6-4fce-9f6c-42aa5510faed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133911604 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3133911604
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.867233125
Short name T392
Test name
Test status
Simulation time 109468480 ps
CPU time 1.07 seconds
Started May 02 02:46:21 PM PDT 24
Finished May 02 02:46:24 PM PDT 24
Peak memory 199624 kb
Host smart-3fffdfa6-a7f1-4864-abe7-ecacab513976
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867233125 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.867233125
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2012948354
Short name T285
Test name
Test status
Simulation time 119894208742 ps
CPU time 502.82 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:54:49 PM PDT 24
Peak memory 199708 kb
Host smart-85212119-582d-409c-8c08-65634908659f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012948354 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2012948354
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1560798925
Short name T473
Test name
Test status
Simulation time 3901593575 ps
CPU time 57.9 seconds
Started May 02 02:46:23 PM PDT 24
Finished May 02 02:47:22 PM PDT 24
Peak memory 199792 kb
Host smart-31e121b0-17cc-49b0-b9e2-3183bdf447a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560798925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1560798925
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1777778691
Short name T231
Test name
Test status
Simulation time 25810394 ps
CPU time 0.57 seconds
Started May 02 02:46:37 PM PDT 24
Finished May 02 02:46:39 PM PDT 24
Peak memory 195276 kb
Host smart-34f4dd52-e1cd-4031-8767-feffeed07b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777778691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1777778691
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3760923239
Short name T47
Test name
Test status
Simulation time 7012343117 ps
CPU time 65.61 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:47:32 PM PDT 24
Peak memory 240700 kb
Host smart-2adf6e6c-ac7d-4feb-bd63-ca17ad17faf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760923239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3760923239
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1535691911
Short name T213
Test name
Test status
Simulation time 13446211651 ps
CPU time 76.39 seconds
Started May 02 02:46:23 PM PDT 24
Finished May 02 02:47:41 PM PDT 24
Peak memory 199716 kb
Host smart-b97053e6-1487-4a4a-87fb-d6d4f569078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535691911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1535691911
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3458564369
Short name T530
Test name
Test status
Simulation time 2268033460 ps
CPU time 125.8 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:48:32 PM PDT 24
Peak memory 199760 kb
Host smart-7832a184-5ca6-4f90-8f10-7c38178b9b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458564369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3458564369
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1411826495
Short name T43
Test name
Test status
Simulation time 30696715813 ps
CPU time 73.32 seconds
Started May 02 02:46:26 PM PDT 24
Finished May 02 02:47:41 PM PDT 24
Peak memory 199748 kb
Host smart-75e4dcdf-6a66-4c44-9582-235a6ab313aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411826495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1411826495
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.210704284
Short name T141
Test name
Test status
Simulation time 1778701245 ps
CPU time 51.77 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:47:19 PM PDT 24
Peak memory 199568 kb
Host smart-fdcb081a-6fe4-4027-8144-5ac0dd97d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210704284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.210704284
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3529712009
Short name T162
Test name
Test status
Simulation time 1091942454 ps
CPU time 3.3 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:46:30 PM PDT 24
Peak memory 199688 kb
Host smart-b30182c5-da79-4907-a41c-2fc9cc26692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529712009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3529712009
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3847703796
Short name T204
Test name
Test status
Simulation time 64793375016 ps
CPU time 1151.45 seconds
Started May 02 02:46:28 PM PDT 24
Finished May 02 03:05:41 PM PDT 24
Peak memory 199736 kb
Host smart-7e7d4d82-6722-418d-8cb0-a4c441946c1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847703796 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3847703796
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.815723560
Short name T410
Test name
Test status
Simulation time 84552694 ps
CPU time 1.15 seconds
Started May 02 02:46:29 PM PDT 24
Finished May 02 02:46:31 PM PDT 24
Peak memory 199608 kb
Host smart-7a24d8be-dfbc-4f13-9b53-4b8f0760771c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815723560 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.815723560
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2473906449
Short name T138
Test name
Test status
Simulation time 138233445466 ps
CPU time 486.25 seconds
Started May 02 02:46:25 PM PDT 24
Finished May 02 02:54:33 PM PDT 24
Peak memory 199624 kb
Host smart-d60707c2-7317-46ed-92e1-1159b1c9d200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473906449 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2473906449
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1707200962
Short name T503
Test name
Test status
Simulation time 1622450403 ps
CPU time 7.55 seconds
Started May 02 02:46:24 PM PDT 24
Finished May 02 02:46:33 PM PDT 24
Peak memory 199648 kb
Host smart-6a9c66fc-c668-42ce-ae88-097c85c844af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707200962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1707200962
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1842637590
Short name T544
Test name
Test status
Simulation time 12203688 ps
CPU time 0.58 seconds
Started May 02 02:46:36 PM PDT 24
Finished May 02 02:46:37 PM PDT 24
Peak memory 195456 kb
Host smart-2f2ea8cb-c816-4ed2-9160-cfad3f8d2235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842637590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1842637590
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1435861568
Short name T48
Test name
Test status
Simulation time 813229619 ps
CPU time 28.17 seconds
Started May 02 02:46:31 PM PDT 24
Finished May 02 02:47:01 PM PDT 24
Peak memory 207868 kb
Host smart-935fd3d1-4b7d-40ae-8bad-7e9d08d041d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435861568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1435861568
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1073958198
Short name T512
Test name
Test status
Simulation time 1767219087 ps
CPU time 37.93 seconds
Started May 02 02:46:30 PM PDT 24
Finished May 02 02:47:09 PM PDT 24
Peak memory 199712 kb
Host smart-cd1b124e-c27a-44c2-8143-5984db086c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073958198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1073958198
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3130812668
Short name T324
Test name
Test status
Simulation time 4586020596 ps
CPU time 66.83 seconds
Started May 02 02:46:31 PM PDT 24
Finished May 02 02:47:39 PM PDT 24
Peak memory 199728 kb
Host smart-a77ecebd-78c0-475e-aa6f-11ae93c8b8ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130812668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3130812668
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2792596750
Short name T598
Test name
Test status
Simulation time 14290551141 ps
CPU time 201.57 seconds
Started May 02 02:46:28 PM PDT 24
Finished May 02 02:49:50 PM PDT 24
Peak memory 199708 kb
Host smart-dd1a374b-56bc-43cd-834b-7f20bec0989f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792596750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2792596750
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.523891880
Short name T375
Test name
Test status
Simulation time 4114067173 ps
CPU time 20.31 seconds
Started May 02 02:46:31 PM PDT 24
Finished May 02 02:46:53 PM PDT 24
Peak memory 199564 kb
Host smart-8307ad96-e799-4622-ba58-abdc7da9a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523891880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.523891880
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2769674438
Short name T547
Test name
Test status
Simulation time 187443705 ps
CPU time 5.58 seconds
Started May 02 02:46:31 PM PDT 24
Finished May 02 02:46:38 PM PDT 24
Peak memory 199612 kb
Host smart-763c4a97-9fee-4228-a68b-723db030d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769674438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2769674438
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.418651887
Short name T316
Test name
Test status
Simulation time 88376348 ps
CPU time 1.04 seconds
Started May 02 02:46:36 PM PDT 24
Finished May 02 02:46:38 PM PDT 24
Peak memory 198240 kb
Host smart-9d923372-36e4-4dd5-bd1b-8ebfe90340d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418651887 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.418651887
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.882630810
Short name T135
Test name
Test status
Simulation time 93847075124 ps
CPU time 455.01 seconds
Started May 02 02:46:29 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 199672 kb
Host smart-04c53740-1786-4b28-9468-a3dcdd2fe75f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882630810 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.882630810
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1689982972
Short name T454
Test name
Test status
Simulation time 220947026 ps
CPU time 6.3 seconds
Started May 02 02:46:28 PM PDT 24
Finished May 02 02:46:36 PM PDT 24
Peak memory 199532 kb
Host smart-12a7e0f7-9b45-49e2-8cd8-ed06bb89e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689982972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1689982972
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1660195625
Short name T313
Test name
Test status
Simulation time 23789092 ps
CPU time 0.56 seconds
Started May 02 02:46:45 PM PDT 24
Finished May 02 02:46:47 PM PDT 24
Peak memory 195284 kb
Host smart-d6c4d55d-79f7-4d75-909d-338a60f95c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660195625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1660195625
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4193716217
Short name T484
Test name
Test status
Simulation time 616662848 ps
CPU time 20.38 seconds
Started May 02 02:46:38 PM PDT 24
Finished May 02 02:46:59 PM PDT 24
Peak memory 215252 kb
Host smart-3cc4d57f-616c-4bc3-81ef-50a99e54fde7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193716217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4193716217
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.486564380
Short name T155
Test name
Test status
Simulation time 2396599471 ps
CPU time 48.81 seconds
Started May 02 02:46:38 PM PDT 24
Finished May 02 02:47:28 PM PDT 24
Peak memory 199704 kb
Host smart-7e5cebc2-7fd3-429d-a3d8-3e263eed3a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486564380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.486564380
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.138171105
Short name T94
Test name
Test status
Simulation time 2993757226 ps
CPU time 83.83 seconds
Started May 02 02:46:36 PM PDT 24
Finished May 02 02:48:00 PM PDT 24
Peak memory 199732 kb
Host smart-3a4accc4-d68f-4863-b7d8-fc832552d82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138171105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.138171105
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.451016377
Short name T422
Test name
Test status
Simulation time 5116803513 ps
CPU time 68.46 seconds
Started May 02 02:46:36 PM PDT 24
Finished May 02 02:47:45 PM PDT 24
Peak memory 199736 kb
Host smart-9bbeca00-d912-4627-8530-08fdaa32e9f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451016377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.451016377
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3653537483
Short name T125
Test name
Test status
Simulation time 1574671732 ps
CPU time 20.79 seconds
Started May 02 02:46:35 PM PDT 24
Finished May 02 02:46:57 PM PDT 24
Peak memory 199624 kb
Host smart-d7f321da-61e3-455f-b084-8543af3d733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653537483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3653537483
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.4277604384
Short name T169
Test name
Test status
Simulation time 406401124 ps
CPU time 4.84 seconds
Started May 02 02:46:38 PM PDT 24
Finished May 02 02:46:44 PM PDT 24
Peak memory 199640 kb
Host smart-71bfc2a5-6658-4057-98ce-4911dc5306c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277604384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4277604384
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1972967906
Short name T559
Test name
Test status
Simulation time 4283104999 ps
CPU time 6.87 seconds
Started May 02 02:46:43 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199656 kb
Host smart-e5b2428f-ec75-475e-898c-282725dba47f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972967906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1972967906
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3310948438
Short name T529
Test name
Test status
Simulation time 207817084 ps
CPU time 1.26 seconds
Started May 02 02:46:38 PM PDT 24
Finished May 02 02:46:41 PM PDT 24
Peak memory 199608 kb
Host smart-8228edb1-7ff6-418c-aae8-8cc46f8bbde9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310948438 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3310948438
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2706477956
Short name T434
Test name
Test status
Simulation time 52341673057 ps
CPU time 494.88 seconds
Started May 02 02:46:37 PM PDT 24
Finished May 02 02:54:52 PM PDT 24
Peak memory 199704 kb
Host smart-0cdb3335-a559-4ebe-b3b1-c69c0085dd3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706477956 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2706477956
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.33924979
Short name T536
Test name
Test status
Simulation time 10790487259 ps
CPU time 35.96 seconds
Started May 02 02:46:40 PM PDT 24
Finished May 02 02:47:18 PM PDT 24
Peak memory 199712 kb
Host smart-23ea78cf-695c-4e1c-9bf6-ce23281d172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33924979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.33924979
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1899054603
Short name T306
Test name
Test status
Simulation time 33020344 ps
CPU time 0.61 seconds
Started May 02 02:46:54 PM PDT 24
Finished May 02 02:46:55 PM PDT 24
Peak memory 194228 kb
Host smart-24b3eb58-3e47-4e9c-8de9-f8b7fc47ea3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899054603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1899054603
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1400369298
Short name T600
Test name
Test status
Simulation time 4676911469 ps
CPU time 38.26 seconds
Started May 02 02:46:42 PM PDT 24
Finished May 02 02:47:22 PM PDT 24
Peak memory 224172 kb
Host smart-eb6f722f-56d2-4737-9657-89cc6c47e5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400369298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1400369298
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.266329344
Short name T303
Test name
Test status
Simulation time 417149627 ps
CPU time 7.02 seconds
Started May 02 02:46:43 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 199632 kb
Host smart-29528698-019b-40e8-83df-afa0d56ac3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266329344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.266329344
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1904563724
Short name T276
Test name
Test status
Simulation time 6119151868 ps
CPU time 120.66 seconds
Started May 02 02:46:44 PM PDT 24
Finished May 02 02:48:46 PM PDT 24
Peak memory 199724 kb
Host smart-f6f8655b-f7a7-4080-9ea9-8c0e4d138a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904563724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1904563724
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2003101594
Short name T566
Test name
Test status
Simulation time 16960674673 ps
CPU time 126.33 seconds
Started May 02 02:46:44 PM PDT 24
Finished May 02 02:48:51 PM PDT 24
Peak memory 199644 kb
Host smart-868da6e9-47ee-4b50-80d1-5adff0cf14be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003101594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2003101594
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1104323784
Short name T194
Test name
Test status
Simulation time 4363937616 ps
CPU time 46.95 seconds
Started May 02 02:46:43 PM PDT 24
Finished May 02 02:47:31 PM PDT 24
Peak memory 199680 kb
Host smart-6ce951f8-e87f-406f-95d2-4a14ac2cffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104323784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1104323784
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3324626725
Short name T526
Test name
Test status
Simulation time 370246648 ps
CPU time 3.03 seconds
Started May 02 02:46:43 PM PDT 24
Finished May 02 02:46:48 PM PDT 24
Peak memory 199664 kb
Host smart-1d9b03e2-031c-4700-8530-865e9c5f69ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324626725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3324626725
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3432445469
Short name T74
Test name
Test status
Simulation time 53870434392 ps
CPU time 695.89 seconds
Started May 02 02:46:44 PM PDT 24
Finished May 02 02:58:21 PM PDT 24
Peak memory 199688 kb
Host smart-5c0156d9-4944-49c8-95cd-afd01edfd278
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432445469 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3432445469
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1686173205
Short name T352
Test name
Test status
Simulation time 389972470 ps
CPU time 1.36 seconds
Started May 02 02:46:43 PM PDT 24
Finished May 02 02:46:46 PM PDT 24
Peak memory 199660 kb
Host smart-7d26e0a7-ec61-49f4-ba84-879cfd61ec65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686173205 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1686173205
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.999496785
Short name T344
Test name
Test status
Simulation time 155393603595 ps
CPU time 497.76 seconds
Started May 02 02:46:43 PM PDT 24
Finished May 02 02:55:02 PM PDT 24
Peak memory 199668 kb
Host smart-36d4409f-0953-45b3-ae05-26bed265488b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999496785 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.999496785
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2637064907
Short name T191
Test name
Test status
Simulation time 3020101413 ps
CPU time 25.62 seconds
Started May 02 02:46:43 PM PDT 24
Finished May 02 02:47:10 PM PDT 24
Peak memory 199708 kb
Host smart-5f88a907-a6ec-42c1-b004-107f92b14ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637064907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2637064907
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.933361725
Short name T289
Test name
Test status
Simulation time 13895007 ps
CPU time 0.56 seconds
Started May 02 02:46:49 PM PDT 24
Finished May 02 02:46:51 PM PDT 24
Peak memory 194292 kb
Host smart-a8a49d9d-5938-46e2-a0e3-673b68a40336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933361725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.933361725
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2591834101
Short name T574
Test name
Test status
Simulation time 9500681372 ps
CPU time 39.55 seconds
Started May 02 02:46:51 PM PDT 24
Finished May 02 02:47:31 PM PDT 24
Peak memory 226360 kb
Host smart-0a802c2b-6086-4a94-bb55-61d65acf1f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591834101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2591834101
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2071623912
Short name T592
Test name
Test status
Simulation time 2103092210 ps
CPU time 52.85 seconds
Started May 02 02:46:49 PM PDT 24
Finished May 02 02:47:42 PM PDT 24
Peak memory 199716 kb
Host smart-76e8759a-078d-4e90-b778-b3fa15ca3c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071623912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2071623912
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.612198443
Short name T7
Test name
Test status
Simulation time 1105351273 ps
CPU time 62.69 seconds
Started May 02 02:46:55 PM PDT 24
Finished May 02 02:47:59 PM PDT 24
Peak memory 199656 kb
Host smart-a8304275-7a77-4f4c-89ff-5597dbb4b1ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612198443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.612198443
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2386588992
Short name T33
Test name
Test status
Simulation time 10733379160 ps
CPU time 138.59 seconds
Started May 02 02:46:56 PM PDT 24
Finished May 02 02:49:16 PM PDT 24
Peak memory 199740 kb
Host smart-a9df0179-bb8b-4571-a576-a48734087b68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386588992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2386588992
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.164860549
Short name T317
Test name
Test status
Simulation time 19705657399 ps
CPU time 40.68 seconds
Started May 02 02:46:49 PM PDT 24
Finished May 02 02:47:31 PM PDT 24
Peak memory 199684 kb
Host smart-33cfb7cb-e3cd-466a-94e3-675294084c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164860549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.164860549
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.14297097
Short name T490
Test name
Test status
Simulation time 3169671415 ps
CPU time 2.29 seconds
Started May 02 02:46:50 PM PDT 24
Finished May 02 02:46:54 PM PDT 24
Peak memory 199724 kb
Host smart-4c5965c7-f4d8-4954-adec-849b0c86810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14297097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.14297097
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.681961000
Short name T44
Test name
Test status
Simulation time 41716737744 ps
CPU time 134.94 seconds
Started May 02 02:46:51 PM PDT 24
Finished May 02 02:49:07 PM PDT 24
Peak memory 199652 kb
Host smart-ebaa1f3c-a311-413d-a7dd-e5fbe55826a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681961000 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.681961000
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2304533509
Short name T365
Test name
Test status
Simulation time 208618353 ps
CPU time 1.17 seconds
Started May 02 02:46:52 PM PDT 24
Finished May 02 02:46:54 PM PDT 24
Peak memory 199668 kb
Host smart-45a48526-d2b3-4080-a158-cfc4c64037c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304533509 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2304533509
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2592261376
Short name T593
Test name
Test status
Simulation time 9917130010 ps
CPU time 404.02 seconds
Started May 02 02:46:51 PM PDT 24
Finished May 02 02:53:36 PM PDT 24
Peak memory 199708 kb
Host smart-8b5ffdae-79e4-4f61-8ef7-e9b7dd2f9200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592261376 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.2592261376
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1976596691
Short name T326
Test name
Test status
Simulation time 4138318421 ps
CPU time 80.68 seconds
Started May 02 02:46:50 PM PDT 24
Finished May 02 02:48:12 PM PDT 24
Peak memory 199716 kb
Host smart-ca97ca39-100d-4537-9ffa-2f713ddca603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976596691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1976596691
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1615517970
Short name T186
Test name
Test status
Simulation time 38427382 ps
CPU time 0.53 seconds
Started May 02 02:47:07 PM PDT 24
Finished May 02 02:47:09 PM PDT 24
Peak memory 194324 kb
Host smart-20098306-d822-46c3-bef0-f0f6c78c21f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615517970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1615517970
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3092154615
Short name T50
Test name
Test status
Simulation time 1510796788 ps
CPU time 32.78 seconds
Started May 02 02:46:52 PM PDT 24
Finished May 02 02:47:26 PM PDT 24
Peak memory 232008 kb
Host smart-435aa078-248f-4fdc-99c9-948ffe105044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092154615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3092154615
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.587021704
Short name T256
Test name
Test status
Simulation time 1079915603 ps
CPU time 51.89 seconds
Started May 02 02:47:07 PM PDT 24
Finished May 02 02:48:00 PM PDT 24
Peak memory 199652 kb
Host smart-60f5eedb-0385-41a6-b46f-2ea3a96c0abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587021704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.587021704
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2828412307
Short name T230
Test name
Test status
Simulation time 8251905354 ps
CPU time 115.71 seconds
Started May 02 02:46:50 PM PDT 24
Finished May 02 02:48:47 PM PDT 24
Peak memory 199696 kb
Host smart-5dfcb2ac-ca01-4759-a92d-3bb51dda43c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828412307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2828412307
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.836820115
Short name T429
Test name
Test status
Simulation time 3886837875 ps
CPU time 72.5 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:48:14 PM PDT 24
Peak memory 199704 kb
Host smart-d9a9f930-4266-4525-9da1-5ebb7bcfd6df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836820115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.836820115
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1504649551
Short name T267
Test name
Test status
Simulation time 1738363264 ps
CPU time 22.85 seconds
Started May 02 02:46:53 PM PDT 24
Finished May 02 02:47:17 PM PDT 24
Peak memory 199632 kb
Host smart-5fdc8ae9-c078-4971-8b03-a13e818bc2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504649551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1504649551
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1166629298
Short name T328
Test name
Test status
Simulation time 212509942 ps
CPU time 6.48 seconds
Started May 02 02:46:59 PM PDT 24
Finished May 02 02:47:08 PM PDT 24
Peak memory 199668 kb
Host smart-a6ca7085-3be0-4305-8c35-805b0655333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166629298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1166629298
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1416721294
Short name T428
Test name
Test status
Simulation time 192509588 ps
CPU time 0.95 seconds
Started May 02 02:47:03 PM PDT 24
Finished May 02 02:47:05 PM PDT 24
Peak memory 198380 kb
Host smart-31b3f042-3088-4871-90a6-56e433010245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416721294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1416721294
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2484030364
Short name T312
Test name
Test status
Simulation time 40987871 ps
CPU time 0.96 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:47:02 PM PDT 24
Peak memory 198424 kb
Host smart-70b36455-e4a1-41c5-be9d-f9adfe904111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484030364 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2484030364
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1271357731
Short name T436
Test name
Test status
Simulation time 50702428886 ps
CPU time 488.05 seconds
Started May 02 02:47:04 PM PDT 24
Finished May 02 02:55:14 PM PDT 24
Peak memory 199692 kb
Host smart-152fa710-a7cc-4827-b930-d90e75c9516f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271357731 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1271357731
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3770815852
Short name T405
Test name
Test status
Simulation time 1069366947 ps
CPU time 32.83 seconds
Started May 02 02:46:57 PM PDT 24
Finished May 02 02:47:33 PM PDT 24
Peak memory 199656 kb
Host smart-3ef4e0bf-efe1-47ee-84a0-ce38892b793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770815852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3770815852
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1081813743
Short name T23
Test name
Test status
Simulation time 32061230 ps
CPU time 0.59 seconds
Started May 02 02:44:20 PM PDT 24
Finished May 02 02:44:21 PM PDT 24
Peak memory 195004 kb
Host smart-6e6cde15-f080-4624-8694-64a58639fe91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081813743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1081813743
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.155717769
Short name T325
Test name
Test status
Simulation time 5843068009 ps
CPU time 37.46 seconds
Started May 02 02:44:10 PM PDT 24
Finished May 02 02:44:48 PM PDT 24
Peak memory 248516 kb
Host smart-dda7afd1-3832-4005-91a1-62f59ea0a63c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155717769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.155717769
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2745469206
Short name T388
Test name
Test status
Simulation time 2541874402 ps
CPU time 61.73 seconds
Started May 02 02:44:08 PM PDT 24
Finished May 02 02:45:11 PM PDT 24
Peak memory 199740 kb
Host smart-e3c3540e-841b-43b6-abed-ebdaf9feadaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745469206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2745469206
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3636539271
Short name T340
Test name
Test status
Simulation time 3067907467 ps
CPU time 29.75 seconds
Started May 02 02:44:08 PM PDT 24
Finished May 02 02:44:38 PM PDT 24
Peak memory 199728 kb
Host smart-ab3e2aab-b71f-4957-8a07-11ba9ef68cbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636539271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3636539271
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3161808672
Short name T457
Test name
Test status
Simulation time 19670226199 ps
CPU time 77.01 seconds
Started May 02 02:44:08 PM PDT 24
Finished May 02 02:45:26 PM PDT 24
Peak memory 199696 kb
Host smart-a2b6a47b-f76b-43a1-bb17-1f63ae01d241
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161808672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3161808672
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4136175037
Short name T537
Test name
Test status
Simulation time 1270057784 ps
CPU time 6.43 seconds
Started May 02 02:44:08 PM PDT 24
Finished May 02 02:44:16 PM PDT 24
Peak memory 199664 kb
Host smart-eec7d436-a934-41da-9ba4-8ca4bcf33129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136175037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4136175037
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2856592539
Short name T1
Test name
Test status
Simulation time 60502701 ps
CPU time 0.87 seconds
Started May 02 02:44:21 PM PDT 24
Finished May 02 02:44:24 PM PDT 24
Peak memory 218080 kb
Host smart-b254267f-20f5-4a1a-8e1b-c99cd27202ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856592539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2856592539
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2832796081
Short name T300
Test name
Test status
Simulation time 2280820609 ps
CPU time 7.1 seconds
Started May 02 02:44:10 PM PDT 24
Finished May 02 02:44:18 PM PDT 24
Peak memory 199720 kb
Host smart-67e53afd-3194-4415-bc0f-de37a3f154f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832796081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2832796081
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1627654308
Short name T573
Test name
Test status
Simulation time 1465442715 ps
CPU time 87.18 seconds
Started May 02 02:44:19 PM PDT 24
Finished May 02 02:45:48 PM PDT 24
Peak memory 199660 kb
Host smart-7a415a9b-ad0a-434d-91b5-c59f203c9c69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627654308 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1627654308
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1537337561
Short name T561
Test name
Test status
Simulation time 258446320 ps
CPU time 1.11 seconds
Started May 02 02:44:18 PM PDT 24
Finished May 02 02:44:20 PM PDT 24
Peak memory 198412 kb
Host smart-7722829b-451c-4503-ac5f-af38223c5228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537337561 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1537337561
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3172102015
Short name T269
Test name
Test status
Simulation time 29672623465 ps
CPU time 420.38 seconds
Started May 02 02:44:20 PM PDT 24
Finished May 02 02:51:21 PM PDT 24
Peak memory 199664 kb
Host smart-02fd157e-b955-4e82-b1d8-9ff26f92edda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172102015 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3172102015
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2747829703
Short name T92
Test name
Test status
Simulation time 1907662296 ps
CPU time 37.51 seconds
Started May 02 02:44:07 PM PDT 24
Finished May 02 02:44:45 PM PDT 24
Peak memory 199688 kb
Host smart-8ba1dc2b-f2fe-40e2-84e2-bcca994eac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747829703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2747829703
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2069470121
Short name T240
Test name
Test status
Simulation time 20661130 ps
CPU time 0.55 seconds
Started May 02 02:46:57 PM PDT 24
Finished May 02 02:47:00 PM PDT 24
Peak memory 195360 kb
Host smart-3247eeff-f3fd-4b0c-beaa-9595bd8ad59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069470121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2069470121
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.473179546
Short name T332
Test name
Test status
Simulation time 4318142575 ps
CPU time 40.6 seconds
Started May 02 02:46:59 PM PDT 24
Finished May 02 02:47:42 PM PDT 24
Peak memory 224296 kb
Host smart-82164413-718e-42e3-a566-7e57097b6fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473179546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.473179546
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3255799153
Short name T579
Test name
Test status
Simulation time 806818364 ps
CPU time 38.82 seconds
Started May 02 02:46:59 PM PDT 24
Finished May 02 02:47:40 PM PDT 24
Peak memory 199708 kb
Host smart-5e933306-9088-4c16-9d1b-683c6447fa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255799153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3255799153
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3459427323
Short name T178
Test name
Test status
Simulation time 1298597402 ps
CPU time 74.93 seconds
Started May 02 02:47:00 PM PDT 24
Finished May 02 02:48:17 PM PDT 24
Peak memory 199668 kb
Host smart-fb1b329e-75fd-46ef-a5fd-9e218a6b916f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459427323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3459427323
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3946125031
Short name T158
Test name
Test status
Simulation time 7412594397 ps
CPU time 208.94 seconds
Started May 02 02:47:07 PM PDT 24
Finished May 02 02:50:37 PM PDT 24
Peak memory 199732 kb
Host smart-4e5e3cdd-a6f0-4eb8-8590-ef4719d96dcc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946125031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3946125031
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3188778262
Short name T126
Test name
Test status
Simulation time 413057999 ps
CPU time 8.44 seconds
Started May 02 02:46:57 PM PDT 24
Finished May 02 02:47:08 PM PDT 24
Peak memory 199620 kb
Host smart-210101e9-3256-48bb-82cc-f6e1ddf77ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188778262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3188778262
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.94487037
Short name T507
Test name
Test status
Simulation time 97584923 ps
CPU time 3.15 seconds
Started May 02 02:47:07 PM PDT 24
Finished May 02 02:47:12 PM PDT 24
Peak memory 199648 kb
Host smart-01e4f4fc-77cc-4283-8538-c00b5030a742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94487037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.94487037
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.159164013
Short name T569
Test name
Test status
Simulation time 34622508282 ps
CPU time 647.73 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:57:48 PM PDT 24
Peak memory 224292 kb
Host smart-58c115d5-6bd4-4ded-af74-8c3834b2c937
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159164013 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.159164013
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3641948541
Short name T288
Test name
Test status
Simulation time 61094107 ps
CPU time 1.17 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:47:01 PM PDT 24
Peak memory 199668 kb
Host smart-41b7c488-b53c-42ba-b391-0aafceedfab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641948541 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3641948541
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3352207864
Short name T418
Test name
Test status
Simulation time 7717664098 ps
CPU time 432.27 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 199704 kb
Host smart-06265c37-1e1c-40ee-8a79-271c8690d4b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352207864 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3352207864
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2673083149
Short name T337
Test name
Test status
Simulation time 2478542541 ps
CPU time 42.93 seconds
Started May 02 02:47:03 PM PDT 24
Finished May 02 02:47:48 PM PDT 24
Peak memory 199692 kb
Host smart-5656d609-5523-409b-8840-7e753531901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673083149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2673083149
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2310387615
Short name T359
Test name
Test status
Simulation time 15143257 ps
CPU time 0.6 seconds
Started May 02 02:47:04 PM PDT 24
Finished May 02 02:47:06 PM PDT 24
Peak memory 195352 kb
Host smart-d47e30da-cc5e-4cc2-9ae3-24797cf95746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310387615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2310387615
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2089397455
Short name T29
Test name
Test status
Simulation time 295485136 ps
CPU time 14.56 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:47:15 PM PDT 24
Peak memory 199640 kb
Host smart-ee41ed43-9941-414c-811e-9002801eb42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089397455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2089397455
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2541551596
Short name T446
Test name
Test status
Simulation time 2785877009 ps
CPU time 159.95 seconds
Started May 02 02:46:57 PM PDT 24
Finished May 02 02:49:40 PM PDT 24
Peak memory 199744 kb
Host smart-cc76851b-9bb5-4450-be0d-b1bf223d6a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541551596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2541551596
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1283549225
Short name T236
Test name
Test status
Simulation time 1810388777 ps
CPU time 21.99 seconds
Started May 02 02:46:57 PM PDT 24
Finished May 02 02:47:22 PM PDT 24
Peak memory 199672 kb
Host smart-bb521537-4113-4f85-bc9f-1a9d8d4ee5c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283549225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1283549225
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2621704535
Short name T431
Test name
Test status
Simulation time 46474275165 ps
CPU time 97.68 seconds
Started May 02 02:46:56 PM PDT 24
Finished May 02 02:48:35 PM PDT 24
Peak memory 199696 kb
Host smart-fd683937-4be7-4531-8c5f-533d4152cdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621704535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2621704535
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1172457122
Short name T180
Test name
Test status
Simulation time 859314709 ps
CPU time 5.28 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:47:05 PM PDT 24
Peak memory 199600 kb
Host smart-5d5771c3-ff36-4813-a6b0-e3502f24ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172457122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1172457122
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1194846556
Short name T523
Test name
Test status
Simulation time 75002944675 ps
CPU time 914.24 seconds
Started May 02 02:47:04 PM PDT 24
Finished May 02 03:02:20 PM PDT 24
Peak memory 216112 kb
Host smart-599a87a7-e5c3-4db9-a51d-d072558d50e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194846556 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1194846556
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1735069479
Short name T545
Test name
Test status
Simulation time 28937003 ps
CPU time 1.02 seconds
Started May 02 02:47:03 PM PDT 24
Finished May 02 02:47:06 PM PDT 24
Peak memory 199328 kb
Host smart-239805a7-27a7-48cf-92ce-e032d692e4c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735069479 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1735069479
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3963189747
Short name T420
Test name
Test status
Simulation time 15143837717 ps
CPU time 433.19 seconds
Started May 02 02:46:57 PM PDT 24
Finished May 02 02:54:12 PM PDT 24
Peak memory 199696 kb
Host smart-0b522a87-ed6e-49c9-81d5-e3f56c57cde3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963189747 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3963189747
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.4027566955
Short name T463
Test name
Test status
Simulation time 18223619377 ps
CPU time 58.46 seconds
Started May 02 02:46:58 PM PDT 24
Finished May 02 02:47:58 PM PDT 24
Peak memory 199812 kb
Host smart-4051b4f4-db35-4952-9e8c-1c9e681257d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027566955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4027566955
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2207783667
Short name T480
Test name
Test status
Simulation time 55242303 ps
CPU time 0.55 seconds
Started May 02 02:47:11 PM PDT 24
Finished May 02 02:47:12 PM PDT 24
Peak memory 195024 kb
Host smart-1364f94c-eba5-4eec-8dbd-17e3755aa875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207783667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2207783667
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3139909371
Short name T594
Test name
Test status
Simulation time 3404156186 ps
CPU time 35.14 seconds
Started May 02 02:47:05 PM PDT 24
Finished May 02 02:47:42 PM PDT 24
Peak memory 231744 kb
Host smart-e2f45f00-8f11-4d1e-b16c-50e2ce1aef61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139909371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3139909371
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2383705091
Short name T447
Test name
Test status
Simulation time 2300107012 ps
CPU time 5.21 seconds
Started May 02 02:47:04 PM PDT 24
Finished May 02 02:47:11 PM PDT 24
Peak memory 199656 kb
Host smart-8fb8b487-d596-4a8a-b413-d9d8e2c0003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383705091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2383705091
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2861057442
Short name T84
Test name
Test status
Simulation time 234217930 ps
CPU time 13.92 seconds
Started May 02 02:47:08 PM PDT 24
Finished May 02 02:47:23 PM PDT 24
Peak memory 199668 kb
Host smart-f11a2e9b-9682-40b6-967d-0b36d04e9fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861057442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2861057442
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2141807762
Short name T237
Test name
Test status
Simulation time 161222234 ps
CPU time 0.64 seconds
Started May 02 02:47:04 PM PDT 24
Finished May 02 02:47:06 PM PDT 24
Peak memory 195668 kb
Host smart-4e369fd2-6373-4939-aac3-9262ae55d591
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141807762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2141807762
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3749654768
Short name T197
Test name
Test status
Simulation time 16559152814 ps
CPU time 110.78 seconds
Started May 02 02:47:04 PM PDT 24
Finished May 02 02:48:56 PM PDT 24
Peak memory 199752 kb
Host smart-5e68acd3-483a-45de-b1dd-3e968a4d95a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749654768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3749654768
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2820946097
Short name T268
Test name
Test status
Simulation time 436576841 ps
CPU time 3.6 seconds
Started May 02 02:47:03 PM PDT 24
Finished May 02 02:47:08 PM PDT 24
Peak memory 199696 kb
Host smart-557c12ad-ebc5-416d-857d-6c23c6318799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820946097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2820946097
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.404753744
Short name T450
Test name
Test status
Simulation time 56771505 ps
CPU time 0.96 seconds
Started May 02 02:47:04 PM PDT 24
Finished May 02 02:47:07 PM PDT 24
Peak memory 199112 kb
Host smart-1d4b6317-393c-403a-851e-a13d95b01477
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404753744 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.404753744
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.549333933
Short name T301
Test name
Test status
Simulation time 75093373653 ps
CPU time 492.17 seconds
Started May 02 02:47:03 PM PDT 24
Finished May 02 02:55:17 PM PDT 24
Peak memory 199620 kb
Host smart-f33581b2-0206-43e4-8660-5a68f4c4b292
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549333933 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.549333933
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3630438791
Short name T471
Test name
Test status
Simulation time 3489356649 ps
CPU time 45.37 seconds
Started May 02 02:47:08 PM PDT 24
Finished May 02 02:47:54 PM PDT 24
Peak memory 199736 kb
Host smart-ced40017-b45a-4e63-8ecf-82da8665db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630438791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3630438791
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.100358673
Short name T541
Test name
Test status
Simulation time 12943727 ps
CPU time 0.62 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:47:19 PM PDT 24
Peak memory 195012 kb
Host smart-0745293a-8164-43ca-92ea-776ffc144677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100358673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.100358673
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2218335187
Short name T2
Test name
Test status
Simulation time 1979424673 ps
CPU time 20.11 seconds
Started May 02 02:47:09 PM PDT 24
Finished May 02 02:47:30 PM PDT 24
Peak memory 235128 kb
Host smart-9df9f081-a5c5-41c4-b551-dafbcb3fcf5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218335187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2218335187
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.335891609
Short name T363
Test name
Test status
Simulation time 12934047024 ps
CPU time 47.78 seconds
Started May 02 02:47:10 PM PDT 24
Finished May 02 02:47:59 PM PDT 24
Peak memory 199676 kb
Host smart-ca080e74-574b-4c40-992b-62dd505f6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335891609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.335891609
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3983969711
Short name T548
Test name
Test status
Simulation time 12369228798 ps
CPU time 93.32 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:48:57 PM PDT 24
Peak memory 199752 kb
Host smart-ce8ad241-8de8-41f2-bf4d-ec6c47a6c3a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983969711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3983969711
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2366392950
Short name T351
Test name
Test status
Simulation time 44915529716 ps
CPU time 146.04 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:49:49 PM PDT 24
Peak memory 199728 kb
Host smart-cd06124a-157f-4523-83d1-ea4742d545b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366392950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2366392950
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2328701630
Short name T91
Test name
Test status
Simulation time 2069120741 ps
CPU time 14.33 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:47:38 PM PDT 24
Peak memory 199648 kb
Host smart-6acfeceb-40ff-45fe-932b-2155877401f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328701630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2328701630
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2808300297
Short name T259
Test name
Test status
Simulation time 186572772 ps
CPU time 3.03 seconds
Started May 02 02:47:09 PM PDT 24
Finished May 02 02:47:13 PM PDT 24
Peak memory 199688 kb
Host smart-02742036-5b02-4263-ad35-4441114dd340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808300297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2808300297
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.388527629
Short name T65
Test name
Test status
Simulation time 10800497349 ps
CPU time 127.19 seconds
Started May 02 02:47:18 PM PDT 24
Finished May 02 02:49:26 PM PDT 24
Peak memory 234516 kb
Host smart-30c563f8-615d-41fd-99a7-102c05884866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388527629 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.388527629
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3610214885
Short name T146
Test name
Test status
Simulation time 30329778 ps
CPU time 1.17 seconds
Started May 02 02:47:10 PM PDT 24
Finished May 02 02:47:12 PM PDT 24
Peak memory 199632 kb
Host smart-f8a3db50-11e1-4647-8f29-d8c0e5441d7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610214885 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3610214885
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.809822802
Short name T358
Test name
Test status
Simulation time 109845437792 ps
CPU time 492.94 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:55:37 PM PDT 24
Peak memory 199676 kb
Host smart-1cd25f18-a707-4460-a3e8-27e941cc2fe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809822802 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.809822802
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1345523164
Short name T542
Test name
Test status
Simulation time 15688692199 ps
CPU time 81.29 seconds
Started May 02 02:47:11 PM PDT 24
Finished May 02 02:48:33 PM PDT 24
Peak memory 199716 kb
Host smart-31bb1dff-7f91-4d21-b948-11e14ac98baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345523164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1345523164
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3499440672
Short name T294
Test name
Test status
Simulation time 184716309 ps
CPU time 0.6 seconds
Started May 02 02:47:18 PM PDT 24
Finished May 02 02:47:20 PM PDT 24
Peak memory 195424 kb
Host smart-2908c4a4-9ac7-49f6-88e8-d12cbb482a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499440672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3499440672
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3684245968
Short name T163
Test name
Test status
Simulation time 4573772459 ps
CPU time 36.77 seconds
Started May 02 02:47:15 PM PDT 24
Finished May 02 02:47:53 PM PDT 24
Peak memory 207932 kb
Host smart-73bd4fee-501d-4121-9ac2-1bed4d373ff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684245968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3684245968
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1193959734
Short name T576
Test name
Test status
Simulation time 11678423099 ps
CPU time 34.8 seconds
Started May 02 02:47:15 PM PDT 24
Finished May 02 02:47:51 PM PDT 24
Peak memory 199752 kb
Host smart-b227c73b-6ccb-403d-848b-55bea45e2d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193959734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1193959734
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2361630168
Short name T435
Test name
Test status
Simulation time 1716043818 ps
CPU time 100.59 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:48:58 PM PDT 24
Peak memory 199664 kb
Host smart-6b5fd2a8-1a84-4739-ac44-29a320857121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361630168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2361630168
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3965403023
Short name T253
Test name
Test status
Simulation time 34786790969 ps
CPU time 122.68 seconds
Started May 02 02:47:14 PM PDT 24
Finished May 02 02:49:18 PM PDT 24
Peak memory 199692 kb
Host smart-9bbaa6d2-6e9e-4aca-975c-6ff411e6703d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965403023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3965403023
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2800887284
Short name T465
Test name
Test status
Simulation time 1519750954 ps
CPU time 44.63 seconds
Started May 02 02:47:18 PM PDT 24
Finished May 02 02:48:04 PM PDT 24
Peak memory 199644 kb
Host smart-f17d9aac-0351-45fc-9eea-3687f5fc612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800887284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2800887284
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3068657963
Short name T443
Test name
Test status
Simulation time 117507847 ps
CPU time 3.25 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:47:21 PM PDT 24
Peak memory 199504 kb
Host smart-f87a0e51-c5ba-440a-b944-9fa64c381b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068657963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3068657963
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2144198744
Short name T487
Test name
Test status
Simulation time 269329172672 ps
CPU time 549.42 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:56:27 PM PDT 24
Peak memory 211576 kb
Host smart-851d05ce-0489-49a7-bcde-d8a6c7996ac4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144198744 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2144198744
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.425124484
Short name T394
Test name
Test status
Simulation time 75239931 ps
CPU time 1.42 seconds
Started May 02 02:47:18 PM PDT 24
Finished May 02 02:47:21 PM PDT 24
Peak memory 199640 kb
Host smart-d6bd3910-bf39-4a1a-a7b1-6fc3d71a7a6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425124484 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.425124484
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.96847148
Short name T283
Test name
Test status
Simulation time 73747043170 ps
CPU time 448.19 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:54:47 PM PDT 24
Peak memory 199620 kb
Host smart-d77b728d-f8f8-44f9-a3cd-4ee55289f015
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96847148 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.96847148
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4231430220
Short name T260
Test name
Test status
Simulation time 3110532513 ps
CPU time 40.07 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:47:58 PM PDT 24
Peak memory 199652 kb
Host smart-62efd880-6ccd-4d4e-9029-03d21e23b6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231430220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4231430220
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1612486044
Short name T25
Test name
Test status
Simulation time 12152694 ps
CPU time 0.57 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:47:24 PM PDT 24
Peak memory 194316 kb
Host smart-e86504cd-d6b3-434c-b3a1-c3dc74008283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612486044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1612486044
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.93232162
Short name T170
Test name
Test status
Simulation time 650868575 ps
CPU time 26.95 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:47:50 PM PDT 24
Peak memory 240388 kb
Host smart-b7467da4-a814-422e-b3ae-441d6a385d21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93232162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.93232162
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3989617523
Short name T331
Test name
Test status
Simulation time 10254095195 ps
CPU time 49.35 seconds
Started May 02 02:47:15 PM PDT 24
Finished May 02 02:48:05 PM PDT 24
Peak memory 199760 kb
Host smart-a52ab9fa-70a7-4d99-af94-ebb159ab5a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989617523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3989617523
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3930256880
Short name T207
Test name
Test status
Simulation time 2203529630 ps
CPU time 129.11 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:49:27 PM PDT 24
Peak memory 199728 kb
Host smart-df9e7f28-1be6-4741-aaee-120150469077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930256880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3930256880
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1664117539
Short name T381
Test name
Test status
Simulation time 150498556118 ps
CPU time 264.9 seconds
Started May 02 02:47:16 PM PDT 24
Finished May 02 02:51:43 PM PDT 24
Peak memory 199712 kb
Host smart-69b0861c-df48-4e0d-9344-6e2c77bbec2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664117539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1664117539
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2910966088
Short name T338
Test name
Test status
Simulation time 15088862614 ps
CPU time 70.29 seconds
Started May 02 02:47:17 PM PDT 24
Finished May 02 02:48:28 PM PDT 24
Peak memory 199572 kb
Host smart-114bdd4c-3df6-45a5-ac2b-e4e5cd593b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910966088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2910966088
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3477871159
Short name T318
Test name
Test status
Simulation time 1549362714 ps
CPU time 5.59 seconds
Started May 02 02:47:16 PM PDT 24
Finished May 02 02:47:23 PM PDT 24
Peak memory 199684 kb
Host smart-ea6df24f-b7ae-4010-ab4e-a66cdadc5450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477871159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3477871159
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3737333846
Short name T216
Test name
Test status
Simulation time 31337656594 ps
CPU time 312.54 seconds
Started May 02 02:47:23 PM PDT 24
Finished May 02 02:52:37 PM PDT 24
Peak memory 234548 kb
Host smart-7d2bd2b0-6b77-495a-890b-e1ed9f551410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737333846 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3737333846
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3163825317
Short name T546
Test name
Test status
Simulation time 30723882 ps
CPU time 1.16 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:47:24 PM PDT 24
Peak memory 199632 kb
Host smart-884c2f2b-27bb-49a2-9b0c-d3a2b338c2d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163825317 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3163825317
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1610864270
Short name T122
Test name
Test status
Simulation time 105099810242 ps
CPU time 478.77 seconds
Started May 02 02:47:24 PM PDT 24
Finished May 02 02:55:24 PM PDT 24
Peak memory 199708 kb
Host smart-33b1e860-3665-4ede-88d9-da7593ee0fdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610864270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1610864270
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3268560450
Short name T323
Test name
Test status
Simulation time 2598748583 ps
CPU time 12.7 seconds
Started May 02 02:47:23 PM PDT 24
Finished May 02 02:47:38 PM PDT 24
Peak memory 199720 kb
Host smart-1efa7ec7-0e63-4250-bd72-b1f3301e7dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268560450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3268560450
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3965452081
Short name T304
Test name
Test status
Simulation time 26963582 ps
CPU time 0.57 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:47:30 PM PDT 24
Peak memory 195372 kb
Host smart-be8ba9ef-b256-475f-a188-5c51f4e16f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965452081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3965452081
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2445191666
Short name T380
Test name
Test status
Simulation time 6327957420 ps
CPU time 27.67 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:47:51 PM PDT 24
Peak memory 207904 kb
Host smart-4ee0448b-57ea-48f1-bf65-12f02eb696f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445191666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2445191666
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1424893114
Short name T219
Test name
Test status
Simulation time 750430747 ps
CPU time 37.48 seconds
Started May 02 02:47:23 PM PDT 24
Finished May 02 02:48:02 PM PDT 24
Peak memory 199668 kb
Host smart-de07892b-d64a-4ec9-adb4-3ccb3db894f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424893114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1424893114
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.841750271
Short name T234
Test name
Test status
Simulation time 16682068 ps
CPU time 0.68 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:47:25 PM PDT 24
Peak memory 196560 kb
Host smart-c420e744-0a1a-403b-9ce3-f18e84640204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841750271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.841750271
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3285485373
Short name T442
Test name
Test status
Simulation time 2685728730 ps
CPU time 35.56 seconds
Started May 02 02:47:22 PM PDT 24
Finished May 02 02:47:59 PM PDT 24
Peak memory 199692 kb
Host smart-2b476732-898c-4232-a9ee-06bb97c99f5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285485373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3285485373
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1086918384
Short name T147
Test name
Test status
Simulation time 22937060210 ps
CPU time 108.94 seconds
Started May 02 02:47:21 PM PDT 24
Finished May 02 02:49:11 PM PDT 24
Peak memory 199740 kb
Host smart-072d58bf-2b89-492a-b20b-c1caa26513f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086918384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1086918384
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3504115843
Short name T398
Test name
Test status
Simulation time 74426753 ps
CPU time 1.45 seconds
Started May 02 02:47:23 PM PDT 24
Finished May 02 02:47:26 PM PDT 24
Peak memory 199596 kb
Host smart-3be662b2-bd7c-4c47-8783-b64632e0cf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504115843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3504115843
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1824237617
Short name T71
Test name
Test status
Simulation time 758459720079 ps
CPU time 714.31 seconds
Started May 02 02:47:32 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 216088 kb
Host smart-0bc96fae-abaf-4a6c-bd1d-568a37450b50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824237617 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1824237617
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3559386861
Short name T505
Test name
Test status
Simulation time 317290221 ps
CPU time 1.33 seconds
Started May 02 02:47:29 PM PDT 24
Finished May 02 02:47:32 PM PDT 24
Peak memory 199556 kb
Host smart-d79d5aad-20de-4189-9891-f837c5ec0eb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559386861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3559386861
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.4060372167
Short name T437
Test name
Test status
Simulation time 77946073490 ps
CPU time 493.12 seconds
Started May 02 02:47:38 PM PDT 24
Finished May 02 02:55:52 PM PDT 24
Peak memory 199668 kb
Host smart-1f904fb4-7b72-4282-9443-f00ab5a0b961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060372167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.4060372167
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.466502477
Short name T335
Test name
Test status
Simulation time 6852172255 ps
CPU time 35.77 seconds
Started May 02 02:47:30 PM PDT 24
Finished May 02 02:48:07 PM PDT 24
Peak memory 199684 kb
Host smart-298a871c-5b10-40f6-97bf-9be3c18a74af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466502477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.466502477
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1331981982
Short name T238
Test name
Test status
Simulation time 11068060 ps
CPU time 0.56 seconds
Started May 02 02:47:32 PM PDT 24
Finished May 02 02:47:33 PM PDT 24
Peak memory 194236 kb
Host smart-79b46876-2f75-4dba-bc98-0d59b1ad36de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331981982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1331981982
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1172397456
Short name T583
Test name
Test status
Simulation time 15587870679 ps
CPU time 58.71 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:48:28 PM PDT 24
Peak memory 226252 kb
Host smart-1d003c15-5f39-45c4-a659-bd766ef38cdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172397456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1172397456
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2561588573
Short name T69
Test name
Test status
Simulation time 94037096 ps
CPU time 1.97 seconds
Started May 02 02:47:38 PM PDT 24
Finished May 02 02:47:41 PM PDT 24
Peak memory 199632 kb
Host smart-8da2c221-1f3d-40d5-a43c-5939f9195fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561588573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2561588573
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.448060887
Short name T161
Test name
Test status
Simulation time 555821057 ps
CPU time 15.48 seconds
Started May 02 02:47:32 PM PDT 24
Finished May 02 02:47:49 PM PDT 24
Peak memory 199640 kb
Host smart-0fcaaa63-2822-43e9-88d4-55f0304ad0bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448060887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.448060887
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2463096491
Short name T222
Test name
Test status
Simulation time 67828665385 ps
CPU time 228.82 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:51:18 PM PDT 24
Peak memory 199692 kb
Host smart-8a3b1160-0ac9-4e6c-9382-ef18bd70950f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463096491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2463096491
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3506703985
Short name T486
Test name
Test status
Simulation time 422566338 ps
CPU time 21.75 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:47:51 PM PDT 24
Peak memory 199664 kb
Host smart-09382044-0104-437a-a198-7138268de1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506703985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3506703985
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1176115520
Short name T577
Test name
Test status
Simulation time 478357523 ps
CPU time 1.39 seconds
Started May 02 02:47:33 PM PDT 24
Finished May 02 02:47:36 PM PDT 24
Peak memory 199652 kb
Host smart-4682a2c8-980a-4245-bc75-46a4cd44db59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176115520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1176115520
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2078712012
Short name T540
Test name
Test status
Simulation time 8048514892 ps
CPU time 46.83 seconds
Started May 02 02:47:30 PM PDT 24
Finished May 02 02:48:18 PM PDT 24
Peak memory 199712 kb
Host smart-884bfc0a-1b7d-4d63-9713-58495adf7d03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078712012 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2078712012
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1911824364
Short name T248
Test name
Test status
Simulation time 43907787 ps
CPU time 1.09 seconds
Started May 02 02:47:32 PM PDT 24
Finished May 02 02:47:34 PM PDT 24
Peak memory 199176 kb
Host smart-f7fe0eea-7a91-40e1-bc48-6347198274fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911824364 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1911824364
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3203881984
Short name T217
Test name
Test status
Simulation time 26111322007 ps
CPU time 464.44 seconds
Started May 02 02:47:29 PM PDT 24
Finished May 02 02:55:15 PM PDT 24
Peak memory 199728 kb
Host smart-9dab8ba2-fd07-47e1-a2c8-72a5366d5459
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203881984 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3203881984
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3124960197
Short name T499
Test name
Test status
Simulation time 20108939715 ps
CPU time 62.63 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:48:32 PM PDT 24
Peak memory 199696 kb
Host smart-43d2b49d-48d3-4c40-b875-e3ffbd010739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124960197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3124960197
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1555477168
Short name T79
Test name
Test status
Simulation time 33199620 ps
CPU time 0.56 seconds
Started May 02 02:47:34 PM PDT 24
Finished May 02 02:47:36 PM PDT 24
Peak memory 195372 kb
Host smart-23a44611-bb44-4f0e-90d8-51055e1b459a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555477168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1555477168
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1829523752
Short name T539
Test name
Test status
Simulation time 3849470577 ps
CPU time 37.36 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:48:07 PM PDT 24
Peak memory 216056 kb
Host smart-9fbd37f6-1669-4379-a8da-d34cdad63da9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829523752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1829523752
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2081788628
Short name T599
Test name
Test status
Simulation time 5551549679 ps
CPU time 65.72 seconds
Started May 02 02:47:29 PM PDT 24
Finished May 02 02:48:36 PM PDT 24
Peak memory 199720 kb
Host smart-b419bb9a-f5bc-4f0e-953e-cde14a6fde2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081788628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2081788628
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1126529570
Short name T39
Test name
Test status
Simulation time 2405088360 ps
CPU time 131.36 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:49:40 PM PDT 24
Peak memory 199740 kb
Host smart-878f6971-6e0b-43f1-b503-54bc177b81d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126529570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1126529570
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.777712416
Short name T551
Test name
Test status
Simulation time 19666562894 ps
CPU time 167.63 seconds
Started May 02 02:47:31 PM PDT 24
Finished May 02 02:50:20 PM PDT 24
Peak memory 199724 kb
Host smart-6c538a1b-c4fb-4907-8d2f-f845503253f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777712416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.777712416
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1981283365
Short name T533
Test name
Test status
Simulation time 2709418933 ps
CPU time 39.92 seconds
Started May 02 02:47:30 PM PDT 24
Finished May 02 02:48:11 PM PDT 24
Peak memory 199732 kb
Host smart-488578e4-a494-4da1-9682-1f77b67d5742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981283365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1981283365
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3659160980
Short name T519
Test name
Test status
Simulation time 654513847 ps
CPU time 6.36 seconds
Started May 02 02:47:29 PM PDT 24
Finished May 02 02:47:37 PM PDT 24
Peak memory 199664 kb
Host smart-dc296344-8fd5-42d2-b603-ecaf571af58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659160980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3659160980
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2322793114
Short name T73
Test name
Test status
Simulation time 77017913653 ps
CPU time 1063.65 seconds
Started May 02 02:47:35 PM PDT 24
Finished May 02 03:05:20 PM PDT 24
Peak memory 240444 kb
Host smart-e286026e-d1fd-4776-813c-c8762edb295c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322793114 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2322793114
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1868974539
Short name T212
Test name
Test status
Simulation time 60064403 ps
CPU time 1.27 seconds
Started May 02 02:47:36 PM PDT 24
Finished May 02 02:47:39 PM PDT 24
Peak memory 199560 kb
Host smart-e8ec57e2-70b3-45f9-ae2f-0127e40e273a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868974539 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1868974539
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.695080501
Short name T68
Test name
Test status
Simulation time 7521431276 ps
CPU time 412.38 seconds
Started May 02 02:47:28 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 199688 kb
Host smart-49d7bf34-c7b0-40dd-a407-46c8d7aa6823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695080501 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.695080501
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1696993032
Short name T485
Test name
Test status
Simulation time 2722760901 ps
CPU time 47.24 seconds
Started May 02 02:47:30 PM PDT 24
Finished May 02 02:48:19 PM PDT 24
Peak memory 199568 kb
Host smart-4883ef4a-dc2d-4366-a72c-47dcd712f609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696993032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1696993032
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4252581344
Short name T193
Test name
Test status
Simulation time 12793275 ps
CPU time 0.56 seconds
Started May 02 02:47:44 PM PDT 24
Finished May 02 02:47:46 PM PDT 24
Peak memory 195248 kb
Host smart-02d29045-487f-4684-9b1b-1753b2f6b135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252581344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4252581344
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2687153589
Short name T349
Test name
Test status
Simulation time 822792283 ps
CPU time 27.31 seconds
Started May 02 02:47:35 PM PDT 24
Finished May 02 02:48:04 PM PDT 24
Peak memory 216056 kb
Host smart-505ad530-30a7-4368-a219-630aa18e5d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687153589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2687153589
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.9421252
Short name T461
Test name
Test status
Simulation time 3872763388 ps
CPU time 26.3 seconds
Started May 02 02:47:36 PM PDT 24
Finished May 02 02:48:04 PM PDT 24
Peak memory 199740 kb
Host smart-9a137e4e-cf83-408e-8010-f78941001105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9421252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.9421252
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2945313817
Short name T441
Test name
Test status
Simulation time 1012118516 ps
CPU time 14.7 seconds
Started May 02 02:47:35 PM PDT 24
Finished May 02 02:47:51 PM PDT 24
Peak memory 199620 kb
Host smart-6f1de9dd-25d5-449a-af02-633dfeb7cdeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945313817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2945313817
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4151688349
Short name T198
Test name
Test status
Simulation time 11601122218 ps
CPU time 118.87 seconds
Started May 02 02:47:36 PM PDT 24
Finished May 02 02:49:36 PM PDT 24
Peak memory 199732 kb
Host smart-c54e4fb0-73e9-4149-98eb-ef84c0a418f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151688349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4151688349
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2252016000
Short name T244
Test name
Test status
Simulation time 18230529013 ps
CPU time 58.88 seconds
Started May 02 02:47:34 PM PDT 24
Finished May 02 02:48:35 PM PDT 24
Peak memory 199772 kb
Host smart-9f2f6bda-617f-4569-90de-5e9eb026e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252016000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2252016000
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3903907899
Short name T132
Test name
Test status
Simulation time 337992085 ps
CPU time 2.25 seconds
Started May 02 02:47:36 PM PDT 24
Finished May 02 02:47:40 PM PDT 24
Peak memory 199640 kb
Host smart-033cb283-17c3-4108-86fa-789d6b85819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903907899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3903907899
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2435222400
Short name T500
Test name
Test status
Simulation time 465979483998 ps
CPU time 1383.32 seconds
Started May 02 02:47:36 PM PDT 24
Finished May 02 03:10:41 PM PDT 24
Peak memory 233532 kb
Host smart-a69b3ea5-13c2-4c68-a030-6a334611504c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435222400 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2435222400
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2913969662
Short name T142
Test name
Test status
Simulation time 32596413 ps
CPU time 1.18 seconds
Started May 02 02:47:36 PM PDT 24
Finished May 02 02:47:38 PM PDT 24
Peak memory 199668 kb
Host smart-eea829e2-8e0e-4358-80c1-7bfc2e42807f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913969662 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2913969662
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1415786155
Short name T295
Test name
Test status
Simulation time 39119329521 ps
CPU time 420.36 seconds
Started May 02 02:47:35 PM PDT 24
Finished May 02 02:54:37 PM PDT 24
Peak memory 199668 kb
Host smart-0660371a-8fd4-4e64-b8a0-c0d19a0dd03c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415786155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1415786155
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3126847807
Short name T531
Test name
Test status
Simulation time 12921770878 ps
CPU time 59.25 seconds
Started May 02 02:47:35 PM PDT 24
Finished May 02 02:48:36 PM PDT 24
Peak memory 199676 kb
Host smart-9ebe5794-331e-4940-8c75-0da70e682db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126847807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3126847807
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3749255939
Short name T342
Test name
Test status
Simulation time 37786996 ps
CPU time 0.57 seconds
Started May 02 02:44:25 PM PDT 24
Finished May 02 02:44:27 PM PDT 24
Peak memory 195340 kb
Host smart-74393298-3a86-44d5-82e4-e670e7624b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749255939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3749255939
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.24211553
Short name T307
Test name
Test status
Simulation time 5105920789 ps
CPU time 44.11 seconds
Started May 02 02:44:21 PM PDT 24
Finished May 02 02:45:07 PM PDT 24
Peak memory 224232 kb
Host smart-f12c5584-86ea-4607-b08d-340f510c7525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24211553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.24211553
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.487308707
Short name T354
Test name
Test status
Simulation time 1048939467 ps
CPU time 26.77 seconds
Started May 02 02:44:21 PM PDT 24
Finished May 02 02:44:49 PM PDT 24
Peak memory 199564 kb
Host smart-2fbb17c4-b2b6-45c3-8185-b18a902ebc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487308707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.487308707
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2608477989
Short name T460
Test name
Test status
Simulation time 2005958622 ps
CPU time 110.98 seconds
Started May 02 02:44:18 PM PDT 24
Finished May 02 02:46:11 PM PDT 24
Peak memory 199620 kb
Host smart-8de9d19a-e899-4ddc-bcea-b44d92da17cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608477989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2608477989
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.84648875
Short name T415
Test name
Test status
Simulation time 40177584958 ps
CPU time 152.51 seconds
Started May 02 02:44:20 PM PDT 24
Finished May 02 02:46:54 PM PDT 24
Peak memory 199756 kb
Host smart-3fee6c70-da52-44d8-8478-3656f9595139
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84648875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.84648875
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.55068370
Short name T254
Test name
Test status
Simulation time 24175916107 ps
CPU time 77.91 seconds
Started May 02 02:44:18 PM PDT 24
Finished May 02 02:45:37 PM PDT 24
Peak memory 199736 kb
Host smart-3cc27ab8-7d9d-4bb0-86fd-5f0b078d0306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55068370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.55068370
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2594310618
Short name T502
Test name
Test status
Simulation time 1548969741 ps
CPU time 6.03 seconds
Started May 02 02:44:21 PM PDT 24
Finished May 02 02:44:28 PM PDT 24
Peak memory 199696 kb
Host smart-61530c91-4e6d-4b4c-a1c8-4f3f65c8d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594310618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2594310618
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2787548275
Short name T350
Test name
Test status
Simulation time 111558364542 ps
CPU time 1115.73 seconds
Started May 02 02:44:19 PM PDT 24
Finished May 02 03:02:56 PM PDT 24
Peak memory 224348 kb
Host smart-1d6a5672-d643-428d-b443-f1bf8a693244
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787548275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2787548275
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2181505354
Short name T130
Test name
Test status
Simulation time 50559224 ps
CPU time 0.99 seconds
Started May 02 02:44:21 PM PDT 24
Finished May 02 02:44:23 PM PDT 24
Peak memory 198952 kb
Host smart-e985af5c-c564-48f6-97f6-8eef7bab98ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181505354 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2181505354
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.453863608
Short name T470
Test name
Test status
Simulation time 38876842801 ps
CPU time 436.63 seconds
Started May 02 02:44:19 PM PDT 24
Finished May 02 02:51:37 PM PDT 24
Peak memory 199664 kb
Host smart-7b41a695-ed93-412a-be44-9ae31b001699
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453863608 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.453863608
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1489660947
Short name T504
Test name
Test status
Simulation time 40255498343 ps
CPU time 88.66 seconds
Started May 02 02:44:20 PM PDT 24
Finished May 02 02:45:50 PM PDT 24
Peak memory 199696 kb
Host smart-6ca7e7d8-6d40-4f79-9a4f-c3b52174fe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489660947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1489660947
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.2341241260
Short name T10
Test name
Test status
Simulation time 111729992258 ps
CPU time 392.76 seconds
Started May 02 02:47:42 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 216128 kb
Host smart-1d25a1db-a498-4cd9-9c5f-8e25dc6f129e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341241260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.2341241260
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3795193547
Short name T182
Test name
Test status
Simulation time 23187785 ps
CPU time 0.58 seconds
Started May 02 02:44:23 PM PDT 24
Finished May 02 02:44:24 PM PDT 24
Peak memory 195336 kb
Host smart-262eb095-4ad8-4ede-8007-39bb018054ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795193547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3795193547
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2697477444
Short name T200
Test name
Test status
Simulation time 6827509214 ps
CPU time 57.32 seconds
Started May 02 02:44:26 PM PDT 24
Finished May 02 02:45:25 PM PDT 24
Peak memory 240648 kb
Host smart-d005552a-994d-4999-8931-cbd9da3b3628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697477444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2697477444
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3289148351
Short name T408
Test name
Test status
Simulation time 2484416868 ps
CPU time 25.66 seconds
Started May 02 02:44:26 PM PDT 24
Finished May 02 02:44:53 PM PDT 24
Peak memory 199760 kb
Host smart-25a0d972-a0ff-4866-b688-8487650331da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289148351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3289148351
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3262579654
Short name T223
Test name
Test status
Simulation time 1250658784 ps
CPU time 71.05 seconds
Started May 02 02:44:23 PM PDT 24
Finished May 02 02:45:36 PM PDT 24
Peak memory 199628 kb
Host smart-55c45756-a1bc-42bf-b1d5-9068259f8a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262579654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3262579654
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2308633876
Short name T175
Test name
Test status
Simulation time 11181064285 ps
CPU time 196.32 seconds
Started May 02 02:44:24 PM PDT 24
Finished May 02 02:47:41 PM PDT 24
Peak memory 199664 kb
Host smart-da377780-8114-4324-963e-1b60063c10b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308633876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2308633876
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2562858096
Short name T270
Test name
Test status
Simulation time 1902326430 ps
CPU time 105.16 seconds
Started May 02 02:44:25 PM PDT 24
Finished May 02 02:46:11 PM PDT 24
Peak memory 199628 kb
Host smart-0219bea5-42ea-4902-870d-af2dd4bf5555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562858096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2562858096
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.186612730
Short name T379
Test name
Test status
Simulation time 339758858 ps
CPU time 4.96 seconds
Started May 02 02:44:28 PM PDT 24
Finished May 02 02:44:34 PM PDT 24
Peak memory 199632 kb
Host smart-d4280ded-4752-41ec-91ca-abf92ae378f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186612730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.186612730
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2224346104
Short name T508
Test name
Test status
Simulation time 60890441205 ps
CPU time 1109.92 seconds
Started May 02 02:44:24 PM PDT 24
Finished May 02 03:02:55 PM PDT 24
Peak memory 199724 kb
Host smart-fa08ae66-3adc-47c3-9362-eb10a4861034
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224346104 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2224346104
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3494037839
Short name T364
Test name
Test status
Simulation time 31632895 ps
CPU time 1.17 seconds
Started May 02 02:44:28 PM PDT 24
Finished May 02 02:44:30 PM PDT 24
Peak memory 198636 kb
Host smart-98fecd7d-d926-4727-8477-f9b68b83b453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494037839 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3494037839
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.4035067486
Short name T139
Test name
Test status
Simulation time 341571057528 ps
CPU time 469.09 seconds
Started May 02 02:44:26 PM PDT 24
Finished May 02 02:52:16 PM PDT 24
Peak memory 199668 kb
Host smart-4a0c70ac-0538-440a-876b-c075ba76ccbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035067486 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.4035067486
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2883177769
Short name T591
Test name
Test status
Simulation time 8503996871 ps
CPU time 86.38 seconds
Started May 02 02:44:27 PM PDT 24
Finished May 02 02:45:54 PM PDT 24
Peak memory 199740 kb
Host smart-6d245489-ec06-4e3a-864a-56840736f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883177769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2883177769
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.1611013022
Short name T449
Test name
Test status
Simulation time 189523392357 ps
CPU time 1950.18 seconds
Started May 02 02:47:43 PM PDT 24
Finished May 02 03:20:14 PM PDT 24
Peak memory 247112 kb
Host smart-f8a3c72c-edad-4793-93c8-1c25b1cfa7d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611013022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.1611013022
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3318272743
Short name T506
Test name
Test status
Simulation time 14183215 ps
CPU time 0.55 seconds
Started May 02 02:44:33 PM PDT 24
Finished May 02 02:44:35 PM PDT 24
Peak memory 194300 kb
Host smart-6a410013-731f-47b0-a9c5-04c7c192070d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318272743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3318272743
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1690188952
Short name T284
Test name
Test status
Simulation time 12546713854 ps
CPU time 51.71 seconds
Started May 02 02:44:39 PM PDT 24
Finished May 02 02:45:31 PM PDT 24
Peak memory 224388 kb
Host smart-7f46e597-fd4c-4aca-9831-e2d950334ea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690188952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1690188952
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.987446885
Short name T525
Test name
Test status
Simulation time 284333314 ps
CPU time 1.31 seconds
Started May 02 02:44:31 PM PDT 24
Finished May 02 02:44:33 PM PDT 24
Peak memory 199648 kb
Host smart-8e95be3f-ae2e-4179-a872-ae69f81ace54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987446885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.987446885
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.167832062
Short name T412
Test name
Test status
Simulation time 111507123 ps
CPU time 0.67 seconds
Started May 02 02:44:33 PM PDT 24
Finished May 02 02:44:35 PM PDT 24
Peak memory 197012 kb
Host smart-8f7b10d2-0a3f-4342-b2b4-ebddda82b423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167832062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.167832062
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.814470455
Short name T556
Test name
Test status
Simulation time 1722756844 ps
CPU time 30.52 seconds
Started May 02 02:44:33 PM PDT 24
Finished May 02 02:45:04 PM PDT 24
Peak memory 199636 kb
Host smart-156328f9-c597-40e1-8c1a-be42807ecb80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814470455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.814470455
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.132361034
Short name T515
Test name
Test status
Simulation time 24592163310 ps
CPU time 57.85 seconds
Started May 02 02:44:25 PM PDT 24
Finished May 02 02:45:24 PM PDT 24
Peak memory 199732 kb
Host smart-19d72129-413a-4b04-b2f2-a81b98920898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132361034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.132361034
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3243705352
Short name T282
Test name
Test status
Simulation time 388755478 ps
CPU time 5.58 seconds
Started May 02 02:44:23 PM PDT 24
Finished May 02 02:44:29 PM PDT 24
Peak memory 199680 kb
Host smart-c0747a41-b920-49a7-a125-bc447fc9e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243705352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3243705352
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2685963649
Short name T373
Test name
Test status
Simulation time 10110427253 ps
CPU time 479.11 seconds
Started May 02 02:44:34 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 199724 kb
Host smart-b8c03132-ec8b-496c-9e9e-2319a91abde5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685963649 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2685963649
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1435167844
Short name T458
Test name
Test status
Simulation time 103937785 ps
CPU time 1.07 seconds
Started May 02 02:44:31 PM PDT 24
Finished May 02 02:44:33 PM PDT 24
Peak memory 199240 kb
Host smart-e0494174-5b58-4a22-8eca-71fc227844e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435167844 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1435167844
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1440766464
Short name T89
Test name
Test status
Simulation time 16503971843 ps
CPU time 429.58 seconds
Started May 02 02:44:32 PM PDT 24
Finished May 02 02:51:43 PM PDT 24
Peak memory 199612 kb
Host smart-07ba9bfa-898f-4526-8908-0e4c29ad08bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440766464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1440766464
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2245426878
Short name T535
Test name
Test status
Simulation time 10360856917 ps
CPU time 34.81 seconds
Started May 02 02:44:31 PM PDT 24
Finished May 02 02:45:07 PM PDT 24
Peak memory 199704 kb
Host smart-fc81fbd0-111c-4d2a-a16b-c967e650c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245426878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2245426878
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.1561034813
Short name T8
Test name
Test status
Simulation time 9559632169 ps
CPU time 146.97 seconds
Started May 02 02:47:50 PM PDT 24
Finished May 02 02:50:18 PM PDT 24
Peak memory 210856 kb
Host smart-fa5e5172-8291-42a2-9065-07a7d7c87e43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561034813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.1561034813
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.4010797213
Short name T61
Test name
Test status
Simulation time 153810838303 ps
CPU time 1494.08 seconds
Started May 02 02:47:50 PM PDT 24
Finished May 02 03:12:46 PM PDT 24
Peak memory 224376 kb
Host smart-e5f096dd-d27f-4ff3-b4d7-58b3331a9781
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010797213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.4010797213
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2786557367
Short name T319
Test name
Test status
Simulation time 35484989 ps
CPU time 0.58 seconds
Started May 02 02:44:39 PM PDT 24
Finished May 02 02:44:40 PM PDT 24
Peak memory 195396 kb
Host smart-c7e13da1-c7ec-4431-8047-68fb08181da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786557367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2786557367
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2005696543
Short name T409
Test name
Test status
Simulation time 5858879657 ps
CPU time 53.46 seconds
Started May 02 02:44:33 PM PDT 24
Finished May 02 02:45:27 PM PDT 24
Peak memory 216112 kb
Host smart-7f9e85d0-881c-4134-88c5-d1079a851eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005696543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2005696543
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2266520103
Short name T423
Test name
Test status
Simulation time 59116948 ps
CPU time 1.62 seconds
Started May 02 02:44:31 PM PDT 24
Finished May 02 02:44:34 PM PDT 24
Peak memory 199668 kb
Host smart-11ed3076-f3ab-48fb-b222-d31064163359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266520103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2266520103
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1285202421
Short name T366
Test name
Test status
Simulation time 3725503933 ps
CPU time 39.14 seconds
Started May 02 02:44:33 PM PDT 24
Finished May 02 02:45:13 PM PDT 24
Peak memory 199716 kb
Host smart-5a027f75-947c-417d-97a4-968212b0c987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285202421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1285202421
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3259210620
Short name T140
Test name
Test status
Simulation time 622692182 ps
CPU time 33.37 seconds
Started May 02 02:44:31 PM PDT 24
Finished May 02 02:45:06 PM PDT 24
Peak memory 199640 kb
Host smart-83341aee-c6f1-4f1e-91ee-bbc37c9bdf58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259210620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3259210620
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.914509834
Short name T156
Test name
Test status
Simulation time 1061427302 ps
CPU time 59.18 seconds
Started May 02 02:44:32 PM PDT 24
Finished May 02 02:45:33 PM PDT 24
Peak memory 199564 kb
Host smart-fef99d6c-c4c9-449e-b8f7-da077afa345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914509834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.914509834
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4005067530
Short name T128
Test name
Test status
Simulation time 801988298 ps
CPU time 1.29 seconds
Started May 02 02:44:31 PM PDT 24
Finished May 02 02:44:33 PM PDT 24
Peak memory 199668 kb
Host smart-9a35c072-9353-4803-9c1a-20f0fdc0eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005067530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4005067530
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.497518691
Short name T586
Test name
Test status
Simulation time 18964819318 ps
CPU time 172.1 seconds
Started May 02 02:44:42 PM PDT 24
Finished May 02 02:47:35 PM PDT 24
Peak memory 216052 kb
Host smart-6346b4bc-d9af-467e-b67c-04624237e512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497518691 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.497518691
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3401500834
Short name T563
Test name
Test status
Simulation time 36416012 ps
CPU time 0.97 seconds
Started May 02 02:44:36 PM PDT 24
Finished May 02 02:44:38 PM PDT 24
Peak memory 199316 kb
Host smart-fd160cb0-74c9-46ea-9161-4394f5078768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401500834 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3401500834
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2564552741
Short name T3
Test name
Test status
Simulation time 8560687310 ps
CPU time 449.39 seconds
Started May 02 02:44:32 PM PDT 24
Finished May 02 02:52:02 PM PDT 24
Peak memory 199676 kb
Host smart-498eafb2-511a-4c73-9a7e-0de34a922556
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564552741 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2564552741
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3579143678
Short name T391
Test name
Test status
Simulation time 8725732093 ps
CPU time 103.85 seconds
Started May 02 02:44:31 PM PDT 24
Finished May 02 02:46:16 PM PDT 24
Peak memory 199700 kb
Host smart-ec6ddd8e-d656-41c6-9b0d-281db1e29929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579143678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3579143678
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.4181288414
Short name T59
Test name
Test status
Simulation time 49760602907 ps
CPU time 2393.24 seconds
Started May 02 02:47:55 PM PDT 24
Finished May 02 03:27:50 PM PDT 24
Peak memory 246876 kb
Host smart-155e85b7-d4e3-477f-932b-a0e3ce4d9db5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181288414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.4181288414
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3756799812
Short name T176
Test name
Test status
Simulation time 13505937 ps
CPU time 0.6 seconds
Started May 02 02:44:37 PM PDT 24
Finished May 02 02:44:38 PM PDT 24
Peak memory 194296 kb
Host smart-20eaa361-9944-425c-a598-a9556b824187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756799812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3756799812
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1260857570
Short name T22
Test name
Test status
Simulation time 3437974387 ps
CPU time 30.12 seconds
Started May 02 02:44:38 PM PDT 24
Finished May 02 02:45:09 PM PDT 24
Peak memory 199732 kb
Host smart-97e1f94f-36c5-4960-82ec-e2e009857236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260857570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1260857570
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.457552695
Short name T532
Test name
Test status
Simulation time 1030757999 ps
CPU time 19.84 seconds
Started May 02 02:44:39 PM PDT 24
Finished May 02 02:45:01 PM PDT 24
Peak memory 199636 kb
Host smart-b7da5961-4f2d-435c-ba25-34a3eea94998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457552695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.457552695
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3415216845
Short name T491
Test name
Test status
Simulation time 2128196693 ps
CPU time 122.27 seconds
Started May 02 02:44:39 PM PDT 24
Finished May 02 02:46:43 PM PDT 24
Peak memory 199668 kb
Host smart-7b6af207-e4cb-4a13-895b-ba67638e046f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415216845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3415216845
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3722144091
Short name T6
Test name
Test status
Simulation time 9510918107 ps
CPU time 111.81 seconds
Started May 02 02:44:35 PM PDT 24
Finished May 02 02:46:27 PM PDT 24
Peak memory 199720 kb
Host smart-c8a9f690-6238-42fd-90a7-3c83832d4c73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722144091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3722144091
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3499486682
Short name T402
Test name
Test status
Simulation time 18255219419 ps
CPU time 85.36 seconds
Started May 02 02:44:38 PM PDT 24
Finished May 02 02:46:04 PM PDT 24
Peak memory 199800 kb
Host smart-41bf0254-b5d1-4060-bb87-0ce7ad211b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499486682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3499486682
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.515670901
Short name T488
Test name
Test status
Simulation time 132703395 ps
CPU time 2.22 seconds
Started May 02 02:44:37 PM PDT 24
Finished May 02 02:44:40 PM PDT 24
Peak memory 199660 kb
Host smart-44193b03-0429-4547-b32c-4271e4b33925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515670901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.515670901
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1205894835
Short name T111
Test name
Test status
Simulation time 27111426457 ps
CPU time 121.81 seconds
Started May 02 02:44:36 PM PDT 24
Finished May 02 02:46:39 PM PDT 24
Peak memory 199676 kb
Host smart-2ef4394b-0d5f-40ec-bd4f-e558158223c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205894835 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1205894835
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1663510021
Short name T348
Test name
Test status
Simulation time 45533868 ps
CPU time 0.97 seconds
Started May 02 02:44:40 PM PDT 24
Finished May 02 02:44:42 PM PDT 24
Peak memory 199516 kb
Host smart-fd6cc1db-a038-409d-84ec-22f7db515836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663510021 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1663510021
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.4007889789
Short name T189
Test name
Test status
Simulation time 11957909965 ps
CPU time 484.47 seconds
Started May 02 02:44:40 PM PDT 24
Finished May 02 02:52:46 PM PDT 24
Peak memory 199648 kb
Host smart-beb97919-06df-4c4f-b1aa-a8b898717542
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007889789 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.4007889789
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1113859584
Short name T183
Test name
Test status
Simulation time 6060672778 ps
CPU time 31.2 seconds
Started May 02 02:44:35 PM PDT 24
Finished May 02 02:45:07 PM PDT 24
Peak memory 199708 kb
Host smart-83575224-2fb9-4794-98a9-b72991c775ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113859584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1113859584
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.166016783
Short name T462
Test name
Test status
Simulation time 76581759167 ps
CPU time 362.71 seconds
Started May 02 02:47:56 PM PDT 24
Finished May 02 02:54:00 PM PDT 24
Peak memory 228084 kb
Host smart-e118ebfe-ffe7-4e0e-88e5-de005d2228d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166016783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.166016783
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest
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