Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5616857	1			T1	212		T2	30923		T3	81814
all_values[1]	5616857	1			T1	212		T2	30923		T3	81814
all_values[2]	5616857	1			T1	212		T2	30923		T3	81814

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49161

1

T1

25

T2

5005

T5

2

auto[1]

16801410

1

T1

611

T2

87764

T3

245442

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15596897

1

T1

528

T2

76504

T3

234182

auto[1]

1253674

1

T1

108

T2

16265

T3

11260

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	26370	1			T1	23		T2	3436		T5	2
all_values[0]	auto[0]	auto[1]	181	1			T1	2		T2	9		T14	2
all_values[0]	auto[1]	auto[0]	5574643	1			T1	176		T2	27405		T3	81620
all_values[0]	auto[1]	auto[1]	15663	1			T1	11		T2	73		T3	194
all_values[1]	auto[0]	auto[0]	11506	1			T2	1557		T19	26		T53	7
all_values[1]	auto[0]	auto[1]	96	1			T2	1		T22	4		T18	1
all_values[1]	auto[1]	auto[0]	5605161	1			T1	210		T2	29364		T3	81814
all_values[1]	auto[1]	auto[1]	94	1			T1	2		T2	1		T22	9
all_values[2]	auto[0]	auto[0]	3072	1			T2	1		T8	1		T96	1
all_values[2]	auto[0]	auto[1]	7936	1			T2	1		T8	2		T96	252
all_values[2]	auto[1]	auto[0]	4376145	1			T1	119		T2	14741		T3	70748
all_values[2]	auto[1]	auto[1]	1229704	1			T1	93		T2	16180		T3	11066