Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2851529

1

T1

4572

T2

13568

T3

37177

auto[1]

628995

1

T1

1960

T2

22220

T4

1862

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606210

1

T1

1755

T2

23199

T4

1190

auto[1]

2874314

1

T1

4777

T2

12589

T3

37177

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2541397

1

T1

1386

T2

6378

T3

37177

auto[1]

939127

1

T1

5146

T2

29410

T4

1624

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	2893705	1			T1	861		T2	35274		T3	35083
fifo_depth[1]	119913	1			T1	8		T2	277		T3	1332
fifo_depth[2]	87974	1			T1	15		T2	154		T3	474
fifo_depth[3]	64914	1			T1	9		T2	41		T3	196
fifo_depth[4]	49689	1			T1	15		T2	26		T3	73
fifo_depth[5]	41204	1			T1	15		T2	9		T3	17
fifo_depth[6]	38227	1			T1	27		T2	7		T3	2
fifo_depth[7]	30997	1			T1	19		T4	5		T6	649
fifo_depth[8]	26074	1			T1	31		T4	15		T6	415
fifo_depth[9]	18384	1			T1	99		T4	7		T6	269
fifo_depth[10]	14153	1			T1	65		T4	11		T6	154
fifo_depth[11]	7970	1			T1	23		T4	2		T6	80
fifo_depth[12]	6785	1			T1	84		T6	45		T27	23
fifo_depth[13]	3165	1			T1	110		T5	1		T6	26
fifo_depth[14]	5962	1			T1	339		T5	1		T6	7
fifo_depth[15]	2184	1			T1	311		T6	3		T27	2
fifo_depth[16]	5897	1			T1	364		T5	1		T6	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

595831

1

T1

5849

T2

514

T3

2094

auto[1]

2884693

1

T1

683

T2

35274

T3

35083

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3471512

1

T1

6354

T2

35788

T3

37177

auto[1]

9012

1

T1

178

T5

1

T94

40

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

21340

1

T1

746

T2

51

T4

20

auto[0]

auto[0]

auto[0]

auto[1]

20152

1

T2

104

T5

5

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

377727

1

T2

27

T3

2094

T7

1273

auto[0]

auto[0]

auto[1]

auto[1]

20160

1

T1

472

T2

15

T4

80

auto[0]

auto[1]

auto[0]

auto[0]

39562

1

T1

61

T2

164

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

33627

1

T1

511

T2

65

T4

8

auto[0]

auto[1]

auto[1]

auto[0]

45502

1

T1

3638

T2

39

T4

62

auto[0]

auto[1]

auto[1]

auto[1]

37761

1

T1

421

T2

49

T4

20

auto[1]

auto[0]

auto[0]

auto[0]

43180

1

T1

3

T2

782

T4

101

auto[1]

auto[0]

auto[0]

auto[1]

61220

1

T1

123

T2

2483

T4

14

auto[1]

auto[0]

auto[1]

auto[0]

1939961

1

T1

23

T2

2135

T3

35083

auto[1]

auto[0]

auto[1]

auto[1]

57657

1

T1

19

T2

781

T4

1071

auto[1]

auto[1]

auto[0]

auto[0]

192402

1

T1

92

T2

8734

T4

481

auto[1]

auto[1]

auto[0]

auto[1]

194727

1

T1

219

T2

10816

T4

565

auto[1]

auto[1]

auto[1]

auto[0]

191855

1

T1

9

T2

1636

T4

383

auto[1]

auto[1]

auto[1]

auto[1]

203691

1

T1

195

T2

7907

T4

104

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

62604

1

T1

689

T2

833

T4

121

auto[0]

auto[0]

auto[0]

auto[1]

80569

1

T1

123

T2

2587

T4

14

auto[0]

auto[0]

auto[1]

auto[0]

2316422

1

T1

23

T2

2162

T3

37177

auto[0]

auto[0]

auto[1]

auto[1]

76540

1

T1

491

T2

796

T4

1151

auto[0]

auto[1]

auto[0]

auto[0]

231549

1

T1

153

T2

8898

T4

482

auto[0]

auto[1]

auto[0]

auto[1]

227626

1

T1

724

T2

10881

T4

573

auto[0]

auto[1]

auto[1]

auto[0]

235818

1

T1

3563

T2

1675

T4

445

auto[0]

auto[1]

auto[1]

auto[1]

240384

1

T1

588

T2

7956

T4

124

auto[1]

auto[0]

auto[0]

auto[0]

1916

1

T1

60

T53

163

T22

32

auto[1]

auto[0]

auto[0]

auto[1]

803

1

T110

145

T95

94

T111

3

auto[1]

auto[0]

auto[1]

auto[0]

1266

1

T5

1

T94

32

T39

1

auto[1]

auto[0]

auto[1]

auto[1]

1277

1

T53

44

T22

47

T112

1

auto[1]

auto[1]

auto[0]

auto[0]

415

1

T110

17

T95

4

T113

1

auto[1]

auto[1]

auto[0]

auto[1]

728

1

T1

6

T22

97

T95

2

auto[1]

auto[1]

auto[1]

auto[0]

1539

1

T1

84

T49

1

T110

7

auto[1]

auto[1]

auto[1]

auto[1]

1068

1

T1

28

T94

8

T22

17

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	45096	1			T1	63		T2	782		T4	101
fifo_depth[0]	auto[0]	auto[0]	auto[1]	62023	1			T1	123		T2	2483		T4	14
fifo_depth[0]	auto[0]	auto[1]	auto[0]	1941227	1			T1	23		T2	2135		T3	35083
fifo_depth[0]	auto[0]	auto[1]	auto[1]	58934	1			T1	19		T2	781		T4	1071
fifo_depth[0]	auto[1]	auto[0]	auto[0]	192817	1			T1	92		T2	8734		T4	481
fifo_depth[0]	auto[1]	auto[0]	auto[1]	195455	1			T1	225		T2	10816		T4	565
fifo_depth[0]	auto[1]	auto[1]	auto[0]	193394	1			T1	93		T2	1636		T4	383
fifo_depth[0]	auto[1]	auto[1]	auto[1]	204759	1			T1	223		T2	7907		T4	104
fifo_depth[1]	auto[0]	auto[0]	auto[0]	1040	1			T2	33		T4	3		T20	78
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1440	1			T2	27		T96	2		T20	16
fifo_depth[1]	auto[0]	auto[1]	auto[0]	102296	1			T2	13		T3	1332		T7	934
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1355	1			T1	3		T2	12		T4	19
fifo_depth[1]	auto[1]	auto[0]	auto[0]	3518	1			T2	93		T27	87		T19	6
fifo_depth[1]	auto[1]	auto[0]	auto[1]	3178	1			T1	1		T2	42		T4	1
fifo_depth[1]	auto[1]	auto[1]	auto[0]	3985	1			T1	4		T2	20		T4	2
fifo_depth[1]	auto[1]	auto[1]	auto[1]	3101	1			T2	37		T4	1		T27	50
fifo_depth[2]	auto[0]	auto[0]	auto[0]	984	1			T2	11		T4	2		T20	43
fifo_depth[2]	auto[0]	auto[0]	auto[1]	1251	1			T2	49		T96	1		T20	10
fifo_depth[2]	auto[0]	auto[1]	auto[0]	71057	1			T2	6		T3	474		T7	265
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1306	1			T1	7		T2	3		T4	22
fifo_depth[2]	auto[1]	auto[0]	auto[0]	3403	1			T2	51		T27	93		T20	4
fifo_depth[2]	auto[1]	auto[0]	auto[1]	3073	1			T1	7		T2	15		T4	1
fifo_depth[2]	auto[1]	auto[1]	auto[0]	3882	1			T1	1		T2	8		T4	18
fifo_depth[2]	auto[1]	auto[1]	auto[1]	3018	1			T2	11		T4	2		T27	37
fifo_depth[3]	auto[0]	auto[0]	auto[0]	746	1			T2	5		T4	3		T20	19
fifo_depth[3]	auto[0]	auto[0]	auto[1]	843	1			T2	8		T20	2		T22	4
fifo_depth[3]	auto[0]	auto[1]	auto[0]	49824	1			T2	4		T3	196		T7	62
fifo_depth[3]	auto[0]	auto[1]	auto[1]	1049	1			T1	5		T4	8		T20	2
fifo_depth[3]	auto[1]	auto[0]	auto[0]	3210	1			T1	1		T2	15		T27	86
fifo_depth[3]	auto[1]	auto[0]	auto[1]	2907	1			T1	2		T2	4		T4	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	3478	1			T1	1		T2	4		T4	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	2857	1			T2	1		T27	44		T20	1
fifo_depth[4]	auto[0]	auto[0]	auto[0]	803	1			T2	1		T4	1		T20	14
fifo_depth[4]	auto[0]	auto[0]	auto[1]	823	1			T2	13		T22	4		T110	7
fifo_depth[4]	auto[0]	auto[1]	auto[0]	34313	1			T2	3		T3	73		T7	10
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1217	1			T1	4		T4	14		T53	1
fifo_depth[4]	auto[1]	auto[0]	auto[0]	3157	1			T1	2		T2	3		T27	76
fifo_depth[4]	auto[1]	auto[0]	auto[1]	2841	1			T1	7		T2	2		T27	44
fifo_depth[4]	auto[1]	auto[1]	auto[0]	3504	1			T1	2		T2	4		T4	16
fifo_depth[4]	auto[1]	auto[1]	auto[1]	3031	1			T4	1		T27	43		T32	91
fifo_depth[5]	auto[0]	auto[0]	auto[0]	623	1			T1	1		T2	1		T4	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	667	1			T2	3		T22	4		T110	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	26806	1			T2	1		T3	17		T7	2
fifo_depth[5]	auto[0]	auto[1]	auto[1]	923	1			T1	5		T4	1		T22	2
fifo_depth[5]	auto[1]	auto[0]	auto[0]	3183	1			T2	1		T27	103		T32	126
fifo_depth[5]	auto[1]	auto[0]	auto[1]	2801	1			T1	1		T4	2		T27	52
fifo_depth[5]	auto[1]	auto[1]	auto[0]	3370	1			T1	4		T2	3		T4	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	2831	1			T1	4		T4	1		T27	38
fifo_depth[6]	auto[0]	auto[0]	auto[0]	778	1			T4	2		T20	1		T53	2
fifo_depth[6]	auto[0]	auto[0]	auto[1]	774	1			T2	4		T22	4		T114	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	23065	1			T3	2		T4	5		T6	923
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1152	1			T1	10		T4	9		T22	2
fifo_depth[6]	auto[1]	auto[0]	auto[0]	3222	1			T1	3		T2	1		T4	1
fifo_depth[6]	auto[1]	auto[0]	auto[1]	2849	1			T1	9		T2	2		T27	47
fifo_depth[6]	auto[1]	auto[1]	auto[0]	3404	1			T1	3		T4	15		T115	1
fifo_depth[6]	auto[1]	auto[1]	auto[1]	2983	1			T1	2		T4	6		T27	43
fifo_depth[7]	auto[0]	auto[0]	auto[0]	630	1			T4	2		T22	6		T95	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	566	1			T22	4		T114	1		T116	3
fifo_depth[7]	auto[0]	auto[1]	auto[0]	17878	1			T6	649		T94	5		T36	624
fifo_depth[7]	auto[0]	auto[1]	auto[1]	862	1			T1	11		T4	2		T22	3
fifo_depth[7]	auto[1]	auto[0]	auto[0]	2848	1			T27	84		T32	117		T35	114
fifo_depth[7]	auto[1]	auto[0]	auto[1]	2596	1			T1	4		T4	1		T27	38
fifo_depth[7]	auto[1]	auto[1]	auto[0]	3104	1			T1	4		T115	3		T79	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	2513	1			T27	33		T94	3		T32	92
fifo_depth[8]	auto[0]	auto[0]	auto[0]	697	1			T4	3		T53	2		T22	4
fifo_depth[8]	auto[0]	auto[0]	auto[1]	588	1			T22	4		T110	8		T95	50
fifo_depth[8]	auto[0]	auto[1]	auto[0]	13335	1			T6	415		T94	5		T36	437
fifo_depth[8]	auto[0]	auto[1]	auto[1]	1153	1			T1	10		T4	2		T22	3
fifo_depth[8]	auto[1]	auto[0]	auto[0]	2741	1			T1	1		T27	69		T32	80
fifo_depth[8]	auto[1]	auto[0]	auto[1]	2366	1			T1	14		T4	1		T27	34
fifo_depth[8]	auto[1]	auto[1]	auto[0]	2865	1			T1	4		T4	6		T115	3
fifo_depth[8]	auto[1]	auto[1]	auto[1]	2329	1			T1	2		T4	3		T27	37
fifo_depth[9]	auto[0]	auto[0]	auto[0]	487	1			T4	1		T53	1		T22	17
fifo_depth[9]	auto[0]	auto[0]	auto[1]	509	1			T22	4		T95	54		T111	44
fifo_depth[9]	auto[0]	auto[1]	auto[0]	8955	1			T4	2		T6	269		T94	1
fifo_depth[9]	auto[0]	auto[1]	auto[1]	678	1			T1	39		T4	1		T22	3
fifo_depth[9]	auto[1]	auto[0]	auto[0]	1934	1			T27	55		T32	88		T35	87
fifo_depth[9]	auto[1]	auto[0]	auto[1]	1793	1			T1	10		T4	1		T27	31
fifo_depth[9]	auto[1]	auto[1]	auto[0]	2208	1			T1	39		T115	1		T79	1
fifo_depth[9]	auto[1]	auto[1]	auto[1]	1820	1			T1	11		T4	2		T27	24
fifo_depth[10]	auto[0]	auto[0]	auto[0]	571	1			T53	2		T22	22		T95	11
fifo_depth[10]	auto[0]	auto[0]	auto[1]	437	1			T22	4		T110	6		T95	48
fifo_depth[10]	auto[0]	auto[1]	auto[0]	6103	1			T4	5		T6	154		T94	3
fifo_depth[10]	auto[0]	auto[1]	auto[1]	693	1			T1	38		T4	2		T22	2
fifo_depth[10]	auto[1]	auto[0]	auto[0]	1729	1			T1	1		T27	38		T32	47
fifo_depth[10]	auto[1]	auto[0]	auto[1]	1373	1			T1	20		T27	25		T32	15
fifo_depth[10]	auto[1]	auto[1]	auto[0]	1639	1			T1	1		T4	1		T115	2
fifo_depth[10]	auto[1]	auto[1]	auto[1]	1608	1			T1	5		T4	3		T27	13
fifo_depth[11]	auto[0]	auto[0]	auto[0]	265	1			T4	1		T22	19		T95	1
fifo_depth[11]	auto[0]	auto[0]	auto[1]	266	1			T22	4		T95	61		T111	13
fifo_depth[11]	auto[0]	auto[1]	auto[0]	3405	1			T6	80		T94	10		T36	112
fifo_depth[11]	auto[0]	auto[1]	auto[1]	367	1			T1	8		T22	3		T110	4
fifo_depth[11]	auto[1]	auto[0]	auto[0]	894	1			T27	21		T32	34		T35	39
fifo_depth[11]	auto[1]	auto[0]	auto[1]	785	1			T1	11		T27	14		T79	1
fifo_depth[11]	auto[1]	auto[1]	auto[0]	1032	1			T1	4		T117	1		T118	4
fifo_depth[11]	auto[1]	auto[1]	auto[1]	956	1			T4	1		T27	8		T94	6
fifo_depth[12]	auto[0]	auto[0]	auto[0]	553	1			T1	1		T53	3		T22	149
fifo_depth[12]	auto[0]	auto[0]	auto[1]	360	1			T22	31		T110	6		T95	51
fifo_depth[12]	auto[0]	auto[1]	auto[0]	2144	1			T6	45		T94	6		T36	53
fifo_depth[12]	auto[0]	auto[1]	auto[1]	534	1			T1	8		T22	11		T110	10
fifo_depth[12]	auto[1]	auto[0]	auto[0]	847	1			T1	2		T27	12		T32	15
fifo_depth[12]	auto[1]	auto[0]	auto[1]	608	1			T1	15		T27	8		T32	3
fifo_depth[12]	auto[1]	auto[1]	auto[0]	880	1			T1	53		T115	1		T79	1
fifo_depth[12]	auto[1]	auto[1]	auto[1]	859	1			T1	5		T27	3		T94	78
fifo_depth[13]	auto[0]	auto[0]	auto[0]	212	1			T22	22		T95	8		T111	2
fifo_depth[13]	auto[0]	auto[0]	auto[1]	229	1			T22	3		T110	1		T95	59
fifo_depth[13]	auto[0]	auto[1]	auto[0]	904	1			T6	26		T94	2		T36	18
fifo_depth[13]	auto[0]	auto[1]	auto[1]	180	1			T1	32		T5	1		T22	7
fifo_depth[13]	auto[1]	auto[0]	auto[0]	329	1			T1	2		T27	10		T32	5
fifo_depth[13]	auto[1]	auto[0]	auto[1]	311	1			T1	11		T27	4		T79	1
fifo_depth[13]	auto[1]	auto[1]	auto[0]	546	1			T1	64		T35	25		T119	5
fifo_depth[13]	auto[1]	auto[1]	auto[1]	454	1			T1	1		T27	2		T94	2
fifo_depth[14]	auto[0]	auto[0]	auto[0]	447	1			T53	4		T22	149		T95	21
fifo_depth[14]	auto[0]	auto[0]	auto[1]	575	1			T22	29		T110	8		T95	99
fifo_depth[14]	auto[0]	auto[1]	auto[0]	1298	1			T5	1		T6	7		T94	3
fifo_depth[14]	auto[0]	auto[1]	auto[1]	324	1			T1	8		T53	1		T22	40
fifo_depth[14]	auto[1]	auto[0]	auto[0]	896	1			T1	1		T27	4		T32	8
fifo_depth[14]	auto[1]	auto[0]	auto[1]	615	1			T1	40		T79	1		T35	1
fifo_depth[14]	auto[1]	auto[1]	auto[0]	722	1			T1	284		T35	12		T119	4
fifo_depth[14]	auto[1]	auto[1]	auto[1]	1085	1			T1	6		T27	1		T94	484
fifo_depth[15]	auto[0]	auto[0]	auto[0]	170	1			T22	18		T95	11		T111	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	234	1			T22	2		T49	2		T110	2
fifo_depth[15]	auto[0]	auto[1]	auto[0]	365	1			T6	3		T94	3		T36	2
fifo_depth[15]	auto[0]	auto[1]	auto[1]	190	1			T1	7		T22	47		T110	3
fifo_depth[15]	auto[1]	auto[0]	auto[0]	194	1			T1	2		T27	1		T8	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	190	1			T1	14		T32	1		T120	2
fifo_depth[15]	auto[1]	auto[1]	auto[0]	538	1			T1	288		T35	6		T119	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	303	1			T27	1		T94	2		T32	1
fifo_depth[16]	auto[0]	auto[0]	auto[0]	985	1			T53	3		T22	364		T95	85
fifo_depth[16]	auto[0]	auto[0]	auto[1]	534	1			T22	25		T110	8		T95	45
fifo_depth[16]	auto[0]	auto[1]	auto[0]	906	1			T6	2		T8	1		T94	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	926	1			T1	31		T5	1		T46	1
fifo_depth[16]	auto[1]	auto[0]	auto[0]	671	1			T1	2		T32	2		T35	5
fifo_depth[16]	auto[1]	auto[0]	auto[1]	253	1			T1	38		T120	1		T22	6
fifo_depth[16]	auto[1]	auto[1]	auto[0]	697	1			T1	289		T8	1		T35	3
fifo_depth[16]	auto[1]	auto[1]	auto[1]	925	1			T1	4		T94	62		T32	1