Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5616857	1			T1	212		T2	30923		T3	81814
all_pins[1]	5616857	1			T1	212		T2	30923		T3	81814
all_pins[2]	5616857	1			T1	212		T2	30923		T3	81814

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	15604906	1			T1	530		T2	76514		T3	234182
values[0x1]	1245665	1			T1	106		T2	16255		T3	11260
transitions[0x0=>0x1]	1245602	1			T1	106		T2	16254		T3	11260
transitions[0x1=>0x0]	1245612	1			T1	106		T2	16254		T3	11260

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5600999	1			T1	201		T2	30849		T3	81620
all_pins[0]	values[0x1]	15858	1			T1	11		T2	74		T3	194
all_pins[0]	transitions[0x0=>0x1]	15828	1			T1	11		T2	74		T3	194
all_pins[0]	transitions[0x1=>0x0]	1229684	1			T1	93		T2	16180		T3	11066
all_pins[1]	values[0x0]	5616754	1			T1	210		T2	30922		T3	81814
all_pins[1]	values[0x1]	103	1			T1	2		T2	1		T22	10
all_pins[1]	transitions[0x0=>0x1]	83	1			T1	2		T2	1		T22	9
all_pins[1]	transitions[0x1=>0x0]	15838	1			T1	11		T2	74		T3	194
all_pins[2]	values[0x0]	4387153	1			T1	119		T2	14743		T3	70748
all_pins[2]	values[0x1]	1229704	1			T1	93		T2	16180		T3	11066
all_pins[2]	transitions[0x0=>0x1]	1229691	1			T1	93		T2	16179		T3	11066
all_pins[2]	transitions[0x1=>0x0]	90	1			T1	2		T22	9		T95	2