Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 435 1 T2 7 T22 17 T18 7
all_values[1] 435 1 T2 7 T22 17 T18 7
all_values[2] 435 1 T2 7 T22 17 T18 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 721 1 T2 12 T22 18 T18 11
auto[1] 584 1 T2 9 T22 33 T18 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 493 1 T2 11 T22 15 T18 5
auto[1] 812 1 T2 10 T22 36 T18 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 754 1 T2 15 T22 22 T18 10
auto[1] 551 1 T2 6 T22 29 T18 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 95 1 T2 2 T18 1 T69 4
all_values[0] auto[0] auto[0] auto[1] 43 1 T2 1 T22 2 T69 3
all_values[0] auto[0] auto[1] auto[0] 75 1 T2 2 T22 6 T18 2
all_values[0] auto[0] auto[1] auto[1] 42 1 T18 1 T69 1 T70 1
all_values[0] auto[1] auto[0] auto[1] 99 1 T2 1 T22 4 T18 2
all_values[0] auto[1] auto[1] auto[1] 81 1 T2 1 T22 5 T18 1
all_values[1] auto[0] auto[0] auto[0] 82 1 T2 3 T22 1 T69 7
all_values[1] auto[0] auto[0] auto[1] 48 1 T22 2 T18 1 T69 1
all_values[1] auto[0] auto[1] auto[0] 78 1 T2 1 T22 5 T18 1
all_values[1] auto[0] auto[1] auto[1] 52 1 T2 1 T22 1 T18 2
all_values[1] auto[1] auto[0] auto[1] 101 1 T2 2 T22 4 T18 2
all_values[1] auto[1] auto[1] auto[1] 74 1 T22 4 T18 1 T69 2
all_values[2] auto[0] auto[0] auto[0] 97 1 T2 2 T22 1 T18 1
all_values[2] auto[0] auto[0] auto[1] 39 1 T18 1 T69 2 T71 2
all_values[2] auto[0] auto[1] auto[0] 66 1 T2 1 T22 2 T69 1
all_values[2] auto[0] auto[1] auto[1] 37 1 T2 2 T22 2 T69 3
all_values[2] auto[1] auto[0] auto[1] 117 1 T2 1 T22 4 T18 3
all_values[2] auto[1] auto[1] auto[1] 79 1 T2 1 T22 8 T18 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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