Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.97 95.76 94.01 100.00 65.79 91.67 99.49 69.08


Total test records in report: 594
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T83 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.423257916 May 05 12:20:16 PM PDT 24 May 05 12:20:27 PM PDT 24 406785112 ps
T522 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2329626462 May 05 12:24:11 PM PDT 24 May 05 12:24:16 PM PDT 24 180352086 ps
T523 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3564965333 May 05 12:20:02 PM PDT 24 May 05 12:20:04 PM PDT 24 80792654 ps
T524 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.239122785 May 05 12:24:51 PM PDT 24 May 05 12:24:57 PM PDT 24 132598377 ps
T525 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.607435961 May 05 12:24:05 PM PDT 24 May 05 12:24:09 PM PDT 24 21891446 ps
T100 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.313958447 May 05 12:24:36 PM PDT 24 May 05 12:24:41 PM PDT 24 665131816 ps
T526 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2912021338 May 05 12:20:01 PM PDT 24 May 05 12:20:03 PM PDT 24 54678175 ps
T527 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1943895857 May 05 12:23:49 PM PDT 24 May 05 12:23:51 PM PDT 24 25849267 ps
T84 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4115104975 May 05 12:21:11 PM PDT 24 May 05 12:21:12 PM PDT 24 53706356 ps
T528 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3506046020 May 05 12:21:56 PM PDT 24 May 05 12:21:57 PM PDT 24 35280777 ps
T85 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3355452458 May 05 12:23:47 PM PDT 24 May 05 12:23:48 PM PDT 24 163046487 ps
T529 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2118272390 May 05 12:24:51 PM PDT 24 May 05 12:24:58 PM PDT 24 251714868 ps
T530 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4144672385 May 05 12:24:10 PM PDT 24 May 05 12:24:20 PM PDT 24 114437269 ps
T86 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2572530610 May 05 12:20:08 PM PDT 24 May 05 12:20:09 PM PDT 24 13761671 ps
T531 /workspace/coverage/cover_reg_top/39.hmac_intr_test.623838328 May 05 12:23:48 PM PDT 24 May 05 12:23:50 PM PDT 24 84534396 ps
T532 /workspace/coverage/cover_reg_top/2.hmac_intr_test.714161063 May 05 12:24:24 PM PDT 24 May 05 12:24:26 PM PDT 24 12508743 ps
T533 /workspace/coverage/cover_reg_top/22.hmac_intr_test.767621239 May 05 12:22:28 PM PDT 24 May 05 12:22:29 PM PDT 24 44714888 ps
T534 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1135091314 May 05 12:24:36 PM PDT 24 May 05 12:24:39 PM PDT 24 31146376 ps
T535 /workspace/coverage/cover_reg_top/4.hmac_intr_test.53472988 May 05 12:24:04 PM PDT 24 May 05 12:24:08 PM PDT 24 39844504 ps
T536 /workspace/coverage/cover_reg_top/7.hmac_intr_test.419930276 May 05 12:24:05 PM PDT 24 May 05 12:24:09 PM PDT 24 13468514 ps
T537 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4161750505 May 05 12:24:48 PM PDT 24 May 05 12:24:53 PM PDT 24 866743039 ps
T104 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.484354874 May 05 12:24:32 PM PDT 24 May 05 12:24:35 PM PDT 24 102581413 ps
T538 /workspace/coverage/cover_reg_top/31.hmac_intr_test.177870964 May 05 12:21:23 PM PDT 24 May 05 12:21:24 PM PDT 24 11006339 ps
T539 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1252393834 May 05 12:20:57 PM PDT 24 May 05 12:20:58 PM PDT 24 19965783 ps
T540 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.120835810 May 05 12:23:47 PM PDT 24 May 05 12:23:50 PM PDT 24 63803182 ps
T87 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1159062927 May 05 12:21:06 PM PDT 24 May 05 12:21:07 PM PDT 24 28309879 ps
T541 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2234665941 May 05 12:24:05 PM PDT 24 May 05 12:24:09 PM PDT 24 42393728 ps
T542 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1559581156 May 05 12:24:05 PM PDT 24 May 05 12:24:12 PM PDT 24 160462440 ps
T543 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1037675219 May 05 12:19:46 PM PDT 24 May 05 12:19:48 PM PDT 24 53926906 ps
T544 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4280744703 May 05 12:24:44 PM PDT 24 May 05 12:24:49 PM PDT 24 375361632 ps
T88 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.339345727 May 05 12:20:15 PM PDT 24 May 05 12:20:24 PM PDT 24 517181703 ps
T545 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2162783935 May 05 12:24:51 PM PDT 24 May 05 12:24:57 PM PDT 24 330821356 ps
T546 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1218695237 May 05 12:20:21 PM PDT 24 May 05 12:20:23 PM PDT 24 39517976 ps
T547 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.516512360 May 05 12:20:43 PM PDT 24 May 05 12:20:46 PM PDT 24 43246933 ps
T548 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1884999132 May 05 12:24:34 PM PDT 24 May 05 12:24:37 PM PDT 24 81661028 ps
T549 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2101383102 May 05 12:23:52 PM PDT 24 May 05 12:23:56 PM PDT 24 112907925 ps
T550 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2004561099 May 05 12:24:36 PM PDT 24 May 05 12:24:39 PM PDT 24 61522956 ps
T551 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1278671754 May 05 12:24:48 PM PDT 24 May 05 12:24:50 PM PDT 24 44429227 ps
T106 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2635412363 May 05 12:24:14 PM PDT 24 May 05 12:24:20 PM PDT 24 150981922 ps
T552 /workspace/coverage/cover_reg_top/5.hmac_intr_test.143166682 May 05 12:24:46 PM PDT 24 May 05 12:24:48 PM PDT 24 69589733 ps
T553 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.609096326 May 05 12:21:41 PM PDT 24 May 05 12:21:43 PM PDT 24 147394169 ps
T554 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3338082873 May 05 12:23:49 PM PDT 24 May 05 12:23:50 PM PDT 24 58011871 ps
T555 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2077823811 May 05 12:20:57 PM PDT 24 May 05 12:20:58 PM PDT 24 54457899 ps
T101 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1730502794 May 05 12:19:49 PM PDT 24 May 05 12:19:53 PM PDT 24 1009220952 ps
T102 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3185972616 May 05 12:22:31 PM PDT 24 May 05 12:22:34 PM PDT 24 402213277 ps
T556 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3160704481 May 05 12:19:54 PM PDT 24 May 05 12:19:57 PM PDT 24 1751018477 ps
T557 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.291255728 May 05 12:24:04 PM PDT 24 May 05 12:24:10 PM PDT 24 649515199 ps
T90 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2216975275 May 05 12:24:10 PM PDT 24 May 05 12:24:25 PM PDT 24 4022932875 ps
T558 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1028725503 May 05 12:24:02 PM PDT 24 May 05 12:24:07 PM PDT 24 519757467 ps
T559 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3039733439 May 05 12:22:01 PM PDT 24 May 05 12:22:04 PM PDT 24 45985073 ps
T560 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2379168940 May 05 12:24:04 PM PDT 24 May 05 12:24:08 PM PDT 24 65038653 ps
T91 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2114084024 May 05 12:19:59 PM PDT 24 May 05 12:20:06 PM PDT 24 1229056666 ps
T561 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3873970935 May 05 12:23:48 PM PDT 24 May 05 12:23:50 PM PDT 24 11647747 ps
T562 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.620895625 May 05 12:21:37 PM PDT 24 May 05 12:21:38 PM PDT 24 44289961 ps
T563 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2996749212 May 05 12:21:41 PM PDT 24 May 05 12:21:43 PM PDT 24 12067524 ps
T92 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2557880280 May 05 12:24:04 PM PDT 24 May 05 12:24:09 PM PDT 24 76535323 ps
T564 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3519378406 May 05 12:20:00 PM PDT 24 May 05 12:20:02 PM PDT 24 192153012 ps
T565 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4109079341 May 05 12:20:09 PM PDT 24 May 05 12:20:12 PM PDT 24 797549696 ps
T566 /workspace/coverage/cover_reg_top/8.hmac_intr_test.58919986 May 05 12:24:40 PM PDT 24 May 05 12:24:42 PM PDT 24 71692854 ps
T105 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3553392695 May 05 12:22:10 PM PDT 24 May 05 12:22:13 PM PDT 24 348771734 ps
T567 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2313241710 May 05 12:19:42 PM PDT 24 May 05 12:19:43 PM PDT 24 57105092 ps
T568 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1483260340 May 05 12:24:36 PM PDT 24 May 05 12:24:39 PM PDT 24 113115831 ps
T569 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2963359064 May 05 12:21:24 PM PDT 24 May 05 12:21:26 PM PDT 24 18935507 ps
T570 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1162392575 May 05 12:20:01 PM PDT 24 May 05 12:20:04 PM PDT 24 93639280 ps
T571 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1061767608 May 05 12:20:42 PM PDT 24 May 05 12:20:44 PM PDT 24 161630878 ps
T107 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2994902190 May 05 12:22:03 PM PDT 24 May 05 12:22:06 PM PDT 24 196934145 ps
T572 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1553420436 May 05 12:24:32 PM PDT 24 May 05 12:24:34 PM PDT 24 109009070 ps
T573 /workspace/coverage/cover_reg_top/23.hmac_intr_test.563423866 May 05 12:24:20 PM PDT 24 May 05 12:24:21 PM PDT 24 18084623 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4226938974 May 05 12:24:39 PM PDT 24 May 05 12:24:42 PM PDT 24 57127693 ps
T575 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3475411277 May 05 12:19:39 PM PDT 24 May 05 12:19:40 PM PDT 24 32073368 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4217708767 May 05 12:24:06 PM PDT 24 May 05 12:24:14 PM PDT 24 555495304 ps
T576 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1451706507 May 05 12:23:56 PM PDT 24 May 05 12:23:59 PM PDT 24 106811486 ps
T577 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2986633305 May 05 12:24:05 PM PDT 24 May 05 12:24:11 PM PDT 24 174487099 ps
T93 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1766765636 May 05 12:24:15 PM PDT 24 May 05 12:24:20 PM PDT 24 108829614 ps
T578 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.812967335 May 05 12:24:04 PM PDT 24 May 05 12:24:08 PM PDT 24 392906646 ps
T579 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2501611267 May 05 12:24:40 PM PDT 24 May 05 12:24:42 PM PDT 24 30008547 ps
T580 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1417527547 May 05 12:24:50 PM PDT 24 May 05 12:24:54 PM PDT 24 15776902 ps
T581 /workspace/coverage/cover_reg_top/12.hmac_intr_test.496737844 May 05 12:21:06 PM PDT 24 May 05 12:21:07 PM PDT 24 10755187 ps
T582 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3656810398 May 05 12:24:28 PM PDT 24 May 05 12:24:31 PM PDT 24 79428761 ps
T583 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.935495350 May 05 12:24:46 PM PDT 24 May 05 12:24:49 PM PDT 24 214088129 ps
T108 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2304664063 May 05 12:24:00 PM PDT 24 May 05 12:24:04 PM PDT 24 1442305453 ps
T584 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.18826049 May 05 12:21:22 PM PDT 24 May 05 12:22:11 PM PDT 24 13365870509 ps
T585 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2915330338 May 05 12:19:46 PM PDT 24 May 05 12:19:47 PM PDT 24 18313631 ps
T586 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.111740787 May 05 12:24:32 PM PDT 24 May 05 12:24:34 PM PDT 24 24822152 ps
T587 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1456162920 May 05 12:24:39 PM PDT 24 May 05 12:24:41 PM PDT 24 45694635 ps
T103 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2759600425 May 05 12:24:34 PM PDT 24 May 05 12:24:38 PM PDT 24 175608591 ps
T588 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3924466216 May 05 12:23:53 PM PDT 24 May 05 12:23:55 PM PDT 24 61841652 ps
T589 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1889228038 May 05 12:19:57 PM PDT 24 May 05 12:20:01 PM PDT 24 245384664 ps
T590 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3250506794 May 05 12:24:06 PM PDT 24 May 05 12:24:17 PM PDT 24 396597516 ps
T591 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.331384864 May 05 12:20:46 PM PDT 24 May 05 12:20:48 PM PDT 24 174665450 ps
T592 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1188710949 May 05 12:23:51 PM PDT 24 May 05 12:23:54 PM PDT 24 16233411 ps
T593 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1917638968 May 05 12:24:13 PM PDT 24 May 05 12:24:18 PM PDT 24 145427321 ps
T594 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3593901960 May 05 12:24:36 PM PDT 24 May 05 12:24:43 PM PDT 24 299949758 ps
T98 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.51020793 May 05 12:24:44 PM PDT 24 May 05 12:24:47 PM PDT 24 830963167 ps

Test location /workspace/coverage/default/44.hmac_burst_wr.708414645
Short name T1
Test name
Test status
Simulation time 1878104736 ps
CPU time 23.01 seconds
Started May 05 12:24:27 PM PDT 24
Finished May 05 12:24:51 PM PDT 24
Peak memory 199716 kb
Host smart-97c07c18-93fa-4435-a53f-8ff3bb489cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708414645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.708414645
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.3603261533
Short name T22
Test name
Test status
Simulation time 83085633947 ps
CPU time 949.71 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:40:35 PM PDT 24
Peak memory 241236 kb
Host smart-004f441a-4889-4336-8b6c-b623f431eef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603261533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.3603261533
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_stress_all.4291419885
Short name T2
Test name
Test status
Simulation time 80436015579 ps
CPU time 266.47 seconds
Started May 05 12:24:37 PM PDT 24
Finished May 05 12:29:05 PM PDT 24
Peak memory 199836 kb
Host smart-62222f6e-aef1-4937-b716-2a0958f8bc62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291419885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.4291419885
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3603909544
Short name T21
Test name
Test status
Simulation time 33562191 ps
CPU time 0.82 seconds
Started May 05 12:21:41 PM PDT 24
Finished May 05 12:21:43 PM PDT 24
Peak memory 218108 kb
Host smart-1df1e6ed-02f6-4953-82c0-83f524b1be12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603909544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3603909544
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2167497406
Short name T50
Test name
Test status
Simulation time 1025327046 ps
CPU time 4.3 seconds
Started May 05 12:20:56 PM PDT 24
Finished May 05 12:21:01 PM PDT 24
Peak memory 199808 kb
Host smart-17404b15-ed2b-48eb-9115-0773dc885e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167497406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2167497406
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.1395248996
Short name T18
Test name
Test status
Simulation time 15648458495 ps
CPU time 267.7 seconds
Started May 05 12:25:10 PM PDT 24
Finished May 05 12:29:44 PM PDT 24
Peak memory 249152 kb
Host smart-ed11dc11-d402-49a8-973a-a54fa7b0a97f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395248996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.1395248996
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3793786940
Short name T74
Test name
Test status
Simulation time 676944338 ps
CPU time 3.27 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:18 PM PDT 24
Peak memory 199292 kb
Host smart-854cc859-3351-4903-8a8b-4e9e1e8da4b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793786940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3793786940
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2679457743
Short name T270
Test name
Test status
Simulation time 9278568744 ps
CPU time 479.05 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:32:09 PM PDT 24
Peak memory 233500 kb
Host smart-42fd71b7-b337-4c92-aa47-df7a17870e49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679457743 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2679457743
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1263694029
Short name T123
Test name
Test status
Simulation time 38608080 ps
CPU time 0.57 seconds
Started May 05 12:20:14 PM PDT 24
Finished May 05 12:20:15 PM PDT 24
Peak memory 195520 kb
Host smart-862c38a2-a805-4935-b4e2-1710b230b5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263694029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1263694029
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.4141234870
Short name T126
Test name
Test status
Simulation time 28815239979 ps
CPU time 470.66 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:32:01 PM PDT 24
Peak memory 198776 kb
Host smart-b211412b-16cb-4bcf-a227-e25e5716551f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141234870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.4141234870
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.245378523
Short name T32
Test name
Test status
Simulation time 1487719490 ps
CPU time 76.27 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:25:28 PM PDT 24
Peak memory 197776 kb
Host smart-c1fe3266-6776-4ce3-aa75-d7e2e739daea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245378523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.245378523
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3185972616
Short name T102
Test name
Test status
Simulation time 402213277 ps
CPU time 2.75 seconds
Started May 05 12:22:31 PM PDT 24
Finished May 05 12:22:34 PM PDT 24
Peak memory 199908 kb
Host smart-18fb19dc-9f94-4363-8417-6f5ef996a4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185972616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3185972616
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1236935692
Short name T99
Test name
Test status
Simulation time 139293630 ps
CPU time 3.88 seconds
Started May 05 12:19:59 PM PDT 24
Finished May 05 12:20:04 PM PDT 24
Peak memory 199808 kb
Host smart-8cc1d5f4-2103-4da8-b1f9-11fbd4b314ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236935692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1236935692
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3886305156
Short name T29
Test name
Test status
Simulation time 82376883 ps
CPU time 0.98 seconds
Started May 05 12:20:42 PM PDT 24
Finished May 05 12:20:44 PM PDT 24
Peak memory 219024 kb
Host smart-e2ce30b2-2353-41b0-a79a-daae97217d7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886305156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3886305156
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2103173967
Short name T350
Test name
Test status
Simulation time 1945014123 ps
CPU time 13.62 seconds
Started May 05 12:21:41 PM PDT 24
Finished May 05 12:21:56 PM PDT 24
Peak memory 199840 kb
Host smart-fef3802e-82d2-46ab-9649-4ed915cdc6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103173967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2103173967
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_error.2838562444
Short name T10
Test name
Test status
Simulation time 29519627221 ps
CPU time 112.82 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:25:46 PM PDT 24
Peak memory 198108 kb
Host smart-b5e61125-c62a-4896-a248-14d2cbcec51d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838562444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2838562444
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3380959244
Short name T59
Test name
Test status
Simulation time 91219249 ps
CPU time 1.89 seconds
Started May 05 12:20:41 PM PDT 24
Finished May 05 12:20:43 PM PDT 24
Peak memory 199888 kb
Host smart-3f87fa0b-c6e0-44b5-aba5-9cafdc67bd24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380959244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3380959244
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2451535465
Short name T489
Test name
Test status
Simulation time 159382986 ps
CPU time 3.42 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 197916 kb
Host smart-297e4add-619a-41ae-b08c-75f9c275e16d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451535465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2451535465
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.423257916
Short name T83
Test name
Test status
Simulation time 406785112 ps
CPU time 9.49 seconds
Started May 05 12:20:16 PM PDT 24
Finished May 05 12:20:27 PM PDT 24
Peak memory 198568 kb
Host smart-abec3e93-27dc-42d2-8f4a-70c5b25f8357
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423257916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.423257916
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2557880280
Short name T92
Test name
Test status
Simulation time 76535323 ps
CPU time 1.01 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 199352 kb
Host smart-80f2650d-d910-4a0b-babc-33ebd8bfb221
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557880280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2557880280
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.940917502
Short name T504
Test name
Test status
Simulation time 55138875 ps
CPU time 3.27 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 213416 kb
Host smart-c3651f8e-0007-4385-8309-cf36d02b27bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940917502 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.940917502
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3564965333
Short name T523
Test name
Test status
Simulation time 80792654 ps
CPU time 0.72 seconds
Started May 05 12:20:02 PM PDT 24
Finished May 05 12:20:04 PM PDT 24
Peak memory 197296 kb
Host smart-30de4729-7cfd-48af-bc90-7e4caa8659d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564965333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3564965333
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2154259030
Short name T482
Test name
Test status
Simulation time 13937896 ps
CPU time 0.64 seconds
Started May 05 12:21:54 PM PDT 24
Finished May 05 12:21:55 PM PDT 24
Peak memory 194808 kb
Host smart-f980fe1a-5b4f-42eb-8943-47aeb490a88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154259030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2154259030
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.812967335
Short name T578
Test name
Test status
Simulation time 392906646 ps
CPU time 1.81 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 198808 kb
Host smart-e298cbc5-9f1f-4037-80d2-3045296b0cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812967335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.812967335
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3160704481
Short name T556
Test name
Test status
Simulation time 1751018477 ps
CPU time 2.9 seconds
Started May 05 12:19:54 PM PDT 24
Finished May 05 12:19:57 PM PDT 24
Peak memory 200184 kb
Host smart-c949e595-c961-46eb-8a1b-c2ad69d92666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160704481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3160704481
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2759600425
Short name T103
Test name
Test status
Simulation time 175608591 ps
CPU time 1.88 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:24:38 PM PDT 24
Peak memory 198972 kb
Host smart-126f6829-57dd-4e0a-973f-e85e6ae1411b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759600425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2759600425
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3194717986
Short name T493
Test name
Test status
Simulation time 1095821159 ps
CPU time 13.3 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:24:07 PM PDT 24
Peak memory 198484 kb
Host smart-ce118b3d-358c-4bb2-8426-718cdf09a427
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194717986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3194717986
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1188710949
Short name T592
Test name
Test status
Simulation time 16233411 ps
CPU time 0.75 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 196160 kb
Host smart-b295f57c-427c-4b14-b180-658cba99dd46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188710949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1188710949
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1815994618
Short name T76
Test name
Test status
Simulation time 229571257 ps
CPU time 1.85 seconds
Started May 05 12:19:55 PM PDT 24
Finished May 05 12:19:57 PM PDT 24
Peak memory 200220 kb
Host smart-adb28f2d-f6ed-4808-8d34-1f757d870dc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815994618 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1815994618
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3924466216
Short name T588
Test name
Test status
Simulation time 61841652 ps
CPU time 0.67 seconds
Started May 05 12:23:53 PM PDT 24
Finished May 05 12:23:55 PM PDT 24
Peak memory 196996 kb
Host smart-b2ec5f25-833f-4e32-9004-f90475913ce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924466216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3924466216
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4156644060
Short name T484
Test name
Test status
Simulation time 27662717 ps
CPU time 0.61 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 194460 kb
Host smart-7dbd0ede-5f5c-4b9b-9fc6-745260f14b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156644060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4156644060
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4226938974
Short name T574
Test name
Test status
Simulation time 57127693 ps
CPU time 1.14 seconds
Started May 05 12:24:39 PM PDT 24
Finished May 05 12:24:42 PM PDT 24
Peak memory 199368 kb
Host smart-44556f23-6292-4531-80fe-a986fdb22871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226938974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4226938974
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3661661980
Short name T51
Test name
Test status
Simulation time 35851381 ps
CPU time 1.68 seconds
Started May 05 12:22:18 PM PDT 24
Finished May 05 12:22:20 PM PDT 24
Peak memory 199904 kb
Host smart-e5349e51-0401-4878-9955-8186e9a3a37d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661661980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3661661980
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4217708767
Short name T97
Test name
Test status
Simulation time 555495304 ps
CPU time 3.01 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:14 PM PDT 24
Peak memory 199600 kb
Host smart-d396cf05-7c76-41d1-a8c0-15534f306870
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217708767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4217708767
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1087984503
Short name T502
Test name
Test status
Simulation time 174173245772 ps
CPU time 1706.53 seconds
Started May 05 12:21:57 PM PDT 24
Finished May 05 12:50:24 PM PDT 24
Peak memory 233800 kb
Host smart-faa4d041-6f5c-45f2-8c61-26cba9950bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087984503 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1087984503
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2719567604
Short name T488
Test name
Test status
Simulation time 17536302 ps
CPU time 0.77 seconds
Started May 05 12:19:39 PM PDT 24
Finished May 05 12:19:40 PM PDT 24
Peak memory 197688 kb
Host smart-0e37dc28-c52c-41a1-9ec9-8e50f37a76bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719567604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2719567604
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2500033370
Short name T505
Test name
Test status
Simulation time 18478388 ps
CPU time 0.56 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:34 PM PDT 24
Peak memory 194612 kb
Host smart-9c465b41-2a2c-4cfe-9adf-1fa7084d314c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500033370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2500033370
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.793739289
Short name T492
Test name
Test status
Simulation time 118681743 ps
CPU time 1.63 seconds
Started May 05 12:20:56 PM PDT 24
Finished May 05 12:20:58 PM PDT 24
Peak memory 199432 kb
Host smart-ae5c32ce-1620-4cae-9890-ba0510e147cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793739289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.793739289
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2459201884
Short name T56
Test name
Test status
Simulation time 213248464 ps
CPU time 2.18 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:36 PM PDT 24
Peak memory 199880 kb
Host smart-104d7a3e-07df-4e48-8212-d7f2f742cdda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459201884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2459201884
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4102320801
Short name T23
Test name
Test status
Simulation time 399821031 ps
CPU time 1.85 seconds
Started May 05 12:24:16 PM PDT 24
Finished May 05 12:24:21 PM PDT 24
Peak memory 199696 kb
Host smart-495b2780-4284-4a51-b6eb-81abb714be73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102320801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4102320801
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3039733439
Short name T559
Test name
Test status
Simulation time 45985073 ps
CPU time 3.01 seconds
Started May 05 12:22:01 PM PDT 24
Finished May 05 12:22:04 PM PDT 24
Peak memory 199996 kb
Host smart-3395d499-e2df-430d-9c28-fce571179142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039733439 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3039733439
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1766765636
Short name T93
Test name
Test status
Simulation time 108829614 ps
CPU time 0.95 seconds
Started May 05 12:24:15 PM PDT 24
Finished May 05 12:24:20 PM PDT 24
Peak memory 198408 kb
Host smart-cda428f3-a722-4c2b-b457-6cba6ce5f813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766765636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1766765636
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1163613032
Short name T485
Test name
Test status
Simulation time 23222499 ps
CPU time 0.63 seconds
Started May 05 12:19:48 PM PDT 24
Finished May 05 12:19:49 PM PDT 24
Peak memory 194456 kb
Host smart-9ac5fc8c-bbd2-48d2-8b2e-92a05b0c6bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163613032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1163613032
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.516512360
Short name T547
Test name
Test status
Simulation time 43246933 ps
CPU time 1.93 seconds
Started May 05 12:20:43 PM PDT 24
Finished May 05 12:20:46 PM PDT 24
Peak memory 199872 kb
Host smart-e7bfc58e-15c6-4f49-a73f-9f5a80c6bdd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516512360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.516512360
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4280744703
Short name T544
Test name
Test status
Simulation time 375361632 ps
CPU time 3.76 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:24:49 PM PDT 24
Peak memory 199776 kb
Host smart-e6142314-06ea-46ef-bd76-53313d6efe07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280744703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4280744703
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2994902190
Short name T107
Test name
Test status
Simulation time 196934145 ps
CPU time 1.96 seconds
Started May 05 12:22:03 PM PDT 24
Finished May 05 12:22:06 PM PDT 24
Peak memory 200124 kb
Host smart-467be14c-395c-4930-acb3-a5ec3ea0d922
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994902190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2994902190
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1278671754
Short name T551
Test name
Test status
Simulation time 44429227 ps
CPU time 1.2 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:50 PM PDT 24
Peak memory 199616 kb
Host smart-4186a882-cfe2-49c8-a856-c1a346cf9fe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278671754 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1278671754
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.111740787
Short name T586
Test name
Test status
Simulation time 24822152 ps
CPU time 0.8 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:34 PM PDT 24
Peak memory 199020 kb
Host smart-2e37e2a9-c5a5-47f1-8408-438a1f71cb98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111740787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.111740787
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.496737844
Short name T581
Test name
Test status
Simulation time 10755187 ps
CPU time 0.57 seconds
Started May 05 12:21:06 PM PDT 24
Finished May 05 12:21:07 PM PDT 24
Peak memory 194492 kb
Host smart-da25ee0c-c678-4daf-a6d1-ee7c7233cda7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496737844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.496737844
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3468350213
Short name T500
Test name
Test status
Simulation time 302950043 ps
CPU time 1.11 seconds
Started May 05 12:21:23 PM PDT 24
Finished May 05 12:21:25 PM PDT 24
Peak memory 200072 kb
Host smart-4134bd28-3edb-44d9-b8a4-a2245a86f2d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468350213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3468350213
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.601764258
Short name T54
Test name
Test status
Simulation time 69765205 ps
CPU time 1.66 seconds
Started May 05 12:24:43 PM PDT 24
Finished May 05 12:24:46 PM PDT 24
Peak memory 199848 kb
Host smart-b307e513-597e-46f7-bd77-34d4987159ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601764258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.601764258
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.51020793
Short name T98
Test name
Test status
Simulation time 830963167 ps
CPU time 2.87 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:24:47 PM PDT 24
Peak memory 199736 kb
Host smart-eb3aea8f-77bf-42b1-a9d2-e6e74b3d472e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51020793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.51020793
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3631848831
Short name T520
Test name
Test status
Simulation time 168969791709 ps
CPU time 774.75 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:37:28 PM PDT 24
Peak memory 211524 kb
Host smart-0e662f1a-203f-4332-8795-749f57e1c0a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631848831 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3631848831
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1553420436
Short name T572
Test name
Test status
Simulation time 109009070 ps
CPU time 0.68 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:34 PM PDT 24
Peak memory 197364 kb
Host smart-2d547ece-0b81-4a89-b963-cb218d4b8bc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553420436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1553420436
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1456162920
Short name T587
Test name
Test status
Simulation time 45694635 ps
CPU time 0.54 seconds
Started May 05 12:24:39 PM PDT 24
Finished May 05 12:24:41 PM PDT 24
Peak memory 194356 kb
Host smart-7bbb1e07-3389-4938-b1bc-fe2bed4e51df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456162920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1456162920
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3631380728
Short name T57
Test name
Test status
Simulation time 87990265 ps
CPU time 1.09 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:24:48 PM PDT 24
Peak memory 199244 kb
Host smart-c2d682b6-7700-405e-a844-3d7dab8f004a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631380728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3631380728
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1162392575
Short name T570
Test name
Test status
Simulation time 93639280 ps
CPU time 2.44 seconds
Started May 05 12:20:01 PM PDT 24
Finished May 05 12:20:04 PM PDT 24
Peak memory 199744 kb
Host smart-0ab801e1-23b2-4d9f-ab61-808242538eed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162392575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1162392575
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.855740274
Short name T501
Test name
Test status
Simulation time 238634392857 ps
CPU time 749.75 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:37:02 PM PDT 24
Peak memory 216312 kb
Host smart-8c3f93e9-2de4-425a-a47b-f21600e60406
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855740274 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.855740274
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4115104975
Short name T84
Test name
Test status
Simulation time 53706356 ps
CPU time 0.8 seconds
Started May 05 12:21:11 PM PDT 24
Finished May 05 12:21:12 PM PDT 24
Peak memory 199500 kb
Host smart-c4de0345-7a43-4ab3-8c31-a9221b768d96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115104975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4115104975
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2501611267
Short name T579
Test name
Test status
Simulation time 30008547 ps
CPU time 0.58 seconds
Started May 05 12:24:40 PM PDT 24
Finished May 05 12:24:42 PM PDT 24
Peak memory 194364 kb
Host smart-98fa2b85-9aa3-4531-bb00-7bb5dbec8167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501611267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2501611267
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.935495350
Short name T583
Test name
Test status
Simulation time 214088129 ps
CPU time 1.11 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:24:49 PM PDT 24
Peak memory 199028 kb
Host smart-83864462-1d9a-43ae-a4b3-198d76addbbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935495350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.935495350
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4161750505
Short name T537
Test name
Test status
Simulation time 866743039 ps
CPU time 3.45 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:53 PM PDT 24
Peak memory 199812 kb
Host smart-fd2b503a-fcd7-41f2-bb7d-1929698b1103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161750505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4161750505
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.484354874
Short name T104
Test name
Test status
Simulation time 102581413 ps
CPU time 1.57 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:35 PM PDT 24
Peak memory 199796 kb
Host smart-13ffca11-b8e9-4058-a5c7-f51c5b0862f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484354874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.484354874
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2162783935
Short name T545
Test name
Test status
Simulation time 330821356 ps
CPU time 2.34 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:57 PM PDT 24
Peak memory 199704 kb
Host smart-81d3795f-bb48-4360-a324-96477cab5e82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162783935 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2162783935
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3325657897
Short name T89
Test name
Test status
Simulation time 25755991 ps
CPU time 0.81 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:20:11 PM PDT 24
Peak memory 198796 kb
Host smart-7ce9c6e0-c35a-4771-b539-2b32a7e43e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325657897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3325657897
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2156404070
Short name T497
Test name
Test status
Simulation time 17400957 ps
CPU time 0.63 seconds
Started May 05 12:19:47 PM PDT 24
Finished May 05 12:19:48 PM PDT 24
Peak memory 194456 kb
Host smart-88bfd86c-fc1b-4f3a-a8b8-ca710655f232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156404070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2156404070
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.331384864
Short name T591
Test name
Test status
Simulation time 174665450 ps
CPU time 2.18 seconds
Started May 05 12:20:46 PM PDT 24
Finished May 05 12:20:48 PM PDT 24
Peak memory 199756 kb
Host smart-21d5f4f0-3ef1-4d60-870d-3ca8cd3d9c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331384864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.331384864
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2490186271
Short name T519
Test name
Test status
Simulation time 287295641 ps
CPU time 3.83 seconds
Started May 05 12:21:11 PM PDT 24
Finished May 05 12:21:15 PM PDT 24
Peak memory 199892 kb
Host smart-02604c81-4e65-4f68-9159-42b20554c406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490186271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2490186271
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1730502794
Short name T101
Test name
Test status
Simulation time 1009220952 ps
CPU time 4.06 seconds
Started May 05 12:19:49 PM PDT 24
Finished May 05 12:19:53 PM PDT 24
Peak memory 199824 kb
Host smart-03e8a6ce-578e-4a59-8e1e-33ee864fcab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730502794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1730502794
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1884999132
Short name T548
Test name
Test status
Simulation time 81661028 ps
CPU time 1.26 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:24:37 PM PDT 24
Peak memory 198144 kb
Host smart-ce143f9b-ef71-4144-890c-129c7382c7ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884999132 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1884999132
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1483260340
Short name T568
Test name
Test status
Simulation time 113115831 ps
CPU time 0.96 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 197464 kb
Host smart-e67024b4-8952-4df2-83aa-d97836b58829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483260340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1483260340
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1135091314
Short name T534
Test name
Test status
Simulation time 31146376 ps
CPU time 0.64 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 192336 kb
Host smart-1ff06781-4c51-4e63-8f6f-5a08009747be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135091314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1135091314
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1218695237
Short name T546
Test name
Test status
Simulation time 39517976 ps
CPU time 1.11 seconds
Started May 05 12:20:21 PM PDT 24
Finished May 05 12:20:23 PM PDT 24
Peak memory 199844 kb
Host smart-b43b6750-6205-4166-9187-7f5e0e0b4312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218695237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1218695237
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2118272390
Short name T529
Test name
Test status
Simulation time 251714868 ps
CPU time 2.98 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:58 PM PDT 24
Peak memory 199796 kb
Host smart-a28f2a82-c616-4dec-9e6f-35f6921f6098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118272390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2118272390
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.313958447
Short name T100
Test name
Test status
Simulation time 665131816 ps
CPU time 2.94 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:41 PM PDT 24
Peak memory 197596 kb
Host smart-8e404cac-0079-4243-965b-563cf7bd0f65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313958447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.313958447
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.18826049
Short name T584
Test name
Test status
Simulation time 13365870509 ps
CPU time 48.2 seconds
Started May 05 12:21:22 PM PDT 24
Finished May 05 12:22:11 PM PDT 24
Peak memory 216396 kb
Host smart-c2e1653f-8ef8-4298-8460-89b4b296b746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18826049 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.18826049
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1917638968
Short name T593
Test name
Test status
Simulation time 145427321 ps
CPU time 0.9 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:18 PM PDT 24
Peak memory 197704 kb
Host smart-260f113c-d77b-4971-9295-fb1d364e9c31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917638968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1917638968
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1811220307
Short name T73
Test name
Test status
Simulation time 16586075 ps
CPU time 0.64 seconds
Started May 05 12:21:26 PM PDT 24
Finished May 05 12:21:27 PM PDT 24
Peak memory 194484 kb
Host smart-8cebe17e-45d2-44fb-985b-81227406a223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811220307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1811220307
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.291255728
Short name T557
Test name
Test status
Simulation time 649515199 ps
CPU time 2.26 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 197424 kb
Host smart-a23dbed5-574c-41a0-a37e-ac8ebdac42be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291255728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.291255728
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3593901960
Short name T594
Test name
Test status
Simulation time 299949758 ps
CPU time 4.93 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:43 PM PDT 24
Peak memory 197796 kb
Host smart-c24ba410-6f20-4adb-bd20-76b464f7fe7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593901960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3593901960
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2635412363
Short name T106
Test name
Test status
Simulation time 150981922 ps
CPU time 1.88 seconds
Started May 05 12:24:14 PM PDT 24
Finished May 05 12:24:20 PM PDT 24
Peak memory 199588 kb
Host smart-28bcceb7-2ad6-446c-84a6-58b825db2427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635412363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2635412363
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2885421052
Short name T510
Test name
Test status
Simulation time 88066997935 ps
CPU time 814.93 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:37:39 PM PDT 24
Peak memory 223424 kb
Host smart-1c2edabd-bf6d-4d16-b21e-cc10536bf563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885421052 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2885421052
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2963359064
Short name T569
Test name
Test status
Simulation time 18935507 ps
CPU time 0.8 seconds
Started May 05 12:21:24 PM PDT 24
Finished May 05 12:21:26 PM PDT 24
Peak memory 197048 kb
Host smart-9b26959f-a1fb-4181-beae-373d7dcbc2a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963359064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2963359064
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3564952841
Short name T515
Test name
Test status
Simulation time 47965564 ps
CPU time 0.68 seconds
Started May 05 12:21:11 PM PDT 24
Finished May 05 12:21:12 PM PDT 24
Peak memory 194520 kb
Host smart-1f517610-e284-4a9d-8e87-3f1948475dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564952841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3564952841
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2003751025
Short name T58
Test name
Test status
Simulation time 185954711 ps
CPU time 2.1 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 199784 kb
Host smart-35863237-95a5-4b6b-9465-113001800484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003751025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2003751025
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.372899696
Short name T511
Test name
Test status
Simulation time 1315042196 ps
CPU time 1.87 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:19 PM PDT 24
Peak memory 199556 kb
Host smart-5865ac07-53cc-4da4-8321-0d967558e4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372899696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.372899696
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1821479243
Short name T514
Test name
Test status
Simulation time 48607076 ps
CPU time 2.84 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 199544 kb
Host smart-8d18baf3-2c8d-44bd-9582-c097b1d196dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821479243 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1821479243
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1841019217
Short name T80
Test name
Test status
Simulation time 31774461 ps
CPU time 0.97 seconds
Started May 05 12:21:42 PM PDT 24
Finished May 05 12:21:44 PM PDT 24
Peak memory 199300 kb
Host smart-9c85dd11-55e6-4c79-a17d-3abd2dfebf0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841019217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1841019217
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2077823811
Short name T555
Test name
Test status
Simulation time 54457899 ps
CPU time 0.64 seconds
Started May 05 12:20:57 PM PDT 24
Finished May 05 12:20:58 PM PDT 24
Peak memory 194516 kb
Host smart-378d336c-b968-4df3-b02c-60c9982ab4cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077823811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2077823811
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.644770453
Short name T481
Test name
Test status
Simulation time 121491025 ps
CPU time 1.56 seconds
Started May 05 12:20:46 PM PDT 24
Finished May 05 12:20:48 PM PDT 24
Peak memory 199516 kb
Host smart-fceb44e5-d070-48a4-9bb5-efe7843b0d2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644770453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.644770453
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1028725503
Short name T558
Test name
Test status
Simulation time 519757467 ps
CPU time 2.97 seconds
Started May 05 12:24:02 PM PDT 24
Finished May 05 12:24:07 PM PDT 24
Peak memory 198144 kb
Host smart-2d54a423-db55-4212-ad76-e065dcb4b911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028725503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1028725503
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.339345727
Short name T88
Test name
Test status
Simulation time 517181703 ps
CPU time 8.51 seconds
Started May 05 12:20:15 PM PDT 24
Finished May 05 12:20:24 PM PDT 24
Peak memory 199864 kb
Host smart-9b1d4a24-a165-4931-9ca1-1f905d115da3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339345727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.339345727
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4144672385
Short name T530
Test name
Test status
Simulation time 114437269 ps
CPU time 5.06 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:20 PM PDT 24
Peak memory 198536 kb
Host smart-35a5ef3c-c9f3-4a12-90cc-0e3e6f7dad49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144672385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4144672385
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3632243192
Short name T81
Test name
Test status
Simulation time 70664898 ps
CPU time 0.97 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 199428 kb
Host smart-9f0ea058-cfb8-45da-8b28-dc3123879b2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632243192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3632243192
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.760227772
Short name T521
Test name
Test status
Simulation time 25762278 ps
CPU time 1.55 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:20:11 PM PDT 24
Peak memory 199832 kb
Host smart-eb15d5b3-b83b-4fba-8272-5ccc22ba3601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760227772 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.760227772
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1159062927
Short name T87
Test name
Test status
Simulation time 28309879 ps
CPU time 0.9 seconds
Started May 05 12:21:06 PM PDT 24
Finished May 05 12:21:07 PM PDT 24
Peak memory 199120 kb
Host smart-b58c5a57-2700-4031-9baf-f1e640422d8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159062927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1159062927
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.714161063
Short name T532
Test name
Test status
Simulation time 12508743 ps
CPU time 0.6 seconds
Started May 05 12:24:24 PM PDT 24
Finished May 05 12:24:26 PM PDT 24
Peak memory 193204 kb
Host smart-fa2cf74f-8999-4db9-b511-26cb355fb942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714161063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.714161063
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1451706507
Short name T576
Test name
Test status
Simulation time 106811486 ps
CPU time 1.85 seconds
Started May 05 12:23:56 PM PDT 24
Finished May 05 12:23:59 PM PDT 24
Peak memory 198584 kb
Host smart-7419865c-35b4-4402-8675-57a4281207db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451706507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1451706507
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.70991154
Short name T503
Test name
Test status
Simulation time 341090318 ps
CPU time 1.11 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 199292 kb
Host smart-44199d0f-604e-4ef4-9cda-7dd3ae9b1a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70991154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.70991154
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3553392695
Short name T105
Test name
Test status
Simulation time 348771734 ps
CPU time 2.06 seconds
Started May 05 12:22:10 PM PDT 24
Finished May 05 12:22:13 PM PDT 24
Peak memory 199856 kb
Host smart-d79f3dc2-224b-4981-b748-19e08b7e53e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553392695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3553392695
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1932486685
Short name T72
Test name
Test status
Simulation time 20499839 ps
CPU time 0.56 seconds
Started May 05 12:24:21 PM PDT 24
Finished May 05 12:24:22 PM PDT 24
Peak memory 194432 kb
Host smart-f5b423e1-d952-449c-b3e7-1ba58279bfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932486685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1932486685
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1079973208
Short name T490
Test name
Test status
Simulation time 16428254 ps
CPU time 0.61 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 193724 kb
Host smart-495f9c8f-05d5-4212-8274-468df8ad2cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079973208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1079973208
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.767621239
Short name T533
Test name
Test status
Simulation time 44714888 ps
CPU time 0.58 seconds
Started May 05 12:22:28 PM PDT 24
Finished May 05 12:22:29 PM PDT 24
Peak memory 194816 kb
Host smart-8631287d-f348-4977-b4a2-cb8678342a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767621239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.767621239
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.563423866
Short name T573
Test name
Test status
Simulation time 18084623 ps
CPU time 0.59 seconds
Started May 05 12:24:20 PM PDT 24
Finished May 05 12:24:21 PM PDT 24
Peak memory 194636 kb
Host smart-238f5f7a-4be6-45b2-af76-236ceaccb927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563423866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.563423866
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1250050932
Short name T507
Test name
Test status
Simulation time 49410730 ps
CPU time 0.59 seconds
Started May 05 12:21:01 PM PDT 24
Finished May 05 12:21:02 PM PDT 24
Peak memory 194632 kb
Host smart-746d0f8a-03c2-4b93-a08b-7a9a2983f82b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250050932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1250050932
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2004561099
Short name T550
Test name
Test status
Simulation time 61522956 ps
CPU time 0.67 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 193184 kb
Host smart-57986c6e-22da-4efd-9a5e-b9447663e3a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004561099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2004561099
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3170301598
Short name T474
Test name
Test status
Simulation time 16693003 ps
CPU time 0.69 seconds
Started May 05 12:22:08 PM PDT 24
Finished May 05 12:22:09 PM PDT 24
Peak memory 194572 kb
Host smart-d49099ad-0549-4403-8e82-35eca57ce2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170301598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3170301598
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3436571812
Short name T506
Test name
Test status
Simulation time 21268069 ps
CPU time 0.63 seconds
Started May 05 12:20:36 PM PDT 24
Finished May 05 12:20:37 PM PDT 24
Peak memory 194448 kb
Host smart-46fbf319-c034-41c1-9a2b-7c0b7d22f11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436571812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3436571812
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.787320552
Short name T512
Test name
Test status
Simulation time 20841224 ps
CPU time 0.64 seconds
Started May 05 12:20:45 PM PDT 24
Finished May 05 12:20:46 PM PDT 24
Peak memory 194644 kb
Host smart-b835c67b-e6e4-48eb-8d4b-3d02f280073e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787320552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.787320552
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1056980191
Short name T75
Test name
Test status
Simulation time 50655611 ps
CPU time 0.57 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 194364 kb
Host smart-b6c1efd4-6a47-47a6-b0d9-c708945cbb43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056980191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1056980191
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3250506794
Short name T590
Test name
Test status
Simulation time 396597516 ps
CPU time 5.96 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:17 PM PDT 24
Peak memory 199144 kb
Host smart-bf56cd9a-4514-4316-9d0e-c7e220feb1ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250506794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3250506794
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2550721597
Short name T495
Test name
Test status
Simulation time 866584804 ps
CPU time 8.83 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:18 PM PDT 24
Peak memory 198488 kb
Host smart-df86a516-27f7-47c0-b6e7-33e4be6360dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550721597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2550721597
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3700189183
Short name T483
Test name
Test status
Simulation time 20081946 ps
CPU time 0.87 seconds
Started May 05 12:20:42 PM PDT 24
Finished May 05 12:20:43 PM PDT 24
Peak memory 199028 kb
Host smart-468a58ed-508f-4314-a2dc-db0a9ae67cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700189183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3700189183
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2379168940
Short name T560
Test name
Test status
Simulation time 65038653 ps
CPU time 1.7 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 199468 kb
Host smart-aa935475-402f-4e8d-abd6-e25880cbfca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379168940 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2379168940
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2044408123
Short name T82
Test name
Test status
Simulation time 44809589 ps
CPU time 0.75 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 196832 kb
Host smart-7364e50f-4326-4aa6-8cd0-f0ad215dca64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044408123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2044408123
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2234665941
Short name T541
Test name
Test status
Simulation time 42393728 ps
CPU time 0.57 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 194284 kb
Host smart-8f5796da-2bc2-4a61-97da-bf66b2c1a546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234665941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2234665941
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.216995286
Short name T508
Test name
Test status
Simulation time 112015076 ps
CPU time 1.12 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 198916 kb
Host smart-4571eff6-1df2-42ee-bc1c-0bd533405bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216995286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.216995286
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1177328353
Short name T60
Test name
Test status
Simulation time 76762527 ps
CPU time 1.51 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:13 PM PDT 24
Peak memory 199668 kb
Host smart-806ddeb8-ce3e-4d85-9447-8ba02dfb11d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177328353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1177328353
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1559581156
Short name T542
Test name
Test status
Simulation time 160462440 ps
CPU time 1.72 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:12 PM PDT 24
Peak memory 199260 kb
Host smart-5d106f95-af97-457d-a810-e820cd07f9bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559581156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1559581156
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3506046020
Short name T528
Test name
Test status
Simulation time 35280777 ps
CPU time 0.61 seconds
Started May 05 12:21:56 PM PDT 24
Finished May 05 12:21:57 PM PDT 24
Peak memory 194524 kb
Host smart-60c327f4-5626-4076-ba27-ebd6ad7e42cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506046020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3506046020
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.177870964
Short name T538
Test name
Test status
Simulation time 11006339 ps
CPU time 0.64 seconds
Started May 05 12:21:23 PM PDT 24
Finished May 05 12:21:24 PM PDT 24
Peak memory 194440 kb
Host smart-2e43cd65-9ee5-44bf-84a8-15db64c94bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177870964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.177870964
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3581527661
Short name T499
Test name
Test status
Simulation time 16372544 ps
CPU time 0.58 seconds
Started May 05 12:24:37 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 194028 kb
Host smart-f888c665-d242-4a48-ad3f-935c435ab9b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581527661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3581527661
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1624863848
Short name T476
Test name
Test status
Simulation time 14702227 ps
CPU time 0.68 seconds
Started May 05 12:19:33 PM PDT 24
Finished May 05 12:19:34 PM PDT 24
Peak memory 194452 kb
Host smart-3c8ac5e6-6998-4f49-aec4-a2ac5bad2a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624863848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1624863848
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2569385835
Short name T475
Test name
Test status
Simulation time 12672545 ps
CPU time 0.62 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 192452 kb
Host smart-cfc6f93c-22d0-492c-bb46-580dc71c159c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569385835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2569385835
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.241627470
Short name T480
Test name
Test status
Simulation time 14725024 ps
CPU time 0.66 seconds
Started May 05 12:19:33 PM PDT 24
Finished May 05 12:19:34 PM PDT 24
Peak memory 194392 kb
Host smart-2eebe1e4-7f24-49ff-b60d-448b2854eb86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241627470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.241627470
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4068875907
Short name T487
Test name
Test status
Simulation time 18614274 ps
CPU time 0.61 seconds
Started May 05 12:23:58 PM PDT 24
Finished May 05 12:23:59 PM PDT 24
Peak memory 194212 kb
Host smart-439d5838-0e2c-4210-9f66-ada427f366ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068875907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4068875907
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2860373797
Short name T517
Test name
Test status
Simulation time 72388687 ps
CPU time 0.57 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 193984 kb
Host smart-e25f65f2-b48c-4b11-a9e3-7b56fcc7d70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860373797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2860373797
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3873970935
Short name T561
Test name
Test status
Simulation time 11647747 ps
CPU time 0.55 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 194052 kb
Host smart-a0eb994f-427b-44af-929f-81e3fe484c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873970935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3873970935
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.623838328
Short name T531
Test name
Test status
Simulation time 84534396 ps
CPU time 0.63 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 192044 kb
Host smart-40f228fd-cd9b-4a53-be45-668a987edfa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623838328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.623838328
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2114084024
Short name T91
Test name
Test status
Simulation time 1229056666 ps
CPU time 5.98 seconds
Started May 05 12:19:59 PM PDT 24
Finished May 05 12:20:06 PM PDT 24
Peak memory 199056 kb
Host smart-4225fa25-2b5b-4062-acb7-1acd4929e135
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114084024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2114084024
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2216975275
Short name T90
Test name
Test status
Simulation time 4022932875 ps
CPU time 10.7 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:25 PM PDT 24
Peak memory 198832 kb
Host smart-b04fab64-0d9b-4987-b262-08856e3c5b84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216975275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2216975275
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2705413752
Short name T496
Test name
Test status
Simulation time 72130577 ps
CPU time 1.02 seconds
Started May 05 12:24:30 PM PDT 24
Finished May 05 12:24:32 PM PDT 24
Peak memory 198616 kb
Host smart-8222a28c-5754-4417-8cef-de8cd3b6d014
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705413752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2705413752
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2329626462
Short name T522
Test name
Test status
Simulation time 180352086 ps
CPU time 1.27 seconds
Started May 05 12:24:11 PM PDT 24
Finished May 05 12:24:16 PM PDT 24
Peak memory 199680 kb
Host smart-6f59b809-b82a-4daa-9a2f-ac6cbffbb5ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329626462 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2329626462
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2572530610
Short name T86
Test name
Test status
Simulation time 13761671 ps
CPU time 0.65 seconds
Started May 05 12:20:08 PM PDT 24
Finished May 05 12:20:09 PM PDT 24
Peak memory 197432 kb
Host smart-3ae02b15-bf6c-429b-92d0-99c4f370683b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572530610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2572530610
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.53472988
Short name T535
Test name
Test status
Simulation time 39844504 ps
CPU time 0.6 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 194204 kb
Host smart-ecde39ba-7553-4077-957a-0584e54ca19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53472988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.53472988
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2101383102
Short name T549
Test name
Test status
Simulation time 112907925 ps
CPU time 1.84 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:23:56 PM PDT 24
Peak memory 199356 kb
Host smart-6d535599-2ad5-450d-a05b-adbc3359badf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101383102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2101383102
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1280712744
Short name T516
Test name
Test status
Simulation time 178955618 ps
CPU time 2.52 seconds
Started May 05 12:20:27 PM PDT 24
Finished May 05 12:20:30 PM PDT 24
Peak memory 199868 kb
Host smart-ca28b1ed-9186-4577-a4e1-221269aa40ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280712744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1280712744
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.33977946
Short name T52
Test name
Test status
Simulation time 87533250 ps
CPU time 1.83 seconds
Started May 05 12:20:13 PM PDT 24
Finished May 05 12:20:15 PM PDT 24
Peak memory 199816 kb
Host smart-12a95d2a-7924-4d2f-a94d-b2ec8e9cc470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.33977946
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1943895857
Short name T527
Test name
Test status
Simulation time 25849267 ps
CPU time 0.57 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:23:51 PM PDT 24
Peak memory 194124 kb
Host smart-2854a66d-a879-4b0f-bffa-ad4365fe6463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943895857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1943895857
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.593714460
Short name T477
Test name
Test status
Simulation time 33919324 ps
CPU time 0.6 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:20:10 PM PDT 24
Peak memory 194568 kb
Host smart-11802c51-cdc8-4d80-b15e-b7098cb3ce1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593714460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.593714460
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3475411277
Short name T575
Test name
Test status
Simulation time 32073368 ps
CPU time 0.66 seconds
Started May 05 12:19:39 PM PDT 24
Finished May 05 12:19:40 PM PDT 24
Peak memory 194372 kb
Host smart-d3c7c8f0-c399-4822-9ff3-707f88d39057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475411277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3475411277
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2313241710
Short name T567
Test name
Test status
Simulation time 57105092 ps
CPU time 0.66 seconds
Started May 05 12:19:42 PM PDT 24
Finished May 05 12:19:43 PM PDT 24
Peak memory 194444 kb
Host smart-55cfb462-3d34-4bcd-b827-0c6ccd8d9ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313241710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2313241710
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3338082873
Short name T554
Test name
Test status
Simulation time 58011871 ps
CPU time 0.6 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 194068 kb
Host smart-1e231414-f71e-49d1-affd-5462335b4fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338082873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3338082873
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.397297323
Short name T478
Test name
Test status
Simulation time 88098979 ps
CPU time 0.67 seconds
Started May 05 12:19:46 PM PDT 24
Finished May 05 12:19:48 PM PDT 24
Peak memory 194456 kb
Host smart-4707afb7-a683-482d-8bcd-6bd48009112b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397297323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.397297323
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3942508430
Short name T513
Test name
Test status
Simulation time 39873591 ps
CPU time 0.62 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 191992 kb
Host smart-8a13700e-3520-4a97-911d-1439595941c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942508430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3942508430
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4233691946
Short name T491
Test name
Test status
Simulation time 46868019 ps
CPU time 0.62 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 192068 kb
Host smart-625ec2a2-c0cd-4a45-946d-5f03b03fd714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233691946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4233691946
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2182298008
Short name T494
Test name
Test status
Simulation time 23520303 ps
CPU time 0.59 seconds
Started May 05 12:19:46 PM PDT 24
Finished May 05 12:19:48 PM PDT 24
Peak memory 194620 kb
Host smart-24c2011d-bfdc-4393-b6aa-b3fdf5412ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182298008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2182298008
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2915330338
Short name T585
Test name
Test status
Simulation time 18313631 ps
CPU time 0.58 seconds
Started May 05 12:19:46 PM PDT 24
Finished May 05 12:19:47 PM PDT 24
Peak memory 194680 kb
Host smart-5631971c-2098-41de-b084-3d005268cc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915330338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2915330338
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2751697025
Short name T77
Test name
Test status
Simulation time 128547636 ps
CPU time 1.63 seconds
Started May 05 12:20:41 PM PDT 24
Finished May 05 12:20:43 PM PDT 24
Peak memory 200208 kb
Host smart-e320f012-9605-4a5d-ae9e-bef373c5a9eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751697025 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2751697025
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2996749212
Short name T563
Test name
Test status
Simulation time 12067524 ps
CPU time 0.71 seconds
Started May 05 12:21:41 PM PDT 24
Finished May 05 12:21:43 PM PDT 24
Peak memory 197504 kb
Host smart-6377df66-4e70-497f-be49-9b42b6215595
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996749212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2996749212
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.143166682
Short name T552
Test name
Test status
Simulation time 69589733 ps
CPU time 0.59 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:24:48 PM PDT 24
Peak memory 194436 kb
Host smart-e891cf86-cd02-4e4e-9d31-cae7135366c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143166682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.143166682
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.609096326
Short name T553
Test name
Test status
Simulation time 147394169 ps
CPU time 1.72 seconds
Started May 05 12:21:41 PM PDT 24
Finished May 05 12:21:43 PM PDT 24
Peak memory 199532 kb
Host smart-4ab44307-096e-49d1-831f-933c453de270
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609096326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.609096326
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2912021338
Short name T526
Test name
Test status
Simulation time 54678175 ps
CPU time 1.15 seconds
Started May 05 12:20:01 PM PDT 24
Finished May 05 12:20:03 PM PDT 24
Peak memory 199772 kb
Host smart-b8eddb97-306a-41f0-8361-064f5eb23e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912021338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2912021338
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2304664063
Short name T108
Test name
Test status
Simulation time 1442305453 ps
CPU time 3.15 seconds
Started May 05 12:24:00 PM PDT 24
Finished May 05 12:24:04 PM PDT 24
Peak memory 198388 kb
Host smart-23470cba-304a-4e25-add3-dbec41399b10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304664063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2304664063
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.239122785
Short name T524
Test name
Test status
Simulation time 132598377 ps
CPU time 2.05 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:57 PM PDT 24
Peak memory 199824 kb
Host smart-1c05bfe2-2e2d-4922-8fd8-d4fbf1332ae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239122785 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.239122785
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.620895625
Short name T562
Test name
Test status
Simulation time 44289961 ps
CPU time 0.83 seconds
Started May 05 12:21:37 PM PDT 24
Finished May 05 12:21:38 PM PDT 24
Peak memory 198848 kb
Host smart-a22fd2ed-c0e8-428b-bb72-d96d717b3f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620895625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.620895625
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1417527547
Short name T580
Test name
Test status
Simulation time 15776902 ps
CPU time 0.56 seconds
Started May 05 12:24:50 PM PDT 24
Finished May 05 12:24:54 PM PDT 24
Peak memory 194376 kb
Host smart-deccca26-fea0-40a4-bc26-2b69265ed261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417527547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1417527547
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3045449349
Short name T486
Test name
Test status
Simulation time 87758958 ps
CPU time 1.98 seconds
Started May 05 12:20:16 PM PDT 24
Finished May 05 12:20:19 PM PDT 24
Peak memory 199684 kb
Host smart-e6fce0b9-d474-49fc-a997-502af2ac0a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045449349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3045449349
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2669801347
Short name T498
Test name
Test status
Simulation time 173299190 ps
CPU time 4.43 seconds
Started May 05 12:24:28 PM PDT 24
Finished May 05 12:24:34 PM PDT 24
Peak memory 198868 kb
Host smart-7e810ec4-0888-4c39-b719-2d7ff53fc993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669801347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2669801347
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3604701912
Short name T509
Test name
Test status
Simulation time 46770546 ps
CPU time 1.33 seconds
Started May 05 12:22:51 PM PDT 24
Finished May 05 12:22:53 PM PDT 24
Peak memory 199984 kb
Host smart-81909214-69e4-4923-9855-34d21e49e87f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604701912 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3604701912
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3355452458
Short name T85
Test name
Test status
Simulation time 163046487 ps
CPU time 0.79 seconds
Started May 05 12:23:47 PM PDT 24
Finished May 05 12:23:48 PM PDT 24
Peak memory 197172 kb
Host smart-453e829b-ab19-41cd-9850-edf7c119ed13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355452458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3355452458
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.419930276
Short name T536
Test name
Test status
Simulation time 13468514 ps
CPU time 0.56 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 194372 kb
Host smart-d42dd1b0-a4aa-473b-85ac-e58abfab0a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419930276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.419930276
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3519378406
Short name T564
Test name
Test status
Simulation time 192153012 ps
CPU time 1.18 seconds
Started May 05 12:20:00 PM PDT 24
Finished May 05 12:20:02 PM PDT 24
Peak memory 199300 kb
Host smart-73f8be50-5984-45f3-8216-2680eeb190c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519378406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3519378406
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.565066638
Short name T61
Test name
Test status
Simulation time 113595036 ps
CPU time 2.56 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:56 PM PDT 24
Peak memory 198272 kb
Host smart-01b906ec-9a69-4c93-a676-0e902791d40b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565066638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.565066638
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2986633305
Short name T577
Test name
Test status
Simulation time 174487099 ps
CPU time 2.88 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 199532 kb
Host smart-5e370d86-1ebd-45d8-bd9a-4909c8ad8100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986633305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2986633305
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3136699748
Short name T55
Test name
Test status
Simulation time 43008723784 ps
CPU time 110.2 seconds
Started May 05 12:22:50 PM PDT 24
Finished May 05 12:24:41 PM PDT 24
Peak memory 215892 kb
Host smart-d55e08f4-5fa6-4897-852c-9d00eada6df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136699748 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3136699748
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1061767608
Short name T571
Test name
Test status
Simulation time 161630878 ps
CPU time 0.81 seconds
Started May 05 12:20:42 PM PDT 24
Finished May 05 12:20:44 PM PDT 24
Peak memory 199584 kb
Host smart-80b9861d-f8d4-4029-95a4-9c58c8f0e9fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061767608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1061767608
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.58919986
Short name T566
Test name
Test status
Simulation time 71692854 ps
CPU time 0.59 seconds
Started May 05 12:24:40 PM PDT 24
Finished May 05 12:24:42 PM PDT 24
Peak memory 194352 kb
Host smart-d4db3397-7b08-4826-8290-49660974ee46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58919986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.58919986
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.198519757
Short name T518
Test name
Test status
Simulation time 142099843 ps
CPU time 1.75 seconds
Started May 05 12:22:50 PM PDT 24
Finished May 05 12:22:52 PM PDT 24
Peak memory 200092 kb
Host smart-122eabc0-de49-43eb-a3c6-20b4bea06b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198519757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.198519757
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.120835810
Short name T540
Test name
Test status
Simulation time 63803182 ps
CPU time 2.92 seconds
Started May 05 12:23:47 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 198156 kb
Host smart-4789fd45-f1be-498f-8137-c67db02e1078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120835810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.120835810
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1889228038
Short name T589
Test name
Test status
Simulation time 245384664 ps
CPU time 3.81 seconds
Started May 05 12:19:57 PM PDT 24
Finished May 05 12:20:01 PM PDT 24
Peak memory 200124 kb
Host smart-94dc92ab-84d5-4b7f-baa4-f3dae8cf2228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889228038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1889228038
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3656810398
Short name T582
Test name
Test status
Simulation time 79428761 ps
CPU time 1.8 seconds
Started May 05 12:24:28 PM PDT 24
Finished May 05 12:24:31 PM PDT 24
Peak memory 198732 kb
Host smart-02f8c4a7-a8ed-44ad-b6b9-064eae64e491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656810398 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3656810398
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.607435961
Short name T525
Test name
Test status
Simulation time 21891446 ps
CPU time 0.68 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 197248 kb
Host smart-7cd4be50-f520-4b89-9d91-409af6e16b67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607435961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.607435961
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1252393834
Short name T539
Test name
Test status
Simulation time 19965783 ps
CPU time 0.65 seconds
Started May 05 12:20:57 PM PDT 24
Finished May 05 12:20:58 PM PDT 24
Peak memory 194688 kb
Host smart-2fc10f40-407c-4f40-a056-e2c40841ae6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252393834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1252393834
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1110907690
Short name T479
Test name
Test status
Simulation time 25045788 ps
CPU time 1.13 seconds
Started May 05 12:23:47 PM PDT 24
Finished May 05 12:23:49 PM PDT 24
Peak memory 196212 kb
Host smart-f66f865d-8dc2-4a36-b720-5c90e2744ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110907690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1110907690
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1037675219
Short name T543
Test name
Test status
Simulation time 53926906 ps
CPU time 1.25 seconds
Started May 05 12:19:46 PM PDT 24
Finished May 05 12:19:48 PM PDT 24
Peak memory 199796 kb
Host smart-0057a3af-0ffa-48f2-8e44-f1ffb42787f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037675219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1037675219
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4109079341
Short name T565
Test name
Test status
Simulation time 797549696 ps
CPU time 2.89 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:20:12 PM PDT 24
Peak memory 199932 kb
Host smart-374751e9-6665-41a3-bdcf-5110ea89af5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109079341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4109079341
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2437803314
Short name T200
Test name
Test status
Simulation time 12840449 ps
CPU time 0.56 seconds
Started May 05 12:24:45 PM PDT 24
Finished May 05 12:24:47 PM PDT 24
Peak memory 195396 kb
Host smart-ba15635b-9252-42b5-97c4-dfe5aed5ebbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437803314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2437803314
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.868930726
Short name T194
Test name
Test status
Simulation time 302614027 ps
CPU time 23.17 seconds
Started May 05 12:19:38 PM PDT 24
Finished May 05 12:20:03 PM PDT 24
Peak memory 216284 kb
Host smart-b5531d32-337a-46fd-80de-341639ac6183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868930726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.868930726
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.790436210
Short name T464
Test name
Test status
Simulation time 158881756 ps
CPU time 2.84 seconds
Started May 05 12:23:56 PM PDT 24
Finished May 05 12:24:00 PM PDT 24
Peak memory 198568 kb
Host smart-e2bcb9c8-396e-417f-98c9-e76e7163006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790436210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.790436210
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.91690160
Short name T66
Test name
Test status
Simulation time 2506016908 ps
CPU time 106.8 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:25:49 PM PDT 24
Peak memory 199528 kb
Host smart-9089bf71-c1d2-4d41-91c6-f6fc1b0991dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91690160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.91690160
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1272199946
Short name T277
Test name
Test status
Simulation time 45899791124 ps
CPU time 94.53 seconds
Started May 05 12:23:56 PM PDT 24
Finished May 05 12:25:32 PM PDT 24
Peak memory 198632 kb
Host smart-72f6ef14-467b-4e76-830e-cfe593c6bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272199946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1272199946
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.965603385
Short name T321
Test name
Test status
Simulation time 532237256 ps
CPU time 4.59 seconds
Started May 05 12:19:15 PM PDT 24
Finished May 05 12:19:20 PM PDT 24
Peak memory 199804 kb
Host smart-3797f78f-9f8a-46cf-a0e1-1d47216d8811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965603385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.965603385
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1386562747
Short name T449
Test name
Test status
Simulation time 53254169 ps
CPU time 1.11 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 198164 kb
Host smart-7b2b2b67-df7a-4f08-b1f1-30d27e7bdacb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386562747 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1386562747
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2620762275
Short name T65
Test name
Test status
Simulation time 12123048 ps
CPU time 0.64 seconds
Started May 05 12:23:47 PM PDT 24
Finished May 05 12:23:48 PM PDT 24
Peak memory 193848 kb
Host smart-5da74f69-5908-4968-8691-107cc05a485d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620762275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2620762275
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.722105259
Short name T320
Test name
Test status
Simulation time 3348105366 ps
CPU time 34.91 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:43 PM PDT 24
Peak memory 207692 kb
Host smart-64567690-9b22-4799-b8bf-58fae3a31a34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722105259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.722105259
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3653314963
Short name T152
Test name
Test status
Simulation time 6448803172 ps
CPU time 41.94 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:25:29 PM PDT 24
Peak memory 199836 kb
Host smart-a0a774de-502d-4a8d-b139-92cdacccfffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653314963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3653314963
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2708113152
Short name T250
Test name
Test status
Simulation time 1629851990 ps
CPU time 30.14 seconds
Started May 05 12:24:09 PM PDT 24
Finished May 05 12:24:44 PM PDT 24
Peak memory 199804 kb
Host smart-bd322dcf-1e3c-446f-8004-a5ff47a1d817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708113152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2708113152
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3626082142
Short name T154
Test name
Test status
Simulation time 211815848 ps
CPU time 1.87 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 198916 kb
Host smart-eb38eb46-ffc9-40ae-b607-18c73bf1d5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626082142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3626082142
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3686308248
Short name T343
Test name
Test status
Simulation time 53489648 ps
CPU time 1.08 seconds
Started May 05 12:21:52 PM PDT 24
Finished May 05 12:21:54 PM PDT 24
Peak memory 199612 kb
Host smart-6612791a-7512-4a76-8e6d-e41cf7001471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686308248 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3686308248
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1782556383
Short name T346
Test name
Test status
Simulation time 31862747802 ps
CPU time 515.23 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:32:37 PM PDT 24
Peak memory 199456 kb
Host smart-413f989a-bca4-4663-93f7-ae9e34d9cf63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782556383 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1782556383
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2414316330
Short name T395
Test name
Test status
Simulation time 12381461 ps
CPU time 0.59 seconds
Started May 05 12:22:35 PM PDT 24
Finished May 05 12:22:36 PM PDT 24
Peak memory 195284 kb
Host smart-78e45b4f-6b86-4016-97d6-0c67a60f4fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414316330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2414316330
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4069511552
Short name T264
Test name
Test status
Simulation time 308148134 ps
CPU time 14.52 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:25:02 PM PDT 24
Peak memory 207784 kb
Host smart-b7885822-4bdc-4f4a-880d-de37fadf065f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069511552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4069511552
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2149470315
Short name T333
Test name
Test status
Simulation time 1544212199 ps
CPU time 40.49 seconds
Started May 05 12:20:47 PM PDT 24
Finished May 05 12:21:28 PM PDT 24
Peak memory 200180 kb
Host smart-a62ebe2e-4ead-4e1a-8165-977c41c635d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149470315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2149470315
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.625915312
Short name T416
Test name
Test status
Simulation time 5763978962 ps
CPU time 58.04 seconds
Started May 05 12:19:56 PM PDT 24
Finished May 05 12:20:55 PM PDT 24
Peak memory 199904 kb
Host smart-7e36aff8-6897-4341-b107-de39fcf4357d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625915312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.625915312
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1887123884
Short name T217
Test name
Test status
Simulation time 8068963667 ps
CPU time 14.13 seconds
Started May 05 12:19:58 PM PDT 24
Finished May 05 12:20:14 PM PDT 24
Peak memory 199900 kb
Host smart-90772810-de74-4851-a14f-4aed91b2c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887123884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1887123884
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2291997804
Short name T197
Test name
Test status
Simulation time 1294536772 ps
CPU time 4.75 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 197592 kb
Host smart-5680ed0b-b948-4df3-bf88-511c2a5ff510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291997804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2291997804
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2858421880
Short name T242
Test name
Test status
Simulation time 176019718 ps
CPU time 1.19 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:06 PM PDT 24
Peak memory 197308 kb
Host smart-d3581a7c-2272-4633-844c-9793d30459fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858421880 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2858421880
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3898639158
Short name T356
Test name
Test status
Simulation time 46125361068 ps
CPU time 463.57 seconds
Started May 05 12:20:13 PM PDT 24
Finished May 05 12:27:57 PM PDT 24
Peak memory 199980 kb
Host smart-e5bc3ace-a200-4bb1-819c-5556c2fa3f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898639158 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3898639158
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3617329250
Short name T26
Test name
Test status
Simulation time 255173000 ps
CPU time 3.24 seconds
Started May 05 12:22:35 PM PDT 24
Finished May 05 12:22:39 PM PDT 24
Peak memory 199788 kb
Host smart-1d984893-a196-4e03-8a30-bc4c1d6a9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617329250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3617329250
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1187204387
Short name T391
Test name
Test status
Simulation time 12078724 ps
CPU time 0.57 seconds
Started May 05 12:21:24 PM PDT 24
Finished May 05 12:21:25 PM PDT 24
Peak memory 195568 kb
Host smart-037970ee-80f9-40a1-b24b-1bd99983851b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187204387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1187204387
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2966911392
Short name T344
Test name
Test status
Simulation time 173184332 ps
CPU time 5.18 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 197748 kb
Host smart-5cc2f19a-460e-400a-a8b2-bdaf41205a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966911392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2966911392
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1342050700
Short name T234
Test name
Test status
Simulation time 5375644674 ps
CPU time 45.32 seconds
Started May 05 12:20:13 PM PDT 24
Finished May 05 12:20:59 PM PDT 24
Peak memory 199880 kb
Host smart-efcac0bd-5c09-4608-b443-0f41427317b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342050700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1342050700
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1652671681
Short name T450
Test name
Test status
Simulation time 8532879303 ps
CPU time 69.79 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:25:11 PM PDT 24
Peak memory 199768 kb
Host smart-20db7f21-6a82-496d-b6c1-50ffa57375ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652671681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1652671681
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3437350643
Short name T385
Test name
Test status
Simulation time 7571128803 ps
CPU time 95.65 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:25:40 PM PDT 24
Peak memory 198320 kb
Host smart-06b15961-24ae-40a7-aaff-e65b5adccf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437350643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3437350643
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3156759275
Short name T155
Test name
Test status
Simulation time 927307656 ps
CPU time 5.81 seconds
Started May 05 12:20:10 PM PDT 24
Finished May 05 12:20:16 PM PDT 24
Peak memory 199880 kb
Host smart-a7bde80b-30c9-41b2-9d69-e98e99b58fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156759275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3156759275
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2278290511
Short name T452
Test name
Test status
Simulation time 28268142 ps
CPU time 0.96 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:06 PM PDT 24
Peak memory 198284 kb
Host smart-6a6d68d9-7f45-40a3-b240-e883672c053f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278290511 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2278290511
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3777755377
Short name T174
Test name
Test status
Simulation time 293917199253 ps
CPU time 446.82 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:31:32 PM PDT 24
Peak memory 198028 kb
Host smart-ed5a370b-aeca-4303-ba95-b99351954b5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777755377 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3777755377
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4082593286
Short name T313
Test name
Test status
Simulation time 14869405 ps
CPU time 0.62 seconds
Started May 05 12:20:10 PM PDT 24
Finished May 05 12:20:12 PM PDT 24
Peak memory 195252 kb
Host smart-53e1b604-ca9e-4ef7-8747-697c6c983643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082593286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4082593286
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3287786173
Short name T46
Test name
Test status
Simulation time 341591903 ps
CPU time 14.91 seconds
Started May 05 12:23:46 PM PDT 24
Finished May 05 12:24:02 PM PDT 24
Peak memory 214264 kb
Host smart-c863a352-9d6d-4706-9548-6d22f56ee3f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287786173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3287786173
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3439769071
Short name T53
Test name
Test status
Simulation time 592879504 ps
CPU time 6.55 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:21 PM PDT 24
Peak memory 198984 kb
Host smart-1f478409-6ab2-4a79-be52-ba6797435675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439769071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3439769071
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3553705354
Short name T458
Test name
Test status
Simulation time 3469099556 ps
CPU time 48.17 seconds
Started May 05 12:20:10 PM PDT 24
Finished May 05 12:20:59 PM PDT 24
Peak memory 199332 kb
Host smart-0ef31a00-7210-4f83-84f9-52fe9e042922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553705354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3553705354
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.306775076
Short name T96
Test name
Test status
Simulation time 4303931197 ps
CPU time 13.39 seconds
Started May 05 12:20:01 PM PDT 24
Finished May 05 12:20:15 PM PDT 24
Peak memory 199896 kb
Host smart-71f91ef2-771a-4418-a6e9-8c6be6ab47c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306775076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.306775076
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1085948449
Short name T19
Test name
Test status
Simulation time 638715219 ps
CPU time 7.09 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:23:58 PM PDT 24
Peak memory 199456 kb
Host smart-d7409dfd-831e-49ad-8b67-c19a0976d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085948449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1085948449
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.220919506
Short name T308
Test name
Test status
Simulation time 114842298 ps
CPU time 1.1 seconds
Started May 05 12:24:50 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 199668 kb
Host smart-92b478b8-5f4f-46a6-bb51-7133e065eec9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220919506 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.220919506
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.347508626
Short name T384
Test name
Test status
Simulation time 14437913299 ps
CPU time 398.08 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:31:32 PM PDT 24
Peak memory 199724 kb
Host smart-89c1b41d-873c-49a0-b3f0-724318c19965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347508626 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.347508626
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2403360777
Short name T239
Test name
Test status
Simulation time 13974792 ps
CPU time 0.56 seconds
Started May 05 12:24:11 PM PDT 24
Finished May 05 12:24:16 PM PDT 24
Peak memory 194260 kb
Host smart-f67459cc-6bf0-4eb3-a98c-11930a534e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403360777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2403360777
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.703636121
Short name T386
Test name
Test status
Simulation time 3048778953 ps
CPU time 27.2 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:25:21 PM PDT 24
Peak memory 216080 kb
Host smart-b56f4872-3fe7-4c4b-8eed-00047d242c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703636121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.703636121
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.816577782
Short name T281
Test name
Test status
Simulation time 273869800 ps
CPU time 14.59 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:24:50 PM PDT 24
Peak memory 199464 kb
Host smart-c1bd688f-fc2e-4a5e-833c-75a4f23f565a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816577782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.816577782
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3040921230
Short name T145
Test name
Test status
Simulation time 4957653511 ps
CPU time 54.03 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:25:09 PM PDT 24
Peak memory 198688 kb
Host smart-8acb7afc-2b44-44e4-8481-a422befd5cbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040921230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3040921230
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1963228943
Short name T259
Test name
Test status
Simulation time 1519498969 ps
CPU time 29.11 seconds
Started May 05 12:22:35 PM PDT 24
Finished May 05 12:23:05 PM PDT 24
Peak memory 199868 kb
Host smart-90922370-883a-470a-bd63-1ad43fd3f797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963228943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1963228943
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.821485626
Short name T433
Test name
Test status
Simulation time 1041619455 ps
CPU time 6.51 seconds
Started May 05 12:20:16 PM PDT 24
Finished May 05 12:20:23 PM PDT 24
Peak memory 199876 kb
Host smart-c88cd054-45e2-48c4-b51a-bff512de338f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821485626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.821485626
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2727722887
Short name T149
Test name
Test status
Simulation time 306355483 ps
CPU time 1.52 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 197212 kb
Host smart-309d057a-9e25-4cfd-a7ed-45190c48cbe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727722887 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2727722887
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2827763293
Short name T188
Test name
Test status
Simulation time 75844769 ps
CPU time 1.32 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 197268 kb
Host smart-56edde88-b95e-4456-9b8c-faf809300468
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827763293 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2827763293
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.72970823
Short name T469
Test name
Test status
Simulation time 8495216755 ps
CPU time 436.29 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:32:02 PM PDT 24
Peak memory 199588 kb
Host smart-74105ecb-64ea-4ce7-ab0b-bd3770c331c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72970823 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.72970823
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1728622232
Short name T136
Test name
Test status
Simulation time 123562125 ps
CPU time 0.57 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:23:51 PM PDT 24
Peak memory 195004 kb
Host smart-8cbfa750-ff1c-47ea-8e80-926359df7f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728622232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1728622232
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.19219306
Short name T223
Test name
Test status
Simulation time 137799357 ps
CPU time 7.13 seconds
Started May 05 12:20:11 PM PDT 24
Finished May 05 12:20:18 PM PDT 24
Peak memory 216224 kb
Host smart-aece1817-8167-4f19-901c-6d50a848226e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19219306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.19219306
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1494529867
Short name T127
Test name
Test status
Simulation time 313398462 ps
CPU time 1.64 seconds
Started May 05 12:23:46 PM PDT 24
Finished May 05 12:23:48 PM PDT 24
Peak memory 197956 kb
Host smart-d2a6a211-b468-454a-8c4a-cfe3c8c0f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494529867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1494529867
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1686052182
Short name T419
Test name
Test status
Simulation time 3723422759 ps
CPU time 101.96 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:25:35 PM PDT 24
Peak memory 199380 kb
Host smart-b64fd4e1-a9d0-472c-8d19-b80e02ae79db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686052182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1686052182
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1961542536
Short name T405
Test name
Test status
Simulation time 5571908698 ps
CPU time 77.05 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:21:26 PM PDT 24
Peak memory 199892 kb
Host smart-5a09ee91-57e2-4558-b433-d80d62d87dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961542536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1961542536
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4289858764
Short name T439
Test name
Test status
Simulation time 183822697 ps
CPU time 1.09 seconds
Started May 05 12:20:08 PM PDT 24
Finished May 05 12:20:09 PM PDT 24
Peak memory 199496 kb
Host smart-f368bd13-65b0-4121-bea3-113d8da88f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289858764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4289858764
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2990072694
Short name T440
Test name
Test status
Simulation time 219157627 ps
CPU time 1.28 seconds
Started May 05 12:20:15 PM PDT 24
Finished May 05 12:20:17 PM PDT 24
Peak memory 199788 kb
Host smart-4a37bb86-400b-4421-92b8-01a328aa2313
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990072694 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2990072694
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3518271911
Short name T263
Test name
Test status
Simulation time 55225835111 ps
CPU time 451.13 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:32:16 PM PDT 24
Peak memory 199408 kb
Host smart-36e548a1-1da1-4c27-a483-04bbf696047f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518271911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3518271911
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1991474591
Short name T228
Test name
Test status
Simulation time 552727562 ps
CPU time 7.19 seconds
Started May 05 12:19:59 PM PDT 24
Finished May 05 12:20:07 PM PDT 24
Peak memory 216068 kb
Host smart-c87e8dd8-2c15-4633-aa5a-bd0655bfc14e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991474591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1991474591
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1908158372
Short name T307
Test name
Test status
Simulation time 578080663 ps
CPU time 30.59 seconds
Started May 05 12:24:00 PM PDT 24
Finished May 05 12:24:32 PM PDT 24
Peak memory 199708 kb
Host smart-9d944026-f3c6-4bbe-9dda-383268bbb699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908158372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1908158372
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.999298859
Short name T297
Test name
Test status
Simulation time 6069636426 ps
CPU time 80 seconds
Started May 05 12:23:46 PM PDT 24
Finished May 05 12:25:07 PM PDT 24
Peak memory 197712 kb
Host smart-95786ef5-7329-4ee3-8e3c-3992f99e0feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999298859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.999298859
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.317335377
Short name T13
Test name
Test status
Simulation time 21653063352 ps
CPU time 29.29 seconds
Started May 05 12:24:11 PM PDT 24
Finished May 05 12:24:45 PM PDT 24
Peak memory 199428 kb
Host smart-366cb4ce-9d47-45d4-b525-da9e22a21664
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317335377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.317335377
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2543383978
Short name T214
Test name
Test status
Simulation time 56146156746 ps
CPU time 54.06 seconds
Started May 05 12:21:44 PM PDT 24
Finished May 05 12:22:39 PM PDT 24
Peak memory 199924 kb
Host smart-9d30f81a-5d24-455a-bed3-8219c88e8b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543383978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2543383978
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3389237374
Short name T412
Test name
Test status
Simulation time 301037227 ps
CPU time 2.55 seconds
Started May 05 12:24:11 PM PDT 24
Finished May 05 12:24:18 PM PDT 24
Peak memory 199556 kb
Host smart-ab9171d6-dfbc-4662-87e2-4fd55450849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389237374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3389237374
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3382625763
Short name T275
Test name
Test status
Simulation time 71619971447 ps
CPU time 973.18 seconds
Started May 05 12:20:10 PM PDT 24
Finished May 05 12:36:24 PM PDT 24
Peak memory 199876 kb
Host smart-e059cf55-fe3f-4a47-a837-b06a29c73221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382625763 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3382625763
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3093653574
Short name T246
Test name
Test status
Simulation time 564072041 ps
CPU time 1.19 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:16 PM PDT 24
Peak memory 197680 kb
Host smart-1851e5e4-761e-48d4-a1b6-e74e167903a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093653574 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3093653574
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1308404293
Short name T211
Test name
Test status
Simulation time 197292123744 ps
CPU time 380.07 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:31:05 PM PDT 24
Peak memory 199592 kb
Host smart-1172625d-e737-4c4f-853c-58e2ee130343
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308404293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1308404293
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1603443677
Short name T256
Test name
Test status
Simulation time 48898852 ps
CPU time 0.58 seconds
Started May 05 12:20:57 PM PDT 24
Finished May 05 12:20:58 PM PDT 24
Peak memory 195540 kb
Host smart-595f4cca-6d54-45be-8f55-3e3c81819114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603443677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1603443677
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1869115588
Short name T209
Test name
Test status
Simulation time 2277557599 ps
CPU time 26.45 seconds
Started May 05 12:20:16 PM PDT 24
Finished May 05 12:20:43 PM PDT 24
Peak memory 224436 kb
Host smart-b6180cdc-f102-47b1-a769-126bc9756ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1869115588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1869115588
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1670152186
Short name T376
Test name
Test status
Simulation time 515525247 ps
CPU time 27.93 seconds
Started May 05 12:21:10 PM PDT 24
Finished May 05 12:21:38 PM PDT 24
Peak memory 199940 kb
Host smart-964f740b-89f7-4cd1-8df6-ebe29bc43658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670152186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1670152186
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3164765223
Short name T120
Test name
Test status
Simulation time 1450111750 ps
CPU time 14.47 seconds
Started May 05 12:24:09 PM PDT 24
Finished May 05 12:24:28 PM PDT 24
Peak memory 199788 kb
Host smart-7c5e4c98-ce90-4931-a404-cf0abec44639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164765223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3164765223
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4233683641
Short name T371
Test name
Test status
Simulation time 819594145 ps
CPU time 12.21 seconds
Started May 05 12:22:24 PM PDT 24
Finished May 05 12:22:37 PM PDT 24
Peak memory 199836 kb
Host smart-49f2942d-0004-48bc-8daf-a874e934449c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233683641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4233683641
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3096089597
Short name T370
Test name
Test status
Simulation time 756000090 ps
CPU time 2.8 seconds
Started May 05 12:20:16 PM PDT 24
Finished May 05 12:20:20 PM PDT 24
Peak memory 199876 kb
Host smart-70e68df9-b21a-4697-9d1b-85469c998d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096089597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3096089597
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3516719122
Short name T400
Test name
Test status
Simulation time 29172026 ps
CPU time 0.95 seconds
Started May 05 12:20:47 PM PDT 24
Finished May 05 12:20:49 PM PDT 24
Peak memory 198788 kb
Host smart-c3216466-9538-43e6-9d07-ceac473fc583
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516719122 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3516719122
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3592007447
Short name T293
Test name
Test status
Simulation time 31962488592 ps
CPU time 413.75 seconds
Started May 05 12:21:04 PM PDT 24
Finished May 05 12:27:59 PM PDT 24
Peak memory 199940 kb
Host smart-37bb09ba-1a56-4319-b10d-4fa2e4ab7bdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592007447 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.3592007447
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.652854236
Short name T288
Test name
Test status
Simulation time 43065461 ps
CPU time 0.61 seconds
Started May 05 12:21:22 PM PDT 24
Finished May 05 12:21:23 PM PDT 24
Peak memory 195276 kb
Host smart-2cbe6bbf-bd6f-4eaf-bbf5-d729696894c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652854236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.652854236
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3176734106
Short name T349
Test name
Test status
Simulation time 1053859302 ps
CPU time 18.7 seconds
Started May 05 12:21:04 PM PDT 24
Finished May 05 12:21:24 PM PDT 24
Peak memory 225132 kb
Host smart-a8ee060c-8936-4f1e-a8be-da89abe67a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176734106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3176734106
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1402772190
Short name T331
Test name
Test status
Simulation time 7336568213 ps
CPU time 54.29 seconds
Started May 05 12:20:55 PM PDT 24
Finished May 05 12:21:50 PM PDT 24
Peak memory 200008 kb
Host smart-45197e6b-d1da-415e-84c2-307d702d84c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402772190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1402772190
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.237894552
Short name T317
Test name
Test status
Simulation time 6666223896 ps
CPU time 91.78 seconds
Started May 05 12:20:26 PM PDT 24
Finished May 05 12:21:59 PM PDT 24
Peak memory 199908 kb
Host smart-fe4357f5-e8dc-4f92-8806-1ffa6b2bd50b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237894552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.237894552
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.915058052
Short name T427
Test name
Test status
Simulation time 260070478 ps
CPU time 3.04 seconds
Started May 05 12:20:54 PM PDT 24
Finished May 05 12:20:58 PM PDT 24
Peak memory 199876 kb
Host smart-3f8efb8b-b94c-45fa-9b88-66142dd1f2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915058052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.915058052
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1044259178
Short name T413
Test name
Test status
Simulation time 310860316 ps
CPU time 3.72 seconds
Started May 05 12:20:20 PM PDT 24
Finished May 05 12:20:24 PM PDT 24
Peak memory 199840 kb
Host smart-c3bd61c3-dbe2-4e4a-b92c-601ad2280ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044259178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1044259178
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3851978135
Short name T157
Test name
Test status
Simulation time 45105846 ps
CPU time 1.06 seconds
Started May 05 12:21:22 PM PDT 24
Finished May 05 12:21:24 PM PDT 24
Peak memory 199196 kb
Host smart-597d757c-6688-4bc8-81fd-76f538a4cc4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851978135 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3851978135
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.218398251
Short name T169
Test name
Test status
Simulation time 573303677806 ps
CPU time 490.33 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:32:17 PM PDT 24
Peak memory 198688 kb
Host smart-d85d8121-d0a2-42b8-9256-d86241090bc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218398251 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.218398251
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_alert_test.742591698
Short name T122
Test name
Test status
Simulation time 16388195 ps
CPU time 0.59 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:24:36 PM PDT 24
Peak memory 195100 kb
Host smart-7520af73-609f-4179-899a-137d3d2d4317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742591698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.742591698
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3198516999
Short name T392
Test name
Test status
Simulation time 470027554 ps
CPU time 25.15 seconds
Started May 05 12:20:45 PM PDT 24
Finished May 05 12:21:11 PM PDT 24
Peak memory 240860 kb
Host smart-1316b0f6-377f-463b-b9db-7d0412b13ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198516999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3198516999
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.550912858
Short name T472
Test name
Test status
Simulation time 1173816302 ps
CPU time 14.05 seconds
Started May 05 12:24:25 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 198084 kb
Host smart-604e49a3-7257-42b6-9044-5633f859ac0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550912858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.550912858
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1844411515
Short name T470
Test name
Test status
Simulation time 1139964334 ps
CPU time 19.24 seconds
Started May 05 12:22:04 PM PDT 24
Finished May 05 12:22:24 PM PDT 24
Peak memory 199888 kb
Host smart-20d7345f-1941-4f33-b70a-a24701930dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844411515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1844411515
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3694331040
Short name T12
Test name
Test status
Simulation time 4386094874 ps
CPU time 14.5 seconds
Started May 05 12:24:00 PM PDT 24
Finished May 05 12:24:16 PM PDT 24
Peak memory 198356 kb
Host smart-bb6773c8-241c-4b5d-a052-6e4ba676d56c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694331040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3694331040
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1109245696
Short name T229
Test name
Test status
Simulation time 4983293791 ps
CPU time 90.56 seconds
Started May 05 12:24:00 PM PDT 24
Finished May 05 12:25:32 PM PDT 24
Peak memory 198488 kb
Host smart-133fc682-c927-4492-9477-955e7a308979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109245696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1109245696
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3390191565
Short name T131
Test name
Test status
Simulation time 51654794 ps
CPU time 0.97 seconds
Started May 05 12:21:20 PM PDT 24
Finished May 05 12:21:22 PM PDT 24
Peak memory 199656 kb
Host smart-8068c76b-f4fd-48d2-bb9b-7507a29b0b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390191565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3390191565
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2962564077
Short name T303
Test name
Test status
Simulation time 233969038 ps
CPU time 1.35 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:03 PM PDT 24
Peak memory 199252 kb
Host smart-11b538f7-adfc-46e6-a61e-11acf9f9d4e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962564077 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2962564077
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1361521223
Short name T402
Test name
Test status
Simulation time 7967793533 ps
CPU time 420.7 seconds
Started May 05 12:24:25 PM PDT 24
Finished May 05 12:31:27 PM PDT 24
Peak memory 198208 kb
Host smart-b6fc91e9-292e-4c52-bf69-d6ce9d58803f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361521223 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.1361521223
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3102220084
Short name T141
Test name
Test status
Simulation time 23598177 ps
CPU time 0.58 seconds
Started May 05 12:20:49 PM PDT 24
Finished May 05 12:20:50 PM PDT 24
Peak memory 195312 kb
Host smart-9e183d7c-ef91-4e83-98d8-f99d486ed4b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102220084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3102220084
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.834211125
Short name T408
Test name
Test status
Simulation time 7777958477 ps
CPU time 31.68 seconds
Started May 05 12:25:01 PM PDT 24
Finished May 05 12:25:35 PM PDT 24
Peak memory 225400 kb
Host smart-d6a10749-fb23-46da-91aa-bc2221900d01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834211125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.834211125
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1862256772
Short name T351
Test name
Test status
Simulation time 4593437849 ps
CPU time 52.75 seconds
Started May 05 12:21:06 PM PDT 24
Finished May 05 12:21:59 PM PDT 24
Peak memory 199924 kb
Host smart-4b10d3a6-ac6a-481d-a0f6-d21d477f044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862256772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1862256772
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3188760798
Short name T231
Test name
Test status
Simulation time 12937462447 ps
CPU time 130.72 seconds
Started May 05 12:21:04 PM PDT 24
Finished May 05 12:23:16 PM PDT 24
Peak memory 199920 kb
Host smart-587ce183-95d0-4f65-b069-5a804da643e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188760798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3188760798
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_long_msg.886998560
Short name T435
Test name
Test status
Simulation time 22639599651 ps
CPU time 84.41 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:26:00 PM PDT 24
Peak memory 199556 kb
Host smart-dfc08fc4-05cd-4ae0-9161-931119cbdf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886998560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.886998560
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2916374205
Short name T460
Test name
Test status
Simulation time 38139094 ps
CPU time 0.86 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:03 PM PDT 24
Peak memory 197772 kb
Host smart-c8ffeadb-6348-463c-84a9-d0269ac672a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916374205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2916374205
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2545817650
Short name T216
Test name
Test status
Simulation time 136776865 ps
CPU time 1.33 seconds
Started May 05 12:20:50 PM PDT 24
Finished May 05 12:20:52 PM PDT 24
Peak memory 199948 kb
Host smart-57683807-e25f-4e12-b6dd-584ef3198cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545817650 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2545817650
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1075630164
Short name T388
Test name
Test status
Simulation time 113296474699 ps
CPU time 509.23 seconds
Started May 05 12:20:47 PM PDT 24
Finished May 05 12:29:16 PM PDT 24
Peak memory 199948 kb
Host smart-b6c557cf-fc77-49e5-aea3-c5c0e1af2f1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075630164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1075630164
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.952904913
Short name T222
Test name
Test status
Simulation time 61672815 ps
CPU time 0.55 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:23:55 PM PDT 24
Peak memory 195120 kb
Host smart-2d1040fc-84d6-430b-a46e-df3fa03b6490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952904913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.952904913
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1917813727
Short name T287
Test name
Test status
Simulation time 1188389806 ps
CPU time 37.93 seconds
Started May 05 12:24:00 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 232776 kb
Host smart-381462c3-5464-4765-8b70-f31d96f0e8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917813727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1917813727
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2496154378
Short name T110
Test name
Test status
Simulation time 6212197342 ps
CPU time 23.47 seconds
Started May 05 12:22:31 PM PDT 24
Finished May 05 12:22:55 PM PDT 24
Peak memory 200048 kb
Host smart-a7ce534a-5e9a-4ae9-8743-4e6c74d7911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496154378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2496154378
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.457833704
Short name T241
Test name
Test status
Simulation time 626836690 ps
CPU time 24.51 seconds
Started May 05 12:24:45 PM PDT 24
Finished May 05 12:25:10 PM PDT 24
Peak memory 199764 kb
Host smart-d9ebf0d6-0955-4cc3-8a67-88a830717b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457833704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.457833704
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3710328657
Short name T202
Test name
Test status
Simulation time 8650682678 ps
CPU time 27.76 seconds
Started May 05 12:23:47 PM PDT 24
Finished May 05 12:24:16 PM PDT 24
Peak memory 199484 kb
Host smart-70b9a32b-b343-4b2b-a3f7-3de74f934957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710328657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3710328657
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3528562824
Short name T31
Test name
Test status
Simulation time 37115579 ps
CPU time 0.81 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 217972 kb
Host smart-cbe5ade8-97f4-440b-bc08-3a6202c57b51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528562824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3528562824
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1641311192
Short name T425
Test name
Test status
Simulation time 1089760542 ps
CPU time 3.97 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:24:50 PM PDT 24
Peak memory 199732 kb
Host smart-8ace1b50-d30f-4279-af46-e8cc13a4c8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641311192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1641311192
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2255446160
Short name T161
Test name
Test status
Simulation time 111026248 ps
CPU time 1.24 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 199372 kb
Host smart-e975afd6-26f5-47af-81d9-e3b4aaee8d73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255446160 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2255446160
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.1946312021
Short name T176
Test name
Test status
Simulation time 57674739324 ps
CPU time 454.75 seconds
Started May 05 12:23:55 PM PDT 24
Finished May 05 12:31:31 PM PDT 24
Peak memory 198636 kb
Host smart-63757c5f-308e-42bb-a33c-4c083615aad0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946312021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.1946312021
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3687026177
Short name T295
Test name
Test status
Simulation time 21876829 ps
CPU time 0.58 seconds
Started May 05 12:21:02 PM PDT 24
Finished May 05 12:21:03 PM PDT 24
Peak memory 195352 kb
Host smart-da3be544-a68f-48fb-ad94-b1b69df40691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687026177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3687026177
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2051900817
Short name T181
Test name
Test status
Simulation time 101511921 ps
CPU time 3.54 seconds
Started May 05 12:20:55 PM PDT 24
Finished May 05 12:20:59 PM PDT 24
Peak memory 199792 kb
Host smart-f6e61cd5-4ca4-454a-b760-a2adffe824ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051900817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2051900817
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1325378604
Short name T156
Test name
Test status
Simulation time 884181201 ps
CPU time 3.62 seconds
Started May 05 12:21:02 PM PDT 24
Finished May 05 12:21:06 PM PDT 24
Peak memory 199968 kb
Host smart-6849cd3c-0561-4080-9bdf-66fe5fcc08c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325378604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1325378604
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3103652722
Short name T285
Test name
Test status
Simulation time 18547058822 ps
CPU time 61.42 seconds
Started May 05 12:25:04 PM PDT 24
Finished May 05 12:26:07 PM PDT 24
Peak memory 199776 kb
Host smart-99608577-0ecf-4b38-9e32-a879f7c64c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103652722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3103652722
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.69773834
Short name T304
Test name
Test status
Simulation time 310021170 ps
CPU time 0.85 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:05 PM PDT 24
Peak memory 196688 kb
Host smart-b0e221f5-d2fb-4405-a8b0-484c7297643d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69773834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.69773834
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3785391952
Short name T225
Test name
Test status
Simulation time 6173720660 ps
CPU time 84.44 seconds
Started May 05 12:21:04 PM PDT 24
Finished May 05 12:22:29 PM PDT 24
Peak memory 199896 kb
Host smart-5bf3176e-2d5b-4dc1-abf6-7d64a6abd42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785391952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3785391952
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3785933507
Short name T179
Test name
Test status
Simulation time 927189437 ps
CPU time 7.1 seconds
Started May 05 12:21:19 PM PDT 24
Finished May 05 12:21:27 PM PDT 24
Peak memory 199864 kb
Host smart-063be875-0b60-487f-9144-0ab192c7b99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785933507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3785933507
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.965228540
Short name T71
Test name
Test status
Simulation time 465703193625 ps
CPU time 536.96 seconds
Started May 05 12:22:39 PM PDT 24
Finished May 05 12:31:37 PM PDT 24
Peak memory 199884 kb
Host smart-b45af5ff-6013-4e9f-a368-d90d59953583
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965228540 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.965228540
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.491104439
Short name T115
Test name
Test status
Simulation time 25915227 ps
CPU time 0.98 seconds
Started May 05 12:22:32 PM PDT 24
Finished May 05 12:22:33 PM PDT 24
Peak memory 197996 kb
Host smart-be251764-ac47-41cf-9623-7104ec30a9fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491104439 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.491104439
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3097200141
Short name T353
Test name
Test status
Simulation time 55534548965 ps
CPU time 487.74 seconds
Started May 05 12:21:02 PM PDT 24
Finished May 05 12:29:11 PM PDT 24
Peak memory 200040 kb
Host smart-1769207b-8b61-40cd-a1f9-72d2df358acc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097200141 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3097200141
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.217340868
Short name T147
Test name
Test status
Simulation time 26439864 ps
CPU time 0.65 seconds
Started May 05 12:21:01 PM PDT 24
Finished May 05 12:21:02 PM PDT 24
Peak memory 195556 kb
Host smart-790bbc72-2d55-4f49-96ce-ac6a72ffe717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217340868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.217340868
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1049400788
Short name T8
Test name
Test status
Simulation time 638943343 ps
CPU time 34.21 seconds
Started May 05 12:21:02 PM PDT 24
Finished May 05 12:21:37 PM PDT 24
Peak memory 224432 kb
Host smart-6fec290b-e30d-4f00-94d4-5d945fc7b2f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049400788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1049400788
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2062489305
Short name T114
Test name
Test status
Simulation time 2908553494 ps
CPU time 27.52 seconds
Started May 05 12:24:02 PM PDT 24
Finished May 05 12:24:31 PM PDT 24
Peak memory 198284 kb
Host smart-044d180a-12c4-4a13-a039-e511d18117be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062489305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2062489305
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1364734788
Short name T347
Test name
Test status
Simulation time 3745001521 ps
CPU time 109.01 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:25:51 PM PDT 24
Peak memory 199440 kb
Host smart-9e6ea0ef-2d01-42fc-acd4-c1f6a016d179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364734788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1364734788
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2206858051
Short name T172
Test name
Test status
Simulation time 562897242 ps
CPU time 31.78 seconds
Started May 05 12:23:50 PM PDT 24
Finished May 05 12:24:23 PM PDT 24
Peak memory 198164 kb
Host smart-3784a1ab-6d03-42d5-99fc-e187289ec2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206858051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2206858051
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3430073183
Short name T436
Test name
Test status
Simulation time 498113882 ps
CPU time 7.68 seconds
Started May 05 12:21:44 PM PDT 24
Finished May 05 12:21:53 PM PDT 24
Peak memory 199876 kb
Host smart-61aba85b-1327-423e-af85-760329b87884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430073183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3430073183
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.795618136
Short name T134
Test name
Test status
Simulation time 180056347 ps
CPU time 1.21 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 199288 kb
Host smart-c9c773a1-1577-4fd3-aa3d-17a336c38a6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795618136 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.795618136
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2557475614
Short name T274
Test name
Test status
Simulation time 15242798726 ps
CPU time 399.25 seconds
Started May 05 12:21:44 PM PDT 24
Finished May 05 12:28:25 PM PDT 24
Peak memory 199944 kb
Host smart-70251a20-2706-4237-a90b-9738bc88f7b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557475614 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2557475614
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3720911230
Short name T359
Test name
Test status
Simulation time 39734978 ps
CPU time 0.62 seconds
Started May 05 12:24:49 PM PDT 24
Finished May 05 12:24:52 PM PDT 24
Peak memory 193516 kb
Host smart-b20a5305-758e-4aa8-9129-a492c7e6fe74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720911230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3720911230
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2091040717
Short name T352
Test name
Test status
Simulation time 127123200 ps
CPU time 1.82 seconds
Started May 05 12:20:59 PM PDT 24
Finished May 05 12:21:02 PM PDT 24
Peak memory 208024 kb
Host smart-d06573ed-a20e-45f8-8706-03eff06ec695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091040717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2091040717
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.830628195
Short name T111
Test name
Test status
Simulation time 314586285 ps
CPU time 15.33 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:25 PM PDT 24
Peak memory 199524 kb
Host smart-34b43ece-dcfa-4cc4-b474-16c78fe9e53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830628195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.830628195
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2922411814
Short name T151
Test name
Test status
Simulation time 1168201383 ps
CPU time 17.1 seconds
Started May 05 12:21:07 PM PDT 24
Finished May 05 12:21:25 PM PDT 24
Peak memory 199836 kb
Host smart-06591bba-7f58-4595-aaee-7401985691a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922411814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2922411814
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4005110442
Short name T305
Test name
Test status
Simulation time 14125913214 ps
CPU time 51.36 seconds
Started May 05 12:22:41 PM PDT 24
Finished May 05 12:23:33 PM PDT 24
Peak memory 200032 kb
Host smart-5769dc95-7041-4378-95d0-99f39ebfe4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005110442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4005110442
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1086593954
Short name T265
Test name
Test status
Simulation time 328720143 ps
CPU time 3.81 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:06 PM PDT 24
Peak memory 199536 kb
Host smart-a0b4943f-2722-4b7b-84a9-ed2ef25e5c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086593954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1086593954
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1527238427
Short name T257
Test name
Test status
Simulation time 319628627 ps
CPU time 1.22 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 199320 kb
Host smart-8b129dfc-d68b-4821-aff1-b0792114c5a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527238427 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1527238427
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.4264903220
Short name T210
Test name
Test status
Simulation time 52752787298 ps
CPU time 433.99 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:31:07 PM PDT 24
Peak memory 199576 kb
Host smart-d9bdbb22-8d08-4843-b928-b2f3e3ce0da1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264903220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.4264903220
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1764464602
Short name T40
Test name
Test status
Simulation time 95556335 ps
CPU time 0.59 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:05 PM PDT 24
Peak memory 194084 kb
Host smart-20672d07-8508-4a87-ae34-390d28f76ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764464602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1764464602
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2827284760
Short name T420
Test name
Test status
Simulation time 746177957 ps
CPU time 38.39 seconds
Started May 05 12:24:08 PM PDT 24
Finished May 05 12:24:52 PM PDT 24
Peak memory 222364 kb
Host smart-649071c8-6960-471e-9fe9-f29099c5102e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827284760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2827284760
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.130696303
Short name T299
Test name
Test status
Simulation time 1433740721 ps
CPU time 14.34 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:22 PM PDT 24
Peak memory 198628 kb
Host smart-bcfa3671-1e54-4326-a509-3ad0bd3183cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130696303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.130696303
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.982686164
Short name T387
Test name
Test status
Simulation time 1061317378 ps
CPU time 55.05 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:25:30 PM PDT 24
Peak memory 198980 kb
Host smart-39970f4a-4a83-49a6-8406-9829c62e642d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=982686164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.982686164
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1542051562
Short name T457
Test name
Test status
Simulation time 19095287164 ps
CPU time 86.87 seconds
Started May 05 12:24:07 PM PDT 24
Finished May 05 12:25:40 PM PDT 24
Peak memory 199556 kb
Host smart-f4b35bd1-cf20-4811-b02c-929db7fbe161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542051562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1542051562
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.220726325
Short name T64
Test name
Test status
Simulation time 185251478 ps
CPU time 3.12 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 197384 kb
Host smart-48851b86-301f-4332-a3c2-a60a888275c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220726325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.220726325
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1706136150
Short name T148
Test name
Test status
Simulation time 99017217 ps
CPU time 1.17 seconds
Started May 05 12:21:15 PM PDT 24
Finished May 05 12:21:17 PM PDT 24
Peak memory 199200 kb
Host smart-ece05c2b-3f1a-4f8a-9d1e-b030f07db55f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706136150 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1706136150
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1964986487
Short name T170
Test name
Test status
Simulation time 178882505947 ps
CPU time 515.56 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:33:11 PM PDT 24
Peak memory 199568 kb
Host smart-40355d07-356c-49da-a04d-0d3b5420018b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964986487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1964986487
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1331581776
Short name T63
Test name
Test status
Simulation time 34852490 ps
CPU time 0.52 seconds
Started May 05 12:24:07 PM PDT 24
Finished May 05 12:24:13 PM PDT 24
Peak memory 193996 kb
Host smart-3d4b8701-f915-42a0-a16d-93805fd9858d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331581776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1331581776
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4207266244
Short name T421
Test name
Test status
Simulation time 851785029 ps
CPU time 40.26 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:48 PM PDT 24
Peak memory 225976 kb
Host smart-c3a5a4b8-315b-4618-8b91-d70e2aa48694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207266244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4207266244
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2483478369
Short name T207
Test name
Test status
Simulation time 7069534893 ps
CPU time 37.01 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:45 PM PDT 24
Peak memory 199448 kb
Host smart-3f09a254-7919-4fe7-a3dc-7f75e16f4ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483478369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2483478369
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3772537147
Short name T130
Test name
Test status
Simulation time 4103969286 ps
CPU time 100.94 seconds
Started May 05 12:24:50 PM PDT 24
Finished May 05 12:26:34 PM PDT 24
Peak memory 199600 kb
Host smart-5559663e-8c77-4096-ad23-1f2bae6a376e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772537147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3772537147
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3348638144
Short name T324
Test name
Test status
Simulation time 593085405 ps
CPU time 32.65 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 198196 kb
Host smart-4aaf7349-ff5c-41df-8cf9-165ffe0c51af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348638144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3348638144
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.838560121
Short name T378
Test name
Test status
Simulation time 414078576 ps
CPU time 3.78 seconds
Started May 05 12:21:13 PM PDT 24
Finished May 05 12:21:17 PM PDT 24
Peak memory 199840 kb
Host smart-2fd555ff-8bcb-44d2-a3ee-61f102a13703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838560121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.838560121
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3309898032
Short name T306
Test name
Test status
Simulation time 100368902 ps
CPU time 0.97 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 199268 kb
Host smart-d3b3092e-cb4f-4830-b61a-0b4aea91f895
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309898032 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3309898032
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3793310836
Short name T3
Test name
Test status
Simulation time 119243977227 ps
CPU time 474.55 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:32:30 PM PDT 24
Peak memory 199652 kb
Host smart-69fde202-4e5f-447f-8eaf-a8a223cc4379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793310836 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3793310836
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2213145351
Short name T121
Test name
Test status
Simulation time 11571667 ps
CPU time 0.59 seconds
Started May 05 12:21:27 PM PDT 24
Finished May 05 12:21:28 PM PDT 24
Peak memory 195360 kb
Host smart-a52be65e-9aaa-480d-b74e-b28df39d1e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213145351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2213145351
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3450640096
Short name T166
Test name
Test status
Simulation time 86907205 ps
CPU time 1.23 seconds
Started May 05 12:24:14 PM PDT 24
Finished May 05 12:24:19 PM PDT 24
Peak memory 198664 kb
Host smart-d89c8169-ad11-4343-b149-4a3fcf93ed85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450640096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3450640096
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2135101818
Short name T244
Test name
Test status
Simulation time 1274646388 ps
CPU time 32.8 seconds
Started May 05 12:23:55 PM PDT 24
Finished May 05 12:24:29 PM PDT 24
Peak memory 198664 kb
Host smart-955a7653-b235-4540-a151-698495799ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135101818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2135101818
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.909455933
Short name T186
Test name
Test status
Simulation time 1731406819 ps
CPU time 87.31 seconds
Started May 05 12:23:55 PM PDT 24
Finished May 05 12:25:24 PM PDT 24
Peak memory 198444 kb
Host smart-46d68b59-5f87-47b8-8a49-75de51194451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909455933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.909455933
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1969567052
Short name T219
Test name
Test status
Simulation time 980772988 ps
CPU time 15.61 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:30 PM PDT 24
Peak memory 199768 kb
Host smart-5e8e3e01-a911-469b-a67e-310aafde80fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969567052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1969567052
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3428413298
Short name T247
Test name
Test status
Simulation time 352888148 ps
CPU time 5.41 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:13 PM PDT 24
Peak memory 197444 kb
Host smart-4b9e8aeb-517f-407f-93ba-1f3416fbc8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428413298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3428413298
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1967651641
Short name T266
Test name
Test status
Simulation time 49678461 ps
CPU time 1.03 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:15 PM PDT 24
Peak memory 198188 kb
Host smart-6e282d6f-ccb3-40aa-a575-c0c8a4468830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967651641 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1967651641
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3221108982
Short name T316
Test name
Test status
Simulation time 38225967844 ps
CPU time 506.62 seconds
Started May 05 12:21:23 PM PDT 24
Finished May 05 12:29:51 PM PDT 24
Peak memory 200224 kb
Host smart-39220c03-3a9d-4c33-b653-0a4799e6570f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221108982 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3221108982
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2429754406
Short name T143
Test name
Test status
Simulation time 12256153 ps
CPU time 0.58 seconds
Started May 05 12:21:39 PM PDT 24
Finished May 05 12:21:40 PM PDT 24
Peak memory 195344 kb
Host smart-4c0cdb9a-40f2-4a68-969c-585db5ad92ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429754406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2429754406
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4106956139
Short name T5
Test name
Test status
Simulation time 752832032 ps
CPU time 41.98 seconds
Started May 05 12:21:29 PM PDT 24
Finished May 05 12:22:12 PM PDT 24
Peak memory 232204 kb
Host smart-4a240b8d-8b2f-459b-acb6-bb12c8c42ddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106956139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4106956139
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2074075481
Short name T330
Test name
Test status
Simulation time 14897207752 ps
CPU time 35.29 seconds
Started May 05 12:23:41 PM PDT 24
Finished May 05 12:24:17 PM PDT 24
Peak memory 199532 kb
Host smart-e4c4249c-4cb3-49f0-8820-ef5467dd9c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074075481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2074075481
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4294128643
Short name T430
Test name
Test status
Simulation time 458549344 ps
CPU time 27.18 seconds
Started May 05 12:21:27 PM PDT 24
Finished May 05 12:21:54 PM PDT 24
Peak memory 199816 kb
Host smart-ba69174d-282d-41bb-9384-4891b2c79c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294128643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4294128643
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2067815876
Short name T390
Test name
Test status
Simulation time 17318234396 ps
CPU time 82.31 seconds
Started May 05 12:21:45 PM PDT 24
Finished May 05 12:23:08 PM PDT 24
Peak memory 199924 kb
Host smart-6f4be60d-2650-4cf7-a2f5-d69530dce5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067815876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2067815876
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.384054792
Short name T332
Test name
Test status
Simulation time 16701560 ps
CPU time 0.83 seconds
Started May 05 12:23:42 PM PDT 24
Finished May 05 12:23:43 PM PDT 24
Peak memory 196276 kb
Host smart-bff1ebfc-63b7-4eee-b014-3a7a1a73e78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384054792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.384054792
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.848878873
Short name T354
Test name
Test status
Simulation time 57408777 ps
CPU time 1.19 seconds
Started May 05 12:24:45 PM PDT 24
Finished May 05 12:24:47 PM PDT 24
Peak memory 199736 kb
Host smart-a6642418-86fe-411a-8840-15c96acb6d37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848878873 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.848878873
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1115703388
Short name T338
Test name
Test status
Simulation time 116608992726 ps
CPU time 369.91 seconds
Started May 05 12:23:42 PM PDT 24
Finished May 05 12:29:53 PM PDT 24
Peak memory 198436 kb
Host smart-eec8324f-a4e1-425a-8757-23678d9bb0c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115703388 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1115703388
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1591248808
Short name T150
Test name
Test status
Simulation time 11862565 ps
CPU time 0.57 seconds
Started May 05 12:21:30 PM PDT 24
Finished May 05 12:21:32 PM PDT 24
Peak memory 195228 kb
Host smart-5dfed72a-6c20-4ca1-875e-60087a65182c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591248808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1591248808
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1191883061
Short name T431
Test name
Test status
Simulation time 4079360581 ps
CPU time 57.29 seconds
Started May 05 12:23:42 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 239492 kb
Host smart-179b8f32-dfe2-46a5-b719-4a38560c4938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191883061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1191883061
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.531352246
Short name T206
Test name
Test status
Simulation time 1498230816 ps
CPU time 8.29 seconds
Started May 05 12:22:49 PM PDT 24
Finished May 05 12:22:58 PM PDT 24
Peak memory 199992 kb
Host smart-c77ae28d-dd49-4b36-bfc1-f7943c212f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531352246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.531352246
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2082102718
Short name T135
Test name
Test status
Simulation time 1996205564 ps
CPU time 119.27 seconds
Started May 05 12:21:29 PM PDT 24
Finished May 05 12:23:28 PM PDT 24
Peak memory 199844 kb
Host smart-724db17a-adf0-42c4-ad5c-d821ae4909e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082102718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2082102718
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1829965345
Short name T367
Test name
Test status
Simulation time 137001304 ps
CPU time 7.59 seconds
Started May 05 12:21:31 PM PDT 24
Finished May 05 12:21:39 PM PDT 24
Peak memory 199848 kb
Host smart-ba43ad3f-5841-4ea5-8210-cd2c50e7149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829965345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1829965345
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3349795104
Short name T67
Test name
Test status
Simulation time 115876100 ps
CPU time 2.11 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:36 PM PDT 24
Peak memory 199772 kb
Host smart-45df2084-483e-4d27-85b3-22c5fedcaebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349795104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3349795104
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.793225834
Short name T283
Test name
Test status
Simulation time 256701128 ps
CPU time 1.2 seconds
Started May 05 12:23:43 PM PDT 24
Finished May 05 12:23:45 PM PDT 24
Peak memory 198448 kb
Host smart-c7f0ba2a-d5c1-401d-a6b8-d9bc7f3b3561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793225834 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.793225834
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3342597267
Short name T252
Test name
Test status
Simulation time 149108065995 ps
CPU time 432.14 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:31:45 PM PDT 24
Peak memory 199836 kb
Host smart-4e81e14f-e4f2-4f3c-ad8a-2ce5aa6d62c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342597267 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.3342597267
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3492579862
Short name T444
Test name
Test status
Simulation time 48265863 ps
CPU time 0.59 seconds
Started May 05 12:22:03 PM PDT 24
Finished May 05 12:22:05 PM PDT 24
Peak memory 195220 kb
Host smart-25e5f33d-9885-4f95-a8e4-a2a742a1c8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492579862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3492579862
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3482464551
Short name T311
Test name
Test status
Simulation time 1848596804 ps
CPU time 9.64 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:19 PM PDT 24
Peak memory 199588 kb
Host smart-c8d1e8fe-8d4a-4051-afe4-36ba9af260be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482464551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3482464551
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.4096065032
Short name T432
Test name
Test status
Simulation time 4755596044 ps
CPU time 38.96 seconds
Started May 05 12:22:16 PM PDT 24
Finished May 05 12:22:55 PM PDT 24
Peak memory 199992 kb
Host smart-d1a89b5a-18c1-468a-90e1-554f01b27578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096065032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.4096065032
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3352670050
Short name T369
Test name
Test status
Simulation time 2250347417 ps
CPU time 64.64 seconds
Started May 05 12:21:38 PM PDT 24
Finished May 05 12:22:43 PM PDT 24
Peak memory 199904 kb
Host smart-c88a0f62-959a-4556-b5f3-29e66113a0be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352670050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3352670050
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.898451298
Short name T291
Test name
Test status
Simulation time 3657724768 ps
CPU time 23.1 seconds
Started May 05 12:23:57 PM PDT 24
Finished May 05 12:24:21 PM PDT 24
Peak memory 198188 kb
Host smart-eaf8fb6c-9533-48a0-af5b-9bddd646b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898451298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.898451298
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3614384857
Short name T215
Test name
Test status
Simulation time 302157352 ps
CPU time 1.4 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:24:10 PM PDT 24
Peak memory 199536 kb
Host smart-72d77563-d52d-4eaa-ab4b-9f642504bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614384857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3614384857
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.685971905
Short name T366
Test name
Test status
Simulation time 70101737 ps
CPU time 0.99 seconds
Started May 05 12:24:50 PM PDT 24
Finished May 05 12:24:54 PM PDT 24
Peak memory 198284 kb
Host smart-e4c7e68d-3f17-4299-b006-81dd7da483a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685971905 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.685971905
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2524827994
Short name T7
Test name
Test status
Simulation time 36997374054 ps
CPU time 452.95 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:31:43 PM PDT 24
Peak memory 199644 kb
Host smart-6ca9269a-4b4e-432c-8980-ba8701574e43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524827994 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2524827994
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4204426615
Short name T15
Test name
Test status
Simulation time 10671910 ps
CPU time 0.6 seconds
Started May 05 12:21:50 PM PDT 24
Finished May 05 12:21:51 PM PDT 24
Peak memory 194532 kb
Host smart-2cd6c23b-1507-43e6-a0f5-871819dadb9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204426615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4204426615
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3053293231
Short name T196
Test name
Test status
Simulation time 716229381 ps
CPU time 38.01 seconds
Started May 05 12:22:37 PM PDT 24
Finished May 05 12:23:16 PM PDT 24
Peak memory 216284 kb
Host smart-45d13fde-13fa-4a44-80c2-c401ec554fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053293231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3053293231
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1342798057
Short name T424
Test name
Test status
Simulation time 2887291341 ps
CPU time 54.37 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:25:02 PM PDT 24
Peak memory 199636 kb
Host smart-05887d1a-f7f8-4e76-9384-bf55c65efca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342798057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1342798057
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1717174086
Short name T187
Test name
Test status
Simulation time 5498794928 ps
CPU time 46.25 seconds
Started May 05 12:22:56 PM PDT 24
Finished May 05 12:23:43 PM PDT 24
Peak memory 199900 kb
Host smart-c66d4096-17c6-4e8d-af55-6a94d80efb99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717174086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1717174086
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2771335731
Short name T133
Test name
Test status
Simulation time 224112614 ps
CPU time 12.65 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:17 PM PDT 24
Peak memory 198036 kb
Host smart-62f5a4e0-bd52-4e32-8c3e-e75c859353f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771335731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2771335731
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2029467158
Short name T165
Test name
Test status
Simulation time 16005761812 ps
CPU time 62.25 seconds
Started May 05 12:21:45 PM PDT 24
Finished May 05 12:22:48 PM PDT 24
Peak memory 199948 kb
Host smart-cbe50d3f-a720-4a03-b36d-d390b6e99e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029467158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2029467158
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.546903743
Short name T357
Test name
Test status
Simulation time 455247467 ps
CPU time 4.2 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 197612 kb
Host smart-0848ff28-5980-420e-926b-26a6a81075ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546903743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.546903743
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3979637113
Short name T383
Test name
Test status
Simulation time 437248401 ps
CPU time 1.24 seconds
Started May 05 12:22:54 PM PDT 24
Finished May 05 12:22:56 PM PDT 24
Peak memory 198944 kb
Host smart-cdfce139-2297-42c2-bb16-20170d6f80d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979637113 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3979637113
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3664826676
Short name T205
Test name
Test status
Simulation time 82094537920 ps
CPU time 499.14 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:32:24 PM PDT 24
Peak memory 197672 kb
Host smart-eb95de51-4fef-464d-93a6-9dd1dd3e7869
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664826676 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3664826676
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3583602286
Short name T213
Test name
Test status
Simulation time 36988457 ps
CPU time 0.57 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:50 PM PDT 24
Peak memory 195264 kb
Host smart-72115cf2-7e26-4c9b-b009-8bd36ef22803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583602286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3583602286
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.957086938
Short name T113
Test name
Test status
Simulation time 1236730228 ps
CPU time 47.66 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:25:42 PM PDT 24
Peak memory 221928 kb
Host smart-11f6143a-d29d-4424-b5b4-01ac8b5d9486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957086938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.957086938
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.812575995
Short name T422
Test name
Test status
Simulation time 2487276945 ps
CPU time 13.63 seconds
Started May 05 12:22:37 PM PDT 24
Finished May 05 12:22:51 PM PDT 24
Peak memory 199964 kb
Host smart-4359bb1a-6117-4d79-9487-66ea850ddb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812575995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.812575995
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2282432084
Short name T212
Test name
Test status
Simulation time 9486476148 ps
CPU time 124.89 seconds
Started May 05 12:24:49 PM PDT 24
Finished May 05 12:26:56 PM PDT 24
Peak memory 197932 kb
Host smart-ae78f8b9-2732-4dc5-903b-117ca5c0f7fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282432084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2282432084
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.716130475
Short name T302
Test name
Test status
Simulation time 365293119 ps
CPU time 13.31 seconds
Started May 05 12:22:39 PM PDT 24
Finished May 05 12:22:52 PM PDT 24
Peak memory 199840 kb
Host smart-46cd8be5-a0d3-4fac-970d-99b0851640a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716130475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.716130475
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3840891036
Short name T30
Test name
Test status
Simulation time 66339283 ps
CPU time 0.93 seconds
Started May 05 12:20:13 PM PDT 24
Finished May 05 12:20:15 PM PDT 24
Peak memory 218016 kb
Host smart-951e7971-a322-4dbe-908d-edb11f8d9919
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840891036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3840891036
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.877419570
Short name T248
Test name
Test status
Simulation time 260461868 ps
CPU time 2.2 seconds
Started May 05 12:23:55 PM PDT 24
Finished May 05 12:23:59 PM PDT 24
Peak memory 198276 kb
Host smart-63f4531c-268c-4a86-973d-e8ea759dd471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877419570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.877419570
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3967287271
Short name T342
Test name
Test status
Simulation time 473981854 ps
CPU time 0.96 seconds
Started May 05 12:21:35 PM PDT 24
Finished May 05 12:21:36 PM PDT 24
Peak memory 198892 kb
Host smart-255191b9-0a28-43cb-b48f-7a0e52c078cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967287271 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3967287271
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3691350991
Short name T309
Test name
Test status
Simulation time 119226332419 ps
CPU time 427.13 seconds
Started May 05 12:24:12 PM PDT 24
Finished May 05 12:31:24 PM PDT 24
Peak memory 198688 kb
Host smart-e8491e88-9ca2-496c-987e-f85f1a59f1d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691350991 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3691350991
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2677259714
Short name T319
Test name
Test status
Simulation time 85473343 ps
CPU time 0.56 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:12 PM PDT 24
Peak memory 193500 kb
Host smart-9e8cc0a2-458b-4821-a22c-536814e00ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677259714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2677259714
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.227893223
Short name T49
Test name
Test status
Simulation time 822662289 ps
CPU time 37.49 seconds
Started May 05 12:21:52 PM PDT 24
Finished May 05 12:22:30 PM PDT 24
Peak memory 208196 kb
Host smart-d7d280aa-0cc0-4b5d-bb17-7bcd9026f588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227893223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.227893223
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3348414285
Short name T373
Test name
Test status
Simulation time 1120100395 ps
CPU time 10.07 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:27 PM PDT 24
Peak memory 199284 kb
Host smart-f40ba5fe-c517-4c2a-8b05-182348c00b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348414285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3348414285
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.747595983
Short name T326
Test name
Test status
Simulation time 5929545687 ps
CPU time 91.33 seconds
Started May 05 12:23:17 PM PDT 24
Finished May 05 12:24:49 PM PDT 24
Peak memory 199912 kb
Host smart-3222c7af-6bf8-43f4-8eae-8d744789c28a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747595983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.747595983
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.946591915
Short name T318
Test name
Test status
Simulation time 2522589022 ps
CPU time 75.68 seconds
Started May 05 12:22:52 PM PDT 24
Finished May 05 12:24:09 PM PDT 24
Peak memory 199908 kb
Host smart-21ce1a9c-2a1c-4d70-9a9e-100854df495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946591915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.946591915
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2254247276
Short name T468
Test name
Test status
Simulation time 1718316672 ps
CPU time 3.39 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:23:57 PM PDT 24
Peak memory 199388 kb
Host smart-b5471e76-1692-46db-a9e5-da35406fddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254247276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2254247276
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4096301871
Short name T117
Test name
Test status
Simulation time 286141750 ps
CPU time 0.95 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:23:55 PM PDT 24
Peak memory 198388 kb
Host smart-e83259ba-df85-48f6-b0a8-65fca4dac95d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096301871 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4096301871
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3066825789
Short name T254
Test name
Test status
Simulation time 123236096275 ps
CPU time 451.81 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:31:25 PM PDT 24
Peak memory 197788 kb
Host smart-b0fcf208-b240-4ccb-a3a1-2ccf7ea6c562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066825789 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3066825789
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2428092730
Short name T218
Test name
Test status
Simulation time 52879516 ps
CPU time 0.56 seconds
Started May 05 12:24:44 PM PDT 24
Finished May 05 12:24:46 PM PDT 24
Peak memory 195184 kb
Host smart-525a633f-6e0c-49fc-8abc-71d84fd4d958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428092730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2428092730
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2058358619
Short name T255
Test name
Test status
Simulation time 2733730638 ps
CPU time 19.06 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:31 PM PDT 24
Peak memory 199456 kb
Host smart-24ed8a11-d382-4a34-96fc-a2e2a3c403b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058358619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2058358619
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3253105700
Short name T418
Test name
Test status
Simulation time 905836674 ps
CPU time 40.87 seconds
Started May 05 12:21:53 PM PDT 24
Finished May 05 12:22:34 PM PDT 24
Peak memory 199840 kb
Host smart-7b643781-31eb-4e52-8aef-7461da8f4476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253105700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3253105700
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_error.1819661859
Short name T44
Test name
Test status
Simulation time 948056877 ps
CPU time 20.64 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:32 PM PDT 24
Peak memory 197492 kb
Host smart-08252d50-8c3f-46ce-9e4c-5d08eb60181b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819661859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1819661859
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1255405816
Short name T245
Test name
Test status
Simulation time 786920345 ps
CPU time 45.61 seconds
Started May 05 12:22:20 PM PDT 24
Finished May 05 12:23:06 PM PDT 24
Peak memory 199840 kb
Host smart-66a9337d-9063-4e60-ace4-7faae5858019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255405816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1255405816
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3634809973
Short name T348
Test name
Test status
Simulation time 311690703 ps
CPU time 2.42 seconds
Started May 05 12:24:38 PM PDT 24
Finished May 05 12:24:42 PM PDT 24
Peak memory 198440 kb
Host smart-f297a84d-883e-4d0e-bcc5-2d4e68784187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634809973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3634809973
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.4275466766
Short name T315
Test name
Test status
Simulation time 59155379 ps
CPU time 1.28 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:13 PM PDT 24
Peak memory 197612 kb
Host smart-e07aafa7-ce78-4280-9d1f-b803f7efc7ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275466766 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.4275466766
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2181300049
Short name T253
Test name
Test status
Simulation time 220951565644 ps
CPU time 419.37 seconds
Started May 05 12:21:53 PM PDT 24
Finished May 05 12:28:53 PM PDT 24
Peak memory 199928 kb
Host smart-e1695d0c-9e72-46d4-b4f9-90e742690168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181300049 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2181300049
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.693927638
Short name T16
Test name
Test status
Simulation time 14011396 ps
CPU time 0.56 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:23:51 PM PDT 24
Peak memory 194936 kb
Host smart-2a15468f-2be0-4a6c-8211-34ec48fd2f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693927638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.693927638
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2309914398
Short name T243
Test name
Test status
Simulation time 254872593 ps
CPU time 5.37 seconds
Started May 05 12:24:45 PM PDT 24
Finished May 05 12:24:51 PM PDT 24
Peak memory 199816 kb
Host smart-f8fd8839-b911-4454-9014-4524f8d0546e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309914398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2309914398
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1911750259
Short name T336
Test name
Test status
Simulation time 121531269 ps
CPU time 6.21 seconds
Started May 05 12:24:00 PM PDT 24
Finished May 05 12:24:07 PM PDT 24
Peak memory 199412 kb
Host smart-9aa0cb3b-90f5-4528-98af-b4d79d68c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911750259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1911750259
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1022494444
Short name T375
Test name
Test status
Simulation time 894029636 ps
CPU time 46.72 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 197992 kb
Host smart-27ac4b4f-b232-48a6-99c8-3b18a728c332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022494444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1022494444
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2995525862
Short name T340
Test name
Test status
Simulation time 3035924700 ps
CPU time 87.97 seconds
Started May 05 12:22:01 PM PDT 24
Finished May 05 12:23:30 PM PDT 24
Peak memory 199900 kb
Host smart-c83594a2-f22b-4f70-8d30-321f645a539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995525862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2995525862
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1537090592
Short name T301
Test name
Test status
Simulation time 123678456 ps
CPU time 3.89 seconds
Started May 05 12:23:42 PM PDT 24
Finished May 05 12:23:47 PM PDT 24
Peak memory 199240 kb
Host smart-b5881224-1082-49c3-80e4-a1c9d0880108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537090592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1537090592
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2739374467
Short name T341
Test name
Test status
Simulation time 31917476 ps
CPU time 1.07 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 199740 kb
Host smart-8daf7bfc-2dc2-41fd-ba75-ff915b3f846c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739374467 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2739374467
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2045656781
Short name T296
Test name
Test status
Simulation time 106113416627 ps
CPU time 403.06 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:30:36 PM PDT 24
Peak memory 198512 kb
Host smart-fbbfb9d4-2d55-4b27-8596-2bf7f620fc93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045656781 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2045656781
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3180783314
Short name T339
Test name
Test status
Simulation time 20078910 ps
CPU time 0.58 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 192952 kb
Host smart-b22ce5ed-3945-4d03-96f1-0014bed04ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180783314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3180783314
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.760300498
Short name T374
Test name
Test status
Simulation time 9345040873 ps
CPU time 29.59 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:24:21 PM PDT 24
Peak memory 229840 kb
Host smart-c6e8875b-6662-4a59-b690-bf3e3036c3e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760300498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.760300498
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3879441311
Short name T467
Test name
Test status
Simulation time 8988037338 ps
CPU time 43.53 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:24:34 PM PDT 24
Peak memory 199472 kb
Host smart-820f714e-37bb-4841-99ab-6a92dc142209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879441311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3879441311
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4149011904
Short name T294
Test name
Test status
Simulation time 1068401276 ps
CPU time 57.1 seconds
Started May 05 12:23:57 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 197844 kb
Host smart-50c1dce4-33cf-4915-a57e-faa75b619d31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149011904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4149011904
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3359866407
Short name T396
Test name
Test status
Simulation time 20462408536 ps
CPU time 78.88 seconds
Started May 05 12:23:57 PM PDT 24
Finished May 05 12:25:17 PM PDT 24
Peak memory 197972 kb
Host smart-7a5b8e43-96f5-4f1a-8d8d-4236e0af329c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359866407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3359866407
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.471918316
Short name T78
Test name
Test status
Simulation time 146392435 ps
CPU time 1.66 seconds
Started May 05 12:22:11 PM PDT 24
Finished May 05 12:22:13 PM PDT 24
Peak memory 199996 kb
Host smart-033c4267-caf2-4351-af21-e5c1c5ccfd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471918316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.471918316
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3290667487
Short name T363
Test name
Test status
Simulation time 56000236 ps
CPU time 1.24 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:23:52 PM PDT 24
Peak memory 199552 kb
Host smart-df24efe7-5549-4fb0-8a5e-da9adab7b25f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290667487 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3290667487
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3964958527
Short name T139
Test name
Test status
Simulation time 97296158350 ps
CPU time 425.6 seconds
Started May 05 12:22:06 PM PDT 24
Finished May 05 12:29:13 PM PDT 24
Peak memory 200224 kb
Host smart-5eef8a37-9425-46ec-9773-468617bcc815
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964958527 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3964958527
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.451442511
Short name T38
Test name
Test status
Simulation time 13416222 ps
CPU time 0.58 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:54 PM PDT 24
Peak memory 193780 kb
Host smart-e19720d4-e3e3-4857-a662-ea8fc8e8b2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451442511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.451442511
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1313729212
Short name T233
Test name
Test status
Simulation time 242655660 ps
CPU time 11.93 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:24:03 PM PDT 24
Peak memory 207756 kb
Host smart-5a4aaf7f-ca9f-4b87-bed2-215a1c864607
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313729212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1313729212
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3528128976
Short name T327
Test name
Test status
Simulation time 7510527001 ps
CPU time 35.93 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:53 PM PDT 24
Peak memory 198244 kb
Host smart-11045734-ae0a-4d05-83e4-095c1d5b12ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528128976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3528128976
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3005468396
Short name T448
Test name
Test status
Simulation time 541193570 ps
CPU time 13.81 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:31 PM PDT 24
Peak memory 198488 kb
Host smart-2da5434b-585c-4238-83ec-39e695f9f7df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005468396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3005468396
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.366296478
Short name T334
Test name
Test status
Simulation time 1119337536 ps
CPU time 20.46 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:24:11 PM PDT 24
Peak memory 199540 kb
Host smart-a1d5064e-45ae-4f6b-a02f-5d9a176a4ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366296478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.366296478
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1561672614
Short name T473
Test name
Test status
Simulation time 442142846 ps
CPU time 6.31 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:56 PM PDT 24
Peak memory 198372 kb
Host smart-4e1b0bc0-b678-4aef-89cc-a2e39b8e055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561672614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1561672614
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3764340623
Short name T33
Test name
Test status
Simulation time 57314226 ps
CPU time 1.25 seconds
Started May 05 12:24:14 PM PDT 24
Finished May 05 12:24:19 PM PDT 24
Peak memory 199472 kb
Host smart-73ce8adb-bea0-4e0e-a46c-39a26b5b7384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764340623 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3764340623
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.90444789
Short name T380
Test name
Test status
Simulation time 18111715110 ps
CPU time 504.69 seconds
Started May 05 12:22:16 PM PDT 24
Finished May 05 12:30:41 PM PDT 24
Peak memory 199900 kb
Host smart-eb1dc954-9507-45bd-8a15-3def992fcef0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90444789 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.90444789
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.280561164
Short name T261
Test name
Test status
Simulation time 25185937 ps
CPU time 0.54 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:24:48 PM PDT 24
Peak memory 194768 kb
Host smart-4ab4908b-e0f2-4d93-8da1-de2b76ed1479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280561164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.280561164
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1881753175
Short name T14
Test name
Test status
Simulation time 519411237 ps
CPU time 16.11 seconds
Started May 05 12:22:25 PM PDT 24
Finished May 05 12:22:42 PM PDT 24
Peak memory 225496 kb
Host smart-d9b26906-6a6c-4fbf-9932-2978ec1b299d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881753175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1881753175
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3230102516
Short name T417
Test name
Test status
Simulation time 2735333732 ps
CPU time 38.04 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:24:31 PM PDT 24
Peak memory 198776 kb
Host smart-c2626163-d0ce-49c8-9d89-596f44478b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230102516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3230102516
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1714725263
Short name T191
Test name
Test status
Simulation time 14481658626 ps
CPU time 39.23 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:42 PM PDT 24
Peak memory 199796 kb
Host smart-7b71a980-1931-4437-bafc-9927380b3f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714725263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1714725263
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1506276378
Short name T221
Test name
Test status
Simulation time 17612266536 ps
CPU time 78.6 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:25:20 PM PDT 24
Peak memory 199796 kb
Host smart-d08728af-cf91-4a91-bfd8-c0f00c9eb4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506276378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1506276378
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3063087249
Short name T398
Test name
Test status
Simulation time 2058522185 ps
CPU time 5.08 seconds
Started May 05 12:22:20 PM PDT 24
Finished May 05 12:22:25 PM PDT 24
Peak memory 199844 kb
Host smart-18147f15-4fdb-4fc7-bd25-4d3a63a0682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063087249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3063087249
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.4085243364
Short name T189
Test name
Test status
Simulation time 169042869 ps
CPU time 1.2 seconds
Started May 05 12:24:47 PM PDT 24
Finished May 05 12:24:49 PM PDT 24
Peak memory 199572 kb
Host smart-c6480f38-05a0-4ae4-bda5-6f0bf086aeed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085243364 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.4085243364
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.4084662227
Short name T345
Test name
Test status
Simulation time 25669772734 ps
CPU time 446.75 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:31:29 PM PDT 24
Peak memory 198924 kb
Host smart-95c7d446-3a45-4ec2-a90e-7b8acb3f2f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084662227 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.4084662227
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2332267021
Short name T471
Test name
Test status
Simulation time 22071343 ps
CPU time 0.64 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:05 PM PDT 24
Peak memory 193400 kb
Host smart-56653d7b-917e-4d9e-93e3-48e7ed7b954c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332267021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2332267021
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.841721726
Short name T258
Test name
Test status
Simulation time 1027352821 ps
CPU time 14.47 seconds
Started May 05 12:22:25 PM PDT 24
Finished May 05 12:22:40 PM PDT 24
Peak memory 208072 kb
Host smart-bd2852c3-f047-4c44-99a0-d1059572e8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841721726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.841721726
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2724092777
Short name T4
Test name
Test status
Simulation time 1856492189 ps
CPU time 34.25 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:25:21 PM PDT 24
Peak memory 199480 kb
Host smart-b46f1d0c-c89e-45f2-b62b-e442f7c413a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724092777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2724092777
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1779484951
Short name T268
Test name
Test status
Simulation time 3320765437 ps
CPU time 86.23 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:26:14 PM PDT 24
Peak memory 199580 kb
Host smart-a57be3c7-6efe-4883-bbff-d95975c5185a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779484951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1779484951
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1741102562
Short name T240
Test name
Test status
Simulation time 4057995893 ps
CPU time 29.87 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:25:17 PM PDT 24
Peak memory 199584 kb
Host smart-ce1476c8-1fb8-4773-bbd8-949788bfaa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741102562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1741102562
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.479101412
Short name T171
Test name
Test status
Simulation time 405320702 ps
CPU time 4.75 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:24:52 PM PDT 24
Peak memory 199520 kb
Host smart-fd613d98-2ca2-4b7f-9ef2-2cbdc596344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479101412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.479101412
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2233915817
Short name T199
Test name
Test status
Simulation time 80640971 ps
CPU time 0.97 seconds
Started May 05 12:22:37 PM PDT 24
Finished May 05 12:22:39 PM PDT 24
Peak memory 198188 kb
Host smart-91c223ea-52d3-48be-8ac9-f1f4e376e87e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233915817 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2233915817
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1911835418
Short name T138
Test name
Test status
Simulation time 31636693527 ps
CPU time 430.94 seconds
Started May 05 12:22:26 PM PDT 24
Finished May 05 12:29:37 PM PDT 24
Peak memory 199952 kb
Host smart-a02efc4c-3ee9-4f95-b8b9-95e0bd36f35d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911835418 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1911835418
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2518106529
Short name T406
Test name
Test status
Simulation time 22313397 ps
CPU time 0.57 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:53 PM PDT 24
Peak memory 194768 kb
Host smart-d2f87e3e-a35f-4cdf-aee4-f1b044f8162c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518106529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2518106529
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1445762615
Short name T43
Test name
Test status
Simulation time 66578950 ps
CPU time 3.26 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:06 PM PDT 24
Peak memory 199340 kb
Host smart-5fef7a46-ac3b-4fde-adfe-0fa2d89ae48b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445762615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1445762615
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1038679428
Short name T414
Test name
Test status
Simulation time 149144802 ps
CPU time 2.62 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:05 PM PDT 24
Peak memory 199536 kb
Host smart-9abc04ec-9a7c-47c0-b70d-176ef8547d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038679428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1038679428
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1935079834
Short name T290
Test name
Test status
Simulation time 3559113483 ps
CPU time 54.47 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:57 PM PDT 24
Peak memory 199000 kb
Host smart-2dd267f3-9313-4b06-bc4e-f678c4de97d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935079834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1935079834
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4281279344
Short name T11
Test name
Test status
Simulation time 9028712157 ps
CPU time 119.59 seconds
Started May 05 12:24:02 PM PDT 24
Finished May 05 12:26:03 PM PDT 24
Peak memory 199588 kb
Host smart-3a4614af-7120-46b8-a1cc-d1cceaa24cb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281279344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4281279344
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.895689368
Short name T282
Test name
Test status
Simulation time 342519002 ps
CPU time 18.43 seconds
Started May 05 12:24:03 PM PDT 24
Finished May 05 12:24:23 PM PDT 24
Peak memory 197436 kb
Host smart-341ccaee-0a85-4ca5-a7a7-395534d387fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895689368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.895689368
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2884830130
Short name T184
Test name
Test status
Simulation time 1744245025 ps
CPU time 6.7 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:13 PM PDT 24
Peak memory 199536 kb
Host smart-ea2f3d72-a868-4391-ba29-3231c43bb1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884830130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2884830130
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1728457746
Short name T69
Test name
Test status
Simulation time 1284074540049 ps
CPU time 2537.94 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 01:06:09 PM PDT 24
Peak memory 215908 kb
Host smart-8bab4c26-13de-4882-93df-0511267134ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728457746 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1728457746
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.636599726
Short name T208
Test name
Test status
Simulation time 32462827 ps
CPU time 1.16 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:53 PM PDT 24
Peak memory 199136 kb
Host smart-1748739f-2360-4c06-bd03-393a84281554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636599726 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.636599726
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3790775307
Short name T6
Test name
Test status
Simulation time 66145193296 ps
CPU time 417.52 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:30:51 PM PDT 24
Peak memory 199572 kb
Host smart-44fbbe15-3f9c-447a-8e0f-3a87a0d6b3e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790775307 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.3790775307
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1992505582
Short name T17
Test name
Test status
Simulation time 14662957 ps
CPU time 0.66 seconds
Started May 05 12:24:38 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 193956 kb
Host smart-9cdd7999-4606-4b61-9d9b-c5fddabcc88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992505582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1992505582
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3254852314
Short name T112
Test name
Test status
Simulation time 726495972 ps
CPU time 32.95 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:24:25 PM PDT 24
Peak memory 205956 kb
Host smart-f63782f0-e7ae-46b2-9163-603eef771c71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254852314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3254852314
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1263726677
Short name T116
Test name
Test status
Simulation time 2374400971 ps
CPU time 33.26 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:24:23 PM PDT 24
Peak memory 198736 kb
Host smart-b309cc7e-d423-4b4d-9877-3192a1cfa362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263726677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1263726677
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4040462481
Short name T238
Test name
Test status
Simulation time 499106446 ps
CPU time 12.95 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:24:05 PM PDT 24
Peak memory 199252 kb
Host smart-d083917a-0119-496e-b62e-630ecd544829
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040462481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4040462481
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2296540360
Short name T142
Test name
Test status
Simulation time 505270649 ps
CPU time 8.44 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:24:01 PM PDT 24
Peak memory 199388 kb
Host smart-354ce964-3ffb-4bed-a1cb-e11856c15f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296540360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2296540360
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3903773525
Short name T235
Test name
Test status
Simulation time 209900047 ps
CPU time 1.94 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:23:53 PM PDT 24
Peak memory 199476 kb
Host smart-23812b47-e7f2-49f4-bea6-7ece385e3c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903773525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3903773525
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2366982230
Short name T394
Test name
Test status
Simulation time 341909936 ps
CPU time 1.2 seconds
Started May 05 12:23:51 PM PDT 24
Finished May 05 12:23:55 PM PDT 24
Peak memory 198304 kb
Host smart-818ac3d0-a5f2-478e-9c3e-4699a80e6b57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366982230 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2366982230
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2329505081
Short name T182
Test name
Test status
Simulation time 55460898388 ps
CPU time 476.39 seconds
Started May 05 12:23:49 PM PDT 24
Finished May 05 12:31:47 PM PDT 24
Peak memory 198504 kb
Host smart-c35a846c-71fc-4345-9941-db89579d5bd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329505081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.2329505081
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4074114465
Short name T409
Test name
Test status
Simulation time 42380529 ps
CPU time 0.56 seconds
Started May 05 12:22:56 PM PDT 24
Finished May 05 12:22:58 PM PDT 24
Peak memory 195364 kb
Host smart-8b55368a-c3d3-4190-a1b9-9bbdcf0b9a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074114465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4074114465
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1410252283
Short name T39
Test name
Test status
Simulation time 761522785 ps
CPU time 18.69 seconds
Started May 05 12:24:50 PM PDT 24
Finished May 05 12:25:12 PM PDT 24
Peak memory 207724 kb
Host smart-a042767a-9417-4610-8efd-b4339112535c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410252283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1410252283
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1615933825
Short name T94
Test name
Test status
Simulation time 285733183 ps
CPU time 14.96 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:53 PM PDT 24
Peak memory 199004 kb
Host smart-ae531b55-8ef0-497f-bd38-fb95b6a1acc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615933825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1615933825
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1689495720
Short name T399
Test name
Test status
Simulation time 963593429 ps
CPU time 39.4 seconds
Started May 05 12:24:40 PM PDT 24
Finished May 05 12:25:21 PM PDT 24
Peak memory 199796 kb
Host smart-952cb37d-2304-430c-9fc4-5d8647fe0ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689495720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1689495720
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.883615919
Short name T423
Test name
Test status
Simulation time 31708849935 ps
CPU time 45.32 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:25:00 PM PDT 24
Peak memory 199792 kb
Host smart-6db92292-b50b-4b33-b8ab-e81e96db2c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883615919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.883615919
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2578338041
Short name T355
Test name
Test status
Simulation time 794795503 ps
CPU time 4.86 seconds
Started May 05 12:24:52 PM PDT 24
Finished May 05 12:25:00 PM PDT 24
Peak memory 199800 kb
Host smart-0065ef00-3625-4ae5-ac2e-728b79b193b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578338041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2578338041
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3685495366
Short name T70
Test name
Test status
Simulation time 6790083378 ps
CPU time 108.95 seconds
Started May 05 12:22:47 PM PDT 24
Finished May 05 12:24:37 PM PDT 24
Peak memory 228684 kb
Host smart-d039f996-1e4e-4f3f-ab09-eeb7bff17b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685495366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3685495366
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2157428019
Short name T428
Test name
Test status
Simulation time 133979359 ps
CPU time 1.24 seconds
Started May 05 12:22:47 PM PDT 24
Finished May 05 12:22:48 PM PDT 24
Peak memory 199848 kb
Host smart-2def7d1d-8f68-44ce-b579-9330736a3e09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157428019 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2157428019
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3868673354
Short name T459
Test name
Test status
Simulation time 107070511354 ps
CPU time 478.12 seconds
Started May 05 12:22:56 PM PDT 24
Finished May 05 12:30:55 PM PDT 24
Peak memory 199944 kb
Host smart-86e3d199-b1f3-4d8f-9b47-f1607bf7eb54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868673354 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3868673354
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_alert_test.160434170
Short name T140
Test name
Test status
Simulation time 28261829 ps
CPU time 0.56 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:20:10 PM PDT 24
Peak memory 195432 kb
Host smart-96f8115d-aae0-4972-b1b7-3f0611f32a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160434170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.160434170
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.777864711
Short name T377
Test name
Test status
Simulation time 624269256 ps
CPU time 6.76 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:24:43 PM PDT 24
Peak memory 214440 kb
Host smart-cd20e226-cb8f-4fd6-8ac9-4b0ec524c551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777864711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.777864711
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2994060258
Short name T280
Test name
Test status
Simulation time 820572944 ps
CPU time 12 seconds
Started May 05 12:20:15 PM PDT 24
Finished May 05 12:20:27 PM PDT 24
Peak memory 199856 kb
Host smart-8d3733d9-280a-4827-86ba-226ce0f81ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994060258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2994060258
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3493055831
Short name T251
Test name
Test status
Simulation time 8965126543 ps
CPU time 114.75 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:26:44 PM PDT 24
Peak memory 199864 kb
Host smart-588fa951-c82e-426d-abdb-97dac15641b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493055831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3493055831
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2716345851
Short name T236
Test name
Test status
Simulation time 424777126 ps
CPU time 6.49 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:24:42 PM PDT 24
Peak memory 199552 kb
Host smart-6455ed22-7a16-43fa-810e-db5e5f37abc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716345851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2716345851
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1682271118
Short name T28
Test name
Test status
Simulation time 131111689 ps
CPU time 0.78 seconds
Started May 05 12:24:37 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 217940 kb
Host smart-1c31211b-17ee-4f77-9c78-6630f9a8d600
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682271118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1682271118
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1939071360
Short name T455
Test name
Test status
Simulation time 925471549 ps
CPU time 2.93 seconds
Started May 05 12:24:48 PM PDT 24
Finished May 05 12:24:52 PM PDT 24
Peak memory 199772 kb
Host smart-87832854-de9e-4197-8e6a-abd8e5a2886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939071360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1939071360
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1083860601
Short name T404
Test name
Test status
Simulation time 94801101 ps
CPU time 0.95 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:18 PM PDT 24
Peak memory 197104 kb
Host smart-ccd63b59-d335-4491-bfab-6fb3d4f0e459
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083860601 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1083860601
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2679085212
Short name T168
Test name
Test status
Simulation time 30505614024 ps
CPU time 505.33 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:33:13 PM PDT 24
Peak memory 199832 kb
Host smart-025831a0-aaf4-4ea9-8b04-5610109bcbeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679085212 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2679085212
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.548555373
Short name T372
Test name
Test status
Simulation time 61488785 ps
CPU time 0.79 seconds
Started May 05 12:19:59 PM PDT 24
Finished May 05 12:20:00 PM PDT 24
Peak memory 198648 kb
Host smart-0ba88042-6e93-4200-a9ce-13601121eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548555373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.548555373
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3671236954
Short name T262
Test name
Test status
Simulation time 22437067 ps
CPU time 0.61 seconds
Started May 05 12:24:04 PM PDT 24
Finished May 05 12:24:08 PM PDT 24
Peak memory 192408 kb
Host smart-a5594037-2a2b-4ab8-be03-44b286068925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671236954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3671236954
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2692961291
Short name T279
Test name
Test status
Simulation time 13353730164 ps
CPU time 44.1 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:25:31 PM PDT 24
Peak memory 232236 kb
Host smart-95bc56d7-6d4b-4097-98e8-c12b69b30a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692961291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2692961291
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1379300937
Short name T183
Test name
Test status
Simulation time 3122614075 ps
CPU time 7.86 seconds
Started May 05 12:24:14 PM PDT 24
Finished May 05 12:24:25 PM PDT 24
Peak memory 199428 kb
Host smart-a666183b-50cb-4759-8d58-b7b1051ace58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379300937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1379300937
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3415805133
Short name T35
Test name
Test status
Simulation time 11431450379 ps
CPU time 161.96 seconds
Started May 05 12:22:49 PM PDT 24
Finished May 05 12:25:31 PM PDT 24
Peak memory 199880 kb
Host smart-f0f02a02-25e2-412f-9e65-728f48de6d43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415805133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3415805133
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_long_msg.160227729
Short name T361
Test name
Test status
Simulation time 2228202303 ps
CPU time 41.21 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:58 PM PDT 24
Peak memory 199380 kb
Host smart-6f6b4994-1a94-4ed2-8c5b-9402867648f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160227729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.160227729
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.810145599
Short name T34
Test name
Test status
Simulation time 706040763 ps
CPU time 5.5 seconds
Started May 05 12:22:51 PM PDT 24
Finished May 05 12:22:57 PM PDT 24
Peak memory 199848 kb
Host smart-d5d3d60f-558c-4d7d-b3b3-427bbae31d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810145599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.810145599
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2218287970
Short name T193
Test name
Test status
Simulation time 25854834 ps
CPU time 0.89 seconds
Started May 05 12:24:45 PM PDT 24
Finished May 05 12:24:47 PM PDT 24
Peak memory 197844 kb
Host smart-e752e572-f456-4c17-821f-988e0324669f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218287970 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2218287970
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2414375174
Short name T249
Test name
Test status
Simulation time 50191264583 ps
CPU time 426.61 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:31:23 PM PDT 24
Peak memory 199404 kb
Host smart-d0b9e388-2acf-4381-93a7-ca4bdfc8527e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414375174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2414375174
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1256686232
Short name T25
Test name
Test status
Simulation time 221383439 ps
CPU time 7.51 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:25 PM PDT 24
Peak memory 199372 kb
Host smart-5f726a43-6625-4d9c-b92e-04fafa67f472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256686232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1256686232
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1036205095
Short name T300
Test name
Test status
Simulation time 55765791 ps
CPU time 0.59 seconds
Started May 05 12:23:13 PM PDT 24
Finished May 05 12:23:14 PM PDT 24
Peak memory 195404 kb
Host smart-1cf803f0-f139-4a67-bc24-62ffce4267d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036205095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1036205095
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3244718589
Short name T429
Test name
Test status
Simulation time 2732863723 ps
CPU time 27.03 seconds
Started May 05 12:23:06 PM PDT 24
Finished May 05 12:23:33 PM PDT 24
Peak memory 232796 kb
Host smart-684c1b00-9ee8-4373-a489-003c80b1899a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244718589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3244718589
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3893101668
Short name T185
Test name
Test status
Simulation time 800179058 ps
CPU time 6.74 seconds
Started May 05 12:22:59 PM PDT 24
Finished May 05 12:23:07 PM PDT 24
Peak memory 199944 kb
Host smart-85003b34-fc8a-4627-b8ff-38b25a902ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893101668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3893101668
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.219927518
Short name T119
Test name
Test status
Simulation time 2161240366 ps
CPU time 119.44 seconds
Started May 05 12:22:59 PM PDT 24
Finished May 05 12:25:00 PM PDT 24
Peak memory 199984 kb
Host smart-cf3789d8-c44c-4107-99d6-2d2ee7131a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219927518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.219927518
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4795349
Short name T403
Test name
Test status
Simulation time 5901013577 ps
CPU time 40.92 seconds
Started May 05 12:24:12 PM PDT 24
Finished May 05 12:24:57 PM PDT 24
Peak memory 198476 kb
Host smart-1ae948e1-39c3-4721-808a-859805f76734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4795349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4795349
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1443631544
Short name T438
Test name
Test status
Simulation time 20167672 ps
CPU time 0.77 seconds
Started May 05 12:24:12 PM PDT 24
Finished May 05 12:24:17 PM PDT 24
Peak memory 195812 kb
Host smart-4538441b-3982-42eb-b330-0bd76212f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443631544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1443631544
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3523720359
Short name T173
Test name
Test status
Simulation time 74107208 ps
CPU time 1.33 seconds
Started May 05 12:22:59 PM PDT 24
Finished May 05 12:23:01 PM PDT 24
Peak memory 199840 kb
Host smart-bffea212-b4c6-43d6-99c7-d8fbcb0fec1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523720359 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3523720359
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2954973221
Short name T322
Test name
Test status
Simulation time 36966656513 ps
CPU time 445.26 seconds
Started May 05 12:23:05 PM PDT 24
Finished May 05 12:30:31 PM PDT 24
Peak memory 200224 kb
Host smart-094f8ebb-8b4b-4956-a365-88c27ad610ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954973221 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2954973221
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1382379030
Short name T401
Test name
Test status
Simulation time 102031119 ps
CPU time 0.55 seconds
Started May 05 12:24:26 PM PDT 24
Finished May 05 12:24:28 PM PDT 24
Peak memory 195396 kb
Host smart-6d8b12a4-0104-4c1d-b251-6a4604c3c215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382379030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1382379030
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.4265398977
Short name T167
Test name
Test status
Simulation time 2858107520 ps
CPU time 43.38 seconds
Started May 05 12:23:12 PM PDT 24
Finished May 05 12:23:56 PM PDT 24
Peak memory 224468 kb
Host smart-e9b8a5a3-29c6-4436-9be1-4659b41c2b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265398977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.4265398977
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3998020181
Short name T289
Test name
Test status
Simulation time 1446529362 ps
CPU time 5.51 seconds
Started May 05 12:23:11 PM PDT 24
Finished May 05 12:23:17 PM PDT 24
Peak memory 200000 kb
Host smart-0655839b-7735-4fc1-be11-828509a2769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998020181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3998020181
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3393429610
Short name T62
Test name
Test status
Simulation time 644078050 ps
CPU time 36.33 seconds
Started May 05 12:23:10 PM PDT 24
Finished May 05 12:23:47 PM PDT 24
Peak memory 199968 kb
Host smart-68d2e5fb-6e05-42e3-8ea6-a397def1bd68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393429610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3393429610
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2857549426
Short name T389
Test name
Test status
Simulation time 1362877046 ps
CPU time 36.21 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:25:09 PM PDT 24
Peak memory 199736 kb
Host smart-62911acb-ad08-42ab-88ab-e57e9d20447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857549426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2857549426
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3257651760
Short name T292
Test name
Test status
Simulation time 750209716 ps
CPU time 3.85 seconds
Started May 05 12:23:16 PM PDT 24
Finished May 05 12:23:20 PM PDT 24
Peak memory 199848 kb
Host smart-0b723bfd-5ac0-4f8f-b26f-c04ab932004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257651760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3257651760
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3882515565
Short name T41
Test name
Test status
Simulation time 153498750 ps
CPU time 1.3 seconds
Started May 05 12:23:15 PM PDT 24
Finished May 05 12:23:17 PM PDT 24
Peak memory 199892 kb
Host smart-09c472e6-2a23-41cd-bed2-beffa0bf7437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882515565 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3882515565
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3952982317
Short name T36
Test name
Test status
Simulation time 8444058251 ps
CPU time 453.96 seconds
Started May 05 12:23:04 PM PDT 24
Finished May 05 12:30:39 PM PDT 24
Peak memory 199968 kb
Host smart-baa74fe8-1011-41a3-8aaa-401e657540f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952982317 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3952982317
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.264982585
Short name T132
Test name
Test status
Simulation time 61251018 ps
CPU time 0.6 seconds
Started May 05 12:23:29 PM PDT 24
Finished May 05 12:23:30 PM PDT 24
Peak memory 194464 kb
Host smart-f1accf19-87ca-4697-a9bb-17d68957e6ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264982585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.264982585
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1566649238
Short name T298
Test name
Test status
Simulation time 777465267 ps
CPU time 13.72 seconds
Started May 05 12:23:13 PM PDT 24
Finished May 05 12:23:28 PM PDT 24
Peak memory 218292 kb
Host smart-5190699e-8384-4553-a54e-4b81f9e8d5b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566649238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1566649238
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2178692321
Short name T204
Test name
Test status
Simulation time 1439660477 ps
CPU time 3.5 seconds
Started May 05 12:24:08 PM PDT 24
Finished May 05 12:24:17 PM PDT 24
Peak memory 199848 kb
Host smart-4c903e16-c72f-40b3-b2b4-e43729ae2ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178692321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2178692321
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.652677705
Short name T203
Test name
Test status
Simulation time 665727093 ps
CPU time 11.27 seconds
Started May 05 12:23:20 PM PDT 24
Finished May 05 12:23:32 PM PDT 24
Peak memory 200160 kb
Host smart-e9b7634e-7bb8-443f-a41a-ce3b985e474c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652677705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.652677705
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1770244586
Short name T445
Test name
Test status
Simulation time 8297488509 ps
CPU time 120.84 seconds
Started May 05 12:23:13 PM PDT 24
Finished May 05 12:25:14 PM PDT 24
Peak memory 200032 kb
Host smart-61a72022-9873-4b11-985e-fed4ecdad6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770244586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1770244586
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1922044315
Short name T162
Test name
Test status
Simulation time 1032610659 ps
CPU time 6.07 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:39 PM PDT 24
Peak memory 199784 kb
Host smart-c28e63f2-79a7-42d2-a24f-4d8cef4362e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922044315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1922044315
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1805847826
Short name T465
Test name
Test status
Simulation time 75637278840 ps
CPU time 75.66 seconds
Started May 05 12:23:21 PM PDT 24
Finished May 05 12:24:37 PM PDT 24
Peak memory 199960 kb
Host smart-f3850598-3292-4b9a-8f4b-551edd629b9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805847826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1805847826
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.731574385
Short name T178
Test name
Test status
Simulation time 124653780 ps
CPU time 1.3 seconds
Started May 05 12:23:19 PM PDT 24
Finished May 05 12:23:20 PM PDT 24
Peak memory 199864 kb
Host smart-9b1ad091-57a3-46e9-946a-38b2abd0b658
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731574385 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.731574385
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1220341082
Short name T227
Test name
Test status
Simulation time 13009364303 ps
CPU time 355.77 seconds
Started May 05 12:23:19 PM PDT 24
Finished May 05 12:29:15 PM PDT 24
Peak memory 199896 kb
Host smart-c11e450d-31a8-4dfb-8b9a-45967c8568b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220341082 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1220341082
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3513489071
Short name T144
Test name
Test status
Simulation time 22581405 ps
CPU time 0.62 seconds
Started May 05 12:23:23 PM PDT 24
Finished May 05 12:23:24 PM PDT 24
Peak memory 195596 kb
Host smart-7e59955c-9bf0-495f-9b18-b5d82567456c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513489071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3513489071
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.679699455
Short name T226
Test name
Test status
Simulation time 1102588763 ps
CPU time 17.1 seconds
Started May 05 12:23:27 PM PDT 24
Finished May 05 12:23:44 PM PDT 24
Peak memory 224576 kb
Host smart-139f9441-b9b1-407c-85ef-6af6cd2375e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679699455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.679699455
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2583683264
Short name T164
Test name
Test status
Simulation time 3773804467 ps
CPU time 106.69 seconds
Started May 05 12:23:28 PM PDT 24
Finished May 05 12:25:15 PM PDT 24
Peak memory 200032 kb
Host smart-b5cafa2d-3919-4ee3-8556-d6e22bd5723d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583683264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2583683264
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2717314564
Short name T271
Test name
Test status
Simulation time 3243908341 ps
CPU time 54.6 seconds
Started May 05 12:23:17 PM PDT 24
Finished May 05 12:24:12 PM PDT 24
Peak memory 200028 kb
Host smart-b34e4162-8214-49ce-9017-0317c4a9ef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717314564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2717314564
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3667341179
Short name T446
Test name
Test status
Simulation time 544456498 ps
CPU time 4.07 seconds
Started May 05 12:23:27 PM PDT 24
Finished May 05 12:23:31 PM PDT 24
Peak memory 199972 kb
Host smart-e0dfa1bb-98b5-49e6-a67c-a51f4695c394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667341179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3667341179
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2981964318
Short name T310
Test name
Test status
Simulation time 203297695 ps
CPU time 1.24 seconds
Started May 05 12:24:32 PM PDT 24
Finished May 05 12:24:34 PM PDT 24
Peak memory 199744 kb
Host smart-82afaeaf-4d4a-41ac-a8c6-6c65afe0ec0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981964318 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2981964318
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1488485213
Short name T466
Test name
Test status
Simulation time 108795956151 ps
CPU time 498.26 seconds
Started May 05 12:24:25 PM PDT 24
Finished May 05 12:32:45 PM PDT 24
Peak memory 199924 kb
Host smart-5749ac03-8f3e-4c6f-846e-1b7bc5f3040d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488485213 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1488485213
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2656478069
Short name T24
Test name
Test status
Simulation time 175929287 ps
CPU time 9.73 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:26 PM PDT 24
Peak memory 199820 kb
Host smart-1a85d5d2-a056-4275-831f-31f32dfef853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656478069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2656478069
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.327289277
Short name T37
Test name
Test status
Simulation time 38900479 ps
CPU time 0.64 seconds
Started May 05 12:23:35 PM PDT 24
Finished May 05 12:23:36 PM PDT 24
Peak memory 195568 kb
Host smart-c9ac10ba-d58c-411b-b785-bbadba4b6344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327289277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.327289277
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1235765727
Short name T47
Test name
Test status
Simulation time 577569730 ps
CPU time 8.97 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:24:20 PM PDT 24
Peak memory 208388 kb
Host smart-a2617c62-0210-4087-b306-34caa7d4f25e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235765727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1235765727
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1026835256
Short name T95
Test name
Test status
Simulation time 18230304033 ps
CPU time 52.44 seconds
Started May 05 12:24:19 PM PDT 24
Finished May 05 12:25:12 PM PDT 24
Peak memory 199900 kb
Host smart-ad81cf2b-4060-4e59-a4ad-16838800c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026835256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1026835256
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1730431467
Short name T314
Test name
Test status
Simulation time 6207014063 ps
CPU time 84.33 seconds
Started May 05 12:24:18 PM PDT 24
Finished May 05 12:25:44 PM PDT 24
Peak memory 199912 kb
Host smart-0fad7ea9-abdf-4767-9a4d-2fa172594f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730431467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1730431467
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3470336688
Short name T286
Test name
Test status
Simulation time 2118811443 ps
CPU time 42.58 seconds
Started May 05 12:23:30 PM PDT 24
Finished May 05 12:24:14 PM PDT 24
Peak memory 200148 kb
Host smart-81984f64-397f-4a64-82c4-2aee418611b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470336688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3470336688
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4265471509
Short name T195
Test name
Test status
Simulation time 1563018982 ps
CPU time 6.74 seconds
Started May 05 12:23:34 PM PDT 24
Finished May 05 12:23:41 PM PDT 24
Peak memory 199872 kb
Host smart-7948be49-5b5b-42a7-9c45-65ee474abc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265471509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4265471509
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.583936491
Short name T159
Test name
Test status
Simulation time 58512789 ps
CPU time 1.1 seconds
Started May 05 12:23:34 PM PDT 24
Finished May 05 12:23:35 PM PDT 24
Peak memory 199228 kb
Host smart-e6c7956c-a49c-4949-ad84-0f512ce0c39c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583936491 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.583936491
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.626839050
Short name T220
Test name
Test status
Simulation time 125845870063 ps
CPU time 513.97 seconds
Started May 05 12:23:32 PM PDT 24
Finished May 05 12:32:07 PM PDT 24
Peak memory 199920 kb
Host smart-36e75d55-5bab-45f1-803a-c6858cc8cb2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626839050 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.626839050
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.410251431
Short name T160
Test name
Test status
Simulation time 42425041 ps
CPU time 0.61 seconds
Started May 05 12:23:44 PM PDT 24
Finished May 05 12:23:45 PM PDT 24
Peak memory 195424 kb
Host smart-af8d7573-4b6d-4633-9630-c90e9a17479d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410251431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.410251431
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3363448389
Short name T45
Test name
Test status
Simulation time 380483384 ps
CPU time 16.25 seconds
Started May 05 12:23:35 PM PDT 24
Finished May 05 12:23:51 PM PDT 24
Peak memory 199956 kb
Host smart-98446ab1-b601-424d-a489-befc6fb92ee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363448389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3363448389
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2417910913
Short name T192
Test name
Test status
Simulation time 1508796790 ps
CPU time 30.83 seconds
Started May 05 12:23:35 PM PDT 24
Finished May 05 12:24:06 PM PDT 24
Peak memory 199868 kb
Host smart-8d26acda-5959-4b5d-ab68-6d66ba3fa139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417910913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2417910913
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.231157223
Short name T434
Test name
Test status
Simulation time 1711611047 ps
CPU time 24.3 seconds
Started May 05 12:23:41 PM PDT 24
Finished May 05 12:24:06 PM PDT 24
Peak memory 199896 kb
Host smart-df223a10-5b01-4bfa-8c10-96c3fdb8d164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231157223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.231157223
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.141208251
Short name T224
Test name
Test status
Simulation time 1048532162 ps
CPU time 31.58 seconds
Started May 05 12:23:40 PM PDT 24
Finished May 05 12:24:13 PM PDT 24
Peak memory 199992 kb
Host smart-46ee67b8-fd15-4627-afc1-9aa5c3005824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141208251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.141208251
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.710580949
Short name T397
Test name
Test status
Simulation time 1830489135 ps
CPU time 5.29 seconds
Started May 05 12:23:40 PM PDT 24
Finished May 05 12:23:47 PM PDT 24
Peak memory 199968 kb
Host smart-dcd1a4aa-e736-4b8b-8fea-564e95fc5a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710580949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.710580949
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1817636101
Short name T276
Test name
Test status
Simulation time 53533636 ps
CPU time 1.02 seconds
Started May 05 12:23:44 PM PDT 24
Finished May 05 12:23:45 PM PDT 24
Peak memory 199460 kb
Host smart-e3f0520f-52b4-4b34-bc5e-d901afaed3b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817636101 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1817636101
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1991002076
Short name T415
Test name
Test status
Simulation time 27098417245 ps
CPU time 431.53 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:31:00 PM PDT 24
Peak memory 200008 kb
Host smart-0e3c0234-a027-4535-81b9-efee2c6fca5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991002076 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1991002076
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.543372539
Short name T190
Test name
Test status
Simulation time 35723436 ps
CPU time 0.59 seconds
Started May 05 12:24:00 PM PDT 24
Finished May 05 12:24:01 PM PDT 24
Peak memory 195468 kb
Host smart-751707ad-5062-46e4-95cc-62318e7e3d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543372539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.543372539
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.915011359
Short name T163
Test name
Test status
Simulation time 773956831 ps
CPU time 21 seconds
Started May 05 12:23:52 PM PDT 24
Finished May 05 12:24:15 PM PDT 24
Peak memory 216592 kb
Host smart-52093205-cb48-4a02-9515-52d2e35b4f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915011359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.915011359
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3414649228
Short name T447
Test name
Test status
Simulation time 599350536 ps
CPU time 9.48 seconds
Started May 05 12:23:54 PM PDT 24
Finished May 05 12:24:05 PM PDT 24
Peak memory 199812 kb
Host smart-c2a9a704-593c-439d-b3f6-79460e41f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414649228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3414649228
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3238039302
Short name T27
Test name
Test status
Simulation time 2213998646 ps
CPU time 135.76 seconds
Started May 05 12:23:50 PM PDT 24
Finished May 05 12:26:07 PM PDT 24
Peak memory 199940 kb
Host smart-4f876027-85e3-4fbb-a624-4bd1c94d964c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238039302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3238039302
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4083937567
Short name T325
Test name
Test status
Simulation time 21739557264 ps
CPU time 77.98 seconds
Started May 05 12:23:43 PM PDT 24
Finished May 05 12:25:02 PM PDT 24
Peak memory 199944 kb
Host smart-d1abe24b-e11d-49c0-b72c-6c5a8d61dcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083937567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4083937567
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3287492384
Short name T379
Test name
Test status
Simulation time 1441639386 ps
CPU time 5.48 seconds
Started May 05 12:23:43 PM PDT 24
Finished May 05 12:23:49 PM PDT 24
Peak memory 199844 kb
Host smart-36a4111a-9402-4b55-a51d-c2cf3a831e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287492384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3287492384
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1833528273
Short name T125
Test name
Test status
Simulation time 99298791 ps
CPU time 1.35 seconds
Started May 05 12:23:55 PM PDT 24
Finished May 05 12:23:57 PM PDT 24
Peak memory 199796 kb
Host smart-8d2c0c38-0036-48b6-89d9-293d21cf3ad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833528273 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1833528273
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2621871337
Short name T443
Test name
Test status
Simulation time 54535616430 ps
CPU time 455.41 seconds
Started May 05 12:23:59 PM PDT 24
Finished May 05 12:31:35 PM PDT 24
Peak memory 200196 kb
Host smart-d112eb46-d987-43ce-8ce0-716774958bb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621871337 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2621871337
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1705085466
Short name T463
Test name
Test status
Simulation time 736681034 ps
CPU time 5.25 seconds
Started May 05 12:24:45 PM PDT 24
Finished May 05 12:24:52 PM PDT 24
Peak memory 199792 kb
Host smart-d053e0e1-8b58-457e-84db-061da8eaaf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705085466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1705085466
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1127303183
Short name T177
Test name
Test status
Simulation time 38957639 ps
CPU time 0.65 seconds
Started May 05 12:24:11 PM PDT 24
Finished May 05 12:24:16 PM PDT 24
Peak memory 195556 kb
Host smart-174cda9d-6942-4e0f-9700-4b99e4c3518b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127303183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1127303183
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1879599062
Short name T48
Test name
Test status
Simulation time 752373048 ps
CPU time 30.25 seconds
Started May 05 12:24:07 PM PDT 24
Finished May 05 12:24:43 PM PDT 24
Peak memory 224388 kb
Host smart-1635b8cb-3963-4bc6-b780-26706dc71b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879599062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1879599062
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3953123219
Short name T323
Test name
Test status
Simulation time 9446889591 ps
CPU time 31.56 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:46 PM PDT 24
Peak memory 199920 kb
Host smart-495fb0a5-3e80-42b2-a354-198a402a64ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953123219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3953123219
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3589810775
Short name T232
Test name
Test status
Simulation time 2947529376 ps
CPU time 178.11 seconds
Started May 05 12:24:07 PM PDT 24
Finished May 05 12:27:11 PM PDT 24
Peak memory 200012 kb
Host smart-6afae76f-cc2d-4162-a320-c714b35783ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589810775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3589810775
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.952676690
Short name T278
Test name
Test status
Simulation time 3591022175 ps
CPU time 62.22 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:25:11 PM PDT 24
Peak memory 200108 kb
Host smart-b338f60a-ab4c-4064-8db4-bc494122b5c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952676690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.952676690
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.283255114
Short name T201
Test name
Test status
Simulation time 434614379 ps
CPU time 27.36 seconds
Started May 05 12:24:09 PM PDT 24
Finished May 05 12:24:41 PM PDT 24
Peak memory 199840 kb
Host smart-7326de6b-d004-4d6c-9ef3-47f3f22c4cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283255114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.283255114
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3300298052
Short name T230
Test name
Test status
Simulation time 51349230 ps
CPU time 1.81 seconds
Started May 05 12:24:01 PM PDT 24
Finished May 05 12:24:04 PM PDT 24
Peak memory 199900 kb
Host smart-50c6c97a-4b45-4047-a67c-eb5d21285950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300298052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3300298052
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3041731846
Short name T146
Test name
Test status
Simulation time 220637582 ps
CPU time 1.32 seconds
Started May 05 12:24:09 PM PDT 24
Finished May 05 12:24:15 PM PDT 24
Peak memory 199896 kb
Host smart-8f75f3e2-79a9-4a01-83ee-b8d11c6d75ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041731846 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3041731846
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3019559605
Short name T137
Test name
Test status
Simulation time 8475092138 ps
CPU time 461.9 seconds
Started May 05 12:24:06 PM PDT 24
Finished May 05 12:31:52 PM PDT 24
Peak memory 200048 kb
Host smart-1fff49d0-d7ad-45c3-a401-ceae0b10f4eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019559605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3019559605
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3970115590
Short name T462
Test name
Test status
Simulation time 15362222 ps
CPU time 0.58 seconds
Started May 05 12:24:21 PM PDT 24
Finished May 05 12:24:22 PM PDT 24
Peak memory 195620 kb
Host smart-d6adfa61-9cd5-41fd-a794-6611b615c058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970115590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3970115590
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3063340117
Short name T175
Test name
Test status
Simulation time 1426928068 ps
CPU time 38.64 seconds
Started May 05 12:24:46 PM PDT 24
Finished May 05 12:25:26 PM PDT 24
Peak memory 214640 kb
Host smart-ca5dc888-ec5a-4bee-99b8-3998448e716b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063340117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3063340117
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.197745349
Short name T364
Test name
Test status
Simulation time 1190316239 ps
CPU time 27.15 seconds
Started May 05 12:24:15 PM PDT 24
Finished May 05 12:24:45 PM PDT 24
Peak memory 199844 kb
Host smart-c9c4c2e4-dcd6-4f04-865e-935382d0af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197745349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.197745349
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2256578646
Short name T437
Test name
Test status
Simulation time 1763523133 ps
CPU time 101.5 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:25:58 PM PDT 24
Peak memory 199892 kb
Host smart-02f3ccff-af26-4f52-91dd-c5efe822c16e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256578646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2256578646
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2505775785
Short name T20
Test name
Test status
Simulation time 4342683544 ps
CPU time 84.35 seconds
Started May 05 12:24:31 PM PDT 24
Finished May 05 12:25:57 PM PDT 24
Peak memory 199932 kb
Host smart-c634b716-dd22-44f5-a5a7-e04e7bf8368e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505775785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2505775785
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.132792644
Short name T393
Test name
Test status
Simulation time 413203777 ps
CPU time 6.88 seconds
Started May 05 12:24:10 PM PDT 24
Finished May 05 12:24:21 PM PDT 24
Peak memory 199884 kb
Host smart-0f6a761b-98de-4ce4-a56f-86059c33cbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132792644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.132792644
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1695591556
Short name T272
Test name
Test status
Simulation time 41165497 ps
CPU time 1.05 seconds
Started May 05 12:24:19 PM PDT 24
Finished May 05 12:24:21 PM PDT 24
Peak memory 198208 kb
Host smart-3d086507-33fd-4602-9e38-72cdb095a9dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695591556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1695591556
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1575772013
Short name T109
Test name
Test status
Simulation time 51383417993 ps
CPU time 421.33 seconds
Started May 05 12:25:59 PM PDT 24
Finished May 05 12:33:01 PM PDT 24
Peak memory 199568 kb
Host smart-e573bea9-a182-4f1b-80af-6a35049ad8eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575772013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1575772013
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2202249105
Short name T124
Test name
Test status
Simulation time 10971901 ps
CPU time 0.57 seconds
Started May 05 12:20:46 PM PDT 24
Finished May 05 12:20:47 PM PDT 24
Peak memory 195160 kb
Host smart-2a5eecdd-33b7-4e14-97be-63836df7a2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202249105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2202249105
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3000884569
Short name T451
Test name
Test status
Simulation time 1875624766 ps
CPU time 49.27 seconds
Started May 05 12:21:42 PM PDT 24
Finished May 05 12:22:32 PM PDT 24
Peak memory 223764 kb
Host smart-bb27ab3d-a6c3-4d4b-9ad3-16480805e8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000884569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3000884569
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.57071187
Short name T335
Test name
Test status
Simulation time 3844056990 ps
CPU time 30.67 seconds
Started May 05 12:21:45 PM PDT 24
Finished May 05 12:22:17 PM PDT 24
Peak memory 199920 kb
Host smart-37e04d2a-e54f-40d2-9384-6bfc70b00275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57071187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.57071187
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.252361982
Short name T237
Test name
Test status
Simulation time 2128525114 ps
CPU time 127.53 seconds
Started May 05 12:21:20 PM PDT 24
Finished May 05 12:23:28 PM PDT 24
Peak memory 199796 kb
Host smart-2e72affa-592d-4299-beb0-5642dcb8b39c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252361982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.252361982
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3212640061
Short name T153
Test name
Test status
Simulation time 5322942326 ps
CPU time 79.1 seconds
Started May 05 12:21:23 PM PDT 24
Finished May 05 12:22:43 PM PDT 24
Peak memory 200240 kb
Host smart-3553c2dd-42fd-49c7-940c-1fd6c8de9572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212640061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3212640061
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.927786713
Short name T68
Test name
Test status
Simulation time 533089839 ps
CPU time 6.14 seconds
Started May 05 12:24:13 PM PDT 24
Finished May 05 12:24:23 PM PDT 24
Peak memory 199472 kb
Host smart-c5b13e43-11a7-4839-baf7-285ea6890084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927786713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.927786713
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3853980250
Short name T129
Test name
Test status
Simulation time 136479030 ps
CPU time 1.36 seconds
Started May 05 12:21:23 PM PDT 24
Finished May 05 12:21:25 PM PDT 24
Peak memory 199788 kb
Host smart-c6d8e02c-a38a-4cbd-b5b8-b7241aef08e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853980250 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3853980250
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2047713349
Short name T382
Test name
Test status
Simulation time 144977941821 ps
CPU time 424.28 seconds
Started May 05 12:24:05 PM PDT 24
Finished May 05 12:31:14 PM PDT 24
Peak memory 199676 kb
Host smart-88752b18-ce34-4553-add6-deb7e88d7c15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047713349 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2047713349
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.984128388
Short name T267
Test name
Test status
Simulation time 19359828 ps
CPU time 0.56 seconds
Started May 05 12:22:57 PM PDT 24
Finished May 05 12:22:58 PM PDT 24
Peak memory 195256 kb
Host smart-e40b897f-1b9b-446b-b606-1428011c7356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984128388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.984128388
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2880552703
Short name T426
Test name
Test status
Simulation time 467219859 ps
CPU time 5.66 seconds
Started May 05 12:21:42 PM PDT 24
Finished May 05 12:21:49 PM PDT 24
Peak memory 216020 kb
Host smart-13bd164e-3e17-4dd2-943c-6665a4d93bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880552703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2880552703
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2853520922
Short name T328
Test name
Test status
Simulation time 22606060 ps
CPU time 0.83 seconds
Started May 05 12:24:51 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 199320 kb
Host smart-e2925763-60ad-4d82-8f39-8fb6ac9ceaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853520922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2853520922
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.462293565
Short name T337
Test name
Test status
Simulation time 1975484465 ps
CPU time 108.69 seconds
Started May 05 12:24:38 PM PDT 24
Finished May 05 12:26:28 PM PDT 24
Peak memory 198612 kb
Host smart-220c680c-1d53-4e3a-94c1-c627e1e1e678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462293565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.462293565
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.179508832
Short name T453
Test name
Test status
Simulation time 15967671278 ps
CPU time 62.28 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:21:12 PM PDT 24
Peak memory 199976 kb
Host smart-0348ef2e-ad09-4e22-966a-f2a51f356678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179508832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.179508832
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2792951700
Short name T79
Test name
Test status
Simulation time 82934032 ps
CPU time 2.96 seconds
Started May 05 12:20:09 PM PDT 24
Finished May 05 12:20:13 PM PDT 24
Peak memory 199836 kb
Host smart-7027d7e5-341d-4763-bd1f-7d168d67e06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792951700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2792951700
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.808246632
Short name T407
Test name
Test status
Simulation time 68830203 ps
CPU time 1.28 seconds
Started May 05 12:21:57 PM PDT 24
Finished May 05 12:21:59 PM PDT 24
Peak memory 199888 kb
Host smart-d27efa09-de85-4891-9423-49b2439a24bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808246632 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.808246632
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3786525953
Short name T360
Test name
Test status
Simulation time 101171289235 ps
CPU time 445.4 seconds
Started May 05 12:24:38 PM PDT 24
Finished May 05 12:32:05 PM PDT 24
Peak memory 199596 kb
Host smart-a58c2384-c1d7-4044-b508-c4cca5259088
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786525953 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3786525953
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4002632539
Short name T456
Test name
Test status
Simulation time 16814238 ps
CPU time 0.59 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:24:36 PM PDT 24
Peak memory 195200 kb
Host smart-34e22cc9-6af4-4e41-b977-d66727647ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002632539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4002632539
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.253860061
Short name T454
Test name
Test status
Simulation time 573945344 ps
CPU time 33.4 seconds
Started May 05 12:22:50 PM PDT 24
Finished May 05 12:23:24 PM PDT 24
Peak memory 216576 kb
Host smart-6fa167d3-7e7a-480c-8cb2-11690ef4c22e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253860061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.253860061
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2983469839
Short name T381
Test name
Test status
Simulation time 1841102736 ps
CPU time 25.49 seconds
Started May 05 12:24:49 PM PDT 24
Finished May 05 12:25:17 PM PDT 24
Peak memory 198780 kb
Host smart-e911a023-ea3a-4ea4-9cf4-6e8c68b76088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983469839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2983469839
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1605003463
Short name T118
Test name
Test status
Simulation time 955406895 ps
CPU time 54.17 seconds
Started May 05 12:23:19 PM PDT 24
Finished May 05 12:24:14 PM PDT 24
Peak memory 199828 kb
Host smart-629a8ade-7bd9-426a-94c4-7930e667c429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605003463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1605003463
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1567577161
Short name T365
Test name
Test status
Simulation time 3699493159 ps
CPU time 52.26 seconds
Started May 05 12:20:10 PM PDT 24
Finished May 05 12:21:03 PM PDT 24
Peak memory 199276 kb
Host smart-f0986cf4-c6d3-4ae6-90c2-33900227980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567577161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1567577161
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2447116028
Short name T442
Test name
Test status
Simulation time 218808245 ps
CPU time 6.33 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:24:45 PM PDT 24
Peak memory 198420 kb
Host smart-66fdb7ea-de3e-45b6-bcdf-5f5f731ef9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447116028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2447116028
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2043375726
Short name T461
Test name
Test status
Simulation time 33328391 ps
CPU time 1.26 seconds
Started May 05 12:22:49 PM PDT 24
Finished May 05 12:22:51 PM PDT 24
Peak memory 199804 kb
Host smart-c204b550-f312-466c-be53-e6b49e036f08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043375726 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2043375726
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.661487886
Short name T410
Test name
Test status
Simulation time 32752137719 ps
CPU time 462.55 seconds
Started May 05 12:23:19 PM PDT 24
Finished May 05 12:31:02 PM PDT 24
Peak memory 199904 kb
Host smart-1500fac7-08f9-4db6-822f-ce4b31bb5e58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661487886 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.661487886
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.142206016
Short name T411
Test name
Test status
Simulation time 11611495 ps
CPU time 0.59 seconds
Started May 05 12:20:13 PM PDT 24
Finished May 05 12:20:14 PM PDT 24
Peak memory 195424 kb
Host smart-7b912fe4-1da4-4269-8785-38ed79ca54c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142206016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.142206016
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2618126178
Short name T312
Test name
Test status
Simulation time 2128676269 ps
CPU time 50.93 seconds
Started May 05 12:22:03 PM PDT 24
Finished May 05 12:22:55 PM PDT 24
Peak memory 247660 kb
Host smart-53642c2d-d6f6-4c79-89a6-98caa62f7f04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618126178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2618126178
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2887305064
Short name T260
Test name
Test status
Simulation time 5804409864 ps
CPU time 27.03 seconds
Started May 05 12:24:26 PM PDT 24
Finished May 05 12:24:55 PM PDT 24
Peak memory 198044 kb
Host smart-49314b93-85c0-49a4-9097-8056b8d79ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887305064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2887305064
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3555535605
Short name T284
Test name
Test status
Simulation time 1949555033 ps
CPU time 58.24 seconds
Started May 05 12:21:43 PM PDT 24
Finished May 05 12:22:42 PM PDT 24
Peak memory 199824 kb
Host smart-d812e9f8-8a12-4216-8ed1-72fe4c67e4d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3555535605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3555535605
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3163785872
Short name T9
Test name
Test status
Simulation time 15218579379 ps
CPU time 84.73 seconds
Started May 05 12:20:00 PM PDT 24
Finished May 05 12:21:26 PM PDT 24
Peak memory 199824 kb
Host smart-9473ff11-c61f-4b68-8518-1da06ba35f50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163785872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3163785872
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.733483755
Short name T362
Test name
Test status
Simulation time 4950357149 ps
CPU time 88.52 seconds
Started May 05 12:24:26 PM PDT 24
Finished May 05 12:25:56 PM PDT 24
Peak memory 198160 kb
Host smart-d6ed94bd-21f9-4fc0-8508-2c9e47195438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733483755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.733483755
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3767981812
Short name T128
Test name
Test status
Simulation time 305706073 ps
CPU time 3.51 seconds
Started May 05 12:24:35 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 199404 kb
Host smart-ba9bb760-967a-4abe-bb4b-1e47604f2a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767981812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3767981812
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1293797599
Short name T42
Test name
Test status
Simulation time 32308568 ps
CPU time 1.21 seconds
Started May 05 12:24:33 PM PDT 24
Finished May 05 12:24:36 PM PDT 24
Peak memory 199480 kb
Host smart-de8470b2-1c69-4f6f-911a-1bb0fdb560ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293797599 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1293797599
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1098503139
Short name T158
Test name
Test status
Simulation time 30940044695 ps
CPU time 503.71 seconds
Started May 05 12:24:34 PM PDT 24
Finished May 05 12:33:00 PM PDT 24
Peak memory 198124 kb
Host smart-c71b0a68-a619-4d3d-8530-7995b10b9cdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098503139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1098503139
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4260049410
Short name T273
Test name
Test status
Simulation time 20119589 ps
CPU time 0.61 seconds
Started May 05 12:23:48 PM PDT 24
Finished May 05 12:23:50 PM PDT 24
Peak memory 194296 kb
Host smart-d1c61948-f41e-4579-af4e-fcd8fa803dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260049410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4260049410
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3793765221
Short name T358
Test name
Test status
Simulation time 550532032 ps
CPU time 23.43 seconds
Started May 05 12:24:36 PM PDT 24
Finished May 05 12:25:01 PM PDT 24
Peak memory 207952 kb
Host smart-420fc938-6b4f-4778-9175-f1970b1e0509
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793765221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3793765221
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1865128957
Short name T329
Test name
Test status
Simulation time 254280384 ps
CPU time 2.19 seconds
Started May 05 12:24:37 PM PDT 24
Finished May 05 12:24:40 PM PDT 24
Peak memory 199684 kb
Host smart-c5ce86d2-9708-4ff8-87b9-ee671807cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865128957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1865128957
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4292616499
Short name T198
Test name
Test status
Simulation time 13988273402 ps
CPU time 88.58 seconds
Started May 05 12:22:08 PM PDT 24
Finished May 05 12:23:37 PM PDT 24
Peak memory 199920 kb
Host smart-34615056-dced-49ba-8d4a-2f585df30b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292616499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4292616499
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3746282630
Short name T368
Test name
Test status
Simulation time 1743067883 ps
CPU time 89.73 seconds
Started May 05 12:24:37 PM PDT 24
Finished May 05 12:26:08 PM PDT 24
Peak memory 199744 kb
Host smart-8cd8cb7b-3835-4404-8b37-be8f52beb3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746282630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3746282630
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3996906038
Short name T180
Test name
Test status
Simulation time 113420941 ps
CPU time 1.32 seconds
Started May 05 12:20:54 PM PDT 24
Finished May 05 12:20:56 PM PDT 24
Peak memory 199904 kb
Host smart-4336652f-25df-41de-aa6c-14a7da289de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996906038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3996906038
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2593958311
Short name T441
Test name
Test status
Simulation time 179485495 ps
CPU time 1.07 seconds
Started May 05 12:24:20 PM PDT 24
Finished May 05 12:24:22 PM PDT 24
Peak memory 199440 kb
Host smart-5499ccb2-6c98-42df-816f-9489f15c7300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593958311 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2593958311
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1982223622
Short name T269
Test name
Test status
Simulation time 8239948045 ps
CPU time 465.91 seconds
Started May 05 12:21:31 PM PDT 24
Finished May 05 12:29:17 PM PDT 24
Peak memory 199980 kb
Host smart-ea35a529-4038-41a3-9d15-773b6fa5a7d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982223622 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1982223622
Directory /workspace/9.hmac_test_sha_vectors/latest
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