Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5019396	1			T1	17		T4	90		T5	14351
all_values[1]	5019396	1			T1	17		T4	90		T5	14351
all_values[2]	5019396	1			T1	17		T4	90		T5	14351

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34080

1

T6

590

T13

9

T18

2

auto[1]

15024108

1

T1

51

T4

270

T5

43053

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13921243

1

T1

37

T4

222

T5

34703

auto[1]

1136945

1

T1

14

T4

48

T5

8350

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	12996	1			T51	3		T115	11		T52	2
all_values[0]	auto[0]	auto[1]	138	1			T115	2		T116	2		T117	2
all_values[0]	auto[1]	auto[0]	4991794	1			T1	17		T4	70		T5	14316
all_values[0]	auto[1]	auto[1]	14468	1			T4	20		T5	35		T6	16
all_values[1]	auto[0]	auto[0]	9575	1			T6	295		T13	9		T18	2
all_values[1]	auto[0]	auto[1]	86	1			T24	1		T20	2		T63	3
all_values[1]	auto[1]	auto[0]	5009637	1			T1	17		T4	90		T5	14351
all_values[1]	auto[1]	auto[1]	98	1			T29	1		T24	2		T118	1
all_values[2]	auto[0]	auto[0]	5690	1			T6	2		T98	10		T100	2
all_values[2]	auto[0]	auto[1]	5595	1			T6	293		T114	403		T51	4
all_values[2]	auto[1]	auto[0]	3891551	1			T1	3		T4	62		T5	6036
all_values[2]	auto[1]	auto[1]	1116560	1			T1	14		T4	28		T5	8315