Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2572658

1

T4

22

T5

5288

T6

3552

auto[1]

641346

1

T1

25

T4

19

T5

9452

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620763

1

T4

19

T5

7134

T6

3002

auto[1]

2593241

1

T1

25

T4

22

T5

7606

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2308018

1

T4

18

T5

10772

T6

3552

auto[1]

905986

1

T1

25

T4

23

T5

3968

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	2649236	1			T1	25		T4	22		T5	14321
fifo_depth[1]	106464	1			T5	193		T6	81		T7	3
fifo_depth[2]	78818	1			T5	128		T6	83		T7	2
fifo_depth[3]	59965	1			T5	68		T6	56		T13	28
fifo_depth[4]	47098	1			T5	21		T6	75		T13	59
fifo_depth[5]	39667	1			T5	5		T6	63		T13	25
fifo_depth[6]	37362	1			T5	3		T6	75		T13	35
fifo_depth[7]	30354	1			T5	1		T6	60		T13	24
fifo_depth[8]	25967	1			T6	57		T13	20		T47	99
fifo_depth[9]	18127	1			T6	52		T13	11		T47	80
fifo_depth[10]	14319	1			T6	21		T13	4		T47	57
fifo_depth[11]	8339	1			T6	24		T13	4		T47	31
fifo_depth[12]	7822	1			T6	14		T18	1		T47	23
fifo_depth[13]	4018	1			T4	1		T6	10		T47	9
fifo_depth[14]	6126	1			T6	5		T47	6		T9	14
fifo_depth[15]	2964	1			T6	1		T47	4		T9	6
fifo_depth[16]	8473	1			T6	1		T18	2		T47	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571485

1

T4

20

T5

419

T6

678

auto[1]

2642519

1

T1

25

T4

21

T5

14321

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3207287

1

T1

25

T4

40

T5

14740

auto[1]

6717

1

T4

1

T18

1

T49

4

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

33998

1

T4

2

T5

94

T6

146

auto[0]

auto[0]

auto[0]

auto[1]

22396

1

T4

3

T5

11

T12

2

auto[0]

auto[0]

auto[1]

auto[0]

335884

1

T4

3

T5

48

T6

90

auto[0]

auto[0]

auto[1]

auto[1]

29863

1

T4

3

T5

236

T6

117

auto[0]

auto[1]

auto[0]

auto[0]

36869

1

T4

3

T5

11

T6

62

auto[0]

auto[1]

auto[0]

auto[1]

32536

1

T4

2

T6

175

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

45732

1

T4

1

T5

7

T6

88

auto[0]

auto[1]

auto[1]

auto[1]

34207

1

T4

3

T5

12

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

51655

1

T4

2

T5

1609

T6

324

auto[1]

auto[0]

auto[0]

auto[1]

69439

1

T4

2

T5

4468

T6

11

auto[1]

auto[0]

auto[1]

auto[0]

1696073

1

T4

2

T5

1500

T6

1710

auto[1]

auto[0]

auto[1]

auto[1]

68710

1

T4

1

T5

2806

T6

1154

auto[1]

auto[1]

auto[0]

auto[0]

189058

1

T4

3

T5

504

T6

953

auto[1]

auto[1]

auto[0]

auto[1]

184812

1

T4

2

T5

437

T6

1331

auto[1]

auto[1]

auto[1]

auto[0]

183389

1

T4

6

T5

1515

T6

179

auto[1]

auto[1]

auto[1]

auto[1]

199383

1

T1

25

T4

3

T5

1482

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

84281

1

T4

4

T5

1703

T6

470

auto[0]

auto[0]

auto[0]

auto[1]

91075

1

T4

5

T5

4479

T6

11

auto[0]

auto[0]

auto[1]

auto[0]

2031023

1

T4

4

T5

1548

T6

1800

auto[0]

auto[0]

auto[1]

auto[1]

97093

1

T4

4

T5

3042

T6

1271

auto[0]

auto[1]

auto[0]

auto[0]

225573

1

T4

6

T5

515

T6

1015

auto[0]

auto[1]

auto[0]

auto[1]

217122

1

T4

4

T5

437

T6

1506

auto[0]

auto[1]

auto[1]

auto[0]

228221

1

T4

7

T5

1522

T6

267

auto[0]

auto[1]

auto[1]

auto[1]

232899

1

T1

25

T4

6

T5

1494

auto[1]

auto[0]

auto[0]

auto[0]

1372

1

T27

17

T39

2

T29

15

auto[1]

auto[0]

auto[0]

auto[1]

760

1

T49

1

T52

1

T29

27

auto[1]

auto[0]

auto[1]

auto[0]

934

1

T4

1

T18

1

T27

152

auto[1]

auto[0]

auto[1]

auto[1]

1480

1

T49

1

T27

270

T54

1

auto[1]

auto[1]

auto[0]

auto[0]

354

1

T49

1

T51

1

T27

26

auto[1]

auto[1]

auto[0]

auto[1]

226

1

T27

6

T52

1

T29

8

auto[1]

auto[1]

auto[1]

auto[0]

900

1

T27

59

T52

1

T128

10

auto[1]

auto[1]

auto[1]

auto[1]

691

1

T49

1

T53

1

T117

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	53027	1			T4	2		T5	1609		T6	324
fifo_depth[0]	auto[0]	auto[0]	auto[1]	70199	1			T4	2		T5	4468		T6	11
fifo_depth[0]	auto[0]	auto[1]	auto[0]	1697007	1			T4	3		T5	1500		T6	1710
fifo_depth[0]	auto[0]	auto[1]	auto[1]	70190	1			T4	1		T5	2806		T6	1154
fifo_depth[0]	auto[1]	auto[0]	auto[0]	189412	1			T4	3		T5	504		T6	953
fifo_depth[0]	auto[1]	auto[0]	auto[1]	185038	1			T4	2		T5	437		T6	1331
fifo_depth[0]	auto[1]	auto[1]	auto[0]	184289	1			T4	6		T5	1515		T6	179
fifo_depth[0]	auto[1]	auto[1]	auto[1]	200074	1			T1	25		T4	3		T5	1482
fifo_depth[1]	auto[0]	auto[0]	auto[0]	1228	1			T5	46		T6	21		T12	1
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1422	1			T5	6		T13	4		T47	18
fifo_depth[1]	auto[0]	auto[1]	auto[0]	88380	1			T5	15		T6	7		T13	2
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1779	1			T5	106		T6	17		T13	5
fifo_depth[1]	auto[1]	auto[0]	auto[0]	3065	1			T5	6		T6	7		T47	8
fifo_depth[1]	auto[1]	auto[0]	auto[1]	2987	1			T6	18		T7	1		T13	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	3955	1			T5	4		T6	11		T7	1
fifo_depth[1]	auto[1]	auto[1]	auto[1]	3648	1			T5	10		T7	1		T13	4
fifo_depth[2]	auto[0]	auto[0]	auto[0]	1127	1			T5	28		T6	19		T13	10
fifo_depth[2]	auto[0]	auto[0]	auto[1]	1290	1			T5	3		T13	3		T47	16
fifo_depth[2]	auto[0]	auto[1]	auto[0]	61791	1			T5	15		T6	16		T8	613
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1676	1			T5	76		T6	10		T13	29
fifo_depth[2]	auto[1]	auto[0]	auto[0]	3026	1			T5	2		T6	8		T13	3
fifo_depth[2]	auto[1]	auto[0]	auto[1]	2768	1			T6	19		T7	1		T13	3
fifo_depth[2]	auto[1]	auto[1]	auto[0]	3676	1			T5	3		T6	11		T7	1
fifo_depth[2]	auto[1]	auto[1]	auto[1]	3464	1			T5	1		T13	6		T47	21
fifo_depth[3]	auto[0]	auto[0]	auto[0]	893	1			T5	13		T6	12		T13	10
fifo_depth[3]	auto[0]	auto[0]	auto[1]	995	1			T5	2		T13	3		T47	17
fifo_depth[3]	auto[0]	auto[1]	auto[0]	44590	1			T5	12		T6	8		T13	1
fifo_depth[3]	auto[0]	auto[1]	auto[1]	1259	1			T5	38		T6	10		T13	3
fifo_depth[3]	auto[1]	auto[0]	auto[0]	2889	1			T5	2		T6	4		T47	11
fifo_depth[3]	auto[1]	auto[0]	auto[1]	2626	1			T6	16		T13	5		T47	72
fifo_depth[3]	auto[1]	auto[1]	auto[0]	3360	1			T6	6		T13	1		T97	1
fifo_depth[3]	auto[1]	auto[1]	auto[1]	3353	1			T5	1		T13	5		T47	21
fifo_depth[4]	auto[0]	auto[0]	auto[0]	1185	1			T5	5		T6	16		T13	9
fifo_depth[4]	auto[0]	auto[0]	auto[1]	1101	1			T13	19		T47	21		T112	5
fifo_depth[4]	auto[0]	auto[1]	auto[0]	31392	1			T5	4		T6	12		T13	16
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1230	1			T5	11		T6	14		T13	6
fifo_depth[4]	auto[1]	auto[0]	auto[0]	2860	1			T5	1		T6	5		T13	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	2567	1			T6	19		T13	4		T47	72
fifo_depth[4]	auto[1]	auto[1]	auto[0]	3437	1			T6	9		T13	1		T47	4
fifo_depth[4]	auto[1]	auto[1]	auto[1]	3326	1			T13	3		T47	26		T10	51
fifo_depth[5]	auto[0]	auto[0]	auto[0]	828	1			T6	16		T13	10		T21	13
fifo_depth[5]	auto[0]	auto[0]	auto[1]	953	1			T13	4		T47	18		T113	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	25196	1			T5	2		T6	9		T8	30
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1054	1			T5	3		T6	9		T13	5
fifo_depth[5]	auto[1]	auto[0]	auto[0]	2727	1			T6	7		T47	12		T10	51
fifo_depth[5]	auto[1]	auto[0]	auto[1]	2522	1			T6	17		T13	3		T47	64
fifo_depth[5]	auto[1]	auto[1]	auto[0]	3280	1			T6	5		T13	1		T97	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	3107	1			T13	2		T47	21		T10	48
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1479	1			T5	2		T6	12		T13	10
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1165	1			T13	2		T47	10		T112	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	21743	1			T6	14		T8	4		T17	7
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1213	1			T5	1		T6	17		T13	11
fifo_depth[6]	auto[1]	auto[0]	auto[0]	2776	1			T6	6		T13	1		T47	11
fifo_depth[6]	auto[1]	auto[0]	auto[1]	2605	1			T6	12		T13	3		T47	74
fifo_depth[6]	auto[1]	auto[1]	auto[0]	3223	1			T6	14		T13	1		T47	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	3158	1			T13	7		T47	22		T10	43
fifo_depth[7]	auto[0]	auto[0]	auto[0]	933	1			T6	13		T13	9		T21	12
fifo_depth[7]	auto[0]	auto[0]	auto[1]	850	1			T13	5		T47	16		T115	37
fifo_depth[7]	auto[0]	auto[1]	auto[0]	16975	1			T6	7		T8	2		T17	1
fifo_depth[7]	auto[0]	auto[1]	auto[1]	993	1			T5	1		T6	10		T13	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	2465	1			T6	8		T47	9		T10	53
fifo_depth[7]	auto[1]	auto[0]	auto[1]	2334	1			T6	14		T13	4		T47	74
fifo_depth[7]	auto[1]	auto[1]	auto[0]	2946	1			T6	8		T13	3		T47	3
fifo_depth[7]	auto[1]	auto[1]	auto[1]	2858	1			T13	2		T47	20		T10	51
fifo_depth[8]	auto[0]	auto[0]	auto[0]	1330	1			T6	13		T13	5		T21	5
fifo_depth[8]	auto[0]	auto[0]	auto[1]	893	1			T13	10		T47	12		T115	44
fifo_depth[8]	auto[0]	auto[1]	auto[0]	12482	1			T6	8		T13	1		T9	591
fifo_depth[8]	auto[0]	auto[1]	auto[1]	1272	1			T6	10		T115	122		T27	2
fifo_depth[8]	auto[1]	auto[0]	auto[0]	2455	1			T6	4		T13	1		T47	5
fifo_depth[8]	auto[1]	auto[0]	auto[1]	2252	1			T6	16		T47	62		T97	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	2789	1			T6	6		T13	1		T47	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	2494	1			T13	2		T47	19		T10	32
fifo_depth[9]	auto[0]	auto[0]	auto[0]	940	1			T6	8		T13	5		T21	3
fifo_depth[9]	auto[0]	auto[0]	auto[1]	643	1			T13	3		T47	10		T115	44
fifo_depth[9]	auto[0]	auto[1]	auto[0]	8568	1			T6	4		T9	372		T129	205
fifo_depth[9]	auto[0]	auto[1]	auto[1]	761	1			T6	13		T115	90		T27	3
fifo_depth[9]	auto[1]	auto[0]	auto[0]	1694	1			T6	3		T47	1		T10	40
fifo_depth[9]	auto[1]	auto[0]	auto[1]	1697	1			T6	18		T13	1		T47	59
fifo_depth[9]	auto[1]	auto[1]	auto[0]	1971	1			T6	6		T13	1		T47	1
fifo_depth[9]	auto[1]	auto[1]	auto[1]	1853	1			T13	1		T47	9		T10	28
fifo_depth[10]	auto[0]	auto[0]	auto[0]	1183	1			T6	6		T13	2		T21	1
fifo_depth[10]	auto[0]	auto[0]	auto[1]	799	1			T13	1		T47	9		T115	27
fifo_depth[10]	auto[0]	auto[1]	auto[0]	5762	1			T6	2		T9	200		T129	119
fifo_depth[10]	auto[0]	auto[1]	auto[1]	838	1			T6	2		T115	71		T27	3
fifo_depth[10]	auto[1]	auto[0]	auto[0]	1373	1			T6	3		T47	6		T10	27
fifo_depth[10]	auto[1]	auto[0]	auto[1]	1340	1			T6	5		T47	37		T11	27
fifo_depth[10]	auto[1]	auto[1]	auto[0]	1668	1			T6	3		T11	12		T21	2
fifo_depth[10]	auto[1]	auto[1]	auto[1]	1356	1			T13	1		T47	5		T10	17
fifo_depth[11]	auto[0]	auto[0]	auto[0]	753	1			T6	4		T13	1		T21	1
fifo_depth[11]	auto[0]	auto[0]	auto[1]	403	1			T47	3		T115	12		T29	11
fifo_depth[11]	auto[0]	auto[1]	auto[0]	3097	1			T6	2		T9	121		T129	49
fifo_depth[11]	auto[0]	auto[1]	auto[1]	436	1			T6	2		T13	2		T115	27
fifo_depth[11]	auto[1]	auto[0]	auto[0]	851	1			T6	4		T47	3		T10	25
fifo_depth[11]	auto[1]	auto[0]	auto[1]	902	1			T6	7		T47	22		T11	18
fifo_depth[11]	auto[1]	auto[1]	auto[0]	1037	1			T6	5		T11	12		T21	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	860	1			T13	1		T47	3		T10	13
fifo_depth[12]	auto[0]	auto[0]	auto[0]	1224	1			T6	4		T115	5		T27	75
fifo_depth[12]	auto[0]	auto[0]	auto[1]	605	1			T47	3		T115	5		T29	57
fifo_depth[12]	auto[0]	auto[1]	auto[0]	1824	1			T9	49		T129	21		T130	47
fifo_depth[12]	auto[0]	auto[1]	auto[1]	641	1			T6	1		T115	18		T27	2
fifo_depth[12]	auto[1]	auto[0]	auto[0]	797	1			T6	1		T10	7		T11	5
fifo_depth[12]	auto[1]	auto[0]	auto[1]	985	1			T6	6		T47	18		T11	2
fifo_depth[12]	auto[1]	auto[1]	auto[0]	1239	1			T6	2		T18	1		T11	9
fifo_depth[12]	auto[1]	auto[1]	auto[1]	507	1			T47	2		T10	8		T11	7
fifo_depth[13]	auto[0]	auto[0]	auto[0]	789	1			T6	2		T115	6		T27	21
fifo_depth[13]	auto[0]	auto[0]	auto[1]	272	1			T47	1		T49	1		T115	4
fifo_depth[13]	auto[0]	auto[1]	auto[0]	986	1			T6	1		T9	30		T129	15
fifo_depth[13]	auto[0]	auto[1]	auto[1]	315	1			T4	1		T115	8		T27	7
fifo_depth[13]	auto[1]	auto[0]	auto[0]	428	1			T6	1		T47	1		T10	4
fifo_depth[13]	auto[1]	auto[0]	auto[1]	477	1			T6	4		T47	5		T11	5
fifo_depth[13]	auto[1]	auto[1]	auto[0]	491	1			T6	2		T11	8		T99	8
fifo_depth[13]	auto[1]	auto[1]	auto[1]	260	1			T47	2		T10	2		T11	2
fifo_depth[14]	auto[0]	auto[0]	auto[0]	1493	1			T50	1		T115	2		T27	180
fifo_depth[14]	auto[0]	auto[0]	auto[1]	737	1			T29	176		T128	1		T131	48
fifo_depth[14]	auto[0]	auto[1]	auto[0]	1040	1			T9	14		T129	4		T130	11
fifo_depth[14]	auto[0]	auto[1]	auto[1]	918	1			T27	23		T28	35		T29	122
fifo_depth[14]	auto[1]	auto[0]	auto[0]	383	1			T6	1		T47	2		T10	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	638	1			T6	4		T47	3		T11	2
fifo_depth[14]	auto[1]	auto[1]	auto[0]	761	1			T11	2		T99	4		T132	2
fifo_depth[14]	auto[1]	auto[1]	auto[1]	156	1			T47	1		T10	2		T11	1
fifo_depth[15]	auto[0]	auto[0]	auto[0]	767	1			T115	1		T27	39		T28	4
fifo_depth[15]	auto[0]	auto[0]	auto[1]	364	1			T29	9		T128	3		T131	46
fifo_depth[15]	auto[0]	auto[1]	auto[0]	432	1			T9	6		T129	3		T130	4
fifo_depth[15]	auto[0]	auto[1]	auto[1]	313	1			T6	1		T49	2		T115	2
fifo_depth[15]	auto[1]	auto[0]	auto[0]	271	1			T10	2		T11	1		T100	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	385	1			T47	4		T11	2		T99	1
fifo_depth[15]	auto[1]	auto[1]	auto[0]	330	1			T11	1		T133	2		T27	9
fifo_depth[15]	auto[1]	auto[1]	auto[1]	102	1			T11	3		T133	2		T27	3
fifo_depth[16]	auto[0]	auto[0]	auto[0]	1034	1			T27	68		T28	6		T29	67
fifo_depth[16]	auto[0]	auto[0]	auto[1]	1003	1			T29	43		T131	339		T134	22
fifo_depth[16]	auto[0]	auto[1]	auto[0]	1025	1			T9	2		T130	1		T27	447
fifo_depth[16]	auto[0]	auto[1]	auto[1]	3083	1			T6	1		T28	33		T29	79
fifo_depth[16]	auto[1]	auto[0]	auto[0]	597	1			T10	1		T27	48		T135	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	949	1			T18	1		T47	2		T99	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	633	1			T18	1		T99	1		T27	40
fifo_depth[16]	auto[1]	auto[1]	auto[1]	149	1			T47	1		T10	2		T99	2