Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5019396	1			T1	17		T4	90		T5	14351
all_pins[1]	5019396	1			T1	17		T4	90		T5	14351
all_pins[2]	5019396	1			T1	17		T4	90		T5	14351

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	13926880	1			T1	37		T4	222		T5	34703
values[0x1]	1131308	1			T1	14		T4	48		T5	8350
transitions[0x0=>0x1]	1131227	1			T1	14		T4	48		T5	8350
transitions[0x1=>0x0]	1131245	1			T1	14		T4	48		T5	8350

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5004752	1			T1	17		T4	70		T5	14316
all_pins[0]	values[0x1]	14644	1			T4	20		T5	35		T6	17
all_pins[0]	transitions[0x0=>0x1]	14608	1			T4	20		T5	35		T6	17
all_pins[0]	transitions[0x1=>0x0]	1116542	1			T1	14		T4	28		T5	8315
all_pins[1]	values[0x0]	5019292	1			T1	17		T4	90		T5	14351
all_pins[1]	values[0x1]	104	1			T29	1		T24	2		T118	1
all_pins[1]	transitions[0x0=>0x1]	80	1			T29	1		T24	1		T118	1
all_pins[1]	transitions[0x1=>0x0]	14620	1			T4	20		T5	35		T6	17
all_pins[2]	values[0x0]	3902836	1			T1	3		T4	62		T5	6036
all_pins[2]	values[0x1]	1116560	1			T1	14		T4	28		T5	8315
all_pins[2]	transitions[0x0=>0x1]	1116539	1			T1	14		T4	28		T5	8315
all_pins[2]	transitions[0x1=>0x0]	83	1			T29	1		T24	2		T118	1