Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 399 1 T24 4 T20 8 T63 21
all_values[1] 399 1 T24 4 T20 8 T63 21
all_values[2] 399 1 T24 4 T20 8 T63 21


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 597 1 T24 5 T20 11 T63 33
auto[1] 600 1 T24 7 T20 13 T63 30


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 441 1 T24 1 T20 11 T63 17
auto[1] 756 1 T24 11 T20 13 T63 46


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 697 1 T24 4 T20 16 T63 32
auto[1] 500 1 T24 8 T20 8 T63 31


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 87 1 T20 2 T63 6 T79 6
all_values[0] auto[0] auto[0] auto[1] 33 1 T24 1 T63 3 T79 1
all_values[0] auto[0] auto[1] auto[0] 79 1 T20 3 T63 1 T79 1
all_values[0] auto[0] auto[1] auto[1] 40 1 T20 1 T63 2 T119 2
all_values[0] auto[1] auto[0] auto[1] 61 1 T24 1 T63 2 T79 2
all_values[0] auto[1] auto[1] auto[1] 99 1 T24 2 T20 2 T63 7
all_values[1] auto[0] auto[0] auto[0] 55 1 T20 1 T63 4 T79 1
all_values[1] auto[0] auto[0] auto[1] 52 1 T20 1 T63 5 T79 2
all_values[1] auto[0] auto[1] auto[0] 65 1 T20 2 T63 1 T79 1
all_values[1] auto[0] auto[1] auto[1] 49 1 T24 1 T20 1 T63 1
all_values[1] auto[1] auto[0] auto[1] 88 1 T24 1 T20 2 T63 4
all_values[1] auto[1] auto[1] auto[1] 90 1 T24 2 T20 1 T63 6
all_values[2] auto[0] auto[0] auto[0] 87 1 T24 1 T20 2 T63 2
all_values[2] auto[0] auto[0] auto[1] 37 1 T24 1 T20 2 T63 1
all_values[2] auto[0] auto[1] auto[0] 68 1 T20 1 T63 3 T79 3
all_values[2] auto[0] auto[1] auto[1] 45 1 T63 3 T79 1 T81 1
all_values[2] auto[1] auto[0] auto[1] 97 1 T20 1 T63 6 T79 3
all_values[2] auto[1] auto[1] auto[1] 65 1 T24 2 T20 2 T63 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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