Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.97 95.76 94.01 100.00 65.79 91.67 99.49 69.08


Total test records in report: 588
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.121893751 May 07 03:01:18 PM PDT 24 May 07 03:10:33 PM PDT 24 273626877871 ps
T507 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3935997476 May 07 03:01:00 PM PDT 24 May 07 03:01:03 PM PDT 24 81345856 ps
T508 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3457995054 May 07 03:01:02 PM PDT 24 May 07 03:01:06 PM PDT 24 1910799884 ps
T509 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3034973935 May 07 03:01:05 PM PDT 24 May 07 03:01:13 PM PDT 24 360261310 ps
T510 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2124873972 May 07 03:01:19 PM PDT 24 May 07 03:01:22 PM PDT 24 192554674 ps
T511 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3038501591 May 07 03:01:26 PM PDT 24 May 07 03:01:28 PM PDT 24 21586699 ps
T512 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3708069479 May 07 03:01:05 PM PDT 24 May 07 03:01:09 PM PDT 24 123202962 ps
T513 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.144616798 May 07 03:01:13 PM PDT 24 May 07 03:01:16 PM PDT 24 60622540 ps
T514 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2988558085 May 07 03:01:41 PM PDT 24 May 07 03:01:42 PM PDT 24 42935657 ps
T67 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1074856789 May 07 03:01:33 PM PDT 24 May 07 03:01:38 PM PDT 24 192233249 ps
T515 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1091461180 May 07 03:01:46 PM PDT 24 May 07 03:01:48 PM PDT 24 29229533 ps
T126 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2693475142 May 07 03:00:58 PM PDT 24 May 07 03:01:03 PM PDT 24 275605661 ps
T516 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4148073188 May 07 03:01:26 PM PDT 24 May 07 03:01:30 PM PDT 24 214773413 ps
T517 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2804394958 May 07 03:01:30 PM PDT 24 May 07 03:01:33 PM PDT 24 168263814 ps
T518 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3875869167 May 07 03:01:02 PM PDT 24 May 07 03:01:05 PM PDT 24 322254751 ps
T519 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3171460217 May 07 03:01:25 PM PDT 24 May 07 03:01:27 PM PDT 24 35666454 ps
T520 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.185874679 May 07 03:01:11 PM PDT 24 May 07 03:01:14 PM PDT 24 253940624 ps
T521 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1671322994 May 07 03:01:44 PM PDT 24 May 07 03:01:46 PM PDT 24 78520058 ps
T522 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3479715803 May 07 03:01:37 PM PDT 24 May 07 03:01:40 PM PDT 24 43213506 ps
T523 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.634987321 May 07 03:01:24 PM PDT 24 May 07 03:01:27 PM PDT 24 83213723 ps
T524 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2649777954 May 07 03:01:24 PM PDT 24 May 07 03:17:22 PM PDT 24 91869727586 ps
T525 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.695636631 May 07 03:00:58 PM PDT 24 May 07 03:01:11 PM PDT 24 3806144268 ps
T526 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.833771165 May 07 03:01:28 PM PDT 24 May 07 03:01:31 PM PDT 24 294299424 ps
T527 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4191865237 May 07 03:01:16 PM PDT 24 May 07 03:01:21 PM PDT 24 777617797 ps
T528 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2112255148 May 07 03:01:06 PM PDT 24 May 07 03:01:14 PM PDT 24 1491497169 ps
T529 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3429327951 May 07 03:01:31 PM PDT 24 May 07 03:01:36 PM PDT 24 483814022 ps
T530 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2218338464 May 07 03:01:39 PM PDT 24 May 07 03:01:41 PM PDT 24 42385253 ps
T531 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.117784352 May 07 03:01:00 PM PDT 24 May 07 03:01:02 PM PDT 24 57955574 ps
T532 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2733797519 May 07 03:01:24 PM PDT 24 May 07 03:01:25 PM PDT 24 41309910 ps
T111 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3530137309 May 07 03:01:18 PM PDT 24 May 07 03:01:20 PM PDT 24 81496389 ps
T533 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2675018392 May 07 03:01:06 PM PDT 24 May 07 03:01:09 PM PDT 24 19077234 ps
T534 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1417616940 May 07 03:01:30 PM PDT 24 May 07 03:01:32 PM PDT 24 20833331 ps
T535 /workspace/coverage/cover_reg_top/41.hmac_intr_test.939891605 May 07 03:01:45 PM PDT 24 May 07 03:01:47 PM PDT 24 21418436 ps
T536 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2133529973 May 07 03:01:39 PM PDT 24 May 07 03:01:40 PM PDT 24 42966747 ps
T121 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.749324687 May 07 03:01:14 PM PDT 24 May 07 03:01:19 PM PDT 24 365785616 ps
T537 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3816421367 May 07 03:01:30 PM PDT 24 May 07 03:01:33 PM PDT 24 26589247 ps
T538 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2345480782 May 07 03:01:31 PM PDT 24 May 07 03:01:34 PM PDT 24 27530561 ps
T539 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3884747519 May 07 03:00:57 PM PDT 24 May 07 03:00:59 PM PDT 24 361243799 ps
T540 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4282231460 May 07 03:00:51 PM PDT 24 May 07 03:00:55 PM PDT 24 244617948 ps
T541 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2212521205 May 07 03:01:15 PM PDT 24 May 07 03:01:19 PM PDT 24 48996213 ps
T542 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1868141675 May 07 03:01:40 PM PDT 24 May 07 03:01:41 PM PDT 24 14336746 ps
T543 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3676229869 May 07 03:01:25 PM PDT 24 May 07 03:01:27 PM PDT 24 56394517 ps
T544 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1897018418 May 07 03:01:13 PM PDT 24 May 07 03:01:15 PM PDT 24 110379462 ps
T545 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3376225250 May 07 03:01:44 PM PDT 24 May 07 03:01:46 PM PDT 24 129163814 ps
T546 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.647150412 May 07 03:01:25 PM PDT 24 May 07 03:01:29 PM PDT 24 142812051 ps
T547 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1216782689 May 07 03:01:40 PM PDT 24 May 07 03:01:42 PM PDT 24 73310331 ps
T548 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1242553841 May 07 03:01:11 PM PDT 24 May 07 03:01:14 PM PDT 24 733553285 ps
T549 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2183410117 May 07 03:01:37 PM PDT 24 May 07 03:01:38 PM PDT 24 14726926 ps
T550 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2055843637 May 07 03:00:59 PM PDT 24 May 07 03:01:06 PM PDT 24 670548670 ps
T551 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1192073852 May 07 03:00:52 PM PDT 24 May 07 03:00:53 PM PDT 24 59734918 ps
T552 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2639973507 May 07 03:00:51 PM PDT 24 May 07 03:01:08 PM PDT 24 2250352045 ps
T553 /workspace/coverage/cover_reg_top/8.hmac_intr_test.129280873 May 07 03:01:16 PM PDT 24 May 07 03:01:17 PM PDT 24 12789365 ps
T554 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.216572547 May 07 03:01:00 PM PDT 24 May 07 03:01:03 PM PDT 24 115131139 ps
T555 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2751969306 May 07 03:01:30 PM PDT 24 May 07 03:01:33 PM PDT 24 40816689 ps
T556 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3016831074 May 07 03:01:29 PM PDT 24 May 07 03:01:31 PM PDT 24 47095020 ps
T557 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1301266719 May 07 03:01:12 PM PDT 24 May 07 03:01:14 PM PDT 24 36517042 ps
T558 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1516954645 May 07 03:01:40 PM PDT 24 May 07 03:01:42 PM PDT 24 12271140 ps
T559 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2174282722 May 07 03:01:38 PM PDT 24 May 07 03:01:40 PM PDT 24 12392324 ps
T560 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1706397436 May 07 03:01:05 PM PDT 24 May 07 03:01:08 PM PDT 24 83948143 ps
T561 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2894514898 May 07 03:01:31 PM PDT 24 May 07 03:01:33 PM PDT 24 29140322 ps
T562 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3060792105 May 07 03:01:31 PM PDT 24 May 07 03:01:36 PM PDT 24 641734891 ps
T563 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3610173777 May 07 03:01:11 PM PDT 24 May 07 03:01:13 PM PDT 24 45866800 ps
T564 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.101526352 May 07 03:01:04 PM PDT 24 May 07 03:01:09 PM PDT 24 482978830 ps
T565 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2056096034 May 07 03:01:17 PM PDT 24 May 07 03:01:19 PM PDT 24 18483821 ps
T566 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3557372694 May 07 03:01:39 PM PDT 24 May 07 03:01:41 PM PDT 24 13007322 ps
T567 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.474274004 May 07 03:00:58 PM PDT 24 May 07 03:01:07 PM PDT 24 609853333 ps
T568 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3701358879 May 07 03:01:16 PM PDT 24 May 07 03:01:18 PM PDT 24 38312948 ps
T569 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3905733079 May 07 03:01:42 PM PDT 24 May 07 03:01:44 PM PDT 24 32136693 ps
T570 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2103758740 May 07 03:01:14 PM PDT 24 May 07 03:01:18 PM PDT 24 392677033 ps
T571 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3186980637 May 07 03:01:05 PM PDT 24 May 07 03:01:08 PM PDT 24 30702009 ps
T572 /workspace/coverage/cover_reg_top/29.hmac_intr_test.303967163 May 07 03:01:38 PM PDT 24 May 07 03:01:40 PM PDT 24 14457075 ps
T573 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2948948713 May 07 03:01:04 PM PDT 24 May 07 03:01:07 PM PDT 24 76789177 ps
T574 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2607387380 May 07 03:01:24 PM PDT 24 May 07 03:01:28 PM PDT 24 200374989 ps
T123 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2848606953 May 07 03:01:28 PM PDT 24 May 07 03:01:32 PM PDT 24 185887773 ps
T575 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.200838130 May 07 03:01:15 PM PDT 24 May 07 03:01:18 PM PDT 24 129860994 ps
T576 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1946320399 May 07 03:01:25 PM PDT 24 May 07 03:01:27 PM PDT 24 39317132 ps
T577 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2362247049 May 07 03:01:45 PM PDT 24 May 07 03:01:47 PM PDT 24 13287813 ps
T578 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3363712997 May 07 03:01:04 PM PDT 24 May 07 03:01:06 PM PDT 24 14758498 ps
T579 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4239544432 May 07 03:01:32 PM PDT 24 May 07 03:01:37 PM PDT 24 181437955 ps
T580 /workspace/coverage/cover_reg_top/49.hmac_intr_test.873213415 May 07 03:01:44 PM PDT 24 May 07 03:01:46 PM PDT 24 17305077 ps
T581 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.328152642 May 07 03:01:18 PM PDT 24 May 07 03:01:21 PM PDT 24 530326800 ps
T582 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.282361002 May 07 03:01:31 PM PDT 24 May 07 03:01:33 PM PDT 24 213741553 ps
T583 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1477818107 May 07 03:01:19 PM PDT 24 May 07 03:01:21 PM PDT 24 37315826 ps
T584 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2116744449 May 07 03:01:15 PM PDT 24 May 07 03:01:19 PM PDT 24 54931945 ps
T585 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3040751959 May 07 03:01:05 PM PDT 24 May 07 03:01:22 PM PDT 24 322682742 ps
T586 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3301807499 May 07 03:01:38 PM PDT 24 May 07 03:01:40 PM PDT 24 46700911 ps
T587 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1505205600 May 07 03:01:00 PM PDT 24 May 07 03:01:02 PM PDT 24 117740256 ps
T588 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4206142884 May 07 03:01:04 PM PDT 24 May 07 03:01:11 PM PDT 24 479872648 ps

Test location /workspace/coverage/default/32.hmac_long_msg.4142005758
Short name T6
Test name
Test status
Simulation time 768201756 ps
CPU time 43.42 seconds
Started May 07 01:12:53 PM PDT 24
Finished May 07 01:13:38 PM PDT 24
Peak memory 199972 kb
Host smart-bd36a138-a830-4d09-b8bf-5c4519f4e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142005758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4142005758
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.2856422159
Short name T20
Test name
Test status
Simulation time 106416866822 ps
CPU time 104.67 seconds
Started May 07 01:14:37 PM PDT 24
Finished May 07 01:16:23 PM PDT 24
Peak memory 216004 kb
Host smart-f2d13919-2000-411d-bf8c-1c41b08cce14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856422159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.2856422159
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2818307710
Short name T4
Test name
Test status
Simulation time 6252418929 ps
CPU time 53.56 seconds
Started May 07 01:11:07 PM PDT 24
Finished May 07 01:12:02 PM PDT 24
Peak memory 224360 kb
Host smart-0055e9d7-f4c2-4983-bacb-afca3b1ad608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818307710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2818307710
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2163555143
Short name T35
Test name
Test status
Simulation time 85725025 ps
CPU time 0.95 seconds
Started May 07 01:10:08 PM PDT 24
Finished May 07 01:10:09 PM PDT 24
Peak memory 219200 kb
Host smart-75b68052-e736-4b8d-bbcc-a431e7ea9535
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163555143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2163555143
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2839242445
Short name T29
Test name
Test status
Simulation time 3592573029 ps
CPU time 41.85 seconds
Started May 07 01:11:06 PM PDT 24
Finished May 07 01:11:49 PM PDT 24
Peak memory 200040 kb
Host smart-19a1698e-e88a-45ba-be1b-01a3a23c8081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839242445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2839242445
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1737574038
Short name T58
Test name
Test status
Simulation time 94161838 ps
CPU time 1.67 seconds
Started May 07 03:01:03 PM PDT 24
Finished May 07 03:01:07 PM PDT 24
Peak memory 199932 kb
Host smart-6703225a-aaf8-4f9d-acea-eec6e9af910a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737574038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1737574038
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1473760624
Short name T19
Test name
Test status
Simulation time 56045639 ps
CPU time 0.57 seconds
Started May 07 01:10:08 PM PDT 24
Finished May 07 01:10:09 PM PDT 24
Peak memory 195312 kb
Host smart-d9153a7a-b7b3-4f46-907e-9244c38fd0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473760624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1473760624
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2721935534
Short name T47
Test name
Test status
Simulation time 3639101161 ps
CPU time 49.67 seconds
Started May 07 01:12:41 PM PDT 24
Finished May 07 01:13:32 PM PDT 24
Peak memory 200012 kb
Host smart-c9f476dc-459d-492d-a3c4-2b9e1007ffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721935534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2721935534
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3935090097
Short name T86
Test name
Test status
Simulation time 2800645590 ps
CPU time 6.3 seconds
Started May 07 03:00:58 PM PDT 24
Finished May 07 03:01:06 PM PDT 24
Peak memory 199844 kb
Host smart-4edbfad6-ed39-40de-86c9-e7f30552de12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935090097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3935090097
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.749324687
Short name T121
Test name
Test status
Simulation time 365785616 ps
CPU time 4.49 seconds
Started May 07 03:01:14 PM PDT 24
Finished May 07 03:01:19 PM PDT 24
Peak memory 199984 kb
Host smart-3933206a-df45-4006-8bfa-d9aad5611b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749324687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.749324687
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3898871407
Short name T27
Test name
Test status
Simulation time 3402252529 ps
CPU time 43.23 seconds
Started May 07 01:12:38 PM PDT 24
Finished May 07 01:13:22 PM PDT 24
Peak memory 200020 kb
Host smart-6648963c-fb2f-472c-8bf3-87c30a9cab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898871407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3898871407
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.4072522887
Short name T9
Test name
Test status
Simulation time 44827049929 ps
CPU time 417.73 seconds
Started May 07 01:10:25 PM PDT 24
Finished May 07 01:17:24 PM PDT 24
Peak memory 200044 kb
Host smart-67046bd5-1e7b-46d5-ba9d-8ba6eff44243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072522887 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.4072522887
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1924049723
Short name T24
Test name
Test status
Simulation time 199405743188 ps
CPU time 921.94 seconds
Started May 07 01:12:24 PM PDT 24
Finished May 07 01:27:47 PM PDT 24
Peak memory 240964 kb
Host smart-8438fc08-8108-4a8e-915d-bac8ac5ee792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924049723 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1924049723
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4005240849
Short name T49
Test name
Test status
Simulation time 922130276 ps
CPU time 43.38 seconds
Started May 07 01:12:04 PM PDT 24
Finished May 07 01:12:48 PM PDT 24
Peak memory 208176 kb
Host smart-6c2600b4-8f94-4657-916a-be0a59a59790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005240849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4005240849
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_error.3338576778
Short name T16
Test name
Test status
Simulation time 303757905 ps
CPU time 6.26 seconds
Started May 07 01:11:06 PM PDT 24
Finished May 07 01:11:14 PM PDT 24
Peak memory 199952 kb
Host smart-fe5359ef-310a-478f-bfda-ccb3ea2b781e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338576778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3338576778
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3971998818
Short name T26
Test name
Test status
Simulation time 368236824 ps
CPU time 1.98 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 200000 kb
Host smart-7444710b-2c5a-491a-84c0-3c8d07a9fe8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971998818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3971998818
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4179321279
Short name T465
Test name
Test status
Simulation time 13394706 ps
CPU time 0.59 seconds
Started May 07 03:01:33 PM PDT 24
Finished May 07 03:01:35 PM PDT 24
Peak memory 194560 kb
Host smart-6e67228a-2393-4496-99d5-7e84e2ac6346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179321279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4179321279
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/default/21.hmac_error.1946018919
Short name T15
Test name
Test status
Simulation time 212714050 ps
CPU time 11.23 seconds
Started May 07 01:12:25 PM PDT 24
Finished May 07 01:12:37 PM PDT 24
Peak memory 199884 kb
Host smart-e7378894-75eb-4322-9234-b7ff0a0d0397
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946018919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1946018919
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1074856789
Short name T67
Test name
Test status
Simulation time 192233249 ps
CPU time 3.3 seconds
Started May 07 03:01:33 PM PDT 24
Finished May 07 03:01:38 PM PDT 24
Peak memory 199988 kb
Host smart-338e6762-44fd-4b7f-b634-f4d5d3f25387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074856789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1074856789
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1714106263
Short name T66
Test name
Test status
Simulation time 240944732 ps
CPU time 2.73 seconds
Started May 07 03:00:53 PM PDT 24
Finished May 07 03:00:56 PM PDT 24
Peak memory 199348 kb
Host smart-f91b074d-c121-4d10-b7e7-027348434bee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714106263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1714106263
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2639973507
Short name T552
Test name
Test status
Simulation time 2250352045 ps
CPU time 16.47 seconds
Started May 07 03:00:51 PM PDT 24
Finished May 07 03:01:08 PM PDT 24
Peak memory 200036 kb
Host smart-c3a05db0-2239-41b9-9484-68c7cf6e64e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639973507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2639973507
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3131875244
Short name T105
Test name
Test status
Simulation time 42458497 ps
CPU time 0.99 seconds
Started May 07 03:00:53 PM PDT 24
Finished May 07 03:00:55 PM PDT 24
Peak memory 198964 kb
Host smart-c89010f1-d721-49f6-b289-207711414b9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131875244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3131875244
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3884747519
Short name T539
Test name
Test status
Simulation time 361243799 ps
CPU time 1.12 seconds
Started May 07 03:00:57 PM PDT 24
Finished May 07 03:00:59 PM PDT 24
Peak memory 199840 kb
Host smart-85e9c687-73de-4c77-b12d-4fb1d05b1a48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884747519 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3884747519
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1678037663
Short name T110
Test name
Test status
Simulation time 34018423 ps
CPU time 0.94 seconds
Started May 07 03:00:54 PM PDT 24
Finished May 07 03:00:56 PM PDT 24
Peak memory 198788 kb
Host smart-7f40835a-c4ed-4526-8986-116daddcf19e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678037663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1678037663
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1192073852
Short name T551
Test name
Test status
Simulation time 59734918 ps
CPU time 0.61 seconds
Started May 07 03:00:52 PM PDT 24
Finished May 07 03:00:53 PM PDT 24
Peak memory 194672 kb
Host smart-ef7c2936-ca61-4b12-bddc-30c110bdb7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192073852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1192073852
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.216572547
Short name T554
Test name
Test status
Simulation time 115131139 ps
CPU time 2.18 seconds
Started May 07 03:01:00 PM PDT 24
Finished May 07 03:01:03 PM PDT 24
Peak memory 199816 kb
Host smart-cd8da9ca-a80f-4391-a2b9-6fae6033f3ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216572547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.216572547
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4282231460
Short name T540
Test name
Test status
Simulation time 244617948 ps
CPU time 3.38 seconds
Started May 07 03:00:51 PM PDT 24
Finished May 07 03:00:55 PM PDT 24
Peak memory 200052 kb
Host smart-6657be89-03af-4188-95fd-f0342bd96ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282231460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.4282231460
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3181674700
Short name T479
Test name
Test status
Simulation time 83667228 ps
CPU time 1.86 seconds
Started May 07 03:00:54 PM PDT 24
Finished May 07 03:00:56 PM PDT 24
Peak memory 199988 kb
Host smart-808f002f-4efb-42bb-b5f4-8e05a87cdd04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181674700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3181674700
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.695636631
Short name T525
Test name
Test status
Simulation time 3806144268 ps
CPU time 12.07 seconds
Started May 07 03:00:58 PM PDT 24
Finished May 07 03:01:11 PM PDT 24
Peak memory 200076 kb
Host smart-b0bb8b07-c398-486c-a3f1-b5cbf7411e90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695636631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.695636631
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1619834195
Short name T496
Test name
Test status
Simulation time 76276080 ps
CPU time 0.95 seconds
Started May 07 03:00:58 PM PDT 24
Finished May 07 03:01:00 PM PDT 24
Peak memory 199728 kb
Host smart-719651e5-1869-48de-b111-5e78af52c63d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619834195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1619834195
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1505205600
Short name T587
Test name
Test status
Simulation time 117740256 ps
CPU time 1.76 seconds
Started May 07 03:01:00 PM PDT 24
Finished May 07 03:01:02 PM PDT 24
Peak memory 200044 kb
Host smart-f271eaf9-6147-49fd-8e33-93e47ada49e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505205600 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1505205600
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.117784352
Short name T531
Test name
Test status
Simulation time 57955574 ps
CPU time 0.91 seconds
Started May 07 03:01:00 PM PDT 24
Finished May 07 03:01:02 PM PDT 24
Peak memory 199776 kb
Host smart-728bea65-6e2f-4cc2-86b8-268595ef7619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117784352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.117784352
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3958909466
Short name T501
Test name
Test status
Simulation time 16431023 ps
CPU time 0.61 seconds
Started May 07 03:00:59 PM PDT 24
Finished May 07 03:01:01 PM PDT 24
Peak memory 194820 kb
Host smart-41094e5e-bd14-4382-84bf-f80b5c9e09dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958909466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3958909466
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3457995054
Short name T508
Test name
Test status
Simulation time 1910799884 ps
CPU time 2.71 seconds
Started May 07 03:01:02 PM PDT 24
Finished May 07 03:01:06 PM PDT 24
Peak memory 199948 kb
Host smart-3eb37b35-97b6-48f4-8a15-6f99076f25aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457995054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3457995054
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3106132146
Short name T482
Test name
Test status
Simulation time 154846434 ps
CPU time 3.5 seconds
Started May 07 03:00:59 PM PDT 24
Finished May 07 03:01:03 PM PDT 24
Peak memory 200076 kb
Host smart-31b83a87-dc0b-490e-8648-7f93fb465433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106132146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3106132146
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3878355685
Short name T68
Test name
Test status
Simulation time 165793762 ps
CPU time 2.88 seconds
Started May 07 03:01:00 PM PDT 24
Finished May 07 03:01:04 PM PDT 24
Peak memory 199988 kb
Host smart-b5b0242b-edaf-4bc8-9bbe-67fb5a229995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878355685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3878355685
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.249853614
Short name T489
Test name
Test status
Simulation time 28586003205 ps
CPU time 315.7 seconds
Started May 07 03:01:20 PM PDT 24
Finished May 07 03:06:37 PM PDT 24
Peak memory 216520 kb
Host smart-c2419895-2b93-4c10-bea2-f2d4782f0345
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249853614 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.249853614
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4177060450
Short name T107
Test name
Test status
Simulation time 20507284 ps
CPU time 0.67 seconds
Started May 07 03:01:17 PM PDT 24
Finished May 07 03:01:18 PM PDT 24
Peak memory 197536 kb
Host smart-77be49ba-0ac3-43eb-8c63-b38eae3452f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177060450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.4177060450
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1054510235
Short name T119
Test name
Test status
Simulation time 78188898 ps
CPU time 0.61 seconds
Started May 07 03:01:17 PM PDT 24
Finished May 07 03:01:19 PM PDT 24
Peak memory 194684 kb
Host smart-65f34d6b-426c-4329-8910-b18e4f375be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054510235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1054510235
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4166940229
Short name T468
Test name
Test status
Simulation time 94133069 ps
CPU time 2.19 seconds
Started May 07 03:01:17 PM PDT 24
Finished May 07 03:01:21 PM PDT 24
Peak memory 199656 kb
Host smart-9f02ccb0-40ea-46b8-ba85-350c69067004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166940229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4166940229
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4191865237
Short name T527
Test name
Test status
Simulation time 777617797 ps
CPU time 3.93 seconds
Started May 07 03:01:16 PM PDT 24
Finished May 07 03:01:21 PM PDT 24
Peak memory 200040 kb
Host smart-bb122bd0-1945-45a7-a9eb-425442dffbf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191865237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4191865237
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2124873972
Short name T510
Test name
Test status
Simulation time 192554674 ps
CPU time 1.81 seconds
Started May 07 03:01:19 PM PDT 24
Finished May 07 03:01:22 PM PDT 24
Peak memory 199944 kb
Host smart-1d01df08-90cb-4a40-aef7-dd4e283f20e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124873972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2124873972
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.126294621
Short name T480
Test name
Test status
Simulation time 331254413 ps
CPU time 1.74 seconds
Started May 07 03:01:17 PM PDT 24
Finished May 07 03:01:20 PM PDT 24
Peak memory 200016 kb
Host smart-d92bd9f2-dd29-47b9-8def-fbd1c20429ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126294621 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.126294621
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3045550536
Short name T104
Test name
Test status
Simulation time 43231242 ps
CPU time 0.67 seconds
Started May 07 03:01:20 PM PDT 24
Finished May 07 03:01:22 PM PDT 24
Peak memory 197540 kb
Host smart-466bef0d-7f9f-4a54-9578-6fd359e143ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045550536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3045550536
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1477818107
Short name T583
Test name
Test status
Simulation time 37315826 ps
CPU time 0.6 seconds
Started May 07 03:01:19 PM PDT 24
Finished May 07 03:01:21 PM PDT 24
Peak memory 194620 kb
Host smart-0be6988a-4adf-4f9c-b914-f905d9f77f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477818107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1477818107
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3554668036
Short name T82
Test name
Test status
Simulation time 117927748 ps
CPU time 1.22 seconds
Started May 07 03:01:16 PM PDT 24
Finished May 07 03:01:19 PM PDT 24
Peak memory 199896 kb
Host smart-88de4e6a-0391-4d1d-93ba-d8daff27c2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554668036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3554668036
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1985281748
Short name T505
Test name
Test status
Simulation time 274239404 ps
CPU time 3.58 seconds
Started May 07 03:01:16 PM PDT 24
Finished May 07 03:01:21 PM PDT 24
Peak memory 200040 kb
Host smart-5fa8ccf4-6d9a-4432-ad96-988a80708229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985281748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1985281748
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1427131925
Short name T124
Test name
Test status
Simulation time 90731866 ps
CPU time 1.77 seconds
Started May 07 03:01:16 PM PDT 24
Finished May 07 03:01:19 PM PDT 24
Peak memory 200000 kb
Host smart-b47d9be6-a57f-4f5d-94bf-d22742a7ea8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427131925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1427131925
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.647150412
Short name T546
Test name
Test status
Simulation time 142812051 ps
CPU time 2.22 seconds
Started May 07 03:01:25 PM PDT 24
Finished May 07 03:01:29 PM PDT 24
Peak memory 200032 kb
Host smart-b05234dc-7b6d-471a-b3f0-56208ccf1d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647150412 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.647150412
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2733797519
Short name T532
Test name
Test status
Simulation time 41309910 ps
CPU time 0.67 seconds
Started May 07 03:01:24 PM PDT 24
Finished May 07 03:01:25 PM PDT 24
Peak memory 197596 kb
Host smart-091795f9-f977-457a-9aee-4b4719b062bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733797519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2733797519
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3038501591
Short name T511
Test name
Test status
Simulation time 21586699 ps
CPU time 0.57 seconds
Started May 07 03:01:26 PM PDT 24
Finished May 07 03:01:28 PM PDT 24
Peak memory 194836 kb
Host smart-8b3063c9-3f20-44d3-9f8c-d4fc58d71ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038501591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3038501591
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3934667691
Short name T466
Test name
Test status
Simulation time 156081681 ps
CPU time 2.09 seconds
Started May 07 03:01:25 PM PDT 24
Finished May 07 03:01:28 PM PDT 24
Peak memory 199932 kb
Host smart-17bc62a7-dc57-4e8c-9e3d-dd78480c4942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934667691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3934667691
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4148073188
Short name T516
Test name
Test status
Simulation time 214773413 ps
CPU time 3.02 seconds
Started May 07 03:01:26 PM PDT 24
Finished May 07 03:01:30 PM PDT 24
Peak memory 200000 kb
Host smart-24ddfe2d-20d3-4ffc-8436-7933497d8b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148073188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.4148073188
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2607387380
Short name T574
Test name
Test status
Simulation time 200374989 ps
CPU time 2.97 seconds
Started May 07 03:01:24 PM PDT 24
Finished May 07 03:01:28 PM PDT 24
Peak memory 200032 kb
Host smart-97307c74-ab63-4ec8-a9c6-e82e6084807f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607387380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2607387380
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2649777954
Short name T524
Test name
Test status
Simulation time 91869727586 ps
CPU time 956.68 seconds
Started May 07 03:01:24 PM PDT 24
Finished May 07 03:17:22 PM PDT 24
Peak memory 224744 kb
Host smart-28b24086-4624-4acd-b170-be5ccdbee2fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649777954 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2649777954
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1946320399
Short name T576
Test name
Test status
Simulation time 39317132 ps
CPU time 0.86 seconds
Started May 07 03:01:25 PM PDT 24
Finished May 07 03:01:27 PM PDT 24
Peak memory 199044 kb
Host smart-c3db20e5-f382-47b7-a634-cbcb3b6cee9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946320399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1946320399
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3676229869
Short name T543
Test name
Test status
Simulation time 56394517 ps
CPU time 0.59 seconds
Started May 07 03:01:25 PM PDT 24
Finished May 07 03:01:27 PM PDT 24
Peak memory 194596 kb
Host smart-792c6180-df5c-41c5-92cd-1e044021d2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676229869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3676229869
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3893220658
Short name T83
Test name
Test status
Simulation time 155549377 ps
CPU time 2 seconds
Started May 07 03:01:28 PM PDT 24
Finished May 07 03:01:31 PM PDT 24
Peak memory 199884 kb
Host smart-351898cf-e88a-4583-ad91-af09b616acee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893220658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3893220658
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3447758904
Short name T497
Test name
Test status
Simulation time 158205762 ps
CPU time 1.51 seconds
Started May 07 03:01:28 PM PDT 24
Finished May 07 03:01:30 PM PDT 24
Peak memory 200056 kb
Host smart-b618c3d2-f4e9-48b3-9a0a-a5a6ce568ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447758904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3447758904
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2683556151
Short name T59
Test name
Test status
Simulation time 113264826 ps
CPU time 2.86 seconds
Started May 07 03:01:24 PM PDT 24
Finished May 07 03:01:28 PM PDT 24
Peak memory 199980 kb
Host smart-8a012e22-5ce2-4315-b09a-545f98ca5864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683556151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2683556151
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1358404627
Short name T485
Test name
Test status
Simulation time 51634282 ps
CPU time 1.77 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:34 PM PDT 24
Peak memory 200096 kb
Host smart-dc2918b7-b746-4e8c-a87e-6291d0ec76c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358404627 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1358404627
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3108098979
Short name T84
Test name
Test status
Simulation time 60375823 ps
CPU time 0.69 seconds
Started May 07 03:01:24 PM PDT 24
Finished May 07 03:01:26 PM PDT 24
Peak memory 197524 kb
Host smart-cfec0394-4adf-4fea-9b57-129ee1756451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108098979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3108098979
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3171460217
Short name T519
Test name
Test status
Simulation time 35666454 ps
CPU time 0.6 seconds
Started May 07 03:01:25 PM PDT 24
Finished May 07 03:01:27 PM PDT 24
Peak memory 194544 kb
Host smart-a47049be-7aae-40ed-bab6-7ae6bb5dcac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171460217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3171460217
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.833771165
Short name T526
Test name
Test status
Simulation time 294299424 ps
CPU time 2.32 seconds
Started May 07 03:01:28 PM PDT 24
Finished May 07 03:01:31 PM PDT 24
Peak memory 200008 kb
Host smart-e6c1f49d-c6fb-45fa-b423-0cebb88e77a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833771165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.833771165
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.634987321
Short name T523
Test name
Test status
Simulation time 83213723 ps
CPU time 1.9 seconds
Started May 07 03:01:24 PM PDT 24
Finished May 07 03:01:27 PM PDT 24
Peak memory 200060 kb
Host smart-a1f797ab-7477-4526-a8a3-1fa67d0e799d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634987321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.634987321
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2848606953
Short name T123
Test name
Test status
Simulation time 185887773 ps
CPU time 2.94 seconds
Started May 07 03:01:28 PM PDT 24
Finished May 07 03:01:32 PM PDT 24
Peak memory 199996 kb
Host smart-719b615a-794a-4805-8be8-b8e2f38e69bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848606953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2848606953
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2804394958
Short name T517
Test name
Test status
Simulation time 168263814 ps
CPU time 1.13 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 199812 kb
Host smart-fc4cffde-6500-4788-a8af-65dc14d97729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804394958 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2804394958
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2894514898
Short name T561
Test name
Test status
Simulation time 29140322 ps
CPU time 0.92 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 199388 kb
Host smart-bb37cec6-c614-467c-9898-fa34ffe6309b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894514898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2894514898
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2345480782
Short name T538
Test name
Test status
Simulation time 27530561 ps
CPU time 1.17 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:34 PM PDT 24
Peak memory 199952 kb
Host smart-dd2ae5e4-7352-40aa-b411-42e1e3f023f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345480782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2345480782
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4239544432
Short name T579
Test name
Test status
Simulation time 181437955 ps
CPU time 3.22 seconds
Started May 07 03:01:32 PM PDT 24
Finished May 07 03:01:37 PM PDT 24
Peak memory 200020 kb
Host smart-48808e00-05d1-4d15-8af7-064c46dc2bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239544432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4239544432
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3429327951
Short name T529
Test name
Test status
Simulation time 483814022 ps
CPU time 3.87 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:36 PM PDT 24
Peak memory 199984 kb
Host smart-2837cda4-d0d1-46da-87f9-ebb3a87922eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429327951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3429327951
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2388517521
Short name T65
Test name
Test status
Simulation time 48498085 ps
CPU time 3.28 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:36 PM PDT 24
Peak memory 199888 kb
Host smart-ef41dd7b-8e4a-4f85-ad92-81e1f89eece7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388517521 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2388517521
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3016831074
Short name T556
Test name
Test status
Simulation time 47095020 ps
CPU time 0.96 seconds
Started May 07 03:01:29 PM PDT 24
Finished May 07 03:01:31 PM PDT 24
Peak memory 199240 kb
Host smart-5616677e-f937-4575-83b3-e47b0fafc412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016831074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3016831074
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3981647851
Short name T495
Test name
Test status
Simulation time 36491711 ps
CPU time 0.58 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 194852 kb
Host smart-0c4da118-2f7c-41b1-9d95-5b89f69fa37e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981647851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3981647851
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.282361002
Short name T582
Test name
Test status
Simulation time 213741553 ps
CPU time 1.24 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 198368 kb
Host smart-d7f12100-05f3-4695-8df6-b1371c840935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282361002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.282361002
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3816421367
Short name T537
Test name
Test status
Simulation time 26589247 ps
CPU time 1.5 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 200056 kb
Host smart-d86e16f4-f01a-4611-a66c-04ad674b04ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816421367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3816421367
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.26520884
Short name T57
Test name
Test status
Simulation time 67704868 ps
CPU time 2.04 seconds
Started May 07 03:01:29 PM PDT 24
Finished May 07 03:01:32 PM PDT 24
Peak memory 200056 kb
Host smart-91af50e5-b635-4e70-b140-cc98f49d768d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520884 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.26520884
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3304208215
Short name T478
Test name
Test status
Simulation time 29207265 ps
CPU time 0.71 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 198064 kb
Host smart-bf8a926b-9de2-4f5c-8a8e-861c73409f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304208215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3304208215
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2959092694
Short name T487
Test name
Test status
Simulation time 23746880 ps
CPU time 0.63 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 194604 kb
Host smart-2025fb40-22f6-4bd1-9d50-6d928d30ba41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959092694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2959092694
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2758332767
Short name T473
Test name
Test status
Simulation time 89525726 ps
CPU time 1.17 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 199860 kb
Host smart-64fa90e8-e0be-4b0b-872a-cf354993d2ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758332767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2758332767
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2751969306
Short name T555
Test name
Test status
Simulation time 40816689 ps
CPU time 1.18 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 200000 kb
Host smart-756f4532-4011-4682-abe6-94a91d5b764f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751969306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2751969306
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1216782689
Short name T547
Test name
Test status
Simulation time 73310331 ps
CPU time 1.2 seconds
Started May 07 03:01:40 PM PDT 24
Finished May 07 03:01:42 PM PDT 24
Peak memory 199780 kb
Host smart-3bec5f39-7f2b-4ad4-af9d-0ce5a4b674a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216782689 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1216782689
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3934191290
Short name T106
Test name
Test status
Simulation time 18575599 ps
CPU time 0.92 seconds
Started May 07 03:01:37 PM PDT 24
Finished May 07 03:01:39 PM PDT 24
Peak memory 199500 kb
Host smart-8ff2b421-a204-41f7-9444-3b0ab62a10a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934191290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3934191290
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1417616940
Short name T534
Test name
Test status
Simulation time 20833331 ps
CPU time 0.61 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:32 PM PDT 24
Peak memory 194664 kb
Host smart-5decef91-d664-4693-911b-9a6047bb0940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417616940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1417616940
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3424830792
Short name T500
Test name
Test status
Simulation time 207493217 ps
CPU time 2.1 seconds
Started May 07 03:01:36 PM PDT 24
Finished May 07 03:01:39 PM PDT 24
Peak memory 199652 kb
Host smart-e8d9c322-76a7-4cc4-8072-3652c215900d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424830792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3424830792
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.366708372
Short name T64
Test name
Test status
Simulation time 306238915 ps
CPU time 3.88 seconds
Started May 07 03:01:30 PM PDT 24
Finished May 07 03:01:36 PM PDT 24
Peak memory 200104 kb
Host smart-a71bbf4a-d374-4904-8b16-b40f2ac19c95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366708372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.366708372
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3060792105
Short name T562
Test name
Test status
Simulation time 641734891 ps
CPU time 3.34 seconds
Started May 07 03:01:31 PM PDT 24
Finished May 07 03:01:36 PM PDT 24
Peak memory 199824 kb
Host smart-cbd00a0b-b7c7-47e0-a640-6920da51c010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060792105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3060792105
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3479715803
Short name T522
Test name
Test status
Simulation time 43213506 ps
CPU time 2.65 seconds
Started May 07 03:01:37 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 208228 kb
Host smart-318d30bd-5b61-4628-8b3c-a429f46125c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479715803 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3479715803
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3259975025
Short name T102
Test name
Test status
Simulation time 18860934 ps
CPU time 0.93 seconds
Started May 07 03:01:38 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 199472 kb
Host smart-4d0c3b45-e050-4bc3-82df-a619a71acb5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259975025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3259975025
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2920870113
Short name T490
Test name
Test status
Simulation time 54401045 ps
CPU time 0.61 seconds
Started May 07 03:01:36 PM PDT 24
Finished May 07 03:01:38 PM PDT 24
Peak memory 194608 kb
Host smart-2e90f0de-8047-4c9e-9667-6add781071f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920870113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2920870113
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2287563551
Short name T492
Test name
Test status
Simulation time 23371877 ps
CPU time 1.15 seconds
Started May 07 03:01:41 PM PDT 24
Finished May 07 03:01:43 PM PDT 24
Peak memory 199432 kb
Host smart-e160687c-538c-4f70-a1b1-4a913ab92900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287563551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2287563551
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3663603638
Short name T61
Test name
Test status
Simulation time 65585543 ps
CPU time 1.65 seconds
Started May 07 03:01:37 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 200048 kb
Host smart-0874a2a0-b83f-4d8f-8e69-dda89d370e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663603638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3663603638
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1948945245
Short name T125
Test name
Test status
Simulation time 1816634951 ps
CPU time 3.38 seconds
Started May 07 03:01:38 PM PDT 24
Finished May 07 03:01:42 PM PDT 24
Peak memory 200000 kb
Host smart-1bbdd60c-c110-48e1-817f-38fc7b5c6a53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948945245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1948945245
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.474274004
Short name T567
Test name
Test status
Simulation time 609853333 ps
CPU time 7.84 seconds
Started May 07 03:00:58 PM PDT 24
Finished May 07 03:01:07 PM PDT 24
Peak memory 199456 kb
Host smart-0c6902f0-9fd2-45f7-9675-002e5611c0cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474274004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.474274004
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2055843637
Short name T550
Test name
Test status
Simulation time 670548670 ps
CPU time 5.62 seconds
Started May 07 03:00:59 PM PDT 24
Finished May 07 03:01:06 PM PDT 24
Peak memory 199120 kb
Host smart-99323e28-6013-4cda-ad6d-2345d14c4fa7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055843637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2055843637
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1830564223
Short name T103
Test name
Test status
Simulation time 23572786 ps
CPU time 0.94 seconds
Started May 07 03:00:56 PM PDT 24
Finished May 07 03:00:58 PM PDT 24
Peak memory 199164 kb
Host smart-dd1a206f-1ac2-40b6-95db-37e7993de88f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830564223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1830564223
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3829026177
Short name T62
Test name
Test status
Simulation time 67891057323 ps
CPU time 711.11 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:12:58 PM PDT 24
Peak memory 224776 kb
Host smart-415c4401-a3f1-4948-96e9-6a46c6b7bf22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829026177 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3829026177
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3206907513
Short name T470
Test name
Test status
Simulation time 56263729 ps
CPU time 0.9 seconds
Started May 07 03:00:58 PM PDT 24
Finished May 07 03:00:59 PM PDT 24
Peak memory 199576 kb
Host smart-1242f225-f76e-41e8-82cc-6ef554454fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206907513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3206907513
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2684969793
Short name T503
Test name
Test status
Simulation time 145113390 ps
CPU time 0.63 seconds
Started May 07 03:00:59 PM PDT 24
Finished May 07 03:01:00 PM PDT 24
Peak memory 194604 kb
Host smart-d8ae4be7-bd5b-4d5d-9ac9-b9aab3f1f1ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684969793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2684969793
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3875869167
Short name T518
Test name
Test status
Simulation time 322254751 ps
CPU time 1.82 seconds
Started May 07 03:01:02 PM PDT 24
Finished May 07 03:01:05 PM PDT 24
Peak memory 199732 kb
Host smart-8429dbdc-db85-4001-a8c4-8909f1cc3d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875869167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3875869167
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3935997476
Short name T507
Test name
Test status
Simulation time 81345856 ps
CPU time 1.77 seconds
Started May 07 03:01:00 PM PDT 24
Finished May 07 03:01:03 PM PDT 24
Peak memory 200036 kb
Host smart-fbd6a166-7d45-4d5a-86ee-22de7403b6f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935997476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3935997476
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2693475142
Short name T126
Test name
Test status
Simulation time 275605661 ps
CPU time 4.18 seconds
Started May 07 03:00:58 PM PDT 24
Finished May 07 03:01:03 PM PDT 24
Peak memory 199836 kb
Host smart-29f2e7cb-c27d-4e01-bcf3-e62547f0246d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693475142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2693475142
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3557372694
Short name T566
Test name
Test status
Simulation time 13007322 ps
CPU time 0.56 seconds
Started May 07 03:01:39 PM PDT 24
Finished May 07 03:01:41 PM PDT 24
Peak memory 194568 kb
Host smart-df7b596a-4013-4363-b3c1-6e55152d5ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557372694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3557372694
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2174282722
Short name T559
Test name
Test status
Simulation time 12392324 ps
CPU time 0.59 seconds
Started May 07 03:01:38 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 194640 kb
Host smart-b4b0ee6a-59f6-43df-95f2-4796d6163f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174282722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2174282722
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1516954645
Short name T558
Test name
Test status
Simulation time 12271140 ps
CPU time 0.61 seconds
Started May 07 03:01:40 PM PDT 24
Finished May 07 03:01:42 PM PDT 24
Peak memory 194560 kb
Host smart-3743ca0f-e094-4426-95ec-3b0a2cc7b87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516954645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1516954645
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2632710374
Short name T474
Test name
Test status
Simulation time 12310131 ps
CPU time 0.58 seconds
Started May 07 03:01:38 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 194812 kb
Host smart-e94726fe-5fa3-4f52-ae21-b0d269dda353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632710374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2632710374
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2218338464
Short name T530
Test name
Test status
Simulation time 42385253 ps
CPU time 0.6 seconds
Started May 07 03:01:39 PM PDT 24
Finished May 07 03:01:41 PM PDT 24
Peak memory 194616 kb
Host smart-a845983c-afab-4f31-a603-15546db9a8b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218338464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2218338464
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2988558085
Short name T514
Test name
Test status
Simulation time 42935657 ps
CPU time 0.58 seconds
Started May 07 03:01:41 PM PDT 24
Finished May 07 03:01:42 PM PDT 24
Peak memory 194592 kb
Host smart-d41ef5d9-d498-4d76-ae61-c84b3f86a6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988558085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2988558085
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2133529973
Short name T536
Test name
Test status
Simulation time 42966747 ps
CPU time 0.56 seconds
Started May 07 03:01:39 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 194808 kb
Host smart-47fde54c-579f-4961-88ec-66587073c6f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133529973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2133529973
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1350395524
Short name T80
Test name
Test status
Simulation time 47278756 ps
CPU time 0.57 seconds
Started May 07 03:01:37 PM PDT 24
Finished May 07 03:01:39 PM PDT 24
Peak memory 194544 kb
Host smart-e4344f35-e06e-4024-a3ce-f81e2d8addea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350395524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1350395524
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3301807499
Short name T586
Test name
Test status
Simulation time 46700911 ps
CPU time 0.61 seconds
Started May 07 03:01:38 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 194832 kb
Host smart-7dd1e7dc-ba0a-4a58-bb1e-6185da3873f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301807499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3301807499
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.303967163
Short name T572
Test name
Test status
Simulation time 14457075 ps
CPU time 0.59 seconds
Started May 07 03:01:38 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 194608 kb
Host smart-bfa53795-fb7d-4166-9e9d-e812b5ecb4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303967163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.303967163
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3034973935
Short name T509
Test name
Test status
Simulation time 360261310 ps
CPU time 6.25 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:13 PM PDT 24
Peak memory 200036 kb
Host smart-5e6098f1-e0c7-46ac-9296-abf15417d790
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034973935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3034973935
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3040751959
Short name T585
Test name
Test status
Simulation time 322682742 ps
CPU time 14.41 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:22 PM PDT 24
Peak memory 198916 kb
Host smart-4fc77503-a022-44c9-abf1-56ee79290894
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040751959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3040751959
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1706397436
Short name T560
Test name
Test status
Simulation time 83948143 ps
CPU time 0.73 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:08 PM PDT 24
Peak memory 197740 kb
Host smart-9f19fdcc-b425-4277-a999-e4edad2f8da1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706397436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1706397436
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3708069479
Short name T512
Test name
Test status
Simulation time 123202962 ps
CPU time 1.89 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:09 PM PDT 24
Peak memory 199976 kb
Host smart-222514c9-7508-4392-8410-e1da6a9fc6a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708069479 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3708069479
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.10294310
Short name T109
Test name
Test status
Simulation time 27669525 ps
CPU time 0.88 seconds
Started May 07 03:01:03 PM PDT 24
Finished May 07 03:01:06 PM PDT 24
Peak memory 198988 kb
Host smart-44c7c1ab-ee85-4c58-bcca-08b3f3c69863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10294310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.10294310
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3363712997
Short name T578
Test name
Test status
Simulation time 14758498 ps
CPU time 0.62 seconds
Started May 07 03:01:04 PM PDT 24
Finished May 07 03:01:06 PM PDT 24
Peak memory 194620 kb
Host smart-9202064c-a60d-4469-b25b-146e96231f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363712997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3363712997
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3349051954
Short name T483
Test name
Test status
Simulation time 22829156 ps
CPU time 1.08 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:09 PM PDT 24
Peak memory 199704 kb
Host smart-87665292-dabb-46d4-a6cb-f401e5a9d0e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349051954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3349051954
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.101526352
Short name T564
Test name
Test status
Simulation time 482978830 ps
CPU time 2.07 seconds
Started May 07 03:01:04 PM PDT 24
Finished May 07 03:01:09 PM PDT 24
Peak memory 200216 kb
Host smart-534b051a-6c07-4fd7-b4d1-4018856dd8ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101526352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.101526352
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.429861158
Short name T120
Test name
Test status
Simulation time 118391597 ps
CPU time 4.06 seconds
Started May 07 03:01:03 PM PDT 24
Finished May 07 03:01:09 PM PDT 24
Peak memory 199996 kb
Host smart-de44b903-5317-4638-a0bc-dbfdbb77e83e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429861158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.429861158
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4167955233
Short name T493
Test name
Test status
Simulation time 14902997 ps
CPU time 0.6 seconds
Started May 07 03:01:41 PM PDT 24
Finished May 07 03:01:42 PM PDT 24
Peak memory 194680 kb
Host smart-eda8a6fd-8be5-453a-a520-1d6054723c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167955233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4167955233
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1868141675
Short name T542
Test name
Test status
Simulation time 14336746 ps
CPU time 0.58 seconds
Started May 07 03:01:40 PM PDT 24
Finished May 07 03:01:41 PM PDT 24
Peak memory 194596 kb
Host smart-6b166b11-66fb-4937-933d-7b72d9603fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868141675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1868141675
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2788406995
Short name T486
Test name
Test status
Simulation time 68095664 ps
CPU time 0.61 seconds
Started May 07 03:01:35 PM PDT 24
Finished May 07 03:01:37 PM PDT 24
Peak memory 194652 kb
Host smart-851a8a5d-7aed-4373-9fe9-efa77557879c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788406995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2788406995
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2183410117
Short name T549
Test name
Test status
Simulation time 14726926 ps
CPU time 0.59 seconds
Started May 07 03:01:37 PM PDT 24
Finished May 07 03:01:38 PM PDT 24
Peak memory 194616 kb
Host smart-74589028-820d-44ce-9de7-428791e106ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183410117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2183410117
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1268845649
Short name T471
Test name
Test status
Simulation time 16292078 ps
CPU time 0.59 seconds
Started May 07 03:01:41 PM PDT 24
Finished May 07 03:01:42 PM PDT 24
Peak memory 194796 kb
Host smart-00596d68-58ec-4446-bce5-1a63715a30a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268845649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1268845649
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2747488273
Short name T475
Test name
Test status
Simulation time 12088816 ps
CPU time 0.58 seconds
Started May 07 03:01:46 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 194556 kb
Host smart-c3a24113-23f0-4220-8985-0913d464202a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747488273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2747488273
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2337322995
Short name T481
Test name
Test status
Simulation time 28302225 ps
CPU time 0.65 seconds
Started May 07 03:01:43 PM PDT 24
Finished May 07 03:01:45 PM PDT 24
Peak memory 194304 kb
Host smart-0d05f452-6ea2-4036-8ed7-51d55e2a4d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337322995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2337322995
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2524265524
Short name T499
Test name
Test status
Simulation time 15034072 ps
CPU time 0.62 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 194832 kb
Host smart-dc9efa91-d3a8-4025-bf9e-c24d09a03f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524265524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2524265524
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2362247049
Short name T577
Test name
Test status
Simulation time 13287813 ps
CPU time 0.59 seconds
Started May 07 03:01:45 PM PDT 24
Finished May 07 03:01:47 PM PDT 24
Peak memory 194988 kb
Host smart-ebba7fb0-f1c0-43e4-8053-89206ac869b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362247049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2362247049
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.631472505
Short name T498
Test name
Test status
Simulation time 12294564 ps
CPU time 0.57 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 194576 kb
Host smart-dacc5d0a-aec6-4671-8a06-38b077b36483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631472505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.631472505
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4037640448
Short name T108
Test name
Test status
Simulation time 1377380706 ps
CPU time 3.34 seconds
Started May 07 03:01:04 PM PDT 24
Finished May 07 03:01:10 PM PDT 24
Peak memory 200036 kb
Host smart-5a94c7ef-622b-46bf-9a4d-203f011a2e36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037640448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4037640448
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2112255148
Short name T528
Test name
Test status
Simulation time 1491497169 ps
CPU time 5.71 seconds
Started May 07 03:01:06 PM PDT 24
Finished May 07 03:01:14 PM PDT 24
Peak memory 199876 kb
Host smart-bc2a8967-b956-4cf6-a1fa-153fda46c83c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112255148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2112255148
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2948948713
Short name T573
Test name
Test status
Simulation time 76789177 ps
CPU time 0.95 seconds
Started May 07 03:01:04 PM PDT 24
Finished May 07 03:01:07 PM PDT 24
Peak memory 199788 kb
Host smart-d49e8f2b-94c1-49dc-b415-5455e50223d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948948713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2948948713
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3090643531
Short name T60
Test name
Test status
Simulation time 162866930 ps
CPU time 2.68 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:10 PM PDT 24
Peak memory 208316 kb
Host smart-dc3b4a36-dacb-449d-99f3-2a543cda39ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090643531 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3090643531
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3186980637
Short name T571
Test name
Test status
Simulation time 30702009 ps
CPU time 0.95 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:08 PM PDT 24
Peak memory 199092 kb
Host smart-5e99add7-eb59-42a7-9367-24887eaf70f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186980637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3186980637
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2675018392
Short name T533
Test name
Test status
Simulation time 19077234 ps
CPU time 0.63 seconds
Started May 07 03:01:06 PM PDT 24
Finished May 07 03:01:09 PM PDT 24
Peak memory 194636 kb
Host smart-cbbc4304-3141-41b9-9af4-7bd8721edf8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675018392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2675018392
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1617047383
Short name T476
Test name
Test status
Simulation time 183695264 ps
CPU time 1.2 seconds
Started May 07 03:01:04 PM PDT 24
Finished May 07 03:01:07 PM PDT 24
Peak memory 198236 kb
Host smart-c1f67c88-c57a-454c-aee6-df349ccf652d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617047383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1617047383
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1994977283
Short name T504
Test name
Test status
Simulation time 358405674 ps
CPU time 3.56 seconds
Started May 07 03:01:05 PM PDT 24
Finished May 07 03:01:11 PM PDT 24
Peak memory 200008 kb
Host smart-05bc66c4-5c9c-4a78-bf92-ff732aacd3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994977283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1994977283
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1091461180
Short name T515
Test name
Test status
Simulation time 29229533 ps
CPU time 0.59 seconds
Started May 07 03:01:46 PM PDT 24
Finished May 07 03:01:48 PM PDT 24
Peak memory 194612 kb
Host smart-53011f1f-c1ec-4323-94e7-d0f09e265939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091461180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1091461180
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.939891605
Short name T535
Test name
Test status
Simulation time 21418436 ps
CPU time 0.59 seconds
Started May 07 03:01:45 PM PDT 24
Finished May 07 03:01:47 PM PDT 24
Peak memory 194804 kb
Host smart-5720b15c-34aa-4d10-a967-6a6225a5255d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939891605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.939891605
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3905733079
Short name T569
Test name
Test status
Simulation time 32136693 ps
CPU time 0.56 seconds
Started May 07 03:01:42 PM PDT 24
Finished May 07 03:01:44 PM PDT 24
Peak memory 194544 kb
Host smart-65834b6d-ddb3-456a-a7e5-a1936b29b78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905733079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3905733079
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1671322994
Short name T521
Test name
Test status
Simulation time 78520058 ps
CPU time 0.57 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 194656 kb
Host smart-48e0f911-71e5-4fe9-b407-9a3f255c0483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671322994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1671322994
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1678023559
Short name T85
Test name
Test status
Simulation time 188667984 ps
CPU time 0.65 seconds
Started May 07 03:01:43 PM PDT 24
Finished May 07 03:01:45 PM PDT 24
Peak memory 194684 kb
Host smart-2cb8ea68-c8dc-4084-bcb0-f6ee0dec80e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678023559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1678023559
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3376225250
Short name T545
Test name
Test status
Simulation time 129163814 ps
CPU time 0.62 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 194612 kb
Host smart-56cddad9-7c60-4489-96d4-96959d82d27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376225250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3376225250
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1234722139
Short name T469
Test name
Test status
Simulation time 21802279 ps
CPU time 0.6 seconds
Started May 07 03:01:41 PM PDT 24
Finished May 07 03:01:43 PM PDT 24
Peak memory 194824 kb
Host smart-fdb1a0c2-bf2c-4382-aa92-f44d4e4f7aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234722139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1234722139
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.951520645
Short name T472
Test name
Test status
Simulation time 14186860 ps
CPU time 0.61 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 194668 kb
Host smart-240399d5-e82d-41ea-891a-9c0d5c90fddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951520645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.951520645
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1251267668
Short name T477
Test name
Test status
Simulation time 46124270 ps
CPU time 0.57 seconds
Started May 07 03:01:42 PM PDT 24
Finished May 07 03:01:44 PM PDT 24
Peak memory 194648 kb
Host smart-83f742c5-fb66-446b-a0e2-c687bf8ea51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251267668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1251267668
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.873213415
Short name T580
Test name
Test status
Simulation time 17305077 ps
CPU time 0.61 seconds
Started May 07 03:01:44 PM PDT 24
Finished May 07 03:01:46 PM PDT 24
Peak memory 194776 kb
Host smart-d3b40ec9-06f1-4fab-9fad-5f08df51c3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873213415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.873213415
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.185874679
Short name T520
Test name
Test status
Simulation time 253940624 ps
CPU time 2.05 seconds
Started May 07 03:01:11 PM PDT 24
Finished May 07 03:01:14 PM PDT 24
Peak memory 200064 kb
Host smart-bb5634b7-65ef-45ae-8aae-b55a545581a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185874679 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.185874679
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1089204392
Short name T101
Test name
Test status
Simulation time 42785448 ps
CPU time 0.82 seconds
Started May 07 03:01:11 PM PDT 24
Finished May 07 03:01:12 PM PDT 24
Peak memory 199392 kb
Host smart-f0514e9b-a66b-4720-8957-d4cc2b86bd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089204392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1089204392
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1361310250
Short name T484
Test name
Test status
Simulation time 49815450 ps
CPU time 0.58 seconds
Started May 07 03:01:11 PM PDT 24
Finished May 07 03:01:12 PM PDT 24
Peak memory 194680 kb
Host smart-c11cead2-01ef-4157-9e43-d07a0ec758ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361310250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1361310250
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1242553841
Short name T548
Test name
Test status
Simulation time 733553285 ps
CPU time 2.27 seconds
Started May 07 03:01:11 PM PDT 24
Finished May 07 03:01:14 PM PDT 24
Peak memory 199788 kb
Host smart-5f55bf8a-842d-4e8c-b86b-ffd7b775c55f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242553841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1242553841
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4206142884
Short name T588
Test name
Test status
Simulation time 479872648 ps
CPU time 4.42 seconds
Started May 07 03:01:04 PM PDT 24
Finished May 07 03:01:11 PM PDT 24
Peak memory 200032 kb
Host smart-d4f67f38-5761-4b3f-92cb-250dc2b4fa2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206142884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4206142884
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3881146313
Short name T122
Test name
Test status
Simulation time 184233190 ps
CPU time 1.87 seconds
Started May 07 03:01:06 PM PDT 24
Finished May 07 03:01:10 PM PDT 24
Peak memory 200052 kb
Host smart-d183a034-6bbb-4930-8d7d-9f4b19e0a5de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881146313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3881146313
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2212521205
Short name T541
Test name
Test status
Simulation time 48996213 ps
CPU time 3.23 seconds
Started May 07 03:01:15 PM PDT 24
Finished May 07 03:01:19 PM PDT 24
Peak memory 216448 kb
Host smart-cd62a528-38f2-4582-8cb4-2bcd14004f38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212521205 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2212521205
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.415285178
Short name T467
Test name
Test status
Simulation time 54448007 ps
CPU time 0.69 seconds
Started May 07 03:01:10 PM PDT 24
Finished May 07 03:01:11 PM PDT 24
Peak memory 197392 kb
Host smart-69e027b8-1451-418d-90f6-388f7898c8ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415285178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.415285178
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1301266719
Short name T557
Test name
Test status
Simulation time 36517042 ps
CPU time 0.59 seconds
Started May 07 03:01:12 PM PDT 24
Finished May 07 03:01:14 PM PDT 24
Peak memory 194576 kb
Host smart-17434106-769f-4dc9-896a-c0803299c1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301266719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1301266719
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1897018418
Short name T544
Test name
Test status
Simulation time 110379462 ps
CPU time 1.18 seconds
Started May 07 03:01:13 PM PDT 24
Finished May 07 03:01:15 PM PDT 24
Peak memory 199588 kb
Host smart-925024a5-4077-4ece-9557-98ec6e6ae04d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897018418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1897018418
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2844788584
Short name T25
Test name
Test status
Simulation time 385262210 ps
CPU time 2.29 seconds
Started May 07 03:01:12 PM PDT 24
Finished May 07 03:01:16 PM PDT 24
Peak memory 200004 kb
Host smart-31a8ddf3-a8b7-4188-88cc-486c40b2ef68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844788584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2844788584
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2103758740
Short name T570
Test name
Test status
Simulation time 392677033 ps
CPU time 3.25 seconds
Started May 07 03:01:14 PM PDT 24
Finished May 07 03:01:18 PM PDT 24
Peak memory 200052 kb
Host smart-853fac41-0ba6-4fde-9732-deace65c3a72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103758740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2103758740
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4112265222
Short name T491
Test name
Test status
Simulation time 4402178220 ps
CPU time 66.75 seconds
Started May 07 03:01:20 PM PDT 24
Finished May 07 03:02:28 PM PDT 24
Peak memory 208552 kb
Host smart-664c132f-ec76-4b94-ba2f-d659d9dab8fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112265222 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4112265222
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3610173777
Short name T563
Test name
Test status
Simulation time 45866800 ps
CPU time 0.71 seconds
Started May 07 03:01:11 PM PDT 24
Finished May 07 03:01:13 PM PDT 24
Peak memory 197880 kb
Host smart-d5f8f211-f24c-43e5-be9a-0922e1d0cfbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610173777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3610173777
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1595317873
Short name T81
Test name
Test status
Simulation time 49059898 ps
CPU time 0.59 seconds
Started May 07 03:01:11 PM PDT 24
Finished May 07 03:01:13 PM PDT 24
Peak memory 194600 kb
Host smart-9c7015c1-0d15-4c4b-8d29-2226dd7ac550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595317873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1595317873
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3887775339
Short name T488
Test name
Test status
Simulation time 220190181 ps
CPU time 1.16 seconds
Started May 07 03:01:10 PM PDT 24
Finished May 07 03:01:12 PM PDT 24
Peak memory 198136 kb
Host smart-5cea2f0a-7849-4d1e-9b05-ecb024dfda41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887775339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3887775339
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.144616798
Short name T513
Test name
Test status
Simulation time 60622540 ps
CPU time 1.62 seconds
Started May 07 03:01:13 PM PDT 24
Finished May 07 03:01:16 PM PDT 24
Peak memory 199860 kb
Host smart-af82771d-d311-4d6d-a0f1-0d8198c1c72b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144616798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.144616798
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2116744449
Short name T584
Test name
Test status
Simulation time 54931945 ps
CPU time 3.19 seconds
Started May 07 03:01:15 PM PDT 24
Finished May 07 03:01:19 PM PDT 24
Peak memory 208308 kb
Host smart-cd0ada98-ebe3-42ab-a154-3fd7eaacb1ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116744449 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2116744449
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3530137309
Short name T111
Test name
Test status
Simulation time 81496389 ps
CPU time 0.79 seconds
Started May 07 03:01:18 PM PDT 24
Finished May 07 03:01:20 PM PDT 24
Peak memory 199140 kb
Host smart-95b98099-d5e8-4966-aa17-3d8597644514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530137309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3530137309
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.129280873
Short name T553
Test name
Test status
Simulation time 12789365 ps
CPU time 0.59 seconds
Started May 07 03:01:16 PM PDT 24
Finished May 07 03:01:17 PM PDT 24
Peak memory 194844 kb
Host smart-57cfeb56-c7ec-4825-8b53-efc11269203b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129280873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.129280873
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.328152642
Short name T581
Test name
Test status
Simulation time 530326800 ps
CPU time 1.15 seconds
Started May 07 03:01:18 PM PDT 24
Finished May 07 03:01:21 PM PDT 24
Peak memory 198200 kb
Host smart-8deeb035-14cf-4588-8169-bfa136cbd832
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328152642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.328152642
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2914496939
Short name T502
Test name
Test status
Simulation time 202387700 ps
CPU time 2.42 seconds
Started May 07 03:01:19 PM PDT 24
Finished May 07 03:01:23 PM PDT 24
Peak memory 200020 kb
Host smart-7a7ddc0a-a618-4645-8a54-d4c7ca434134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914496939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2914496939
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2468279340
Short name T96
Test name
Test status
Simulation time 832275546 ps
CPU time 3.16 seconds
Started May 07 03:01:16 PM PDT 24
Finished May 07 03:01:20 PM PDT 24
Peak memory 199968 kb
Host smart-480d1b19-44e7-46d9-99f9-1c021e513c77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468279340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2468279340
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.121893751
Short name T506
Test name
Test status
Simulation time 273626877871 ps
CPU time 553.17 seconds
Started May 07 03:01:18 PM PDT 24
Finished May 07 03:10:33 PM PDT 24
Peak memory 216372 kb
Host smart-79f915a1-1051-429d-b680-e746439afde1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121893751 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.121893751
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3701358879
Short name T568
Test name
Test status
Simulation time 38312948 ps
CPU time 0.67 seconds
Started May 07 03:01:16 PM PDT 24
Finished May 07 03:01:18 PM PDT 24
Peak memory 197764 kb
Host smart-b75ecd41-3d5c-4822-b85c-4630396609a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701358879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3701358879
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2056096034
Short name T565
Test name
Test status
Simulation time 18483821 ps
CPU time 0.63 seconds
Started May 07 03:01:17 PM PDT 24
Finished May 07 03:01:19 PM PDT 24
Peak memory 194672 kb
Host smart-7353d83a-d8ce-4764-9f47-0d618490b44a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056096034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2056096034
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3735355647
Short name T494
Test name
Test status
Simulation time 54907718 ps
CPU time 1.23 seconds
Started May 07 03:01:17 PM PDT 24
Finished May 07 03:01:20 PM PDT 24
Peak memory 199780 kb
Host smart-11119548-fb01-4943-ae82-533baa2cee18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735355647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3735355647
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.200838130
Short name T575
Test name
Test status
Simulation time 129860994 ps
CPU time 1.45 seconds
Started May 07 03:01:15 PM PDT 24
Finished May 07 03:01:18 PM PDT 24
Peak memory 200080 kb
Host smart-3a7d8e4c-81fb-4a1d-8b00-617a1c10a41d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200838130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.200838130
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4219964525
Short name T69
Test name
Test status
Simulation time 98067520 ps
CPU time 2.81 seconds
Started May 07 03:01:20 PM PDT 24
Finished May 07 03:01:24 PM PDT 24
Peak memory 199948 kb
Host smart-fd165bb7-405f-4f73-898a-d608a9af6bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219964525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4219964525
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1669346069
Short name T379
Test name
Test status
Simulation time 1203689894 ps
CPU time 29 seconds
Started May 07 01:10:16 PM PDT 24
Finished May 07 01:10:46 PM PDT 24
Peak memory 211128 kb
Host smart-a600b8d3-98f2-4a16-8a19-b62df702f32b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669346069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1669346069
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2615192991
Short name T163
Test name
Test status
Simulation time 2624533473 ps
CPU time 42.94 seconds
Started May 07 01:10:07 PM PDT 24
Finished May 07 01:10:50 PM PDT 24
Peak memory 200036 kb
Host smart-49fe015f-6b76-4827-bfc8-b29d024018de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615192991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2615192991
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.482254706
Short name T238
Test name
Test status
Simulation time 79863775 ps
CPU time 0.91 seconds
Started May 07 01:10:07 PM PDT 24
Finished May 07 01:10:09 PM PDT 24
Peak memory 199208 kb
Host smart-03fae43c-abf1-4e4a-9983-a47c397e5fce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482254706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.482254706
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2277080068
Short name T365
Test name
Test status
Simulation time 3389602568 ps
CPU time 98.79 seconds
Started May 07 01:10:07 PM PDT 24
Finished May 07 01:11:47 PM PDT 24
Peak memory 200028 kb
Host smart-0a7769de-8e07-4691-8ff3-082227d56eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277080068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2277080068
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2977681351
Short name T303
Test name
Test status
Simulation time 159949924 ps
CPU time 5.1 seconds
Started May 07 01:10:08 PM PDT 24
Finished May 07 01:10:15 PM PDT 24
Peak memory 199948 kb
Host smart-3b3eb0b4-c549-4119-8eb2-3f3f78b20692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977681351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2977681351
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.588922439
Short name T374
Test name
Test status
Simulation time 31595850 ps
CPU time 1.04 seconds
Started May 07 01:10:09 PM PDT 24
Finished May 07 01:10:11 PM PDT 24
Peak memory 199332 kb
Host smart-be8f0979-a5f0-4624-a1db-5c151b50112a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588922439 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.588922439
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1868555736
Short name T356
Test name
Test status
Simulation time 8120420027 ps
CPU time 419.37 seconds
Started May 07 01:10:08 PM PDT 24
Finished May 07 01:17:09 PM PDT 24
Peak memory 200076 kb
Host smart-181838ee-d3c4-4aeb-b052-3965326d952a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868555736 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1868555736
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3215586448
Short name T354
Test name
Test status
Simulation time 13119370 ps
CPU time 0.61 seconds
Started May 07 01:10:16 PM PDT 24
Finished May 07 01:10:17 PM PDT 24
Peak memory 195652 kb
Host smart-be30f01d-dea0-4c7a-83e5-b3acfee82572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215586448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3215586448
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1319938297
Short name T241
Test name
Test status
Simulation time 15519709585 ps
CPU time 37.81 seconds
Started May 07 01:10:10 PM PDT 24
Finished May 07 01:10:49 PM PDT 24
Peak memory 215440 kb
Host smart-aea9654a-5190-462c-b9e5-3355a1714050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319938297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1319938297
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2964792000
Short name T92
Test name
Test status
Simulation time 1417036989 ps
CPU time 56.37 seconds
Started May 07 01:10:09 PM PDT 24
Finished May 07 01:11:06 PM PDT 24
Peak memory 199972 kb
Host smart-bd7bdcc6-cb13-49cf-8fca-7016031914e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964792000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2964792000
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3740453609
Short name T334
Test name
Test status
Simulation time 1400897226 ps
CPU time 80.64 seconds
Started May 07 01:10:06 PM PDT 24
Finished May 07 01:11:28 PM PDT 24
Peak memory 199952 kb
Host smart-629fcadb-aada-4b97-a129-bd9aa9c89ba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740453609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3740453609
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3660150730
Short name T204
Test name
Test status
Simulation time 3105411821 ps
CPU time 16.46 seconds
Started May 07 01:10:09 PM PDT 24
Finished May 07 01:10:26 PM PDT 24
Peak memory 199984 kb
Host smart-7c57060f-28a2-41a0-a40e-51f6a7afde57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660150730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3660150730
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3214915040
Short name T36
Test name
Test status
Simulation time 372366928 ps
CPU time 0.89 seconds
Started May 07 01:10:16 PM PDT 24
Finished May 07 01:10:18 PM PDT 24
Peak memory 218372 kb
Host smart-2a4aecc9-0712-4a99-939e-d7b0c6724c04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214915040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3214915040
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3341828511
Short name T186
Test name
Test status
Simulation time 260140594 ps
CPU time 1.56 seconds
Started May 07 01:10:08 PM PDT 24
Finished May 07 01:10:11 PM PDT 24
Peak memory 199936 kb
Host smart-d6fff395-bc6c-43f5-959d-de0e1a53b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341828511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3341828511
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3553236251
Short name T372
Test name
Test status
Simulation time 75655903 ps
CPU time 0.94 seconds
Started May 07 01:10:16 PM PDT 24
Finished May 07 01:10:18 PM PDT 24
Peak memory 198588 kb
Host smart-1b8e898f-c2f7-41b6-854b-cf6a3095e27b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553236251 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3553236251
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.173271280
Short name T279
Test name
Test status
Simulation time 72550776 ps
CPU time 1.21 seconds
Started May 07 01:10:15 PM PDT 24
Finished May 07 01:10:17 PM PDT 24
Peak memory 199948 kb
Host smart-8d5adb4f-6c6c-4cc2-8934-7377e1f05767
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173271280 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.173271280
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2201443750
Short name T387
Test name
Test status
Simulation time 28699309774 ps
CPU time 451.61 seconds
Started May 07 01:10:15 PM PDT 24
Finished May 07 01:17:48 PM PDT 24
Peak memory 200012 kb
Host smart-be4089af-1f30-4965-a4d0-6a0f0b3c74c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201443750 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2201443750
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1949983551
Short name T366
Test name
Test status
Simulation time 5625586220 ps
CPU time 7.6 seconds
Started May 07 01:10:14 PM PDT 24
Finished May 07 01:10:23 PM PDT 24
Peak memory 200016 kb
Host smart-77ca45fd-c703-406a-a135-55831d537776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949983551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1949983551
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2668767556
Short name T320
Test name
Test status
Simulation time 46128157 ps
CPU time 0.55 seconds
Started May 07 01:11:21 PM PDT 24
Finished May 07 01:11:23 PM PDT 24
Peak memory 195372 kb
Host smart-32aa4dba-f273-4188-a193-b6be499ec272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668767556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2668767556
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2463511175
Short name T414
Test name
Test status
Simulation time 1154799920 ps
CPU time 66.44 seconds
Started May 07 01:11:13 PM PDT 24
Finished May 07 01:12:20 PM PDT 24
Peak memory 229396 kb
Host smart-934fae56-6496-4ad5-b7da-a1b6d6497dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463511175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2463511175
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.862063410
Short name T350
Test name
Test status
Simulation time 3221997672 ps
CPU time 33.26 seconds
Started May 07 01:11:12 PM PDT 24
Finished May 07 01:11:46 PM PDT 24
Peak memory 200088 kb
Host smart-4d763a5b-0acc-464c-88f2-cf881bed6d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862063410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.862063410
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4010083640
Short name T460
Test name
Test status
Simulation time 10779647485 ps
CPU time 133.41 seconds
Started May 07 01:11:14 PM PDT 24
Finished May 07 01:13:28 PM PDT 24
Peak memory 199936 kb
Host smart-e29072c0-f4c2-473b-942f-9eb445170660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010083640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4010083640
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3567590853
Short name T244
Test name
Test status
Simulation time 25578607534 ps
CPU time 124.39 seconds
Started May 07 01:11:12 PM PDT 24
Finished May 07 01:13:18 PM PDT 24
Peak memory 200048 kb
Host smart-e50720e5-bb7e-49e3-b456-65cccef58bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567590853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3567590853
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3640640842
Short name T78
Test name
Test status
Simulation time 399704737 ps
CPU time 1.62 seconds
Started May 07 01:11:13 PM PDT 24
Finished May 07 01:11:16 PM PDT 24
Peak memory 199900 kb
Host smart-76cb3f77-036e-45b3-b442-04998ac3e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640640842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3640640842
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2275688119
Short name T412
Test name
Test status
Simulation time 103708628 ps
CPU time 1.03 seconds
Started May 07 01:11:23 PM PDT 24
Finished May 07 01:11:25 PM PDT 24
Peak memory 199404 kb
Host smart-ecf0dedf-0a34-47c3-945f-4d5ccf42f25a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275688119 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2275688119
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.984644113
Short name T319
Test name
Test status
Simulation time 7909213428 ps
CPU time 389.52 seconds
Started May 07 01:11:22 PM PDT 24
Finished May 07 01:17:53 PM PDT 24
Peak memory 200016 kb
Host smart-7348efc1-6ec0-4cd8-acef-0a5fe4fb8f63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984644113 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.984644113
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2900602437
Short name T179
Test name
Test status
Simulation time 14069719 ps
CPU time 0.58 seconds
Started May 07 01:11:30 PM PDT 24
Finished May 07 01:11:32 PM PDT 24
Peak memory 195372 kb
Host smart-f4c4f564-923f-4478-81c1-a2e40e9ed485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900602437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2900602437
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.679159997
Short name T50
Test name
Test status
Simulation time 249277844 ps
CPU time 12.73 seconds
Started May 07 01:11:23 PM PDT 24
Finished May 07 01:11:37 PM PDT 24
Peak memory 216112 kb
Host smart-332f3a8f-c90f-40ba-ae56-639bf055f91c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679159997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.679159997
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.416864532
Short name T177
Test name
Test status
Simulation time 7604492937 ps
CPU time 12.28 seconds
Started May 07 01:11:22 PM PDT 24
Finished May 07 01:11:36 PM PDT 24
Peak memory 200012 kb
Host smart-17b33a22-d3fd-4bfd-b4c1-9c290f18ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416864532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.416864532
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.935898443
Short name T386
Test name
Test status
Simulation time 951557663 ps
CPU time 53.83 seconds
Started May 07 01:11:23 PM PDT 24
Finished May 07 01:12:18 PM PDT 24
Peak memory 199972 kb
Host smart-556877fa-6667-49ab-bb32-f36cf12ddb7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935898443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.935898443
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3707109845
Short name T458
Test name
Test status
Simulation time 6835800329 ps
CPU time 100.38 seconds
Started May 07 01:11:22 PM PDT 24
Finished May 07 01:13:04 PM PDT 24
Peak memory 200036 kb
Host smart-6cbb210b-e800-4a0c-99b0-c24d3371ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707109845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3707109845
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2636323360
Short name T7
Test name
Test status
Simulation time 511730695 ps
CPU time 4.57 seconds
Started May 07 01:11:20 PM PDT 24
Finished May 07 01:11:25 PM PDT 24
Peak memory 199944 kb
Host smart-70c696cd-f261-4bf1-abc3-00568d6ed5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636323360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2636323360
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3895463978
Short name T63
Test name
Test status
Simulation time 15754381506 ps
CPU time 241.44 seconds
Started May 07 01:11:22 PM PDT 24
Finished May 07 01:15:25 PM PDT 24
Peak memory 208256 kb
Host smart-dc2215cf-7303-4d01-950b-11ac25568067
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895463978 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3895463978
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.585617828
Short name T262
Test name
Test status
Simulation time 505846655 ps
CPU time 0.99 seconds
Started May 07 01:11:21 PM PDT 24
Finished May 07 01:11:24 PM PDT 24
Peak memory 198824 kb
Host smart-467b79e3-fd03-4a5a-976d-b97a686ae262
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585617828 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.585617828
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2046177944
Short name T187
Test name
Test status
Simulation time 184034171281 ps
CPU time 580.57 seconds
Started May 07 01:11:22 PM PDT 24
Finished May 07 01:21:04 PM PDT 24
Peak memory 200056 kb
Host smart-c50f87b4-90d5-476a-be5d-dc284072c027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046177944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2046177944
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3542103551
Short name T33
Test name
Test status
Simulation time 13912782 ps
CPU time 0.56 seconds
Started May 07 01:12:00 PM PDT 24
Finished May 07 01:12:01 PM PDT 24
Peak memory 195376 kb
Host smart-63f402e6-3b55-4ce1-964b-abf46500fe8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542103551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3542103551
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1547104523
Short name T417
Test name
Test status
Simulation time 3970816553 ps
CPU time 50.97 seconds
Started May 07 01:12:02 PM PDT 24
Finished May 07 01:12:54 PM PDT 24
Peak memory 200036 kb
Host smart-e8458fd9-35ae-4d27-ba4e-9dd3d74b2887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547104523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1547104523
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.438548734
Short name T402
Test name
Test status
Simulation time 48396362862 ps
CPU time 141.39 seconds
Started May 07 01:11:36 PM PDT 24
Finished May 07 01:13:59 PM PDT 24
Peak memory 200040 kb
Host smart-9bf1200c-c8b1-4beb-af07-f966e08cd10e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438548734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.438548734
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2348723108
Short name T115
Test name
Test status
Simulation time 6418752210 ps
CPU time 82.01 seconds
Started May 07 01:12:06 PM PDT 24
Finished May 07 01:13:29 PM PDT 24
Peak memory 200016 kb
Host smart-4b697046-1de3-45c3-bed2-909ea8cde7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348723108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2348723108
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1644349659
Short name T274
Test name
Test status
Simulation time 1867384955 ps
CPU time 4.37 seconds
Started May 07 01:11:30 PM PDT 24
Finished May 07 01:11:35 PM PDT 24
Peak memory 199952 kb
Host smart-56293747-7512-483c-94f6-76b819274fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644349659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1644349659
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2151927056
Short name T297
Test name
Test status
Simulation time 214651009 ps
CPU time 1.14 seconds
Started May 07 01:12:04 PM PDT 24
Finished May 07 01:12:06 PM PDT 24
Peak memory 199964 kb
Host smart-311361c2-7c1c-4b5e-9941-6dd3a6ac0d49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151927056 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2151927056
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.862206599
Short name T330
Test name
Test status
Simulation time 308523011079 ps
CPU time 538.51 seconds
Started May 07 01:11:35 PM PDT 24
Finished May 07 01:20:35 PM PDT 24
Peak memory 199988 kb
Host smart-f4a54c05-1a44-4965-b149-77faba330a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862206599 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.862206599
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3123792189
Short name T136
Test name
Test status
Simulation time 61267010 ps
CPU time 0.72 seconds
Started May 07 01:11:35 PM PDT 24
Finished May 07 01:11:37 PM PDT 24
Peak memory 195380 kb
Host smart-f5d016af-f86c-4f69-90ab-59d0b660d679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123792189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3123792189
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2438180398
Short name T39
Test name
Test status
Simulation time 3267399684 ps
CPU time 36.59 seconds
Started May 07 01:11:36 PM PDT 24
Finished May 07 01:12:14 PM PDT 24
Peak memory 209208 kb
Host smart-cc238761-37ca-49f5-8279-0856875046b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438180398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2438180398
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2226363403
Short name T451
Test name
Test status
Simulation time 572433796 ps
CPU time 7.76 seconds
Started May 07 01:11:33 PM PDT 24
Finished May 07 01:11:41 PM PDT 24
Peak memory 199952 kb
Host smart-1f1f9e6f-f41c-4cac-abd3-1eeddba33a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226363403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2226363403
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3347888489
Short name T340
Test name
Test status
Simulation time 1935491358 ps
CPU time 110.93 seconds
Started May 07 01:12:06 PM PDT 24
Finished May 07 01:13:58 PM PDT 24
Peak memory 199960 kb
Host smart-3b03141d-198c-4622-8d7b-67cf77491213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347888489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3347888489
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.227050655
Short name T289
Test name
Test status
Simulation time 9282059130 ps
CPU time 30.96 seconds
Started May 07 01:11:35 PM PDT 24
Finished May 07 01:12:08 PM PDT 24
Peak memory 200072 kb
Host smart-b8adb069-67e5-4823-8fa1-bad4c07add12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227050655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.227050655
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1091509679
Short name T154
Test name
Test status
Simulation time 491674316 ps
CPU time 3.15 seconds
Started May 07 01:11:35 PM PDT 24
Finished May 07 01:11:40 PM PDT 24
Peak memory 199976 kb
Host smart-c4562e72-a1a3-43e8-acd9-8551572a4634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091509679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1091509679
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2166193091
Short name T183
Test name
Test status
Simulation time 120041070 ps
CPU time 1.22 seconds
Started May 07 01:11:55 PM PDT 24
Finished May 07 01:11:57 PM PDT 24
Peak memory 199960 kb
Host smart-03fb8fd8-1ca6-442c-81c4-a053b7f88487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166193091 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2166193091
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1525942385
Short name T95
Test name
Test status
Simulation time 119755835340 ps
CPU time 477.73 seconds
Started May 07 01:11:51 PM PDT 24
Finished May 07 01:19:50 PM PDT 24
Peak memory 200008 kb
Host smart-9f95e669-5048-49e1-9519-efed7cfa5765
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525942385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1525942385
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3255578819
Short name T298
Test name
Test status
Simulation time 87357196 ps
CPU time 0.62 seconds
Started May 07 01:11:38 PM PDT 24
Finished May 07 01:11:40 PM PDT 24
Peak memory 195780 kb
Host smart-a859c0ec-3bae-4210-babf-c4b0c95be402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255578819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3255578819
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.155616142
Short name T349
Test name
Test status
Simulation time 120337941 ps
CPU time 1.3 seconds
Started May 07 01:11:35 PM PDT 24
Finished May 07 01:11:38 PM PDT 24
Peak memory 199960 kb
Host smart-f748c65c-b5ea-45d9-9fed-82066c0fabac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155616142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.155616142
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2285387040
Short name T131
Test name
Test status
Simulation time 891299300 ps
CPU time 22.05 seconds
Started May 07 01:11:39 PM PDT 24
Finished May 07 01:12:02 PM PDT 24
Peak memory 199936 kb
Host smart-a87787a8-e0dd-4272-b3e5-c49495b67331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285387040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2285387040
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1474918183
Short name T413
Test name
Test status
Simulation time 3021458620 ps
CPU time 63.72 seconds
Started May 07 01:12:07 PM PDT 24
Finished May 07 01:13:12 PM PDT 24
Peak memory 200036 kb
Host smart-af6ebdb4-c025-4f11-9b7c-d742b89f01aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474918183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1474918183
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_long_msg.555607824
Short name T436
Test name
Test status
Simulation time 9479462090 ps
CPU time 134.17 seconds
Started May 07 01:12:07 PM PDT 24
Finished May 07 01:14:22 PM PDT 24
Peak memory 200020 kb
Host smart-c17638a0-54af-4260-a473-681cf44661b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555607824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.555607824
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.307070725
Short name T440
Test name
Test status
Simulation time 202686686 ps
CPU time 3.16 seconds
Started May 07 01:12:09 PM PDT 24
Finished May 07 01:12:13 PM PDT 24
Peak memory 199948 kb
Host smart-962f6146-e814-4783-badd-d9d10d1e8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307070725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.307070725
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2542334305
Short name T155
Test name
Test status
Simulation time 38110121 ps
CPU time 1.23 seconds
Started May 07 01:11:36 PM PDT 24
Finished May 07 01:11:38 PM PDT 24
Peak memory 199140 kb
Host smart-c4ef4218-5baa-4722-aef2-61ba86d6368a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542334305 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2542334305
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1506911975
Short name T215
Test name
Test status
Simulation time 103393151302 ps
CPU time 436.65 seconds
Started May 07 01:11:37 PM PDT 24
Finished May 07 01:18:55 PM PDT 24
Peak memory 200052 kb
Host smart-5ab33f69-aeb8-4f1f-9a33-ea79ac7e7220
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506911975 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1506911975
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1546599556
Short name T201
Test name
Test status
Simulation time 17107589 ps
CPU time 0.6 seconds
Started May 07 01:12:15 PM PDT 24
Finished May 07 01:12:16 PM PDT 24
Peak memory 195680 kb
Host smart-ff30763a-038e-458a-a95a-8e80992153c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546599556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1546599556
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.555456683
Short name T259
Test name
Test status
Simulation time 3659155848 ps
CPU time 43.21 seconds
Started May 07 01:11:54 PM PDT 24
Finished May 07 01:12:38 PM PDT 24
Peak memory 215036 kb
Host smart-2c344f83-fca6-4223-9c86-00745eb05209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555456683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.555456683
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4220379734
Short name T367
Test name
Test status
Simulation time 647962732 ps
CPU time 6.86 seconds
Started May 07 01:11:38 PM PDT 24
Finished May 07 01:11:46 PM PDT 24
Peak memory 199844 kb
Host smart-c501090b-ab20-459f-830a-98a95cdfb46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220379734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4220379734
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2205220183
Short name T248
Test name
Test status
Simulation time 549879324 ps
CPU time 16.42 seconds
Started May 07 01:11:37 PM PDT 24
Finished May 07 01:11:55 PM PDT 24
Peak memory 199876 kb
Host smart-fba083dd-6662-49e2-bbac-9320c944fa5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205220183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2205220183
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_long_msg.188679375
Short name T160
Test name
Test status
Simulation time 12323929224 ps
CPU time 45.24 seconds
Started May 07 01:12:08 PM PDT 24
Finished May 07 01:12:54 PM PDT 24
Peak memory 200060 kb
Host smart-ceee255c-aaeb-41a1-9c7d-8eebcba20208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188679375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.188679375
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.337456698
Short name T211
Test name
Test status
Simulation time 383693082 ps
CPU time 1.8 seconds
Started May 07 01:12:13 PM PDT 24
Finished May 07 01:12:16 PM PDT 24
Peak memory 199928 kb
Host smart-8aea6a30-dcee-44c7-999f-72a5570c107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337456698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.337456698
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2741463633
Short name T224
Test name
Test status
Simulation time 59211715 ps
CPU time 1.28 seconds
Started May 07 01:12:17 PM PDT 24
Finished May 07 01:12:19 PM PDT 24
Peak memory 199996 kb
Host smart-0b138222-f48a-4c7e-8157-c21886dfbc7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741463633 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2741463633
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.840339953
Short name T278
Test name
Test status
Simulation time 37760428861 ps
CPU time 508.19 seconds
Started May 07 01:11:54 PM PDT 24
Finished May 07 01:20:23 PM PDT 24
Peak memory 200012 kb
Host smart-932e6479-710c-40c0-9d9d-1fdad8dd8ec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840339953 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.840339953
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.569159697
Short name T383
Test name
Test status
Simulation time 56724629 ps
CPU time 0.59 seconds
Started May 07 01:12:08 PM PDT 24
Finished May 07 01:12:09 PM PDT 24
Peak memory 195552 kb
Host smart-65f234da-6242-4124-88b3-2dcf70b92511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569159697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.569159697
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.386534419
Short name T170
Test name
Test status
Simulation time 2146411009 ps
CPU time 50.97 seconds
Started May 07 01:12:13 PM PDT 24
Finished May 07 01:13:05 PM PDT 24
Peak memory 211920 kb
Host smart-87a18332-3985-40c4-9224-5b06f50733f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386534419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.386534419
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.910018380
Short name T239
Test name
Test status
Simulation time 4492021902 ps
CPU time 32.89 seconds
Started May 07 01:12:17 PM PDT 24
Finished May 07 01:12:51 PM PDT 24
Peak memory 200044 kb
Host smart-44b20036-46c6-45c6-8ac8-ef0bd4a9dff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910018380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.910018380
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3392929894
Short name T449
Test name
Test status
Simulation time 219965337 ps
CPU time 12.01 seconds
Started May 07 01:12:09 PM PDT 24
Finished May 07 01:12:22 PM PDT 24
Peak memory 199904 kb
Host smart-dd4da324-1381-4e17-9f7a-fc879c5f1c68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392929894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3392929894
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2053001820
Short name T214
Test name
Test status
Simulation time 17628211302 ps
CPU time 48.24 seconds
Started May 07 01:11:43 PM PDT 24
Finished May 07 01:12:32 PM PDT 24
Peak memory 200004 kb
Host smart-2eb3bde2-494f-40f2-93c1-b71256cfc91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053001820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2053001820
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1799546021
Short name T233
Test name
Test status
Simulation time 707593914 ps
CPU time 3.11 seconds
Started May 07 01:12:02 PM PDT 24
Finished May 07 01:12:06 PM PDT 24
Peak memory 199968 kb
Host smart-3bbd3f07-fa33-475b-ad74-d733dd08a606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799546021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1799546021
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3885288668
Short name T455
Test name
Test status
Simulation time 49606761 ps
CPU time 1.06 seconds
Started May 07 01:11:42 PM PDT 24
Finished May 07 01:11:44 PM PDT 24
Peak memory 199508 kb
Host smart-9f494bae-ef5c-42a2-9202-d6d3f4e2fceb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885288668 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3885288668
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2430411360
Short name T200
Test name
Test status
Simulation time 25882719448 ps
CPU time 457.54 seconds
Started May 07 01:12:17 PM PDT 24
Finished May 07 01:19:56 PM PDT 24
Peak memory 200064 kb
Host smart-3047f262-fb32-4be0-a10b-a4afed0cebaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430411360 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2430411360
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3852679869
Short name T342
Test name
Test status
Simulation time 13276269 ps
CPU time 0.58 seconds
Started May 07 01:12:08 PM PDT 24
Finished May 07 01:12:10 PM PDT 24
Peak memory 195340 kb
Host smart-b70650ec-d607-46db-95c3-2372a74a666e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852679869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3852679869
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1333786656
Short name T265
Test name
Test status
Simulation time 511173137 ps
CPU time 24.14 seconds
Started May 07 01:11:52 PM PDT 24
Finished May 07 01:12:17 PM PDT 24
Peak memory 199860 kb
Host smart-f1fa7426-221b-4dd9-8cc1-398fc7cd7a0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333786656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1333786656
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3863506181
Short name T397
Test name
Test status
Simulation time 1511277239 ps
CPU time 36.2 seconds
Started May 07 01:12:30 PM PDT 24
Finished May 07 01:13:08 PM PDT 24
Peak memory 199916 kb
Host smart-472f681f-33cc-4751-9f67-b61f88b1846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863506181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3863506181
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1642966038
Short name T199
Test name
Test status
Simulation time 2357117318 ps
CPU time 135.33 seconds
Started May 07 01:11:50 PM PDT 24
Finished May 07 01:14:06 PM PDT 24
Peak memory 200020 kb
Host smart-15209d99-a29c-4925-97fb-cad848db31a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642966038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1642966038
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2421170476
Short name T77
Test name
Test status
Simulation time 15183883332 ps
CPU time 91.81 seconds
Started May 07 01:12:18 PM PDT 24
Finished May 07 01:13:51 PM PDT 24
Peak memory 200044 kb
Host smart-d4e524f5-742c-4d07-810f-8f6dbd39f67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421170476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2421170476
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1354256166
Short name T395
Test name
Test status
Simulation time 116885757 ps
CPU time 3.66 seconds
Started May 07 01:12:29 PM PDT 24
Finished May 07 01:12:33 PM PDT 24
Peak memory 199952 kb
Host smart-5b02dda4-ca80-4235-b1dd-9d8e7c5835a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354256166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1354256166
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.536958590
Short name T79
Test name
Test status
Simulation time 99486339242 ps
CPU time 644.48 seconds
Started May 07 01:12:19 PM PDT 24
Finished May 07 01:23:04 PM PDT 24
Peak memory 200040 kb
Host smart-be7ec0d0-2525-4641-9e42-e6cd65aafbe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536958590 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.536958590
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3066615898
Short name T144
Test name
Test status
Simulation time 63666760 ps
CPU time 1.26 seconds
Started May 07 01:12:07 PM PDT 24
Finished May 07 01:12:09 PM PDT 24
Peak memory 199968 kb
Host smart-5cf26068-1380-40ea-a87d-425acaf6b519
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066615898 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3066615898
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2725296976
Short name T267
Test name
Test status
Simulation time 16816552243 ps
CPU time 448.07 seconds
Started May 07 01:12:30 PM PDT 24
Finished May 07 01:20:00 PM PDT 24
Peak memory 200032 kb
Host smart-e267c9f2-dc55-4cd4-8691-a21ae07e2aad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725296976 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2725296976
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2155569698
Short name T151
Test name
Test status
Simulation time 12673110 ps
CPU time 0.57 seconds
Started May 07 01:12:06 PM PDT 24
Finished May 07 01:12:07 PM PDT 24
Peak memory 195320 kb
Host smart-3945ce0a-f056-4481-83ea-8884a1867305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155569698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2155569698
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1253375168
Short name T188
Test name
Test status
Simulation time 1678487064 ps
CPU time 19.26 seconds
Started May 07 01:12:20 PM PDT 24
Finished May 07 01:12:40 PM PDT 24
Peak memory 215328 kb
Host smart-3e3adf69-9345-4691-beb1-ad845f57c70d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253375168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1253375168
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.114945238
Short name T371
Test name
Test status
Simulation time 2309336775 ps
CPU time 17.5 seconds
Started May 07 01:12:26 PM PDT 24
Finished May 07 01:12:44 PM PDT 24
Peak memory 200044 kb
Host smart-62bce712-0ebb-470e-aaeb-da5717ba1844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114945238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.114945238
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3358075225
Short name T208
Test name
Test status
Simulation time 370089741 ps
CPU time 20.77 seconds
Started May 07 01:12:18 PM PDT 24
Finished May 07 01:12:40 PM PDT 24
Peak memory 199932 kb
Host smart-c35ca629-bffa-47a7-b139-2d5e5a2843a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358075225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3358075225
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_long_msg.187331492
Short name T347
Test name
Test status
Simulation time 25868853683 ps
CPU time 69.25 seconds
Started May 07 01:11:50 PM PDT 24
Finished May 07 01:13:00 PM PDT 24
Peak memory 200044 kb
Host smart-aaa3179d-8f01-4742-b16b-720ff2a84868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187331492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.187331492
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1544684642
Short name T152
Test name
Test status
Simulation time 606935569 ps
CPU time 6.61 seconds
Started May 07 01:12:04 PM PDT 24
Finished May 07 01:12:12 PM PDT 24
Peak memory 200016 kb
Host smart-c7a48b4c-e0fc-4c78-b5ad-b4b292c46323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544684642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1544684642
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.451428880
Short name T448
Test name
Test status
Simulation time 33547878 ps
CPU time 1.22 seconds
Started May 07 01:11:56 PM PDT 24
Finished May 07 01:11:58 PM PDT 24
Peak memory 199780 kb
Host smart-e00c6293-b677-4b1a-b2ec-c703d2dee869
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451428880 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.451428880
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.65729349
Short name T73
Test name
Test status
Simulation time 104883803040 ps
CPU time 461.39 seconds
Started May 07 01:12:24 PM PDT 24
Finished May 07 01:20:07 PM PDT 24
Peak memory 200064 kb
Host smart-a1e3c3c5-710d-41d4-9f13-6d6fc02f5b82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65729349 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.65729349
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_alert_test.203021725
Short name T324
Test name
Test status
Simulation time 26080788 ps
CPU time 0.57 seconds
Started May 07 01:12:37 PM PDT 24
Finished May 07 01:12:38 PM PDT 24
Peak memory 194504 kb
Host smart-333f075c-b919-425a-ae7f-5cf4bf14b04f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203021725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.203021725
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1299697875
Short name T242
Test name
Test status
Simulation time 386307765 ps
CPU time 4.53 seconds
Started May 07 01:12:27 PM PDT 24
Finished May 07 01:12:33 PM PDT 24
Peak memory 216316 kb
Host smart-0ab9d29d-f5af-4e6d-a02d-390ee0b3cd64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299697875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1299697875
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3245305313
Short name T290
Test name
Test status
Simulation time 26702981751 ps
CPU time 36.47 seconds
Started May 07 01:11:57 PM PDT 24
Finished May 07 01:12:35 PM PDT 24
Peak memory 200040 kb
Host smart-9e9acf53-8fe0-4564-b669-8d18361c6ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245305313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3245305313
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3433983293
Short name T91
Test name
Test status
Simulation time 1735186383 ps
CPU time 24.7 seconds
Started May 07 01:12:15 PM PDT 24
Finished May 07 01:12:40 PM PDT 24
Peak memory 199968 kb
Host smart-5bd51b91-4c17-48cb-a3ae-44338a7d00db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433983293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3433983293
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1346573993
Short name T404
Test name
Test status
Simulation time 3677602000 ps
CPU time 69.2 seconds
Started May 07 01:12:18 PM PDT 24
Finished May 07 01:13:29 PM PDT 24
Peak memory 200044 kb
Host smart-003203cb-b4c8-4e0c-8c94-9f2ffd909699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346573993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1346573993
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.995716432
Short name T281
Test name
Test status
Simulation time 728448561 ps
CPU time 2.56 seconds
Started May 07 01:12:25 PM PDT 24
Finished May 07 01:12:28 PM PDT 24
Peak memory 199868 kb
Host smart-c8d57656-04ff-44b1-b372-06ceb0c3dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995716432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.995716432
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2356295910
Short name T234
Test name
Test status
Simulation time 509325351 ps
CPU time 1.1 seconds
Started May 07 01:12:18 PM PDT 24
Finished May 07 01:12:20 PM PDT 24
Peak memory 200024 kb
Host smart-094d4fa3-f916-4ccc-8613-456ea0f4f9d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356295910 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2356295910
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3117947658
Short name T266
Test name
Test status
Simulation time 101630947086 ps
CPU time 450.59 seconds
Started May 07 01:12:31 PM PDT 24
Finished May 07 01:20:03 PM PDT 24
Peak memory 200016 kb
Host smart-e3d7bc82-ec4c-465d-a3e6-45edb89005ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117947658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3117947658
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1143554973
Short name T175
Test name
Test status
Simulation time 32171217 ps
CPU time 0.58 seconds
Started May 07 01:10:25 PM PDT 24
Finished May 07 01:10:27 PM PDT 24
Peak memory 195620 kb
Host smart-cd84c608-6253-40c4-bb3e-b2d2d8b4a506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143554973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1143554973
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.879388958
Short name T240
Test name
Test status
Simulation time 811034458 ps
CPU time 10.46 seconds
Started May 07 01:10:15 PM PDT 24
Finished May 07 01:10:26 PM PDT 24
Peak memory 208136 kb
Host smart-f39ccea4-1d03-468b-9ea8-26751c50cdc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879388958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.879388958
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3786029805
Short name T134
Test name
Test status
Simulation time 406519645 ps
CPU time 21.23 seconds
Started May 07 01:10:16 PM PDT 24
Finished May 07 01:10:39 PM PDT 24
Peak memory 199916 kb
Host smart-248a773f-cf36-4f78-80dc-2c8091f32bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786029805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3786029805
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3328640765
Short name T256
Test name
Test status
Simulation time 2149683659 ps
CPU time 118.36 seconds
Started May 07 01:10:15 PM PDT 24
Finished May 07 01:12:14 PM PDT 24
Peak memory 200048 kb
Host smart-bcc49a6d-563d-4105-9755-0f3db3073412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328640765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3328640765
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.4257468111
Short name T162
Test name
Test status
Simulation time 6562674487 ps
CPU time 85.47 seconds
Started May 07 01:10:15 PM PDT 24
Finished May 07 01:11:41 PM PDT 24
Peak memory 200044 kb
Host smart-eac25ac5-5fc8-43b3-bbbe-6701bc927c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257468111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.4257468111
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2492095446
Short name T23
Test name
Test status
Simulation time 104563914 ps
CPU time 1.01 seconds
Started May 07 01:10:25 PM PDT 24
Finished May 07 01:10:27 PM PDT 24
Peak memory 219200 kb
Host smart-8d463315-aa01-4961-afe5-0fab8178c3c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492095446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2492095446
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4281143360
Short name T166
Test name
Test status
Simulation time 1412391620 ps
CPU time 1.91 seconds
Started May 07 01:10:15 PM PDT 24
Finished May 07 01:10:18 PM PDT 24
Peak memory 199976 kb
Host smart-7fe8e391-0909-4946-b423-f1724046f917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281143360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4281143360
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.606728139
Short name T227
Test name
Test status
Simulation time 56617105 ps
CPU time 1.24 seconds
Started May 07 01:10:25 PM PDT 24
Finished May 07 01:10:28 PM PDT 24
Peak memory 199976 kb
Host smart-c47420bc-c555-404a-9bd2-16dcce15ac81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606728139 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.606728139
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2535998114
Short name T75
Test name
Test status
Simulation time 42160478 ps
CPU time 0.58 seconds
Started May 07 01:12:08 PM PDT 24
Finished May 07 01:12:09 PM PDT 24
Peak memory 195276 kb
Host smart-68a376fc-606c-40fd-a0aa-bcee78b268ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535998114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2535998114
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3364156225
Short name T231
Test name
Test status
Simulation time 3088169317 ps
CPU time 40.81 seconds
Started May 07 01:12:40 PM PDT 24
Finished May 07 01:13:22 PM PDT 24
Peak memory 216408 kb
Host smart-8cd4d862-d205-4149-9afe-d8b4f7999789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364156225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3364156225
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1559292246
Short name T429
Test name
Test status
Simulation time 1721152284 ps
CPU time 32.87 seconds
Started May 07 01:12:07 PM PDT 24
Finished May 07 01:12:41 PM PDT 24
Peak memory 199968 kb
Host smart-3aa0eb9f-3356-4833-bb75-0aa1f9f5d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559292246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1559292246
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.578116860
Short name T377
Test name
Test status
Simulation time 690198020 ps
CPU time 10.17 seconds
Started May 07 01:12:07 PM PDT 24
Finished May 07 01:12:18 PM PDT 24
Peak memory 199968 kb
Host smart-f534edd0-3434-4c32-a99b-1ddac8139f92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578116860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.578116860
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2205904284
Short name T391
Test name
Test status
Simulation time 2513630945 ps
CPU time 82.57 seconds
Started May 07 01:12:20 PM PDT 24
Finished May 07 01:13:44 PM PDT 24
Peak memory 200036 kb
Host smart-0f1d1911-4d76-4972-8770-a3197396b412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205904284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2205904284
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2849383845
Short name T346
Test name
Test status
Simulation time 537692750 ps
CPU time 4.44 seconds
Started May 07 01:12:20 PM PDT 24
Finished May 07 01:12:26 PM PDT 24
Peak memory 199976 kb
Host smart-0641a093-0018-4a15-b94c-243fbecdd160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849383845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2849383845
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.121703373
Short name T143
Test name
Test status
Simulation time 114720663 ps
CPU time 1.2 seconds
Started May 07 01:12:37 PM PDT 24
Finished May 07 01:12:39 PM PDT 24
Peak memory 200000 kb
Host smart-02231f93-3b60-4610-b66e-ef1f2f2e670e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121703373 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.121703373
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3242758158
Short name T174
Test name
Test status
Simulation time 205746224728 ps
CPU time 464.9 seconds
Started May 07 01:12:32 PM PDT 24
Finished May 07 01:20:18 PM PDT 24
Peak memory 200240 kb
Host smart-396a048b-598d-4a21-8487-86621e0e317e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242758158 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3242758158
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2342273174
Short name T205
Test name
Test status
Simulation time 61104318 ps
CPU time 0.56 seconds
Started May 07 01:12:26 PM PDT 24
Finished May 07 01:12:27 PM PDT 24
Peak memory 195576 kb
Host smart-17258cd8-e4c5-4119-bc50-08720debcfde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342273174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2342273174
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.896566135
Short name T87
Test name
Test status
Simulation time 2898407909 ps
CPU time 39.62 seconds
Started May 07 01:12:07 PM PDT 24
Finished May 07 01:12:48 PM PDT 24
Peak memory 228552 kb
Host smart-955ab1a4-c8f9-42e7-a4b4-ee7d6f87190e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896566135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.896566135
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3943011391
Short name T176
Test name
Test status
Simulation time 5841254859 ps
CPU time 53.96 seconds
Started May 07 01:12:39 PM PDT 24
Finished May 07 01:13:34 PM PDT 24
Peak memory 200072 kb
Host smart-0f9dd624-4a54-462c-a6d7-41ea478c6d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943011391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3943011391
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2189179501
Short name T157
Test name
Test status
Simulation time 3437028763 ps
CPU time 25.5 seconds
Started May 07 01:12:45 PM PDT 24
Finished May 07 01:13:11 PM PDT 24
Peak memory 200036 kb
Host smart-a5d09af1-b2ab-4aac-87d6-d1510b16c3ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189179501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2189179501
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1309599125
Short name T114
Test name
Test status
Simulation time 1434170390 ps
CPU time 7.33 seconds
Started May 07 01:12:32 PM PDT 24
Finished May 07 01:12:40 PM PDT 24
Peak memory 199996 kb
Host smart-23bfe281-4e5a-4c07-b819-3cfad3f03e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309599125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1309599125
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2565493101
Short name T393
Test name
Test status
Simulation time 1760096128 ps
CPU time 6.49 seconds
Started May 07 01:12:33 PM PDT 24
Finished May 07 01:12:40 PM PDT 24
Peak memory 200000 kb
Host smart-8f727d4a-073b-4563-a041-bbb1c9ca5745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565493101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2565493101
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3396953487
Short name T294
Test name
Test status
Simulation time 113966818 ps
CPU time 1.26 seconds
Started May 07 01:12:44 PM PDT 24
Finished May 07 01:12:46 PM PDT 24
Peak memory 199952 kb
Host smart-8b89e29c-7397-40e0-a79e-18d2534bf620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396953487 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3396953487
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.179491451
Short name T314
Test name
Test status
Simulation time 154302695820 ps
CPU time 486.35 seconds
Started May 07 01:12:45 PM PDT 24
Finished May 07 01:20:52 PM PDT 24
Peak memory 200008 kb
Host smart-054e7f11-0bb7-4043-a3ff-9d3506eac300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179491451 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.179491451
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.305986719
Short name T249
Test name
Test status
Simulation time 10908323 ps
CPU time 0.56 seconds
Started May 07 01:12:29 PM PDT 24
Finished May 07 01:12:31 PM PDT 24
Peak memory 195332 kb
Host smart-387d6e91-5ddd-4581-adff-b3d31ac8659c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305986719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.305986719
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2724384757
Short name T18
Test name
Test status
Simulation time 960265968 ps
CPU time 49.29 seconds
Started May 07 01:12:36 PM PDT 24
Finished May 07 01:13:27 PM PDT 24
Peak memory 216308 kb
Host smart-d21d015b-0ff1-4ed1-8cd8-9c80626d8e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724384757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2724384757
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4120858846
Short name T146
Test name
Test status
Simulation time 345041074 ps
CPU time 7.08 seconds
Started May 07 01:12:30 PM PDT 24
Finished May 07 01:12:38 PM PDT 24
Peak memory 199968 kb
Host smart-54efbaba-20bc-4aff-8fc7-6fff7ebdb0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120858846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4120858846
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2775420688
Short name T220
Test name
Test status
Simulation time 3353267377 ps
CPU time 149.99 seconds
Started May 07 01:12:48 PM PDT 24
Finished May 07 01:15:20 PM PDT 24
Peak memory 200244 kb
Host smart-3815f0ed-de48-412b-b61d-c8a331ee0ca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775420688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2775420688
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_smoke.1599986239
Short name T252
Test name
Test status
Simulation time 136672361 ps
CPU time 2.51 seconds
Started May 07 01:12:41 PM PDT 24
Finished May 07 01:12:44 PM PDT 24
Peak memory 199968 kb
Host smart-8d0e2821-6fb5-4eaa-9735-9cbab9d32cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599986239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1599986239
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1706649867
Short name T384
Test name
Test status
Simulation time 100973705 ps
CPU time 0.93 seconds
Started May 07 01:12:20 PM PDT 24
Finished May 07 01:12:22 PM PDT 24
Peak memory 198836 kb
Host smart-e92c9257-bbc9-4e48-9d2a-8f43f2a35c29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706649867 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1706649867
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.911025274
Short name T145
Test name
Test status
Simulation time 146235198781 ps
CPU time 517.33 seconds
Started May 07 01:12:30 PM PDT 24
Finished May 07 01:21:09 PM PDT 24
Peak memory 200032 kb
Host smart-e244680a-43f8-4829-b40b-0b88e2a9768d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911025274 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.911025274
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.179530001
Short name T3
Test name
Test status
Simulation time 43029731 ps
CPU time 0.61 seconds
Started May 07 01:12:40 PM PDT 24
Finished May 07 01:12:42 PM PDT 24
Peak memory 195616 kb
Host smart-ec9600c0-3984-4062-a7df-4bb41faa8f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179530001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.179530001
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.34235090
Short name T55
Test name
Test status
Simulation time 619153981 ps
CPU time 35.43 seconds
Started May 07 01:12:44 PM PDT 24
Finished May 07 01:13:21 PM PDT 24
Peak memory 229264 kb
Host smart-455d1b03-ea51-4c14-af79-5c5b528921e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34235090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.34235090
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1657171311
Short name T323
Test name
Test status
Simulation time 318133561 ps
CPU time 8.38 seconds
Started May 07 01:12:19 PM PDT 24
Finished May 07 01:12:28 PM PDT 24
Peak memory 199940 kb
Host smart-0c9c347a-a0b9-4dcf-99af-ce1129b1c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657171311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1657171311
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1757924274
Short name T159
Test name
Test status
Simulation time 940773284 ps
CPU time 28.92 seconds
Started May 07 01:12:14 PM PDT 24
Finished May 07 01:12:44 PM PDT 24
Peak memory 199952 kb
Host smart-a18c9f8c-ad66-4825-9e6c-370cf6fb3c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757924274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1757924274
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3611060908
Short name T438
Test name
Test status
Simulation time 7631258795 ps
CPU time 108.71 seconds
Started May 07 01:12:17 PM PDT 24
Finished May 07 01:14:06 PM PDT 24
Peak memory 200072 kb
Host smart-03aa135e-9c15-4691-8ea5-8bdf8f63ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611060908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3611060908
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3720462705
Short name T284
Test name
Test status
Simulation time 446333175 ps
CPU time 5.25 seconds
Started May 07 01:12:39 PM PDT 24
Finished May 07 01:12:45 PM PDT 24
Peak memory 199976 kb
Host smart-093648ab-e992-488d-8e09-729ab254cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720462705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3720462705
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.662289445
Short name T237
Test name
Test status
Simulation time 156636783 ps
CPU time 1.06 seconds
Started May 07 01:12:14 PM PDT 24
Finished May 07 01:12:17 PM PDT 24
Peak memory 199452 kb
Host smart-43e961ff-b79f-484f-9c0a-97d65a20ad74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662289445 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.662289445
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.335320671
Short name T315
Test name
Test status
Simulation time 117104064760 ps
CPU time 497.4 seconds
Started May 07 01:12:29 PM PDT 24
Finished May 07 01:20:48 PM PDT 24
Peak memory 200032 kb
Host smart-5d017117-ba4b-4f9f-9da2-7841e0e00e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335320671 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.335320671
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2956139366
Short name T263
Test name
Test status
Simulation time 11692900 ps
CPU time 0.58 seconds
Started May 07 01:12:46 PM PDT 24
Finished May 07 01:12:48 PM PDT 24
Peak memory 195368 kb
Host smart-a2e7c916-8719-4d11-83a9-9f6fc4a07ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956139366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2956139366
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1945839703
Short name T12
Test name
Test status
Simulation time 2350065484 ps
CPU time 35.95 seconds
Started May 07 01:12:47 PM PDT 24
Finished May 07 01:13:25 PM PDT 24
Peak memory 226544 kb
Host smart-ede1fe83-bb81-4302-92ec-5f9b878a0690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945839703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1945839703
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3388536949
Short name T178
Test name
Test status
Simulation time 1274432615 ps
CPU time 12.44 seconds
Started May 07 01:12:26 PM PDT 24
Finished May 07 01:12:40 PM PDT 24
Peak memory 199952 kb
Host smart-0db77662-31dd-49c9-ba36-1b7c14649689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388536949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3388536949
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3610092222
Short name T230
Test name
Test status
Simulation time 556124368 ps
CPU time 33.63 seconds
Started May 07 01:12:50 PM PDT 24
Finished May 07 01:13:25 PM PDT 24
Peak memory 199904 kb
Host smart-9a9f66f6-94ac-4c35-9c03-d2010c2eb7da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610092222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3610092222
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_long_msg.363067678
Short name T300
Test name
Test status
Simulation time 2686754545 ps
CPU time 37.06 seconds
Started May 07 01:12:52 PM PDT 24
Finished May 07 01:13:30 PM PDT 24
Peak memory 200040 kb
Host smart-bb40cb70-462f-40db-ac12-038bfff800e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363067678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.363067678
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3791688464
Short name T318
Test name
Test status
Simulation time 1092928145 ps
CPU time 3.1 seconds
Started May 07 01:12:49 PM PDT 24
Finished May 07 01:12:53 PM PDT 24
Peak memory 199872 kb
Host smart-c68525fa-f1dd-4a0f-b90d-577de52b366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791688464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3791688464
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.4053633642
Short name T331
Test name
Test status
Simulation time 325021429 ps
CPU time 1.28 seconds
Started May 07 01:12:36 PM PDT 24
Finished May 07 01:12:38 PM PDT 24
Peak memory 199916 kb
Host smart-1e702c81-517e-40f9-ba12-672c98d7edf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053633642 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.4053633642
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.523469228
Short name T251
Test name
Test status
Simulation time 148751210877 ps
CPU time 470.7 seconds
Started May 07 01:12:48 PM PDT 24
Finished May 07 01:20:40 PM PDT 24
Peak memory 200064 kb
Host smart-9e9745da-792e-4851-8e5b-571f5ae621d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523469228 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.523469228
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_alert_test.791224817
Short name T34
Test name
Test status
Simulation time 63860810 ps
CPU time 0.59 seconds
Started May 07 01:12:26 PM PDT 24
Finished May 07 01:12:28 PM PDT 24
Peak memory 195572 kb
Host smart-207af7cf-8864-4959-bfd5-969bac9613bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791224817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.791224817
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3796483790
Short name T167
Test name
Test status
Simulation time 578472358 ps
CPU time 6.6 seconds
Started May 07 01:12:26 PM PDT 24
Finished May 07 01:12:34 PM PDT 24
Peak memory 199908 kb
Host smart-64fd7d96-ebec-43df-833d-c5ce7e7c885c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796483790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3796483790
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2555142316
Short name T357
Test name
Test status
Simulation time 3985081100 ps
CPU time 31.14 seconds
Started May 07 01:12:47 PM PDT 24
Finished May 07 01:13:19 PM PDT 24
Peak memory 200040 kb
Host smart-af8b9d28-21ab-4e8c-899e-7afc14f41d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555142316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2555142316
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1771827964
Short name T439
Test name
Test status
Simulation time 1646556147 ps
CPU time 62.75 seconds
Started May 07 01:12:55 PM PDT 24
Finished May 07 01:13:59 PM PDT 24
Peak memory 199952 kb
Host smart-22b9c20d-dcc8-4b8f-915e-3c16255c5cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771827964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1771827964
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3668308889
Short name T164
Test name
Test status
Simulation time 375169235 ps
CPU time 19.69 seconds
Started May 07 01:12:24 PM PDT 24
Finished May 07 01:12:45 PM PDT 24
Peak memory 200008 kb
Host smart-e0cc6275-770f-40dd-8c8a-8a5b6bace798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668308889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3668308889
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1823808882
Short name T213
Test name
Test status
Simulation time 361180523 ps
CPU time 5.57 seconds
Started May 07 01:12:52 PM PDT 24
Finished May 07 01:12:58 PM PDT 24
Peak memory 199996 kb
Host smart-b6f9597a-5aa1-4c6a-8123-928a4cc172c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823808882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1823808882
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2309920486
Short name T444
Test name
Test status
Simulation time 288463569 ps
CPU time 1.35 seconds
Started May 07 01:12:24 PM PDT 24
Finished May 07 01:12:26 PM PDT 24
Peak memory 199972 kb
Host smart-99325b8f-a80c-494a-a299-57255627e593
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309920486 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.2309920486
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.4012770217
Short name T207
Test name
Test status
Simulation time 183426713447 ps
CPU time 409.84 seconds
Started May 07 01:12:53 PM PDT 24
Finished May 07 01:19:43 PM PDT 24
Peak memory 200028 kb
Host smart-f992c32b-cdd2-493b-93e2-fa198b2f5693
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012770217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.4012770217
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3228145945
Short name T276
Test name
Test status
Simulation time 44809133 ps
CPU time 0.61 seconds
Started May 07 01:13:01 PM PDT 24
Finished May 07 01:13:03 PM PDT 24
Peak memory 195564 kb
Host smart-1284eadf-fba9-4702-a752-6b492729111f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228145945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3228145945
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2101729278
Short name T206
Test name
Test status
Simulation time 2613063029 ps
CPU time 34.79 seconds
Started May 07 01:13:05 PM PDT 24
Finished May 07 01:13:41 PM PDT 24
Peak memory 216324 kb
Host smart-f15437f3-90a4-41db-aede-eb7cf38f3fc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2101729278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2101729278
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.804725500
Short name T97
Test name
Test status
Simulation time 721125814 ps
CPU time 6.13 seconds
Started May 07 01:12:36 PM PDT 24
Finished May 07 01:12:43 PM PDT 24
Peak memory 199896 kb
Host smart-4ebfd754-78eb-4186-bb4d-d298add0992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804725500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.804725500
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3120472062
Short name T226
Test name
Test status
Simulation time 450031009 ps
CPU time 25.56 seconds
Started May 07 01:12:40 PM PDT 24
Finished May 07 01:13:06 PM PDT 24
Peak memory 199924 kb
Host smart-21cdf50c-dbcd-459d-8ff6-6744d4dd44be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120472062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3120472062
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2621265158
Short name T149
Test name
Test status
Simulation time 1380759177 ps
CPU time 7.62 seconds
Started May 07 01:12:35 PM PDT 24
Finished May 07 01:12:43 PM PDT 24
Peak memory 199564 kb
Host smart-c180d4b6-e293-4f4b-be45-18d4cb81689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621265158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2621265158
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1344935893
Short name T140
Test name
Test status
Simulation time 384045202 ps
CPU time 4.85 seconds
Started May 07 01:12:24 PM PDT 24
Finished May 07 01:12:30 PM PDT 24
Peak memory 199984 kb
Host smart-898b2389-234a-4223-a918-7a77ede271d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344935893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1344935893
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.4259104523
Short name T71
Test name
Test status
Simulation time 175322714 ps
CPU time 1.02 seconds
Started May 07 01:13:01 PM PDT 24
Finished May 07 01:13:02 PM PDT 24
Peak memory 199164 kb
Host smart-9e750c0c-95b6-4bf5-924c-7cdfa1c5b7c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259104523 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.4259104523
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2948345516
Short name T17
Test name
Test status
Simulation time 46706311468 ps
CPU time 413.88 seconds
Started May 07 01:12:34 PM PDT 24
Finished May 07 01:19:28 PM PDT 24
Peak memory 200016 kb
Host smart-aa0a1fc4-23b5-46fc-94bd-f47657de7821
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948345516 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.2948345516
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1905344731
Short name T171
Test name
Test status
Simulation time 11887129 ps
CPU time 0.59 seconds
Started May 07 01:12:40 PM PDT 24
Finished May 07 01:12:41 PM PDT 24
Peak memory 195444 kb
Host smart-f94f5c87-b400-423c-bf88-9f527fd367ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905344731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1905344731
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2088680672
Short name T193
Test name
Test status
Simulation time 1086253951 ps
CPU time 55.83 seconds
Started May 07 01:13:02 PM PDT 24
Finished May 07 01:13:59 PM PDT 24
Peak memory 230788 kb
Host smart-655e0024-390a-4018-8058-f6a2f37138e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088680672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2088680672
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2900139183
Short name T28
Test name
Test status
Simulation time 837004914 ps
CPU time 21.71 seconds
Started May 07 01:12:31 PM PDT 24
Finished May 07 01:12:53 PM PDT 24
Peak memory 199996 kb
Host smart-3dab3517-8456-4aee-9798-7c8fc448a6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900139183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2900139183
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1406817075
Short name T132
Test name
Test status
Simulation time 415450765 ps
CPU time 4.78 seconds
Started May 07 01:13:04 PM PDT 24
Finished May 07 01:13:10 PM PDT 24
Peak memory 199916 kb
Host smart-19bedda6-339a-46fe-b62a-138f6bcdd96f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406817075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1406817075
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1394348568
Short name T327
Test name
Test status
Simulation time 85477989712 ps
CPU time 131.42 seconds
Started May 07 01:12:33 PM PDT 24
Finished May 07 01:14:46 PM PDT 24
Peak memory 200008 kb
Host smart-8525545b-7677-4898-9e49-adb77d99254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394348568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1394348568
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3727683218
Short name T182
Test name
Test status
Simulation time 932829546 ps
CPU time 3.91 seconds
Started May 07 01:13:05 PM PDT 24
Finished May 07 01:13:10 PM PDT 24
Peak memory 200056 kb
Host smart-77403468-0c1e-4636-9e29-2634fca0d727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727683218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3727683218
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.102745321
Short name T180
Test name
Test status
Simulation time 119844332 ps
CPU time 1 seconds
Started May 07 01:12:31 PM PDT 24
Finished May 07 01:12:33 PM PDT 24
Peak memory 197964 kb
Host smart-9f02ff77-f484-4088-9074-60592e81732a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102745321 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.102745321
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.866815274
Short name T243
Test name
Test status
Simulation time 120090473661 ps
CPU time 540.54 seconds
Started May 07 01:13:05 PM PDT 24
Finished May 07 01:22:06 PM PDT 24
Peak memory 200112 kb
Host smart-b99d40c6-4855-4d55-a54e-33bf6039da2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866815274 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.866815274
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.169272571
Short name T341
Test name
Test status
Simulation time 14898753 ps
CPU time 0.6 seconds
Started May 07 01:12:46 PM PDT 24
Finished May 07 01:12:47 PM PDT 24
Peak memory 195616 kb
Host smart-7a908e65-de12-427d-a506-7ea9f51961b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169272571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.169272571
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3710314989
Short name T410
Test name
Test status
Simulation time 3798313052 ps
CPU time 43.95 seconds
Started May 07 01:12:37 PM PDT 24
Finished May 07 01:13:22 PM PDT 24
Peak memory 210816 kb
Host smart-5853cc87-cece-4c61-9208-ba15a9f86fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710314989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3710314989
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.414536798
Short name T461
Test name
Test status
Simulation time 1039643515 ps
CPU time 55.24 seconds
Started May 07 01:12:38 PM PDT 24
Finished May 07 01:13:34 PM PDT 24
Peak memory 199924 kb
Host smart-39908d73-5c10-4a20-9b90-23a6f2685aeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414536798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.414536798
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2405444041
Short name T100
Test name
Test status
Simulation time 284822413 ps
CPU time 7.46 seconds
Started May 07 01:13:06 PM PDT 24
Finished May 07 01:13:14 PM PDT 24
Peak memory 200020 kb
Host smart-b1b261e6-4448-4d10-a50f-2cc1b0800133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405444041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2405444041
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.4248491291
Short name T161
Test name
Test status
Simulation time 235526948 ps
CPU time 0.96 seconds
Started May 07 01:12:44 PM PDT 24
Finished May 07 01:12:46 PM PDT 24
Peak memory 199780 kb
Host smart-b95a2e79-6c86-45d0-94fa-762eb7fd8710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248491291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.4248491291
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3473215431
Short name T223
Test name
Test status
Simulation time 36046630 ps
CPU time 1.17 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:12:57 PM PDT 24
Peak memory 199932 kb
Host smart-ad086de7-41df-4187-bb25-ea0c44ae2c5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473215431 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3473215431
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3504809960
Short name T443
Test name
Test status
Simulation time 29660071157 ps
CPU time 390.32 seconds
Started May 07 01:13:06 PM PDT 24
Finished May 07 01:19:37 PM PDT 24
Peak memory 199964 kb
Host smart-32801258-eb74-4b9b-ac0b-9c2ac5630791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504809960 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3504809960
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2746548885
Short name T299
Test name
Test status
Simulation time 37556182 ps
CPU time 0.58 seconds
Started May 07 01:12:53 PM PDT 24
Finished May 07 01:12:55 PM PDT 24
Peak memory 194668 kb
Host smart-3fe10d33-7405-4139-891c-0e71cdd28404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746548885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2746548885
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1771375933
Short name T343
Test name
Test status
Simulation time 72328814 ps
CPU time 1.11 seconds
Started May 07 01:12:49 PM PDT 24
Finished May 07 01:12:51 PM PDT 24
Peak memory 199820 kb
Host smart-5401b0ce-086a-4bee-b466-45e6179feaaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771375933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1771375933
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.4288508380
Short name T212
Test name
Test status
Simulation time 955696136 ps
CPU time 3.73 seconds
Started May 07 01:12:46 PM PDT 24
Finished May 07 01:12:51 PM PDT 24
Peak memory 199856 kb
Host smart-2010f7ef-12f4-4670-9579-d09426493545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288508380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.4288508380
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1689883322
Short name T253
Test name
Test status
Simulation time 913720326 ps
CPU time 49.45 seconds
Started May 07 01:12:47 PM PDT 24
Finished May 07 01:13:38 PM PDT 24
Peak memory 199972 kb
Host smart-fc05adb9-81c6-427f-a6c1-2b47a60e881b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689883322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1689883322
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4062301429
Short name T399
Test name
Test status
Simulation time 3654112868 ps
CPU time 108.87 seconds
Started May 07 01:13:15 PM PDT 24
Finished May 07 01:15:04 PM PDT 24
Peak memory 200040 kb
Host smart-087153a3-6992-452c-a246-fff03f95e701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062301429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4062301429
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2079184174
Short name T173
Test name
Test status
Simulation time 165393743 ps
CPU time 1.87 seconds
Started May 07 01:12:47 PM PDT 24
Finished May 07 01:12:50 PM PDT 24
Peak memory 199940 kb
Host smart-50d5f950-4020-45af-b206-a2c518ee68fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079184174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2079184174
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2032888580
Short name T195
Test name
Test status
Simulation time 56628836 ps
CPU time 1.15 seconds
Started May 07 01:12:47 PM PDT 24
Finished May 07 01:12:49 PM PDT 24
Peak memory 200004 kb
Host smart-19304b0b-5ced-4e08-b0b9-8d8363656d0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032888580 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2032888580
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2780660543
Short name T425
Test name
Test status
Simulation time 132945007223 ps
CPU time 461.62 seconds
Started May 07 01:12:49 PM PDT 24
Finished May 07 01:20:32 PM PDT 24
Peak memory 200036 kb
Host smart-1dba122a-c6d8-440c-92b2-83c239257754
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780660543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2780660543
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2489379950
Short name T138
Test name
Test status
Simulation time 33217221 ps
CPU time 0.56 seconds
Started May 07 01:10:39 PM PDT 24
Finished May 07 01:10:41 PM PDT 24
Peak memory 195560 kb
Host smart-79f420f3-b99b-4afb-9822-79d1ff73d3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489379950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2489379950
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3904054655
Short name T275
Test name
Test status
Simulation time 1009281361 ps
CPU time 27.14 seconds
Started May 07 01:10:26 PM PDT 24
Finished May 07 01:10:54 PM PDT 24
Peak memory 226576 kb
Host smart-59b47dee-7f97-42bd-b26a-41f14bfb7fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904054655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3904054655
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3725117723
Short name T348
Test name
Test status
Simulation time 219481085 ps
CPU time 10.67 seconds
Started May 07 01:10:25 PM PDT 24
Finished May 07 01:10:37 PM PDT 24
Peak memory 199972 kb
Host smart-bf24e504-5fd4-4f83-b452-f6d9854d3706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725117723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3725117723
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2906021140
Short name T301
Test name
Test status
Simulation time 644615231 ps
CPU time 36.82 seconds
Started May 07 01:10:24 PM PDT 24
Finished May 07 01:11:02 PM PDT 24
Peak memory 199992 kb
Host smart-cdf72ccb-682d-4c7b-b467-576076ebcc52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906021140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2906021140
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2778278527
Short name T76
Test name
Test status
Simulation time 36511646080 ps
CPU time 74.36 seconds
Started May 07 01:10:24 PM PDT 24
Finished May 07 01:11:39 PM PDT 24
Peak memory 200060 kb
Host smart-abc695e3-3156-42a9-b6b9-3e9b14224d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778278527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2778278527
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1488516405
Short name T38
Test name
Test status
Simulation time 216666784 ps
CPU time 0.97 seconds
Started May 07 01:10:41 PM PDT 24
Finished May 07 01:10:43 PM PDT 24
Peak memory 218164 kb
Host smart-f8460c09-8e5c-42cc-9eb2-245b985c45ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488516405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1488516405
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3947783184
Short name T435
Test name
Test status
Simulation time 643053971 ps
CPU time 2.7 seconds
Started May 07 01:10:24 PM PDT 24
Finished May 07 01:10:27 PM PDT 24
Peak memory 199940 kb
Host smart-cc7a27c9-ffba-4487-9f30-429110bf5891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947783184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3947783184
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2455519730
Short name T42
Test name
Test status
Simulation time 33981684 ps
CPU time 1.17 seconds
Started May 07 01:10:35 PM PDT 24
Finished May 07 01:10:37 PM PDT 24
Peak memory 199960 kb
Host smart-3a03a19f-0d2c-440c-af41-0f4d4d398a8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455519730 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2455519730
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1341903744
Short name T403
Test name
Test status
Simulation time 274387710136 ps
CPU time 532.91 seconds
Started May 07 01:10:36 PM PDT 24
Finished May 07 01:19:29 PM PDT 24
Peak memory 200036 kb
Host smart-97c38a80-89ce-4b17-8643-e6a2da332773
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341903744 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1341903744
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1795598681
Short name T30
Test name
Test status
Simulation time 511280956 ps
CPU time 7.12 seconds
Started May 07 01:10:32 PM PDT 24
Finished May 07 01:10:40 PM PDT 24
Peak memory 199956 kb
Host smart-573b06f8-e94d-4dc5-8ac2-e6df2609c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795598681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1795598681
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2806812469
Short name T291
Test name
Test status
Simulation time 14186912 ps
CPU time 0.58 seconds
Started May 07 01:13:31 PM PDT 24
Finished May 07 01:13:33 PM PDT 24
Peak memory 195372 kb
Host smart-825ee7d7-9cc7-455a-a0d0-c78c044214d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806812469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2806812469
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.244898612
Short name T53
Test name
Test status
Simulation time 924193755 ps
CPU time 29.09 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:13:25 PM PDT 24
Peak memory 208128 kb
Host smart-ed955b7f-9d08-4072-9b50-cf8d704ae7a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244898612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.244898612
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3889931364
Short name T388
Test name
Test status
Simulation time 640975022 ps
CPU time 31.34 seconds
Started May 07 01:12:47 PM PDT 24
Finished May 07 01:13:19 PM PDT 24
Peak memory 199964 kb
Host smart-4b07ee4e-89ad-4db1-9797-8d4f75fa7004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889931364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3889931364
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4201678423
Short name T292
Test name
Test status
Simulation time 7367636447 ps
CPU time 97.29 seconds
Started May 07 01:12:51 PM PDT 24
Finished May 07 01:14:30 PM PDT 24
Peak memory 200012 kb
Host smart-042c7d0b-eb5b-42e6-aa85-548fe4a5e62c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201678423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4201678423
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1072166912
Short name T198
Test name
Test status
Simulation time 16958135 ps
CPU time 0.65 seconds
Started May 07 01:13:14 PM PDT 24
Finished May 07 01:13:15 PM PDT 24
Peak memory 196328 kb
Host smart-ac299baa-ce00-4147-b4ac-ba7ea490fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072166912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1072166912
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2102999254
Short name T221
Test name
Test status
Simulation time 812111255 ps
CPU time 3.54 seconds
Started May 07 01:12:46 PM PDT 24
Finished May 07 01:12:50 PM PDT 24
Peak memory 199960 kb
Host smart-5479ab40-bb26-403e-bd63-250ab1e8b687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102999254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2102999254
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2150230749
Short name T312
Test name
Test status
Simulation time 46697398 ps
CPU time 1.02 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:12:56 PM PDT 24
Peak memory 199104 kb
Host smart-6ed46b81-a8d9-482e-86e1-f708f21404bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150230749 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2150230749
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3444614431
Short name T420
Test name
Test status
Simulation time 26943729309 ps
CPU time 380.06 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:19:15 PM PDT 24
Peak memory 199976 kb
Host smart-93780509-f11d-4efe-92f3-55d86feac32e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444614431 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3444614431
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2126327317
Short name T32
Test name
Test status
Simulation time 714226594 ps
CPU time 10.13 seconds
Started May 07 01:12:53 PM PDT 24
Finished May 07 01:13:04 PM PDT 24
Peak memory 199844 kb
Host smart-6076a078-ef7e-4bf8-b08f-5bb1a95cd2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126327317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2126327317
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.268984352
Short name T70
Test name
Test status
Simulation time 17629705 ps
CPU time 0.56 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:12:56 PM PDT 24
Peak memory 194672 kb
Host smart-ba505dcc-5ace-4fe0-85b8-41b94da9593c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268984352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.268984352
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2038490505
Short name T450
Test name
Test status
Simulation time 4499997895 ps
CPU time 44.22 seconds
Started May 07 01:13:32 PM PDT 24
Finished May 07 01:14:17 PM PDT 24
Peak memory 212268 kb
Host smart-9baea441-03c8-4b98-9f3c-7c0fd6b52c07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038490505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2038490505
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3094483598
Short name T268
Test name
Test status
Simulation time 7523024700 ps
CPU time 44.14 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:13:39 PM PDT 24
Peak memory 200040 kb
Host smart-e60316a5-c09b-499c-a93d-95580db3db13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094483598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3094483598
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2722071789
Short name T325
Test name
Test status
Simulation time 25818698368 ps
CPU time 109.18 seconds
Started May 07 01:13:31 PM PDT 24
Finished May 07 01:15:21 PM PDT 24
Peak memory 200004 kb
Host smart-76b8f263-6b2b-4c7a-b3ff-eb0fed1e2c7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722071789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2722071789
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.589223626
Short name T328
Test name
Test status
Simulation time 5276950964 ps
CPU time 97.14 seconds
Started May 07 01:12:52 PM PDT 24
Finished May 07 01:14:30 PM PDT 24
Peak memory 200040 kb
Host smart-e6a0399d-e27e-42b5-8d06-23754cae266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589223626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.589223626
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2715984658
Short name T364
Test name
Test status
Simulation time 1399637045 ps
CPU time 6.49 seconds
Started May 07 01:12:53 PM PDT 24
Finished May 07 01:13:01 PM PDT 24
Peak memory 199952 kb
Host smart-b423f8e2-a7d6-43ba-9910-b5f364241805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715984658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2715984658
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3779740949
Short name T5
Test name
Test status
Simulation time 23421684100 ps
CPU time 103.59 seconds
Started May 07 01:12:53 PM PDT 24
Finished May 07 01:14:38 PM PDT 24
Peak memory 199972 kb
Host smart-269bab59-b966-446c-8f09-dcc0b20dbf13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779740949 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3779740949
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2992497793
Short name T306
Test name
Test status
Simulation time 145005747 ps
CPU time 1.07 seconds
Started May 07 01:13:27 PM PDT 24
Finished May 07 01:13:28 PM PDT 24
Peak memory 199916 kb
Host smart-096cb410-9fa3-4cb5-98df-d445cf27693f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992497793 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2992497793
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3938824790
Short name T94
Test name
Test status
Simulation time 17647992529 ps
CPU time 469.63 seconds
Started May 07 01:13:36 PM PDT 24
Finished May 07 01:21:27 PM PDT 24
Peak memory 200048 kb
Host smart-a00adaf6-000b-4329-9dab-aa50ed7463ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938824790 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3938824790
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2466285444
Short name T277
Test name
Test status
Simulation time 28033296 ps
CPU time 0.61 seconds
Started May 07 01:13:03 PM PDT 24
Finished May 07 01:13:04 PM PDT 24
Peak memory 195672 kb
Host smart-f376d2ea-f819-43a5-9592-855a91349724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466285444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2466285444
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2620405221
Short name T271
Test name
Test status
Simulation time 390629266 ps
CPU time 18.42 seconds
Started May 07 01:12:52 PM PDT 24
Finished May 07 01:13:11 PM PDT 24
Peak memory 208156 kb
Host smart-bea43155-61ba-442f-9128-0d4ddc827d62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2620405221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2620405221
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1716030169
Short name T446
Test name
Test status
Simulation time 1695802905 ps
CPU time 41.59 seconds
Started May 07 01:12:53 PM PDT 24
Finished May 07 01:13:36 PM PDT 24
Peak memory 199984 kb
Host smart-615cd489-3d2e-46bb-a023-2db7f64cc5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716030169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1716030169
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2286076596
Short name T304
Test name
Test status
Simulation time 8147744608 ps
CPU time 106.97 seconds
Started May 07 01:12:55 PM PDT 24
Finished May 07 01:14:43 PM PDT 24
Peak memory 200072 kb
Host smart-ec1e01e8-6e51-4bb1-88bd-e73756116cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286076596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2286076596
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_smoke.1254587838
Short name T158
Test name
Test status
Simulation time 449145661 ps
CPU time 3.04 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:12:58 PM PDT 24
Peak memory 199944 kb
Host smart-277384c6-f5fb-409f-acc2-f53b9f6d8281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254587838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1254587838
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3311715842
Short name T22
Test name
Test status
Simulation time 627424711 ps
CPU time 1.27 seconds
Started May 07 01:13:30 PM PDT 24
Finished May 07 01:13:32 PM PDT 24
Peak memory 199980 kb
Host smart-6821a5ca-4182-4af9-b64b-c5db9e8e3993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311715842 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3311715842
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2340520693
Short name T286
Test name
Test status
Simulation time 14369322254 ps
CPU time 380.51 seconds
Started May 07 01:12:54 PM PDT 24
Finished May 07 01:19:16 PM PDT 24
Peak memory 200048 kb
Host smart-d89d4e53-de25-4cf0-a221-98d722f1ddec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340520693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2340520693
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1061703523
Short name T382
Test name
Test status
Simulation time 23318046 ps
CPU time 0.56 seconds
Started May 07 01:13:30 PM PDT 24
Finished May 07 01:13:32 PM PDT 24
Peak memory 195688 kb
Host smart-b9dd6c18-c320-4c0e-b854-5258f57c1a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061703523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1061703523
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2782884226
Short name T52
Test name
Test status
Simulation time 7941702649 ps
CPU time 44.39 seconds
Started May 07 01:13:14 PM PDT 24
Finished May 07 01:13:59 PM PDT 24
Peak memory 216260 kb
Host smart-7addf888-8ab4-409d-a9f1-9e7fbdd2b485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782884226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2782884226
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2302082876
Short name T335
Test name
Test status
Simulation time 1904762279 ps
CPU time 34.02 seconds
Started May 07 01:13:02 PM PDT 24
Finished May 07 01:13:37 PM PDT 24
Peak memory 200008 kb
Host smart-9393222b-402c-4626-aa76-2bfd743af5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302082876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2302082876
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1774730756
Short name T381
Test name
Test status
Simulation time 133522980 ps
CPU time 7.17 seconds
Started May 07 01:13:02 PM PDT 24
Finished May 07 01:13:10 PM PDT 24
Peak memory 199928 kb
Host smart-0aecc99a-a24f-46bc-ba11-478ae8bcc14f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774730756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1774730756
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2737366039
Short name T441
Test name
Test status
Simulation time 11401895001 ps
CPU time 39.24 seconds
Started May 07 01:13:01 PM PDT 24
Finished May 07 01:13:41 PM PDT 24
Peak memory 200052 kb
Host smart-d02ec28c-535e-4aae-b508-d754fef264f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737366039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2737366039
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2645952882
Short name T172
Test name
Test status
Simulation time 78660259 ps
CPU time 1.28 seconds
Started May 07 01:13:03 PM PDT 24
Finished May 07 01:13:05 PM PDT 24
Peak memory 199960 kb
Host smart-563fcf8e-625b-4874-ab00-451da030f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645952882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2645952882
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.197201114
Short name T273
Test name
Test status
Simulation time 148527232 ps
CPU time 1.31 seconds
Started May 07 01:13:03 PM PDT 24
Finished May 07 01:13:05 PM PDT 24
Peak memory 199856 kb
Host smart-86ef212f-1f5a-4348-973c-eab73bf6627c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197201114 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.197201114
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3293604485
Short name T288
Test name
Test status
Simulation time 121397484732 ps
CPU time 504.79 seconds
Started May 07 01:13:02 PM PDT 24
Finished May 07 01:21:28 PM PDT 24
Peak memory 200008 kb
Host smart-89cd8344-2d8b-4fc0-9bd7-5237a1ee34da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293604485 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3293604485
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.139251344
Short name T2
Test name
Test status
Simulation time 11768439 ps
CPU time 0.58 seconds
Started May 07 01:13:07 PM PDT 24
Finished May 07 01:13:09 PM PDT 24
Peak memory 195608 kb
Host smart-95cf3637-32db-421c-8325-3ead7ef508dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139251344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.139251344
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1461994754
Short name T428
Test name
Test status
Simulation time 3691920559 ps
CPU time 8.68 seconds
Started May 07 01:13:08 PM PDT 24
Finished May 07 01:13:17 PM PDT 24
Peak memory 199996 kb
Host smart-93ea5fa4-8771-4428-989b-2e81ddec855e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461994754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1461994754
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.662629951
Short name T442
Test name
Test status
Simulation time 270868658 ps
CPU time 14.45 seconds
Started May 07 01:13:08 PM PDT 24
Finished May 07 01:13:24 PM PDT 24
Peak memory 199984 kb
Host smart-2838fe08-2582-4918-9e4f-778991fde4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662629951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.662629951
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1467742005
Short name T41
Test name
Test status
Simulation time 1004805386 ps
CPU time 57.71 seconds
Started May 07 01:13:14 PM PDT 24
Finished May 07 01:14:12 PM PDT 24
Peak memory 199960 kb
Host smart-45af45ff-0fd4-45bb-8adc-0d0812ca4b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467742005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1467742005
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.486053620
Short name T305
Test name
Test status
Simulation time 3654645073 ps
CPU time 107.32 seconds
Started May 07 01:13:39 PM PDT 24
Finished May 07 01:15:27 PM PDT 24
Peak memory 200080 kb
Host smart-43296f32-8137-4c33-b4ad-b76c2e63f0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486053620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.486053620
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3789838614
Short name T432
Test name
Test status
Simulation time 202622210 ps
CPU time 3.29 seconds
Started May 07 01:13:07 PM PDT 24
Finished May 07 01:13:11 PM PDT 24
Peak memory 199984 kb
Host smart-5ca3ef95-58f4-4664-84c5-a45e6759a3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789838614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3789838614
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.243134113
Short name T46
Test name
Test status
Simulation time 54893034 ps
CPU time 1.22 seconds
Started May 07 01:13:09 PM PDT 24
Finished May 07 01:13:11 PM PDT 24
Peak memory 200008 kb
Host smart-96ce1d8f-9df6-4808-8e59-473f96d2d407
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243134113 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.243134113
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2706748710
Short name T272
Test name
Test status
Simulation time 36688915371 ps
CPU time 470.83 seconds
Started May 07 01:13:07 PM PDT 24
Finished May 07 01:20:59 PM PDT 24
Peak memory 200036 kb
Host smart-26644907-67b3-42a8-8e0b-3e68b569d66a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706748710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2706748710
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2678341845
Short name T264
Test name
Test status
Simulation time 34504490 ps
CPU time 0.57 seconds
Started May 07 01:13:38 PM PDT 24
Finished May 07 01:13:39 PM PDT 24
Peak memory 195596 kb
Host smart-53a80125-28c8-4ce3-aeb5-5c40afdedd66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678341845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2678341845
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3118843650
Short name T380
Test name
Test status
Simulation time 1682505073 ps
CPU time 43.23 seconds
Started May 07 01:13:08 PM PDT 24
Finished May 07 01:13:52 PM PDT 24
Peak memory 199912 kb
Host smart-61c58ff2-38aa-4ed7-8ef4-560d9c213064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3118843650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3118843650
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3871612270
Short name T392
Test name
Test status
Simulation time 7432203271 ps
CPU time 22.97 seconds
Started May 07 01:13:26 PM PDT 24
Finished May 07 01:13:50 PM PDT 24
Peak memory 200028 kb
Host smart-26aa8389-5d63-4da2-8097-a4c77bc54556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871612270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3871612270
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1524500295
Short name T10
Test name
Test status
Simulation time 3251928448 ps
CPU time 90.78 seconds
Started May 07 01:13:09 PM PDT 24
Finished May 07 01:14:40 PM PDT 24
Peak memory 200012 kb
Host smart-101c5b44-ea57-4a41-ae5c-04106c8e6771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524500295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1524500295
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2625150958
Short name T355
Test name
Test status
Simulation time 29557851003 ps
CPU time 103.22 seconds
Started May 07 01:13:40 PM PDT 24
Finished May 07 01:15:24 PM PDT 24
Peak memory 200048 kb
Host smart-e60c2acd-1fe8-4c1b-91bb-a7f15a84a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625150958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2625150958
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2966882070
Short name T416
Test name
Test status
Simulation time 3234271027 ps
CPU time 4.79 seconds
Started May 07 01:13:40 PM PDT 24
Finished May 07 01:13:46 PM PDT 24
Peak memory 200040 kb
Host smart-3ef97a2e-abc5-4828-819c-ee919e5747fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966882070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2966882070
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2574897704
Short name T232
Test name
Test status
Simulation time 410929769 ps
CPU time 0.95 seconds
Started May 07 01:13:12 PM PDT 24
Finished May 07 01:13:13 PM PDT 24
Peak memory 199124 kb
Host smart-825e7536-0ad6-4fc6-9291-49f4ab9246b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574897704 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2574897704
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.4219331994
Short name T445
Test name
Test status
Simulation time 36816386452 ps
CPU time 473.14 seconds
Started May 07 01:13:07 PM PDT 24
Finished May 07 01:21:02 PM PDT 24
Peak memory 200056 kb
Host smart-51537bb2-b1cb-4d18-957e-77d874c43775
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219331994 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.4219331994
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1655131945
Short name T407
Test name
Test status
Simulation time 27127686 ps
CPU time 0.55 seconds
Started May 07 01:13:15 PM PDT 24
Finished May 07 01:13:16 PM PDT 24
Peak memory 195572 kb
Host smart-867e85a8-0780-4dad-8f5f-01fe7285b5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655131945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1655131945
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1710062906
Short name T456
Test name
Test status
Simulation time 4433142673 ps
CPU time 59.18 seconds
Started May 07 01:13:08 PM PDT 24
Finished May 07 01:14:08 PM PDT 24
Peak memory 232800 kb
Host smart-0fcf2348-295b-4c57-ac15-bd5e1eedf444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710062906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1710062906
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1667172300
Short name T282
Test name
Test status
Simulation time 5447881621 ps
CPU time 21.41 seconds
Started May 07 01:13:18 PM PDT 24
Finished May 07 01:13:40 PM PDT 24
Peak memory 200008 kb
Host smart-f68cecfb-c659-49be-accc-21552968f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667172300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1667172300
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2066042662
Short name T202
Test name
Test status
Simulation time 5306742585 ps
CPU time 68.47 seconds
Started May 07 01:13:19 PM PDT 24
Finished May 07 01:14:28 PM PDT 24
Peak memory 199976 kb
Host smart-55120fae-c3b8-4ab9-bd51-3076ab415a74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066042662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2066042662
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2858816929
Short name T389
Test name
Test status
Simulation time 6786883440 ps
CPU time 130.88 seconds
Started May 07 01:13:08 PM PDT 24
Finished May 07 01:15:20 PM PDT 24
Peak memory 200000 kb
Host smart-ae4bc30a-5ee8-4620-9db1-7a284d9fd4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858816929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2858816929
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3674974252
Short name T116
Test name
Test status
Simulation time 295280898 ps
CPU time 3.85 seconds
Started May 07 01:13:31 PM PDT 24
Finished May 07 01:13:36 PM PDT 24
Peak memory 199944 kb
Host smart-823aa7fa-9272-4e95-87ac-ad8a66b8d500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674974252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3674974252
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.155826357
Short name T376
Test name
Test status
Simulation time 4518576152 ps
CPU time 49.03 seconds
Started May 07 01:13:17 PM PDT 24
Finished May 07 01:14:07 PM PDT 24
Peak memory 232756 kb
Host smart-9f3acd3e-c2a0-4a6b-a2d8-ac239400d9c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155826357 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.155826357
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3820191956
Short name T462
Test name
Test status
Simulation time 58025081 ps
CPU time 1.21 seconds
Started May 07 01:13:15 PM PDT 24
Finished May 07 01:13:16 PM PDT 24
Peak memory 199984 kb
Host smart-6ee356c7-915c-4542-816b-0bcc41093c81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820191956 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3820191956
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1768569265
Short name T363
Test name
Test status
Simulation time 114501647092 ps
CPU time 488.75 seconds
Started May 07 01:13:17 PM PDT 24
Finished May 07 01:21:26 PM PDT 24
Peak memory 200024 kb
Host smart-43b921f4-c036-47ce-9e56-cde405681656
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768569265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1768569265
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.180842823
Short name T415
Test name
Test status
Simulation time 12450645 ps
CPU time 0.56 seconds
Started May 07 01:13:19 PM PDT 24
Finished May 07 01:13:20 PM PDT 24
Peak memory 195360 kb
Host smart-083c42b0-643b-4fdc-a1ed-7ceffa38f0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180842823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.180842823
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1701075162
Short name T313
Test name
Test status
Simulation time 350330364 ps
CPU time 17.74 seconds
Started May 07 01:13:46 PM PDT 24
Finished May 07 01:14:04 PM PDT 24
Peak memory 224420 kb
Host smart-0e945a8e-53d2-4204-a724-11e1959edc8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701075162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1701075162
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1949884222
Short name T128
Test name
Test status
Simulation time 2256041831 ps
CPU time 29.78 seconds
Started May 07 01:13:18 PM PDT 24
Finished May 07 01:13:48 PM PDT 24
Peak memory 200004 kb
Host smart-9d6744ef-eae6-4b36-be0d-258e79d095a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949884222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1949884222
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1452399862
Short name T430
Test name
Test status
Simulation time 5629198111 ps
CPU time 77.13 seconds
Started May 07 01:13:17 PM PDT 24
Finished May 07 01:14:35 PM PDT 24
Peak memory 200008 kb
Host smart-280d29bd-bf31-4105-b4da-697fd79e3ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452399862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1452399862
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1743307469
Short name T14
Test name
Test status
Simulation time 1167512976 ps
CPU time 20.14 seconds
Started May 07 01:13:15 PM PDT 24
Finished May 07 01:13:36 PM PDT 24
Peak memory 199904 kb
Host smart-3647784e-db9c-40e1-928e-e77bbd01fe7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743307469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1743307469
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3131867374
Short name T293
Test name
Test status
Simulation time 1740416779 ps
CPU time 17.38 seconds
Started May 07 01:13:19 PM PDT 24
Finished May 07 01:13:37 PM PDT 24
Peak memory 199936 kb
Host smart-6cb4255c-bbd1-4029-b987-0a34ea412b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131867374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3131867374
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.279879048
Short name T203
Test name
Test status
Simulation time 79790549 ps
CPU time 2.73 seconds
Started May 07 01:13:20 PM PDT 24
Finished May 07 01:13:24 PM PDT 24
Peak memory 199964 kb
Host smart-c8b2dd70-a6f2-4321-951d-a090c68efcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279879048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.279879048
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2021642670
Short name T452
Test name
Test status
Simulation time 5637524209 ps
CPU time 7.5 seconds
Started May 07 01:13:17 PM PDT 24
Finished May 07 01:13:25 PM PDT 24
Peak memory 200012 kb
Host smart-fec3f0be-739a-47fd-a1c9-7a918580983c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021642670 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2021642670
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2813314044
Short name T190
Test name
Test status
Simulation time 52122102 ps
CPU time 1.24 seconds
Started May 07 01:13:17 PM PDT 24
Finished May 07 01:13:18 PM PDT 24
Peak memory 199992 kb
Host smart-ce39d15a-e5fb-408a-876d-3c1196d737f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813314044 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2813314044
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1031459998
Short name T317
Test name
Test status
Simulation time 66232453404 ps
CPU time 491.21 seconds
Started May 07 01:13:15 PM PDT 24
Finished May 07 01:21:27 PM PDT 24
Peak memory 200048 kb
Host smart-e5fa027f-7b97-4292-a99e-a46ccfc96d88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031459998 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1031459998
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3482064550
Short name T437
Test name
Test status
Simulation time 42986729 ps
CPU time 0.59 seconds
Started May 07 01:13:27 PM PDT 24
Finished May 07 01:13:28 PM PDT 24
Peak memory 195696 kb
Host smart-74acf600-88ed-4538-bd49-0cd121499011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482064550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3482064550
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2139200384
Short name T361
Test name
Test status
Simulation time 816488486 ps
CPU time 47.34 seconds
Started May 07 01:13:18 PM PDT 24
Finished May 07 01:14:06 PM PDT 24
Peak memory 232120 kb
Host smart-bf3f1dbd-cc32-46af-b676-04a812cfa865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139200384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2139200384
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.433844287
Short name T191
Test name
Test status
Simulation time 522130015 ps
CPU time 1.77 seconds
Started May 07 01:13:28 PM PDT 24
Finished May 07 01:13:30 PM PDT 24
Peak memory 199908 kb
Host smart-03040eed-ff74-4a1d-87cd-058a8eabd559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433844287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.433844287
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1450698438
Short name T218
Test name
Test status
Simulation time 1833034781 ps
CPU time 107.6 seconds
Started May 07 01:13:26 PM PDT 24
Finished May 07 01:15:14 PM PDT 24
Peak memory 199988 kb
Host smart-475f063d-5bd0-4d1b-a6e5-b70431c6b4e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450698438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1450698438
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2420848183
Short name T344
Test name
Test status
Simulation time 11219599588 ps
CPU time 38.65 seconds
Started May 07 01:13:15 PM PDT 24
Finished May 07 01:13:55 PM PDT 24
Peak memory 200044 kb
Host smart-5d34f3df-76d8-41a7-a408-d568c699fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420848183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2420848183
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.195901939
Short name T360
Test name
Test status
Simulation time 3981917661 ps
CPU time 6.75 seconds
Started May 07 01:13:18 PM PDT 24
Finished May 07 01:13:25 PM PDT 24
Peak memory 200000 kb
Host smart-34613055-03b4-404b-a398-f7520b42bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195901939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.195901939
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3850862125
Short name T398
Test name
Test status
Simulation time 218498725 ps
CPU time 1.18 seconds
Started May 07 01:13:26 PM PDT 24
Finished May 07 01:13:28 PM PDT 24
Peak memory 200096 kb
Host smart-b0cf4c6d-ed0f-4f5f-a294-b46c34d2049d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850862125 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3850862125
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1136056569
Short name T345
Test name
Test status
Simulation time 105443330177 ps
CPU time 443.85 seconds
Started May 07 01:13:25 PM PDT 24
Finished May 07 01:20:50 PM PDT 24
Peak memory 200032 kb
Host smart-6c303da9-5e5f-4b0f-a34f-7788ccb41c5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136056569 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1136056569
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1906257372
Short name T31
Test name
Test status
Simulation time 116066216 ps
CPU time 6.47 seconds
Started May 07 01:13:26 PM PDT 24
Finished May 07 01:13:33 PM PDT 24
Peak memory 199864 kb
Host smart-623459d9-67c3-4c0c-9630-af3f06a1de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906257372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1906257372
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4111232269
Short name T137
Test name
Test status
Simulation time 13982094 ps
CPU time 0.59 seconds
Started May 07 01:13:25 PM PDT 24
Finished May 07 01:13:26 PM PDT 24
Peak memory 195596 kb
Host smart-b122613c-728a-4c92-90cc-1d95a6822aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111232269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4111232269
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1074664767
Short name T394
Test name
Test status
Simulation time 1428726837 ps
CPU time 17.61 seconds
Started May 07 01:13:25 PM PDT 24
Finished May 07 01:13:43 PM PDT 24
Peak memory 216088 kb
Host smart-61c7b259-f494-4e97-8ffd-380528947217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074664767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1074664767
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3376710252
Short name T353
Test name
Test status
Simulation time 7026472503 ps
CPU time 23.7 seconds
Started May 07 01:13:24 PM PDT 24
Finished May 07 01:13:49 PM PDT 24
Peak memory 199984 kb
Host smart-aff54be7-4946-4070-95ae-ad4b58e61044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376710252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3376710252
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1097251492
Short name T43
Test name
Test status
Simulation time 1223151452 ps
CPU time 17.29 seconds
Started May 07 01:13:26 PM PDT 24
Finished May 07 01:13:44 PM PDT 24
Peak memory 199924 kb
Host smart-4bca4b9a-42a4-48dc-a431-59ee72962627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097251492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1097251492
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3914389823
Short name T406
Test name
Test status
Simulation time 8917584094 ps
CPU time 14.46 seconds
Started May 07 01:13:26 PM PDT 24
Finished May 07 01:13:41 PM PDT 24
Peak memory 200028 kb
Host smart-e418b4db-6fd7-455d-bec8-1ed3ca91b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914389823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3914389823
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1061443793
Short name T90
Test name
Test status
Simulation time 563803690 ps
CPU time 6.73 seconds
Started May 07 01:13:25 PM PDT 24
Finished May 07 01:13:32 PM PDT 24
Peak memory 199964 kb
Host smart-435f3c41-cfa7-41f7-b857-3208334e045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061443793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1061443793
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.98431100
Short name T370
Test name
Test status
Simulation time 57655771 ps
CPU time 1.18 seconds
Started May 07 01:13:28 PM PDT 24
Finished May 07 01:13:30 PM PDT 24
Peak memory 199884 kb
Host smart-3c959b5b-1ca1-4dff-a478-fc3c266b0268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98431100 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_test_hmac_vectors.98431100
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.360663478
Short name T336
Test name
Test status
Simulation time 8009837673 ps
CPU time 435.9 seconds
Started May 07 01:13:26 PM PDT 24
Finished May 07 01:20:43 PM PDT 24
Peak memory 200036 kb
Host smart-70370bfe-32eb-4256-9850-120ffb63339f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360663478 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.360663478
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3357437026
Short name T250
Test name
Test status
Simulation time 28335263 ps
CPU time 0.56 seconds
Started May 07 01:10:50 PM PDT 24
Finished May 07 01:10:51 PM PDT 24
Peak memory 194604 kb
Host smart-14f0106c-c816-4052-8bce-9c1976c286f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357437026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3357437026
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3896496827
Short name T454
Test name
Test status
Simulation time 1098340134 ps
CPU time 28.43 seconds
Started May 07 01:10:40 PM PDT 24
Finished May 07 01:11:09 PM PDT 24
Peak memory 223548 kb
Host smart-e525f55b-66ff-49a5-8a2f-1ee6264bc603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896496827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3896496827
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1216255165
Short name T74
Test name
Test status
Simulation time 514484449 ps
CPU time 10.13 seconds
Started May 07 01:10:41 PM PDT 24
Finished May 07 01:10:52 PM PDT 24
Peak memory 199808 kb
Host smart-735a61e1-08ec-4469-964f-c10642677d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216255165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1216255165
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1559125490
Short name T431
Test name
Test status
Simulation time 723446606 ps
CPU time 20.27 seconds
Started May 07 01:10:40 PM PDT 24
Finished May 07 01:11:01 PM PDT 24
Peak memory 199956 kb
Host smart-53c033ca-7060-4d9a-b4c3-718c3a9f15de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559125490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1559125490
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1699244848
Short name T396
Test name
Test status
Simulation time 2772982345 ps
CPU time 36.68 seconds
Started May 07 01:10:39 PM PDT 24
Finished May 07 01:11:17 PM PDT 24
Peak memory 199948 kb
Host smart-c582917e-6000-4c12-bd2e-06fdb8f63009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699244848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1699244848
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2819821944
Short name T37
Test name
Test status
Simulation time 95150494 ps
CPU time 1.02 seconds
Started May 07 01:10:51 PM PDT 24
Finished May 07 01:10:52 PM PDT 24
Peak memory 219184 kb
Host smart-0ff43f1c-ccf1-4671-8226-c1525d741a49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819821944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2819821944
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1112972375
Short name T225
Test name
Test status
Simulation time 375627051 ps
CPU time 5.81 seconds
Started May 07 01:10:39 PM PDT 24
Finished May 07 01:10:46 PM PDT 24
Peak memory 199964 kb
Host smart-53f0116c-27ad-43ac-8f13-6f978421168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112972375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1112972375
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2085732276
Short name T422
Test name
Test status
Simulation time 225643120 ps
CPU time 1.29 seconds
Started May 07 01:10:46 PM PDT 24
Finished May 07 01:10:48 PM PDT 24
Peak memory 199988 kb
Host smart-a5b92eaa-4316-42a0-ae91-3e02f054129c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085732276 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2085732276
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3930237646
Short name T184
Test name
Test status
Simulation time 52541390549 ps
CPU time 481.91 seconds
Started May 07 01:10:48 PM PDT 24
Finished May 07 01:18:50 PM PDT 24
Peak memory 200036 kb
Host smart-1b2dd76f-f5c5-4644-bd37-9a2baf99abdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930237646 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3930237646
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.281904078
Short name T433
Test name
Test status
Simulation time 14275483 ps
CPU time 0.66 seconds
Started May 07 01:13:35 PM PDT 24
Finished May 07 01:13:37 PM PDT 24
Peak memory 195636 kb
Host smart-1ab76dbd-382d-47a9-ab86-74b2ae6597ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281904078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.281904078
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.391727326
Short name T338
Test name
Test status
Simulation time 88690238 ps
CPU time 2.86 seconds
Started May 07 01:13:31 PM PDT 24
Finished May 07 01:13:35 PM PDT 24
Peak memory 216024 kb
Host smart-4e70ac46-c231-48c7-8766-38ccea3d1954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391727326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.391727326
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.62771024
Short name T112
Test name
Test status
Simulation time 7565857846 ps
CPU time 25.75 seconds
Started May 07 01:13:33 PM PDT 24
Finished May 07 01:14:00 PM PDT 24
Peak memory 200020 kb
Host smart-6d24508c-e366-4440-b2ac-5da3e6b8cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62771024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.62771024
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3964976431
Short name T165
Test name
Test status
Simulation time 1674117777 ps
CPU time 101.66 seconds
Started May 07 01:13:33 PM PDT 24
Finished May 07 01:15:15 PM PDT 24
Peak memory 199912 kb
Host smart-771f3f11-44f7-48d4-9f21-0e55a2f22ec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964976431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3964976431
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1201304996
Short name T400
Test name
Test status
Simulation time 1600255194 ps
CPU time 86.8 seconds
Started May 07 01:13:34 PM PDT 24
Finished May 07 01:15:02 PM PDT 24
Peak memory 199852 kb
Host smart-5411b640-a7d4-4765-a0ac-9f7ce5ceb6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201304996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1201304996
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2284378224
Short name T447
Test name
Test status
Simulation time 25614315 ps
CPU time 1.07 seconds
Started May 07 01:13:25 PM PDT 24
Finished May 07 01:13:26 PM PDT 24
Peak memory 199944 kb
Host smart-7513515a-0b1c-45c1-bc8f-0dbc8bc4f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284378224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2284378224
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.380933125
Short name T426
Test name
Test status
Simulation time 147382607 ps
CPU time 1.04 seconds
Started May 07 01:13:32 PM PDT 24
Finished May 07 01:13:34 PM PDT 24
Peak memory 198104 kb
Host smart-22724c31-a630-4f1f-a3fa-57b8b82c1b7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380933125 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.380933125
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3498617124
Short name T463
Test name
Test status
Simulation time 23487063530 ps
CPU time 414.07 seconds
Started May 07 01:13:32 PM PDT 24
Finished May 07 01:20:27 PM PDT 24
Peak memory 200024 kb
Host smart-30edc6ad-b06f-4bf0-9b5c-6bc7d6437f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498617124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3498617124
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1483504653
Short name T93
Test name
Test status
Simulation time 30089254 ps
CPU time 0.57 seconds
Started May 07 01:13:46 PM PDT 24
Finished May 07 01:13:47 PM PDT 24
Peak memory 195556 kb
Host smart-1f8e9a3c-5709-4f66-800a-ac1d018eee52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483504653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1483504653
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4245233108
Short name T181
Test name
Test status
Simulation time 2644121884 ps
CPU time 34.65 seconds
Started May 07 01:13:33 PM PDT 24
Finished May 07 01:14:08 PM PDT 24
Peak memory 208192 kb
Host smart-3c0d9c46-b83c-46c7-8a01-6313567de974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245233108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4245233108
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.115272579
Short name T261
Test name
Test status
Simulation time 694858306 ps
CPU time 9.12 seconds
Started May 07 01:13:35 PM PDT 24
Finished May 07 01:13:45 PM PDT 24
Peak memory 199948 kb
Host smart-f50dda3c-5e72-49e2-b37d-5095caf0bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115272579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.115272579
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.74362156
Short name T196
Test name
Test status
Simulation time 81187773 ps
CPU time 4.12 seconds
Started May 07 01:13:33 PM PDT 24
Finished May 07 01:13:38 PM PDT 24
Peak memory 199980 kb
Host smart-a39c4bfa-229d-4e33-b6f6-5b434352f882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74362156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.74362156
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2180150614
Short name T139
Test name
Test status
Simulation time 68073056 ps
CPU time 0.72 seconds
Started May 07 01:13:36 PM PDT 24
Finished May 07 01:13:38 PM PDT 24
Peak memory 196144 kb
Host smart-e385dbd1-353c-42e6-9bab-54113a61b2fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180150614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2180150614
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2918772258
Short name T254
Test name
Test status
Simulation time 494144940 ps
CPU time 7.5 seconds
Started May 07 01:13:34 PM PDT 24
Finished May 07 01:13:42 PM PDT 24
Peak memory 199988 kb
Host smart-610e99b1-1029-417c-ad67-e96eb8b362b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918772258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2918772258
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1157061100
Short name T385
Test name
Test status
Simulation time 352193714 ps
CPU time 4.36 seconds
Started May 07 01:13:34 PM PDT 24
Finished May 07 01:13:39 PM PDT 24
Peak memory 199968 kb
Host smart-a8e5e636-2546-49ab-9a64-fcbbf2dc1f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157061100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1157061100
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.4248542556
Short name T326
Test name
Test status
Simulation time 146070969 ps
CPU time 1.33 seconds
Started May 07 01:13:33 PM PDT 24
Finished May 07 01:13:36 PM PDT 24
Peak memory 199996 kb
Host smart-ddedf804-3f22-4e71-adcb-7bdb0d9bbf75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248542556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.4248542556
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1315060911
Short name T409
Test name
Test status
Simulation time 156319129520 ps
CPU time 442.27 seconds
Started May 07 01:13:33 PM PDT 24
Finished May 07 01:20:57 PM PDT 24
Peak memory 199984 kb
Host smart-17349a3e-0de6-4542-ae8f-4350f1300808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315060911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1315060911
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_alert_test.459480611
Short name T258
Test name
Test status
Simulation time 14562621 ps
CPU time 0.63 seconds
Started May 07 01:13:41 PM PDT 24
Finished May 07 01:13:42 PM PDT 24
Peak memory 195640 kb
Host smart-5ab42990-5dc4-4d6a-9c23-524ae24df3ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459480611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.459480611
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2162673552
Short name T54
Test name
Test status
Simulation time 7101932564 ps
CPU time 42.42 seconds
Started May 07 01:13:35 PM PDT 24
Finished May 07 01:14:18 PM PDT 24
Peak memory 222580 kb
Host smart-13e1ec5d-0455-4526-bdfb-e861a15ae1e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162673552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2162673552
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2688999949
Short name T368
Test name
Test status
Simulation time 3883946348 ps
CPU time 13.75 seconds
Started May 07 01:13:35 PM PDT 24
Finished May 07 01:13:50 PM PDT 24
Peak memory 199992 kb
Host smart-c67f23ae-9a7f-4070-baa3-5297637304b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688999949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2688999949
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2728765037
Short name T99
Test name
Test status
Simulation time 5615426552 ps
CPU time 62.47 seconds
Started May 07 01:13:34 PM PDT 24
Finished May 07 01:14:37 PM PDT 24
Peak memory 200028 kb
Host smart-b97a8481-9697-4f31-ae89-4b32f05c7b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728765037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2728765037
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.682374963
Short name T217
Test name
Test status
Simulation time 1289556513 ps
CPU time 17.67 seconds
Started May 07 01:13:32 PM PDT 24
Finished May 07 01:13:50 PM PDT 24
Peak memory 199928 kb
Host smart-5000580a-74fb-440f-b94f-ec89c6332902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682374963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.682374963
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4122434521
Short name T270
Test name
Test status
Simulation time 199297622 ps
CPU time 3.4 seconds
Started May 07 01:13:36 PM PDT 24
Finished May 07 01:13:40 PM PDT 24
Peak memory 200008 kb
Host smart-d751cf3d-7e49-462a-82ce-995dd438f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122434521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4122434521
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.837092277
Short name T373
Test name
Test status
Simulation time 88799089 ps
CPU time 1.07 seconds
Started May 07 01:13:40 PM PDT 24
Finished May 07 01:13:42 PM PDT 24
Peak memory 199392 kb
Host smart-51659687-8069-458c-9788-15c373b84fec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837092277 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.837092277
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3877357609
Short name T337
Test name
Test status
Simulation time 37773440900 ps
CPU time 466.09 seconds
Started May 07 01:13:41 PM PDT 24
Finished May 07 01:21:27 PM PDT 24
Peak memory 199988 kb
Host smart-43d988e8-7933-42b5-873e-3a4d4f5ce02f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877357609 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3877357609
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1740809223
Short name T48
Test name
Test status
Simulation time 30747075 ps
CPU time 0.56 seconds
Started May 07 01:13:46 PM PDT 24
Finished May 07 01:13:47 PM PDT 24
Peak memory 194668 kb
Host smart-358ab192-45a6-4a41-909e-db015121b1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740809223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1740809223
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1376994579
Short name T189
Test name
Test status
Simulation time 937951332 ps
CPU time 50.42 seconds
Started May 07 01:13:42 PM PDT 24
Finished May 07 01:14:33 PM PDT 24
Peak memory 225536 kb
Host smart-8e79d026-d64b-47ef-8b97-bc6363532bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376994579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1376994579
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1365794939
Short name T118
Test name
Test status
Simulation time 1091663202 ps
CPU time 55.31 seconds
Started May 07 01:13:40 PM PDT 24
Finished May 07 01:14:37 PM PDT 24
Peak memory 199996 kb
Host smart-c519e304-3ed7-4b38-9ede-4fa86dcb171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365794939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1365794939
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.362264979
Short name T459
Test name
Test status
Simulation time 1299667049 ps
CPU time 73.62 seconds
Started May 07 01:13:41 PM PDT 24
Finished May 07 01:14:56 PM PDT 24
Peak memory 199992 kb
Host smart-7eda0bd5-aa95-4b27-8f34-c69bdbe69cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362264979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.362264979
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3778312057
Short name T222
Test name
Test status
Simulation time 618170698 ps
CPU time 12.8 seconds
Started May 07 01:13:43 PM PDT 24
Finished May 07 01:13:57 PM PDT 24
Peak memory 199972 kb
Host smart-90c015eb-b9ab-4e1b-8075-ac77a21716f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778312057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3778312057
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2655139480
Short name T464
Test name
Test status
Simulation time 293557004 ps
CPU time 4.55 seconds
Started May 07 01:13:42 PM PDT 24
Finished May 07 01:13:47 PM PDT 24
Peak memory 199996 kb
Host smart-979fe61a-72f5-43eb-8972-593379ebfd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655139480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2655139480
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.377904336
Short name T369
Test name
Test status
Simulation time 86124012 ps
CPU time 1.01 seconds
Started May 07 01:13:42 PM PDT 24
Finished May 07 01:13:44 PM PDT 24
Peak memory 198384 kb
Host smart-65c382ae-2953-48d8-856e-c9c2a4745de6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377904336 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.377904336
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3114153893
Short name T246
Test name
Test status
Simulation time 109226858063 ps
CPU time 491.09 seconds
Started May 07 01:13:42 PM PDT 24
Finished May 07 01:21:54 PM PDT 24
Peak memory 200036 kb
Host smart-720b675f-6de3-416f-bc9b-cfd3208d2331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114153893 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3114153893
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2214137680
Short name T378
Test name
Test status
Simulation time 35011258 ps
CPU time 0.62 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:13:51 PM PDT 24
Peak memory 195456 kb
Host smart-3d569d1f-3185-48e4-8ab5-648f38b15cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214137680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2214137680
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3772885128
Short name T88
Test name
Test status
Simulation time 715053256 ps
CPU time 42.64 seconds
Started May 07 01:13:39 PM PDT 24
Finished May 07 01:14:23 PM PDT 24
Peak memory 232692 kb
Host smart-fceedd29-6b3e-42dc-9225-b8015c2b6868
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772885128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3772885128
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1775903909
Short name T295
Test name
Test status
Simulation time 1398608380 ps
CPU time 28.23 seconds
Started May 07 01:13:42 PM PDT 24
Finished May 07 01:14:11 PM PDT 24
Peak memory 199960 kb
Host smart-a4ef9477-e2b9-4031-a7d4-4df5e236ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775903909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1775903909
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3689027165
Short name T332
Test name
Test status
Simulation time 657027149 ps
CPU time 37.39 seconds
Started May 07 01:13:42 PM PDT 24
Finished May 07 01:14:21 PM PDT 24
Peak memory 199968 kb
Host smart-c5e92810-4119-4106-b8ba-e0e6a3304256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689027165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3689027165
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3622959867
Short name T308
Test name
Test status
Simulation time 3281466065 ps
CPU time 48.17 seconds
Started May 07 01:13:40 PM PDT 24
Finished May 07 01:14:29 PM PDT 24
Peak memory 200012 kb
Host smart-ce7407a6-3023-43c6-8036-e7b67d9bc7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622959867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3622959867
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2520365906
Short name T148
Test name
Test status
Simulation time 1038666351 ps
CPU time 4.41 seconds
Started May 07 01:13:43 PM PDT 24
Finished May 07 01:13:48 PM PDT 24
Peak memory 199980 kb
Host smart-64870021-6529-4595-95cb-e307d46dffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520365906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2520365906
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1910878318
Short name T40
Test name
Test status
Simulation time 669812124 ps
CPU time 1.31 seconds
Started May 07 01:14:11 PM PDT 24
Finished May 07 01:14:13 PM PDT 24
Peak memory 199920 kb
Host smart-c158c3a3-acac-404a-8080-8a1a859f77f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910878318 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1910878318
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1290388543
Short name T316
Test name
Test status
Simulation time 27927919084 ps
CPU time 402.31 seconds
Started May 07 01:13:48 PM PDT 24
Finished May 07 01:20:32 PM PDT 24
Peak memory 200024 kb
Host smart-a298c58a-ca1a-448f-98d5-94cc440e6398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290388543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1290388543
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3494510257
Short name T197
Test name
Test status
Simulation time 32361830 ps
CPU time 0.58 seconds
Started May 07 01:13:50 PM PDT 24
Finished May 07 01:13:51 PM PDT 24
Peak memory 195012 kb
Host smart-75712506-9bf8-4d9f-b1dc-adeb82f1878c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494510257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3494510257
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1552920284
Short name T45
Test name
Test status
Simulation time 153959482 ps
CPU time 6.93 seconds
Started May 07 01:13:51 PM PDT 24
Finished May 07 01:13:58 PM PDT 24
Peak memory 199964 kb
Host smart-f5a12cd5-e49f-4de6-a6ad-8fe64137d682
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552920284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1552920284
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.256801460
Short name T408
Test name
Test status
Simulation time 1206866005 ps
CPU time 24.57 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:14:15 PM PDT 24
Peak memory 199948 kb
Host smart-bb7d661b-02cb-4329-880c-92bcb463ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256801460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.256801460
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3764813503
Short name T358
Test name
Test status
Simulation time 11996362755 ps
CPU time 136.43 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:16:06 PM PDT 24
Peak memory 200028 kb
Host smart-56cd3059-cfaa-4c59-bec6-7b9311e23b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764813503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3764813503
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2820548945
Short name T236
Test name
Test status
Simulation time 21859257850 ps
CPU time 64.88 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:14:55 PM PDT 24
Peak memory 200000 kb
Host smart-0f2f869b-edb5-4b29-9e62-db019b4c8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820548945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2820548945
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1698365212
Short name T309
Test name
Test status
Simulation time 598970016 ps
CPU time 5.99 seconds
Started May 07 01:13:46 PM PDT 24
Finished May 07 01:13:53 PM PDT 24
Peak memory 199980 kb
Host smart-baaf72dd-1399-4e20-a746-e429ebe114f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698365212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1698365212
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.206693686
Short name T453
Test name
Test status
Simulation time 174612743 ps
CPU time 1.08 seconds
Started May 07 01:13:47 PM PDT 24
Finished May 07 01:13:49 PM PDT 24
Peak memory 199720 kb
Host smart-5b0bd24f-c50e-44db-b616-800cdf102833
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206693686 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.206693686
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2932901814
Short name T150
Test name
Test status
Simulation time 51728898882 ps
CPU time 450.32 seconds
Started May 07 01:13:50 PM PDT 24
Finished May 07 01:21:21 PM PDT 24
Peak memory 200040 kb
Host smart-df16e150-f23f-4b10-b7c4-d70305d2a639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932901814 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.2932901814
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.706706042
Short name T352
Test name
Test status
Simulation time 24112222 ps
CPU time 0.61 seconds
Started May 07 01:13:54 PM PDT 24
Finished May 07 01:13:56 PM PDT 24
Peak memory 195224 kb
Host smart-b9c5fbfc-cee2-475b-be5e-67442c30ab9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706706042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.706706042
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.57566597
Short name T311
Test name
Test status
Simulation time 1417526648 ps
CPU time 18.6 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:14:08 PM PDT 24
Peak memory 216072 kb
Host smart-e8f163a9-82c5-4be9-abbd-039982dda99d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57566597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.57566597
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.83182701
Short name T13
Test name
Test status
Simulation time 1474912159 ps
CPU time 30.06 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:14:20 PM PDT 24
Peak memory 199936 kb
Host smart-ad9c7b86-782c-451a-af5b-082da7da022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83182701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.83182701
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3916090785
Short name T257
Test name
Test status
Simulation time 741816211 ps
CPU time 39.97 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:14:30 PM PDT 24
Peak memory 199840 kb
Host smart-be376d1f-c595-4efb-8f13-55b9360c3e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916090785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3916090785
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.273018103
Short name T390
Test name
Test status
Simulation time 2129215792 ps
CPU time 63.23 seconds
Started May 07 01:13:50 PM PDT 24
Finished May 07 01:14:54 PM PDT 24
Peak memory 200032 kb
Host smart-3c034aeb-b671-42a6-b617-61a05dbf2295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273018103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.273018103
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3991829532
Short name T351
Test name
Test status
Simulation time 522061810 ps
CPU time 6.23 seconds
Started May 07 01:13:49 PM PDT 24
Finished May 07 01:13:56 PM PDT 24
Peak memory 199956 kb
Host smart-26140b83-e8af-4c0e-9ada-fbc3cdde7aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991829532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3991829532
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1702183577
Short name T401
Test name
Test status
Simulation time 32674233 ps
CPU time 1.14 seconds
Started May 07 01:13:50 PM PDT 24
Finished May 07 01:13:52 PM PDT 24
Peak memory 199776 kb
Host smart-bc9da614-2482-4a4f-8380-ab3804f1d435
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702183577 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1702183577
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2718577247
Short name T130
Test name
Test status
Simulation time 7798297212 ps
CPU time 416.28 seconds
Started May 07 01:13:47 PM PDT 24
Finished May 07 01:20:44 PM PDT 24
Peak memory 200048 kb
Host smart-12bdef3a-7039-48b4-83f9-09474083af56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718577247 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2718577247
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3468054569
Short name T405
Test name
Test status
Simulation time 43780083 ps
CPU time 0.62 seconds
Started May 07 01:13:56 PM PDT 24
Finished May 07 01:13:57 PM PDT 24
Peak memory 195556 kb
Host smart-c3e31e95-3cc6-4e0d-ab14-d8488567c7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468054569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3468054569
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1068886411
Short name T321
Test name
Test status
Simulation time 3443790711 ps
CPU time 35.87 seconds
Started May 07 01:13:56 PM PDT 24
Finished May 07 01:14:32 PM PDT 24
Peak memory 217416 kb
Host smart-408e684a-d384-4e85-8fd1-b924d3c01bad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068886411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1068886411
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.157532631
Short name T411
Test name
Test status
Simulation time 1604064930 ps
CPU time 22.76 seconds
Started May 07 01:13:56 PM PDT 24
Finished May 07 01:14:20 PM PDT 24
Peak memory 199928 kb
Host smart-c3e860e9-dc73-4af8-b02d-0eb55a7eb2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157532631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.157532631
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2146421697
Short name T133
Test name
Test status
Simulation time 6470147233 ps
CPU time 87.6 seconds
Started May 07 01:14:11 PM PDT 24
Finished May 07 01:15:40 PM PDT 24
Peak memory 200020 kb
Host smart-cfd1b5f4-d0ed-4d0c-b522-2641c6a1dea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146421697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2146421697
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3066736225
Short name T329
Test name
Test status
Simulation time 4278282983 ps
CPU time 60.88 seconds
Started May 07 01:13:56 PM PDT 24
Finished May 07 01:14:58 PM PDT 24
Peak memory 200084 kb
Host smart-45c3705c-8ba5-4c60-ad23-7d7aeca59ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066736225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3066736225
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1325858037
Short name T185
Test name
Test status
Simulation time 443924147 ps
CPU time 5.02 seconds
Started May 07 01:13:56 PM PDT 24
Finished May 07 01:14:01 PM PDT 24
Peak memory 200040 kb
Host smart-11308a52-4abc-47c9-9a61-11dccc7c55c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325858037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1325858037
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.478833181
Short name T423
Test name
Test status
Simulation time 4486058722 ps
CPU time 17.94 seconds
Started May 07 01:13:56 PM PDT 24
Finished May 07 01:14:15 PM PDT 24
Peak memory 200008 kb
Host smart-dbb5a308-07e2-4b82-bfda-5002359113a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478833181 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.478833181
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.612613055
Short name T245
Test name
Test status
Simulation time 179687097 ps
CPU time 0.98 seconds
Started May 07 01:13:54 PM PDT 24
Finished May 07 01:13:55 PM PDT 24
Peak memory 199316 kb
Host smart-2a461278-e51d-4601-8fc0-ec57eebb8ed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612613055 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.612613055
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1070725802
Short name T209
Test name
Test status
Simulation time 121562267463 ps
CPU time 501.56 seconds
Started May 07 01:13:57 PM PDT 24
Finished May 07 01:22:19 PM PDT 24
Peak memory 200052 kb
Host smart-d06423df-dd80-49aa-9e31-6690a473c202
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070725802 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1070725802
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4170794587
Short name T89
Test name
Test status
Simulation time 12773521 ps
CPU time 0.59 seconds
Started May 07 01:14:02 PM PDT 24
Finished May 07 01:14:03 PM PDT 24
Peak memory 195372 kb
Host smart-e331d43e-34b9-45ed-ba40-3461c3930619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170794587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4170794587
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3918179932
Short name T418
Test name
Test status
Simulation time 1032209051 ps
CPU time 50.97 seconds
Started May 07 01:13:58 PM PDT 24
Finished May 07 01:14:50 PM PDT 24
Peak memory 217236 kb
Host smart-65d4bbaa-ea7b-48c0-b2a3-f118abcc25d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918179932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3918179932
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3746037927
Short name T296
Test name
Test status
Simulation time 1207480270 ps
CPU time 22.34 seconds
Started May 07 01:13:54 PM PDT 24
Finished May 07 01:14:17 PM PDT 24
Peak memory 199972 kb
Host smart-436e3e8b-4445-41d5-aab5-24957429e964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746037927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3746037927
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.4063398511
Short name T135
Test name
Test status
Simulation time 11467317329 ps
CPU time 170.06 seconds
Started May 07 01:13:54 PM PDT 24
Finished May 07 01:16:45 PM PDT 24
Peak memory 200024 kb
Host smart-55a39b11-3950-4c4d-9f4c-4719b98fc567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063398511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.4063398511
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2502465066
Short name T113
Test name
Test status
Simulation time 7573881129 ps
CPU time 76.67 seconds
Started May 07 01:13:58 PM PDT 24
Finished May 07 01:15:16 PM PDT 24
Peak memory 199936 kb
Host smart-f00c3068-fbb9-4e1c-b523-623d9e29aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502465066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2502465066
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1440792903
Short name T339
Test name
Test status
Simulation time 368949021 ps
CPU time 3.41 seconds
Started May 07 01:13:54 PM PDT 24
Finished May 07 01:13:58 PM PDT 24
Peak memory 199900 kb
Host smart-d9d0d8c6-a07b-4eb4-9a5d-51798fee9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440792903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1440792903
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3386094911
Short name T285
Test name
Test status
Simulation time 114052816 ps
CPU time 1.18 seconds
Started May 07 01:13:58 PM PDT 24
Finished May 07 01:14:00 PM PDT 24
Peak memory 199980 kb
Host smart-f3f87d2d-89b9-4dbe-b7de-2ff3b4751fb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386094911 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3386094911
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3080213592
Short name T8
Test name
Test status
Simulation time 111510348457 ps
CPU time 462.75 seconds
Started May 07 01:13:55 PM PDT 24
Finished May 07 01:21:38 PM PDT 24
Peak memory 200064 kb
Host smart-fa1b4201-e691-4d15-b7fb-89c5dc029a0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080213592 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3080213592
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1185902028
Short name T72
Test name
Test status
Simulation time 139737485 ps
CPU time 0.61 seconds
Started May 07 01:14:02 PM PDT 24
Finished May 07 01:14:03 PM PDT 24
Peak memory 195552 kb
Host smart-c84eac72-2d45-47ba-8142-e568adced7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185902028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1185902028
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1679101966
Short name T117
Test name
Test status
Simulation time 15682827799 ps
CPU time 49.36 seconds
Started May 07 01:14:04 PM PDT 24
Finished May 07 01:14:54 PM PDT 24
Peak memory 216040 kb
Host smart-c0d89e5d-7de1-4690-a7bc-dea0f0ecdae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679101966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1679101966
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3688271372
Short name T56
Test name
Test status
Simulation time 3543526279 ps
CPU time 22.2 seconds
Started May 07 01:14:10 PM PDT 24
Finished May 07 01:14:33 PM PDT 24
Peak memory 200068 kb
Host smart-b81b97ca-43c4-40a7-869a-3168ba534f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688271372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3688271372
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3750201266
Short name T260
Test name
Test status
Simulation time 1641537146 ps
CPU time 20.94 seconds
Started May 07 01:14:02 PM PDT 24
Finished May 07 01:14:24 PM PDT 24
Peak memory 199976 kb
Host smart-95cff14f-43fe-43d4-bec7-fc4445671920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750201266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3750201266
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.374540782
Short name T307
Test name
Test status
Simulation time 7248050940 ps
CPU time 26.42 seconds
Started May 07 01:14:09 PM PDT 24
Finished May 07 01:14:36 PM PDT 24
Peak memory 200012 kb
Host smart-ccd25c4f-8e3b-4b3e-9bfb-6462d899f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374540782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.374540782
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2298126835
Short name T168
Test name
Test status
Simulation time 450827047 ps
CPU time 6.74 seconds
Started May 07 01:14:11 PM PDT 24
Finished May 07 01:14:19 PM PDT 24
Peak memory 200000 kb
Host smart-255518d1-8e5e-43e9-a37a-1a099c3bd4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298126835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2298126835
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3110819892
Short name T192
Test name
Test status
Simulation time 60161791 ps
CPU time 1.27 seconds
Started May 07 01:14:00 PM PDT 24
Finished May 07 01:14:02 PM PDT 24
Peak memory 199676 kb
Host smart-2f6e5c25-4bba-44ee-9da9-5a1310f0ba08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110819892 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3110819892
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2293666180
Short name T194
Test name
Test status
Simulation time 39657934324 ps
CPU time 504.41 seconds
Started May 07 01:14:08 PM PDT 24
Finished May 07 01:22:34 PM PDT 24
Peak memory 200028 kb
Host smart-6b8edf28-6e3d-4aeb-96da-792bcd1f7a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293666180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2293666180
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_alert_test.620506208
Short name T229
Test name
Test status
Simulation time 19218632 ps
CPU time 0.56 seconds
Started May 07 01:10:57 PM PDT 24
Finished May 07 01:10:59 PM PDT 24
Peak memory 195372 kb
Host smart-fd9ad081-13d7-48b0-a910-14a58d23ac3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620506208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.620506208
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1167469769
Short name T51
Test name
Test status
Simulation time 5398676873 ps
CPU time 57.44 seconds
Started May 07 01:10:50 PM PDT 24
Finished May 07 01:11:48 PM PDT 24
Peak memory 222932 kb
Host smart-057136bf-18ee-480c-a027-00d319de4c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167469769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1167469769
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3915161692
Short name T21
Test name
Test status
Simulation time 1991339662 ps
CPU time 38.63 seconds
Started May 07 01:10:49 PM PDT 24
Finished May 07 01:11:28 PM PDT 24
Peak memory 199996 kb
Host smart-d82f48c9-f20d-415f-b333-c2ddf3a5649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915161692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3915161692
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.160041779
Short name T141
Test name
Test status
Simulation time 1007133369 ps
CPU time 59.07 seconds
Started May 07 01:10:48 PM PDT 24
Finished May 07 01:11:47 PM PDT 24
Peak memory 200012 kb
Host smart-10a8e926-f6ac-4f06-a52a-ce1d9dbe95d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160041779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.160041779
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2851728786
Short name T235
Test name
Test status
Simulation time 6074053196 ps
CPU time 85.84 seconds
Started May 07 01:10:48 PM PDT 24
Finished May 07 01:12:15 PM PDT 24
Peak memory 200012 kb
Host smart-237b0517-4c15-49e7-9fc5-42fb4414b0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851728786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2851728786
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3376721638
Short name T283
Test name
Test status
Simulation time 186295895 ps
CPU time 1.03 seconds
Started May 07 01:10:48 PM PDT 24
Finished May 07 01:10:50 PM PDT 24
Peak memory 199972 kb
Host smart-2a99b201-93d5-4f72-ad4d-930d595ffca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376721638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3376721638
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1920895955
Short name T147
Test name
Test status
Simulation time 271750265 ps
CPU time 1.23 seconds
Started May 07 01:10:51 PM PDT 24
Finished May 07 01:10:53 PM PDT 24
Peak memory 199080 kb
Host smart-76e9ae45-0602-4be7-b53e-0dbc34f3289c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920895955 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1920895955
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2716335885
Short name T129
Test name
Test status
Simulation time 8409716634 ps
CPU time 437.28 seconds
Started May 07 01:10:51 PM PDT 24
Finished May 07 01:18:09 PM PDT 24
Peak memory 200084 kb
Host smart-a81202c1-202f-48ac-a9e2-15ebc3a8f63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716335885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2716335885
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3734411955
Short name T287
Test name
Test status
Simulation time 18233215 ps
CPU time 0.56 seconds
Started May 07 01:10:56 PM PDT 24
Finished May 07 01:10:58 PM PDT 24
Peak memory 194460 kb
Host smart-2df11e63-d1f0-4e78-a8fd-62a88cacc10d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734411955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3734411955
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.458620917
Short name T427
Test name
Test status
Simulation time 295922116 ps
CPU time 15.94 seconds
Started May 07 01:10:56 PM PDT 24
Finished May 07 01:11:12 PM PDT 24
Peak memory 215880 kb
Host smart-e569ec24-18d3-47a8-aefc-0441a7068347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458620917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.458620917
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.601406168
Short name T1
Test name
Test status
Simulation time 158558810 ps
CPU time 1.19 seconds
Started May 07 01:10:56 PM PDT 24
Finished May 07 01:10:58 PM PDT 24
Peak memory 199828 kb
Host smart-b41bbc8b-c1cf-4f68-813d-dcbbbb7690f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601406168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.601406168
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1265485069
Short name T333
Test name
Test status
Simulation time 37124678368 ps
CPU time 106.6 seconds
Started May 07 01:10:57 PM PDT 24
Finished May 07 01:12:44 PM PDT 24
Peak memory 200048 kb
Host smart-d5e1f1c1-b274-418d-bd95-4aa2c8553ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265485069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1265485069
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1141082326
Short name T280
Test name
Test status
Simulation time 2080959660 ps
CPU time 28.24 seconds
Started May 07 01:10:55 PM PDT 24
Finished May 07 01:11:25 PM PDT 24
Peak memory 199932 kb
Host smart-7ee1ae67-8c3d-42a3-b9e2-b992bf9c27d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141082326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1141082326
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1831967320
Short name T98
Test name
Test status
Simulation time 443840698 ps
CPU time 5.28 seconds
Started May 07 01:10:56 PM PDT 24
Finished May 07 01:11:03 PM PDT 24
Peak memory 199976 kb
Host smart-b1695951-24e1-42b2-b79f-8079afbfb025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831967320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1831967320
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1557522400
Short name T228
Test name
Test status
Simulation time 33120174 ps
CPU time 1.28 seconds
Started May 07 01:10:56 PM PDT 24
Finished May 07 01:10:59 PM PDT 24
Peak memory 199940 kb
Host smart-24a8c157-e244-4ad3-9938-53e7d27035ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557522400 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.1557522400
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3902661565
Short name T210
Test name
Test status
Simulation time 31948527893 ps
CPU time 445.93 seconds
Started May 07 01:10:56 PM PDT 24
Finished May 07 01:18:23 PM PDT 24
Peak memory 200036 kb
Host smart-0aa9c4df-7458-4149-8a65-f783605ff37d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902661565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3902661565
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.502205055
Short name T142
Test name
Test status
Simulation time 10827686 ps
CPU time 0.57 seconds
Started May 07 01:11:05 PM PDT 24
Finished May 07 01:11:07 PM PDT 24
Peak memory 194684 kb
Host smart-9795322d-664f-4015-a3f9-095571655f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502205055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.502205055
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2610576618
Short name T156
Test name
Test status
Simulation time 1529032612 ps
CPU time 87.19 seconds
Started May 07 01:11:05 PM PDT 24
Finished May 07 01:12:33 PM PDT 24
Peak memory 199976 kb
Host smart-44dab021-121b-4604-8ff8-e4a696d2b5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610576618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2610576618
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.297089159
Short name T419
Test name
Test status
Simulation time 24312856550 ps
CPU time 95.18 seconds
Started May 07 01:10:57 PM PDT 24
Finished May 07 01:12:33 PM PDT 24
Peak memory 200032 kb
Host smart-186240f9-2dfe-41ed-8d91-f7b1dbfba14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297089159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.297089159
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.723600598
Short name T362
Test name
Test status
Simulation time 1420013298 ps
CPU time 5.56 seconds
Started May 07 01:10:56 PM PDT 24
Finished May 07 01:11:03 PM PDT 24
Peak memory 199928 kb
Host smart-571a4abb-4c5c-44b3-afe4-be5dd67810f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723600598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.723600598
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2292992420
Short name T457
Test name
Test status
Simulation time 29256045 ps
CPU time 0.92 seconds
Started May 07 01:11:05 PM PDT 24
Finished May 07 01:11:08 PM PDT 24
Peak memory 198228 kb
Host smart-5fb79e5e-a501-4e83-9cde-502f2a5c9c01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292992420 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2292992420
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3167834074
Short name T421
Test name
Test status
Simulation time 77131438692 ps
CPU time 454.26 seconds
Started May 07 01:11:06 PM PDT 24
Finished May 07 01:18:42 PM PDT 24
Peak memory 200036 kb
Host smart-36d71256-1b6a-4d6b-a332-df4c80e9a16e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167834074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.3167834074
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1501233417
Short name T434
Test name
Test status
Simulation time 20423784 ps
CPU time 0.56 seconds
Started May 07 01:11:15 PM PDT 24
Finished May 07 01:11:16 PM PDT 24
Peak memory 195456 kb
Host smart-51b9318d-e0ee-46dd-9c08-e9a62432522a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501233417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1501233417
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3328058880
Short name T247
Test name
Test status
Simulation time 1736478407 ps
CPU time 40.15 seconds
Started May 07 01:11:04 PM PDT 24
Finished May 07 01:11:45 PM PDT 24
Peak memory 213820 kb
Host smart-894c0306-815c-4bb0-be85-1a8fefbf9401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328058880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3328058880
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3249999706
Short name T153
Test name
Test status
Simulation time 1022363197 ps
CPU time 19.12 seconds
Started May 07 01:11:06 PM PDT 24
Finished May 07 01:11:26 PM PDT 24
Peak memory 199916 kb
Host smart-05925bfa-d086-4b43-8706-2f10bf700d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249999706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3249999706
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4060411876
Short name T255
Test name
Test status
Simulation time 949613473 ps
CPU time 26.22 seconds
Started May 07 01:11:03 PM PDT 24
Finished May 07 01:11:30 PM PDT 24
Peak memory 199988 kb
Host smart-538c3012-19b0-45e3-a5ea-813fddab60b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060411876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4060411876
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3935741668
Short name T169
Test name
Test status
Simulation time 642506232 ps
CPU time 35.32 seconds
Started May 07 01:11:06 PM PDT 24
Finished May 07 01:11:43 PM PDT 24
Peak memory 199976 kb
Host smart-a3d53f62-5d0f-47c4-99cf-056b5938da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935741668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3935741668
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4217475560
Short name T322
Test name
Test status
Simulation time 296694269 ps
CPU time 2.18 seconds
Started May 07 01:11:05 PM PDT 24
Finished May 07 01:11:08 PM PDT 24
Peak memory 199960 kb
Host smart-f888856e-cb8c-4faa-a150-a75566358ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217475560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4217475560
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1576394924
Short name T310
Test name
Test status
Simulation time 275730460 ps
CPU time 1.03 seconds
Started May 07 01:11:06 PM PDT 24
Finished May 07 01:11:09 PM PDT 24
Peak memory 199532 kb
Host smart-366fee81-1128-41b4-a357-4692f2b3f128
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576394924 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1576394924
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.842307246
Short name T44
Test name
Test status
Simulation time 14428387411 ps
CPU time 400.95 seconds
Started May 07 01:11:04 PM PDT 24
Finished May 07 01:17:46 PM PDT 24
Peak memory 200052 kb
Host smart-fa16ef62-943c-4c37-b10e-aefa571dafe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842307246 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.842307246
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3928616445
Short name T424
Test name
Test status
Simulation time 48564028 ps
CPU time 0.6 seconds
Started May 07 01:11:11 PM PDT 24
Finished May 07 01:11:12 PM PDT 24
Peak memory 195656 kb
Host smart-b2cba96e-628e-4c9b-8d67-c68b3340e5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928616445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3928616445
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.738221478
Short name T375
Test name
Test status
Simulation time 538143363 ps
CPU time 30.37 seconds
Started May 07 01:11:11 PM PDT 24
Finished May 07 01:11:43 PM PDT 24
Peak memory 216356 kb
Host smart-1d76631e-b1b5-491f-acbd-079ce4e9f8ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738221478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.738221478
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2867154292
Short name T216
Test name
Test status
Simulation time 1077716048 ps
CPU time 13.07 seconds
Started May 07 01:11:12 PM PDT 24
Finished May 07 01:11:26 PM PDT 24
Peak memory 200000 kb
Host smart-8b72c56f-5463-4487-b44b-27bf9f4713f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867154292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2867154292
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1323703083
Short name T11
Test name
Test status
Simulation time 2203722480 ps
CPU time 125.58 seconds
Started May 07 01:11:14 PM PDT 24
Finished May 07 01:13:21 PM PDT 24
Peak memory 200052 kb
Host smart-b6eacbf5-044c-4f2f-a3ed-5b47c9807216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323703083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1323703083
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.817275339
Short name T127
Test name
Test status
Simulation time 1124627249 ps
CPU time 4.41 seconds
Started May 07 01:11:12 PM PDT 24
Finished May 07 01:11:17 PM PDT 24
Peak memory 199844 kb
Host smart-4628cbe6-a296-435d-ac21-5ea90728e819
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817275339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.817275339
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3987897566
Short name T219
Test name
Test status
Simulation time 7449212201 ps
CPU time 108.42 seconds
Started May 07 01:11:12 PM PDT 24
Finished May 07 01:13:01 PM PDT 24
Peak memory 200056 kb
Host smart-5942206b-f107-4222-9f90-e90915e2964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987897566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3987897566
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2483305902
Short name T269
Test name
Test status
Simulation time 2039163651 ps
CPU time 6.09 seconds
Started May 07 01:11:12 PM PDT 24
Finished May 07 01:11:20 PM PDT 24
Peak memory 200008 kb
Host smart-1acc3a0e-99d0-4d24-9ef4-3cece0342b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483305902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2483305902
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1977796075
Short name T302
Test name
Test status
Simulation time 263976011 ps
CPU time 1.3 seconds
Started May 07 01:11:11 PM PDT 24
Finished May 07 01:11:13 PM PDT 24
Peak memory 199968 kb
Host smart-8b2e808c-c7e0-4034-8f35-c9453dbd028b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977796075 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1977796075
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.2436081665
Short name T359
Test name
Test status
Simulation time 7741619338 ps
CPU time 403.52 seconds
Started May 07 01:11:12 PM PDT 24
Finished May 07 01:17:56 PM PDT 24
Peak memory 200032 kb
Host smart-4718781a-d46a-4e55-91a3-44384479ac41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436081665 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.2436081665
Directory /workspace/9.hmac_test_sha_vectors/latest
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