Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5919293	1			T1	1771		T2	1617		T3	14082
all_values[1]	5919293	1			T1	1771		T2	1617		T3	14082
all_values[2]	5919293	1			T1	1771		T2	1617		T3	14082

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58118

1

T2

32

T5

2

T10

167

auto[1]

17699761

1

T1

5313

T2

4819

T3

42246

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16152407

1

T1

4212

T2

4257

T3

36608

auto[1]

1605472

1

T1

1101

T2

594

T3

5638

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	16119	1			T23	1022		T7	2		T54	142
all_values[0]	auto[0]	auto[1]	139	1			T23	2		T54	2		T107	2
all_values[0]	auto[1]	auto[0]	5888257	1			T1	1748		T2	1596		T3	14062
all_values[0]	auto[1]	auto[1]	14778	1			T1	23		T2	21		T3	20
all_values[1]	auto[0]	auto[0]	16592	1			T5	2		T53	144		T30	181
all_values[1]	auto[0]	auto[1]	93	1			T25	2		T61	6		T106	2
all_values[1]	auto[1]	auto[0]	5902506	1			T1	1771		T2	1617		T3	14082
all_values[1]	auto[1]	auto[1]	102	1			T25	2		T119	1		T120	2
all_values[2]	auto[0]	auto[0]	10385	1			T2	32		T10	167		T7	2
all_values[2]	auto[0]	auto[1]	14790	1			T25	48		T47	2		T91	11
all_values[2]	auto[1]	auto[0]	4318548	1			T1	693		T2	1012		T3	8464
all_values[2]	auto[1]	auto[1]	1575570	1			T1	1078		T2	573		T3	5618