Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2999873

1

T1

1797

T2

1557

T3

6034

auto[1]

1011322

1

T1

1371

T2

1340

T3

7979

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018734

1

T1

1345

T2

949

T3

8406

auto[1]

2992461

1

T1

1823

T2

1948

T3

5607

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2393415

1

T1

1563

T2

1476

T3

4343

auto[1]

1617780

1

T1

1605

T2

1421

T3

9670

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	3282565	1			T1	3083		T2	2673		T3	13874
fifo_depth[1]	121740	1			T1	18		T2	21		T3	95
fifo_depth[2]	98848	1			T1	34		T2	69		T3	34
fifo_depth[3]	77876	1			T1	5		T2	16		T3	9
fifo_depth[4]	64841	1			T1	15		T2	38		T3	1
fifo_depth[5]	55123	1			T1	5		T2	8		T4	602
fifo_depth[6]	53597	1			T1	7		T2	38		T4	588
fifo_depth[7]	43424	1			T1	1		T2	6		T4	529

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

728630

1

T1

85

T2

224

T3

139

auto[1]

3282565

1

T1

3083

T2

2673

T3

13874

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4008090

1

T1

3168

T2

2897

T3

14013

auto[1]

3105

1

T5

1

T8

1

T7

115

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

32555

1

T1

19

T2

46

T3

10

auto[0]

auto[0]

auto[0]

auto[1]

28972

1

T2

10

T3

2

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

383538

1

T1

18

T2

38

T5

2

auto[0]

auto[0]

auto[1]

auto[1]

25270

1

T1

4

T2

1

T3

29

auto[0]

auto[1]

auto[0]

auto[0]

54831

1

T1

11

T2

48

T3

20

auto[0]

auto[1]

auto[0]

auto[1]

72019

1

T3

48

T4

2773

T5

1

auto[0]

auto[1]

auto[1]

auto[0]

68835

1

T1

7

T2

80

T3

28

auto[0]

auto[1]

auto[1]

auto[1]

62610

1

T1

26

T2

1

T3

2

auto[1]

auto[0]

auto[0]

auto[0]

68508

1

T1

231

T2

309

T3

1480

auto[1]

auto[0]

auto[0]

auto[1]

72797

1

T1

402

T2

241

T3

1394

auto[1]

auto[0]

auto[1]

auto[0]

1708540

1

T1

834

T2

262

T3

150

auto[1]

auto[0]

auto[1]

auto[1]

73235

1

T1

55

T2

569

T3

1278

auto[1]

auto[1]

auto[0]

auto[0]

366704

1

T1

272

T2

152

T3

892

auto[1]

auto[1]

auto[0]

auto[1]

322348

1

T1

410

T2

143

T3

4560

auto[1]

auto[1]

auto[1]

auto[0]

316362

1

T1

405

T2

622

T3

3454

auto[1]

auto[1]

auto[1]

auto[1]

354071

1

T1

474

T2

375

T3

666

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

100699

1

T1

250

T2

355

T3

1490

auto[0]

auto[0]

auto[0]

auto[1]

101052

1

T1

402

T2

251

T3

1396

auto[0]

auto[0]

auto[1]

auto[0]

2091849

1

T1

852

T2

300

T3

150

auto[0]

auto[0]

auto[1]

auto[1]

98183

1

T1

59

T2

570

T3

1307

auto[0]

auto[1]

auto[0]

auto[0]

421445

1

T1

283

T2

200

T3

912

auto[0]

auto[1]

auto[0]

auto[1]

394216

1

T1

410

T2

143

T3

4608

auto[0]

auto[1]

auto[1]

auto[0]

384234

1

T1

412

T2

702

T3

3482

auto[0]

auto[1]

auto[1]

auto[1]

416412

1

T1

500

T2

376

T3

668

auto[1]

auto[0]

auto[0]

auto[0]

364

1

T8

1

T7

1

T51

1

auto[1]

auto[0]

auto[0]

auto[1]

717

1

T7

1

T29

1

T40

1

auto[1]

auto[0]

auto[1]

auto[0]

229

1

T7

96

T48

1

T108

2

auto[1]

auto[0]

auto[1]

auto[1]

322

1

T5

1

T48

1

T49

1

auto[1]

auto[1]

auto[0]

auto[0]

90

1

T40

1

T133

1

T120

15

auto[1]

auto[1]

auto[0]

auto[1]

151

1

T7

3

T119

1

T134

9

auto[1]

auto[1]

auto[1]

auto[0]

963

1

T7

1

T29

1

T119

9

auto[1]

auto[1]

auto[1]

auto[1]

269

1

T7

13

T119

1

T134

45

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	68508	1			T1	231		T2	309		T3	1480
fifo_depth[0]	auto[0]	auto[0]	auto[1]	72797	1			T1	402		T2	241		T3	1394
fifo_depth[0]	auto[0]	auto[1]	auto[0]	1708540	1			T1	834		T2	262		T3	150
fifo_depth[0]	auto[0]	auto[1]	auto[1]	73235	1			T1	55		T2	569		T3	1278
fifo_depth[0]	auto[1]	auto[0]	auto[0]	366704	1			T1	272		T2	152		T3	892
fifo_depth[0]	auto[1]	auto[0]	auto[1]	322348	1			T1	410		T2	143		T3	4560
fifo_depth[0]	auto[1]	auto[1]	auto[0]	316362	1			T1	405		T2	622		T3	3454
fifo_depth[0]	auto[1]	auto[1]	auto[1]	354071	1			T1	474		T2	375		T3	666
fifo_depth[1]	auto[0]	auto[0]	auto[0]	2007	1			T1	7		T2	2		T3	7
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1152	1			T2	3		T3	1		T9	10
fifo_depth[1]	auto[0]	auto[1]	auto[0]	93997	1			T1	4		T2	4		T6	2453
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1259	1			T1	3		T3	19		T9	5
fifo_depth[1]	auto[1]	auto[0]	auto[0]	5223	1			T1	4		T2	6		T3	16
fifo_depth[1]	auto[1]	auto[0]	auto[1]	6777	1			T3	33		T4	306		T10	1
fifo_depth[1]	auto[1]	auto[1]	auto[0]	5830	1			T2	5		T3	18		T4	93
fifo_depth[1]	auto[1]	auto[1]	auto[1]	5495	1			T2	1		T3	1		T4	159
fifo_depth[2]	auto[0]	auto[0]	auto[0]	2145	1			T1	4		T2	22		T3	2
fifo_depth[2]	auto[0]	auto[0]	auto[1]	1188	1			T2	1		T3	1		T9	12
fifo_depth[2]	auto[0]	auto[1]	auto[0]	70525	1			T1	8		T2	16		T9	20
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1547	1			T2	1		T3	6		T9	17
fifo_depth[2]	auto[1]	auto[0]	auto[0]	5369	1			T1	3		T2	10		T3	3
fifo_depth[2]	auto[1]	auto[0]	auto[1]	6653	1			T3	13		T4	293		T10	9
fifo_depth[2]	auto[1]	auto[1]	auto[0]	5938	1			T1	4		T2	19		T3	8
fifo_depth[2]	auto[1]	auto[1]	auto[1]	5483	1			T1	15		T3	1		T4	164
fifo_depth[3]	auto[0]	auto[0]	auto[0]	1634	1			T1	4		T2	1		T3	1
fifo_depth[3]	auto[0]	auto[0]	auto[1]	949	1			T2	2		T9	7		T10	3
fifo_depth[3]	auto[0]	auto[1]	auto[0]	52317	1			T2	2		T6	2046		T10	6
fifo_depth[3]	auto[0]	auto[1]	auto[1]	870	1			T3	4		T9	3		T10	12
fifo_depth[3]	auto[1]	auto[0]	auto[0]	4869	1			T2	5		T3	1		T4	32
fifo_depth[3]	auto[1]	auto[0]	auto[1]	6437	1			T3	2		T4	289		T10	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	5591	1			T1	1		T2	6		T3	1
fifo_depth[3]	auto[1]	auto[1]	auto[1]	5209	1			T4	156		T9	2		T23	12
fifo_depth[4]	auto[0]	auto[0]	auto[0]	1946	1			T1	2		T2	10		T9	1
fifo_depth[4]	auto[0]	auto[0]	auto[1]	1146	1			T9	10		T23	6		T7	94
fifo_depth[4]	auto[0]	auto[1]	auto[0]	38123	1			T1	2		T2	5		T9	15
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1137	1			T9	8		T10	12		T23	16
fifo_depth[4]	auto[1]	auto[0]	auto[0]	5040	1			T1	2		T2	10		T4	38
fifo_depth[4]	auto[1]	auto[0]	auto[1]	6490	1			T4	324		T10	7		T23	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	5754	1			T2	13		T3	1		T4	115
fifo_depth[4]	auto[1]	auto[1]	auto[1]	5205	1			T1	9		T4	164		T9	1
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1328	1			T1	1		T10	3		T23	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	926	1			T2	1		T9	2		T23	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	30620	1			T1	1		T2	2		T6	1534
fifo_depth[5]	auto[0]	auto[1]	auto[1]	773	1			T1	1		T9	3		T10	4
fifo_depth[5]	auto[1]	auto[0]	auto[0]	4744	1			T2	1		T4	37		T23	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	6266	1			T4	289		T23	2		T7	206
fifo_depth[5]	auto[1]	auto[1]	auto[0]	5478	1			T1	1		T2	4		T4	110
fifo_depth[5]	auto[1]	auto[1]	auto[1]	4988	1			T1	1		T4	166		T9	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1733	1			T2	6		T9	1		T10	2
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1164	1			T2	3		T9	2		T10	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	26822	1			T1	3		T2	4		T6	1349
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1644	1			T9	2		T10	11		T29	27
fifo_depth[6]	auto[1]	auto[0]	auto[0]	4882	1			T1	2		T2	9		T4	31
fifo_depth[6]	auto[1]	auto[0]	auto[1]	6483	1			T4	287		T10	9		T7	239
fifo_depth[6]	auto[1]	auto[1]	auto[0]	5801	1			T1	1		T2	16		T4	113
fifo_depth[6]	auto[1]	auto[1]	auto[1]	5068	1			T1	1		T4	157		T9	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1198	1			T1	1		T10	1		T7	49
fifo_depth[7]	auto[0]	auto[0]	auto[1]	843	1			T7	20		T59	2		T29	8
fifo_depth[7]	auto[0]	auto[1]	auto[0]	20664	1			T2	3		T6	1120		T7	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	840	1			T29	1		T135	28		T108	42
fifo_depth[7]	auto[1]	auto[0]	auto[0]	4496	1			T2	2		T4	31		T10	2
fifo_depth[7]	auto[1]	auto[0]	auto[1]	5860	1			T4	247		T7	184		T136	289
fifo_depth[7]	auto[1]	auto[1]	auto[0]	4950	1			T2	1		T4	111		T33	3
fifo_depth[7]	auto[1]	auto[1]	auto[1]	4573	1			T4	140		T9	1		T7	111