Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5919293	1			T1	1771		T2	1617		T3	14082
all_pins[1]	5919293	1			T1	1771		T2	1617		T3	14082
all_pins[2]	5919293	1			T1	1771		T2	1617		T3	14082

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	16167174	1			T1	4212		T2	4257		T3	36607
values[0x1]	1590705	1			T1	1101		T2	594		T3	5639
transitions[0x0=>0x1]	1590622	1			T1	1101		T2	594		T3	5639
transitions[0x1=>0x0]	1590634	1			T1	1101		T2	594		T3	5639

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5904271	1			T1	1748		T2	1596		T3	14061
all_pins[0]	values[0x1]	15022	1			T1	23		T2	21		T3	21
all_pins[0]	transitions[0x0=>0x1]	14988	1			T1	23		T2	21		T3	21
all_pins[0]	transitions[0x1=>0x0]	1575548	1			T1	1078		T2	573		T3	5618
all_pins[1]	values[0x0]	5919180	1			T1	1771		T2	1617		T3	14082
all_pins[1]	values[0x1]	113	1			T7	2		T29	1		T25	2
all_pins[1]	transitions[0x0=>0x1]	88	1			T7	2		T29	1		T25	1
all_pins[1]	transitions[0x1=>0x0]	14997	1			T1	23		T2	21		T3	21
all_pins[2]	values[0x0]	4343723	1			T1	693		T2	1044		T3	8464
all_pins[2]	values[0x1]	1575570	1			T1	1078		T2	573		T3	5618
all_pins[2]	transitions[0x0=>0x1]	1575546	1			T1	1078		T2	573		T3	5618
all_pins[2]	transitions[0x1=>0x0]	89	1			T7	2		T29	1		T25	1