Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 406 1 T7 4 T25 7 T61 14
all_values[1] 406 1 T7 4 T25 7 T61 14
all_values[2] 406 1 T7 4 T25 7 T61 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 649 1 T7 6 T25 12 T61 26
auto[1] 569 1 T7 6 T25 9 T61 16


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 447 1 T7 12 T25 6 T61 24
auto[1] 771 1 T25 15 T61 18 T106 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 700 1 T7 12 T25 9 T61 30
auto[1] 518 1 T25 12 T61 12 T106 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 83 1 T7 3 T25 1 T61 5
all_values[0] auto[0] auto[0] auto[1] 33 1 T106 1 T121 1 T12 2
all_values[0] auto[0] auto[1] auto[0] 80 1 T7 1 T25 1 T61 8
all_values[0] auto[0] auto[1] auto[1] 36 1 T121 1 T12 1 T122 1
all_values[0] auto[1] auto[0] auto[1] 88 1 T25 3 T61 1 T106 2
all_values[0] auto[1] auto[1] auto[1] 86 1 T25 2 T106 2 T121 2
all_values[1] auto[0] auto[0] auto[0] 63 1 T7 2 T61 2 T106 1
all_values[1] auto[0] auto[0] auto[1] 49 1 T25 1 T61 2 T106 1
all_values[1] auto[0] auto[1] auto[0] 65 1 T7 2 T25 1 T61 2
all_values[1] auto[0] auto[1] auto[1] 53 1 T25 1 T61 1 T106 1
all_values[1] auto[1] auto[0] auto[1] 107 1 T25 2 T61 7 T106 2
all_values[1] auto[1] auto[1] auto[1] 69 1 T25 2 T106 2 T121 4
all_values[2] auto[0] auto[0] auto[0] 97 1 T7 1 T25 3 T61 6
all_values[2] auto[0] auto[0] auto[1] 40 1 T61 1 T106 2 T121 2
all_values[2] auto[0] auto[1] auto[0] 59 1 T7 3 T61 1 T121 2
all_values[2] auto[0] auto[1] auto[1] 42 1 T25 1 T61 2 T121 2
all_values[2] auto[1] auto[0] auto[1] 89 1 T25 2 T61 2 T106 2
all_values[2] auto[1] auto[1] auto[1] 79 1 T25 1 T61 2 T106 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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