Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.03 95.76 93.95 100.00 71.05 91.67 99.49 71.33


Total test records in report: 601
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T512 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1878392117 May 09 01:03:10 PM PDT 24 May 09 01:03:14 PM PDT 24 16966062 ps
T126 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2742426747 May 09 01:03:04 PM PDT 24 May 09 01:03:07 PM PDT 24 413264444 ps
T513 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4209510853 May 09 01:03:06 PM PDT 24 May 09 01:03:11 PM PDT 24 255207231 ps
T514 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2704567932 May 09 01:03:12 PM PDT 24 May 09 01:03:17 PM PDT 24 1734089145 ps
T515 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.405564892 May 09 01:03:19 PM PDT 24 May 09 01:03:23 PM PDT 24 67129493 ps
T516 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2765776008 May 09 01:03:03 PM PDT 24 May 09 01:03:05 PM PDT 24 55330465 ps
T517 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1234922761 May 09 01:03:09 PM PDT 24 May 09 01:03:14 PM PDT 24 53626273 ps
T518 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.558337638 May 09 01:03:02 PM PDT 24 May 09 01:03:05 PM PDT 24 288389460 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1383651419 May 09 01:02:47 PM PDT 24 May 09 01:03:03 PM PDT 24 603971660 ps
T519 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2175034608 May 09 01:03:25 PM PDT 24 May 09 01:03:29 PM PDT 24 13292789 ps
T520 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.960038614 May 09 01:02:49 PM PDT 24 May 09 01:02:53 PM PDT 24 87502882 ps
T521 /workspace/coverage/cover_reg_top/40.hmac_intr_test.390925788 May 09 01:03:22 PM PDT 24 May 09 01:03:25 PM PDT 24 28507571 ps
T522 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4220612631 May 09 01:03:23 PM PDT 24 May 09 01:03:29 PM PDT 24 309598613 ps
T523 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3622941230 May 09 01:03:16 PM PDT 24 May 09 01:03:20 PM PDT 24 69178026 ps
T524 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.786977253 May 09 01:02:51 PM PDT 24 May 09 01:02:57 PM PDT 24 147315715 ps
T525 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.910132439 May 09 01:03:20 PM PDT 24 May 09 01:03:24 PM PDT 24 100194849 ps
T127 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1777693069 May 09 01:03:14 PM PDT 24 May 09 01:03:19 PM PDT 24 643447620 ps
T526 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4051324325 May 09 01:03:17 PM PDT 24 May 09 01:03:21 PM PDT 24 155390245 ps
T527 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3341789202 May 09 01:03:23 PM PDT 24 May 09 01:03:28 PM PDT 24 43363286 ps
T528 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1972934174 May 09 01:03:22 PM PDT 24 May 09 01:03:26 PM PDT 24 13329264 ps
T529 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3922111193 May 09 01:03:22 PM PDT 24 May 09 01:03:25 PM PDT 24 45658325 ps
T530 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3373781757 May 09 01:03:04 PM PDT 24 May 09 01:03:10 PM PDT 24 478656845 ps
T531 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2180170827 May 09 01:03:21 PM PDT 24 May 09 01:03:24 PM PDT 24 15045897 ps
T532 /workspace/coverage/cover_reg_top/3.hmac_intr_test.594575303 May 09 01:03:04 PM PDT 24 May 09 01:03:06 PM PDT 24 17064676 ps
T533 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1912237079 May 09 01:03:14 PM PDT 24 May 09 01:03:17 PM PDT 24 16364735 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3210391219 May 09 01:03:02 PM PDT 24 May 09 01:03:05 PM PDT 24 100504567 ps
T534 /workspace/coverage/cover_reg_top/4.hmac_intr_test.4060186346 May 09 01:03:03 PM PDT 24 May 09 01:03:04 PM PDT 24 16939352 ps
T535 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2443345214 May 09 01:02:48 PM PDT 24 May 09 01:02:52 PM PDT 24 345015954 ps
T536 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3588582508 May 09 01:03:22 PM PDT 24 May 09 01:03:27 PM PDT 24 29191253 ps
T537 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.334895817 May 09 01:03:08 PM PDT 24 May 09 01:03:12 PM PDT 24 61162096 ps
T128 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1854726669 May 09 01:03:25 PM PDT 24 May 09 01:03:31 PM PDT 24 189586036 ps
T538 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1458261490 May 09 01:03:21 PM PDT 24 May 09 01:03:24 PM PDT 24 26039668 ps
T539 /workspace/coverage/cover_reg_top/10.hmac_intr_test.8567108 May 09 01:03:07 PM PDT 24 May 09 01:03:10 PM PDT 24 20654111 ps
T540 /workspace/coverage/cover_reg_top/22.hmac_intr_test.4020336923 May 09 01:03:20 PM PDT 24 May 09 01:03:23 PM PDT 24 35135126 ps
T541 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3862342248 May 09 01:03:22 PM PDT 24 May 09 01:03:27 PM PDT 24 164527391 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.67291130 May 09 01:03:04 PM PDT 24 May 09 01:03:18 PM PDT 24 1067084414 ps
T542 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1012038793 May 09 01:03:08 PM PDT 24 May 09 01:03:13 PM PDT 24 34275416 ps
T543 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1543494235 May 09 01:03:17 PM PDT 24 May 09 01:03:20 PM PDT 24 102207844 ps
T544 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1841533358 May 09 01:03:09 PM PDT 24 May 09 01:03:14 PM PDT 24 425255937 ps
T545 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1898504753 May 09 01:03:08 PM PDT 24 May 09 01:03:13 PM PDT 24 168438662 ps
T546 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2880584238 May 09 01:02:58 PM PDT 24 May 09 01:03:03 PM PDT 24 190888837 ps
T547 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2888228708 May 09 01:03:05 PM PDT 24 May 09 01:03:09 PM PDT 24 91496352 ps
T548 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.553394724 May 09 01:03:11 PM PDT 24 May 09 01:03:16 PM PDT 24 230028990 ps
T103 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1419699188 May 09 01:02:47 PM PDT 24 May 09 01:02:49 PM PDT 24 26488743 ps
T549 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3357582568 May 09 01:03:04 PM PDT 24 May 09 01:03:22 PM PDT 24 1100658246 ps
T550 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2862782449 May 09 01:03:11 PM PDT 24 May 09 01:03:15 PM PDT 24 26411150 ps
T551 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2441461434 May 09 01:03:21 PM PDT 24 May 09 01:03:25 PM PDT 24 308246739 ps
T552 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1404701746 May 09 01:03:22 PM PDT 24 May 09 01:03:26 PM PDT 24 25805342 ps
T132 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2559068529 May 09 01:03:10 PM PDT 24 May 09 01:03:16 PM PDT 24 86067502 ps
T553 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4140591673 May 09 01:03:17 PM PDT 24 May 09 01:03:20 PM PDT 24 246368686 ps
T554 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.136216070 May 09 01:03:02 PM PDT 24 May 09 01:03:06 PM PDT 24 168894058 ps
T104 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1547277868 May 09 01:02:48 PM PDT 24 May 09 01:02:53 PM PDT 24 749552884 ps
T555 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3667270056 May 09 01:02:48 PM PDT 24 May 09 01:02:54 PM PDT 24 243614537 ps
T556 /workspace/coverage/cover_reg_top/33.hmac_intr_test.806178057 May 09 01:03:22 PM PDT 24 May 09 01:03:26 PM PDT 24 32410965 ps
T557 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1709720290 May 09 01:03:11 PM PDT 24 May 09 01:13:38 PM PDT 24 40859659759 ps
T558 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1754255490 May 09 01:02:48 PM PDT 24 May 09 01:02:51 PM PDT 24 179860849 ps
T559 /workspace/coverage/cover_reg_top/16.hmac_intr_test.708408282 May 09 01:03:22 PM PDT 24 May 09 01:03:26 PM PDT 24 14720860 ps
T560 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.182218950 May 09 01:03:04 PM PDT 24 May 09 01:03:14 PM PDT 24 437059190 ps
T561 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3026255319 May 09 01:03:20 PM PDT 24 May 09 01:03:23 PM PDT 24 47064397 ps
T562 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1145839198 May 09 01:03:18 PM PDT 24 May 09 01:03:20 PM PDT 24 60747420 ps
T563 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3157318667 May 09 01:02:49 PM PDT 24 May 09 01:03:00 PM PDT 24 1783288296 ps
T564 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3940939450 May 09 01:03:03 PM PDT 24 May 09 01:03:04 PM PDT 24 16132376 ps
T565 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1856877776 May 09 01:03:05 PM PDT 24 May 09 01:03:08 PM PDT 24 146962802 ps
T566 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2883387508 May 09 01:03:13 PM PDT 24 May 09 01:03:16 PM PDT 24 72220328 ps
T567 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2308947453 May 09 01:03:23 PM PDT 24 May 09 01:03:27 PM PDT 24 17846302 ps
T568 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1662443119 May 09 01:03:20 PM PDT 24 May 09 01:03:22 PM PDT 24 101379405 ps
T569 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1372006583 May 09 01:03:21 PM PDT 24 May 09 01:03:26 PM PDT 24 735458269 ps
T570 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1386476861 May 09 01:02:50 PM PDT 24 May 09 01:02:53 PM PDT 24 32385502 ps
T571 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2432184564 May 09 01:03:05 PM PDT 24 May 09 01:03:10 PM PDT 24 160330192 ps
T572 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3873500195 May 09 01:03:06 PM PDT 24 May 09 01:03:09 PM PDT 24 48074540 ps
T129 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.157160884 May 09 01:03:06 PM PDT 24 May 09 01:03:12 PM PDT 24 722933920 ps
T573 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.324392709 May 09 01:03:09 PM PDT 24 May 09 01:03:14 PM PDT 24 307740443 ps
T574 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3923829825 May 09 01:03:08 PM PDT 24 May 09 01:03:12 PM PDT 24 396255201 ps
T575 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1065959058 May 09 01:03:11 PM PDT 24 May 09 01:03:15 PM PDT 24 16298806 ps
T576 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1822387709 May 09 01:03:06 PM PDT 24 May 09 01:03:12 PM PDT 24 671432522 ps
T577 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1739506131 May 09 01:03:04 PM PDT 24 May 09 01:03:07 PM PDT 24 41641981 ps
T578 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2431938393 May 09 01:03:20 PM PDT 24 May 09 01:03:23 PM PDT 24 53350983 ps
T579 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3172374124 May 09 01:03:09 PM PDT 24 May 09 01:03:13 PM PDT 24 48891529 ps
T580 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3745203036 May 09 01:02:58 PM PDT 24 May 09 01:03:02 PM PDT 24 617277008 ps
T581 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2288271948 May 09 01:03:23 PM PDT 24 May 09 01:03:28 PM PDT 24 27151752 ps
T582 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2266008281 May 09 01:03:23 PM PDT 24 May 09 01:03:28 PM PDT 24 11234312 ps
T583 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3182613619 May 09 01:03:08 PM PDT 24 May 09 01:03:13 PM PDT 24 128360205 ps
T584 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1511605580 May 09 01:03:22 PM PDT 24 May 09 01:03:25 PM PDT 24 26766178 ps
T585 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2692212078 May 09 01:03:20 PM PDT 24 May 09 01:03:23 PM PDT 24 248235957 ps
T586 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3404388353 May 09 01:03:22 PM PDT 24 May 09 01:03:26 PM PDT 24 41354494 ps
T587 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1367511125 May 09 01:03:07 PM PDT 24 May 09 01:03:14 PM PDT 24 273024901 ps
T588 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4282440142 May 09 01:03:01 PM PDT 24 May 09 01:03:05 PM PDT 24 269692005 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.267513188 May 09 01:02:52 PM PDT 24 May 09 01:02:55 PM PDT 24 13380337 ps
T590 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1729635607 May 09 01:03:11 PM PDT 24 May 09 01:03:16 PM PDT 24 1018235112 ps
T591 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.29840079 May 09 01:03:04 PM PDT 24 May 09 01:03:09 PM PDT 24 96273775 ps
T592 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.498771344 May 09 01:03:06 PM PDT 24 May 09 01:03:10 PM PDT 24 164110903 ps
T593 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2661724457 May 09 01:03:08 PM PDT 24 May 09 01:03:14 PM PDT 24 39606492 ps
T105 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1913486712 May 09 01:03:05 PM PDT 24 May 09 01:03:08 PM PDT 24 148271780 ps
T594 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4207156423 May 09 01:03:11 PM PDT 24 May 09 01:03:15 PM PDT 24 22642324 ps
T595 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1736541669 May 09 01:03:20 PM PDT 24 May 09 01:03:24 PM PDT 24 89727875 ps
T596 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.476266433 May 09 01:03:09 PM PDT 24 May 09 01:03:13 PM PDT 24 33139597 ps
T597 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1931995691 May 09 01:03:25 PM PDT 24 May 09 01:03:29 PM PDT 24 12121699 ps
T598 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2251878341 May 09 01:03:10 PM PDT 24 May 09 01:03:16 PM PDT 24 355608219 ps
T599 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2455798635 May 09 01:03:22 PM PDT 24 May 09 01:03:27 PM PDT 24 41654074 ps
T600 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3258053420 May 09 01:03:23 PM PDT 24 May 09 01:03:27 PM PDT 24 12334819 ps
T601 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4132384782 May 09 01:03:10 PM PDT 24 May 09 01:03:16 PM PDT 24 604496787 ps

Test location /workspace/coverage/default/27.hmac_datapath_stress.1584348146
Short name T4
Test name
Test status
Simulation time 4299069809 ps
CPU time 954.09 seconds
Started May 09 01:04:25 PM PDT 24
Finished May 09 01:20:21 PM PDT 24
Peak memory 754756 kb
Host smart-640723ab-ddf0-4871-9743-46244b428112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1584348146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1584348146
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.565658893
Short name T12
Test name
Test status
Simulation time 16024058510 ps
CPU time 1575.95 seconds
Started May 09 01:05:34 PM PDT 24
Finished May 09 01:31:52 PM PDT 24
Peak memory 697804 kb
Host smart-6d6ae823-5888-4060-a64c-65ba8731f435
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565658893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.565658893
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2585074952
Short name T10
Test name
Test status
Simulation time 2034806785 ps
CPU time 38.69 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:05:17 PM PDT 24
Peak memory 200676 kb
Host smart-528abe0e-262b-448d-8e2c-21842bd236be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585074952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2585074952
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3796400797
Short name T26
Test name
Test status
Simulation time 262187432 ps
CPU time 0.91 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:03:37 PM PDT 24
Peak memory 218764 kb
Host smart-14d369e1-9ea2-473d-a648-98a0b64e11c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796400797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3796400797
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1670433936
Short name T7
Test name
Test status
Simulation time 19608091019 ps
CPU time 1095.63 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:23:30 PM PDT 24
Peak memory 768720 kb
Host smart-d010fb3a-62b3-4723-b27d-77d99bb9d2b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670433936 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1670433936
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.2981710146
Short name T11
Test name
Test status
Simulation time 44444543445 ps
CPU time 266.73 seconds
Started May 09 01:05:44 PM PDT 24
Finished May 09 01:10:12 PM PDT 24
Peak memory 217300 kb
Host smart-1e10eeeb-1b6b-478d-9e9e-1d238654d018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981710146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.2981710146
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.984127535
Short name T56
Test name
Test status
Simulation time 315954386 ps
CPU time 1.85 seconds
Started May 09 01:03:07 PM PDT 24
Finished May 09 01:03:12 PM PDT 24
Peak memory 200148 kb
Host smart-f7f6dfe8-309b-43c7-8c50-d5dc3a86fa2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984127535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.984127535
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1581117248
Short name T5
Test name
Test status
Simulation time 370869420 ps
CPU time 19.61 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:05:31 PM PDT 24
Peak memory 200484 kb
Host smart-da8eb5c0-9ea7-4900-8c64-3c5c1fe399d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581117248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1581117248
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1687403272
Short name T79
Test name
Test status
Simulation time 25753385 ps
CPU time 0.78 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 199168 kb
Host smart-6a4d4c56-56f1-4dde-9021-aee1f2270e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687403272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1687403272
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4101315053
Short name T25
Test name
Test status
Simulation time 86648885593 ps
CPU time 996.66 seconds
Started May 09 01:03:31 PM PDT 24
Finished May 09 01:20:10 PM PDT 24
Peak memory 705932 kb
Host smart-c7a8269e-89e0-47d4-a4a5-bdd6e095cd58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101315053 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4101315053
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1777693069
Short name T127
Test name
Test status
Simulation time 643447620 ps
CPU time 3.05 seconds
Started May 09 01:03:14 PM PDT 24
Finished May 09 01:03:19 PM PDT 24
Peak memory 200012 kb
Host smart-75053fed-a3fe-4e00-9ca9-2a757b4a9d51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777693069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1777693069
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.826337576
Short name T86
Test name
Test status
Simulation time 107723762 ps
CPU time 1.16 seconds
Started May 09 01:04:50 PM PDT 24
Finished May 09 01:04:52 PM PDT 24
Peak memory 200480 kb
Host smart-403e2b4d-594f-4f47-82b2-28f653738af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826337576 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.826337576
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.196430416
Short name T437
Test name
Test status
Simulation time 1164984193 ps
CPU time 4.02 seconds
Started May 09 01:03:56 PM PDT 24
Finished May 09 01:04:04 PM PDT 24
Peak memory 200512 kb
Host smart-e7033ebe-2baf-4dee-a38d-6e99b46eb64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196430416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.196430416
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4162186763
Short name T22
Test name
Test status
Simulation time 22769239 ps
CPU time 0.59 seconds
Started May 09 01:04:09 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 195956 kb
Host smart-de57f70f-2192-4bd5-966c-9109bab1ee43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162186763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4162186763
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.169769543
Short name T57
Test name
Test status
Simulation time 82563641 ps
CPU time 1.82 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:24 PM PDT 24
Peak memory 200100 kb
Host smart-426ff1fd-dddc-4321-989a-71ceab4a2571
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169769543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.169769543
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1351399273
Short name T117
Test name
Test status
Simulation time 2903223965 ps
CPU time 46.21 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:47 PM PDT 24
Peak memory 208988 kb
Host smart-e54f71ef-eba4-4fb3-8f8c-d31744c51c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351399273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1351399273
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3083475984
Short name T108
Test name
Test status
Simulation time 304832296 ps
CPU time 15.79 seconds
Started May 09 01:04:33 PM PDT 24
Finished May 09 01:04:51 PM PDT 24
Peak memory 200548 kb
Host smart-5e67657e-aee1-42b0-ac3a-25a151ca43e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083475984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3083475984
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.265747773
Short name T113
Test name
Test status
Simulation time 1369620213 ps
CPU time 118.02 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:06:12 PM PDT 24
Peak memory 352596 kb
Host smart-1bf57e32-e726-4d0d-aeb4-4f1faddfc6e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265747773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.265747773
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.529216648
Short name T114
Test name
Test status
Simulation time 3622629335 ps
CPU time 404.63 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:11:46 PM PDT 24
Peak memory 503864 kb
Host smart-3dc41536-1ec1-4c6e-849c-1af59a248eac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529216648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.529216648
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1754255490
Short name T558
Test name
Test status
Simulation time 179860849 ps
CPU time 1.67 seconds
Started May 09 01:02:48 PM PDT 24
Finished May 09 01:02:51 PM PDT 24
Peak memory 200176 kb
Host smart-4500596c-5bcb-4321-8748-a9492cb86b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754255490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1754255490
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3295219849
Short name T111
Test name
Test status
Simulation time 32955411571 ps
CPU time 117.94 seconds
Started May 09 01:03:59 PM PDT 24
Finished May 09 01:05:59 PM PDT 24
Peak memory 200640 kb
Host smart-e58d02e6-a26f-4e21-81c8-ed6ec5899210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295219849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3295219849
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1547277868
Short name T104
Test name
Test status
Simulation time 749552884 ps
CPU time 3.41 seconds
Started May 09 01:02:48 PM PDT 24
Finished May 09 01:02:53 PM PDT 24
Peak memory 199956 kb
Host smart-666ea8f9-53cf-4c8e-9a30-bdd2d64d2fb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547277868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1547277868
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1383651419
Short name T101
Test name
Test status
Simulation time 603971660 ps
CPU time 14.06 seconds
Started May 09 01:02:47 PM PDT 24
Finished May 09 01:03:03 PM PDT 24
Peak memory 199056 kb
Host smart-81728bd4-8aa8-4b4a-9d8a-d94481118600
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383651419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1383651419
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3595809623
Short name T479
Test name
Test status
Simulation time 22178244 ps
CPU time 1.03 seconds
Started May 09 01:02:50 PM PDT 24
Finished May 09 01:02:53 PM PDT 24
Peak memory 199896 kb
Host smart-bf3aa200-a3a7-468d-a5bf-1d17d4e860e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595809623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3595809623
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2443345214
Short name T535
Test name
Test status
Simulation time 345015954 ps
CPU time 2.5 seconds
Started May 09 01:02:48 PM PDT 24
Finished May 09 01:02:52 PM PDT 24
Peak memory 208320 kb
Host smart-cd758aae-88c5-426a-ac42-bab6fae1d4c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443345214 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2443345214
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.267513188
Short name T589
Test name
Test status
Simulation time 13380337 ps
CPU time 0.71 seconds
Started May 09 01:02:52 PM PDT 24
Finished May 09 01:02:55 PM PDT 24
Peak memory 198024 kb
Host smart-7479c70e-9886-4d14-ade2-d279d55adc2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267513188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.267513188
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.672425621
Short name T478
Test name
Test status
Simulation time 23895356 ps
CPU time 0.61 seconds
Started May 09 01:02:50 PM PDT 24
Finished May 09 01:02:52 PM PDT 24
Peak memory 194860 kb
Host smart-a80cefc4-1e80-4e2b-b3c5-3234c280e3e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672425621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.672425621
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1932878567
Short name T498
Test name
Test status
Simulation time 308618573 ps
CPU time 2.37 seconds
Started May 09 01:02:51 PM PDT 24
Finished May 09 01:02:55 PM PDT 24
Peak memory 200052 kb
Host smart-14028c1d-d3d5-430e-84ad-e625c77f2799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932878567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1932878567
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.960038614
Short name T520
Test name
Test status
Simulation time 87502882 ps
CPU time 1.54 seconds
Started May 09 01:02:49 PM PDT 24
Finished May 09 01:02:53 PM PDT 24
Peak memory 200044 kb
Host smart-930b3417-3f81-4d05-b628-9fa605f22351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960038614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.960038614
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3157318667
Short name T563
Test name
Test status
Simulation time 1783288296 ps
CPU time 8.56 seconds
Started May 09 01:02:49 PM PDT 24
Finished May 09 01:03:00 PM PDT 24
Peak memory 200024 kb
Host smart-5afbba02-1c51-4e91-965d-d8b109c2c18d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157318667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3157318667
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4187770814
Short name T484
Test name
Test status
Simulation time 130135243 ps
CPU time 5.16 seconds
Started May 09 01:02:51 PM PDT 24
Finished May 09 01:02:58 PM PDT 24
Peak memory 200028 kb
Host smart-f643199e-782a-45fc-9ede-8708fc852e00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187770814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4187770814
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.931141579
Short name T80
Test name
Test status
Simulation time 145939364 ps
CPU time 0.89 seconds
Started May 09 01:02:47 PM PDT 24
Finished May 09 01:02:50 PM PDT 24
Peak memory 199420 kb
Host smart-5cacf9fb-510f-41fe-a85f-63148cbfdba8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931141579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.931141579
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2452514161
Short name T503
Test name
Test status
Simulation time 183503468 ps
CPU time 1.34 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:08 PM PDT 24
Peak memory 199840 kb
Host smart-9a90087c-adfa-46cd-a1b0-e99f527a7ae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452514161 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2452514161
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1419699188
Short name T103
Test name
Test status
Simulation time 26488743 ps
CPU time 0.86 seconds
Started May 09 01:02:47 PM PDT 24
Finished May 09 01:02:49 PM PDT 24
Peak memory 199672 kb
Host smart-97eef611-857a-4f9f-8211-f8b2b47633c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419699188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1419699188
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4289595971
Short name T508
Test name
Test status
Simulation time 16611967 ps
CPU time 0.64 seconds
Started May 09 01:02:52 PM PDT 24
Finished May 09 01:02:54 PM PDT 24
Peak memory 194912 kb
Host smart-fa33ab44-aa55-4ab9-b73d-13a24fb64099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289595971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4289595971
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1386476861
Short name T570
Test name
Test status
Simulation time 32385502 ps
CPU time 1.01 seconds
Started May 09 01:02:50 PM PDT 24
Finished May 09 01:02:53 PM PDT 24
Peak memory 198456 kb
Host smart-727f75d2-4b33-46aa-92c9-9b7fe3eb279e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386476861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1386476861
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.786977253
Short name T524
Test name
Test status
Simulation time 147315715 ps
CPU time 3.99 seconds
Started May 09 01:02:51 PM PDT 24
Finished May 09 01:02:57 PM PDT 24
Peak memory 200056 kb
Host smart-82efb8b7-81b4-4749-a97b-0688ef38c636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786977253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.786977253
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3667270056
Short name T555
Test name
Test status
Simulation time 243614537 ps
CPU time 4.44 seconds
Started May 09 01:02:48 PM PDT 24
Finished May 09 01:02:54 PM PDT 24
Peak memory 200088 kb
Host smart-026e5ccb-af97-4f38-a1fd-9dfae9b68b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667270056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3667270056
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4140591673
Short name T553
Test name
Test status
Simulation time 246368686 ps
CPU time 1.84 seconds
Started May 09 01:03:17 PM PDT 24
Finished May 09 01:03:20 PM PDT 24
Peak memory 200160 kb
Host smart-e13b58b2-adf0-4fa5-9b67-fcdbe3b0df1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140591673 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4140591673
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3172374124
Short name T579
Test name
Test status
Simulation time 48891529 ps
CPU time 0.74 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 197648 kb
Host smart-2e3a638f-4293-44d8-a595-eb1e655949b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172374124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3172374124
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.8567108
Short name T539
Test name
Test status
Simulation time 20654111 ps
CPU time 0.59 seconds
Started May 09 01:03:07 PM PDT 24
Finished May 09 01:03:10 PM PDT 24
Peak memory 194876 kb
Host smart-b459cb75-89a6-4856-831f-36a4a5da6d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8567108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.8567108
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3452843113
Short name T497
Test name
Test status
Simulation time 36661821 ps
CPU time 1.69 seconds
Started May 09 01:03:13 PM PDT 24
Finished May 09 01:03:17 PM PDT 24
Peak memory 199896 kb
Host smart-d820a50b-22ec-4f22-b89c-66f89b697d7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452843113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3452843113
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4051324325
Short name T526
Test name
Test status
Simulation time 155390245 ps
CPU time 2.89 seconds
Started May 09 01:03:17 PM PDT 24
Finished May 09 01:03:21 PM PDT 24
Peak memory 200044 kb
Host smart-d131800f-9b62-4083-802a-02224e01989e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051324325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4051324325
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1639346408
Short name T58
Test name
Test status
Simulation time 205543222 ps
CPU time 1.77 seconds
Started May 09 01:03:12 PM PDT 24
Finished May 09 01:03:17 PM PDT 24
Peak memory 200028 kb
Host smart-cc1e2b04-48f4-4e37-bdef-e4a2f4c9951b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639346408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1639346408
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.476266433
Short name T596
Test name
Test status
Simulation time 33139597 ps
CPU time 1.03 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 199832 kb
Host smart-7df8242b-7a32-443d-8e83-3e0495139ab0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476266433 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.476266433
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1018230003
Short name T97
Test name
Test status
Simulation time 15665781 ps
CPU time 0.83 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 199280 kb
Host smart-829d0237-b17a-46c8-89d1-4e2a61e9b8ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018230003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1018230003
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1065959058
Short name T575
Test name
Test status
Simulation time 16298806 ps
CPU time 0.61 seconds
Started May 09 01:03:11 PM PDT 24
Finished May 09 01:03:15 PM PDT 24
Peak memory 194932 kb
Host smart-98114044-5801-4e0c-b17e-75a14359100d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065959058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1065959058
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3182613619
Short name T583
Test name
Test status
Simulation time 128360205 ps
CPU time 1.8 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 200040 kb
Host smart-8c7da7b7-873b-4e60-8438-3725a0113301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182613619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3182613619
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4106026648
Short name T67
Test name
Test status
Simulation time 484252643 ps
CPU time 2.72 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 200080 kb
Host smart-210043d7-21e3-4cda-b374-dcdd8df03a79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106026648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4106026648
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1145839198
Short name T562
Test name
Test status
Simulation time 60747420 ps
CPU time 1.08 seconds
Started May 09 01:03:18 PM PDT 24
Finished May 09 01:03:20 PM PDT 24
Peak memory 199860 kb
Host smart-57b42f73-ce91-4e3c-9a15-13a56e0ad154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145839198 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1145839198
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3266379212
Short name T84
Test name
Test status
Simulation time 17897207 ps
CPU time 0.65 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 194868 kb
Host smart-0aa5b0f6-577e-4a63-93ce-f6c9c5d30875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266379212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3266379212
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2926939557
Short name T485
Test name
Test status
Simulation time 44842551 ps
CPU time 2 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:15 PM PDT 24
Peak memory 199676 kb
Host smart-69f21ea9-f9df-4de8-8535-b52a2b4efd81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926939557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2926939557
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1234922761
Short name T517
Test name
Test status
Simulation time 53626273 ps
CPU time 1.33 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 200052 kb
Host smart-d94c96b9-91e2-4325-af08-53b8c45e1e3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234922761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1234922761
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.553394724
Short name T548
Test name
Test status
Simulation time 230028990 ps
CPU time 2.51 seconds
Started May 09 01:03:11 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 200120 kb
Host smart-56baae87-7482-40b6-8e65-0dfc5fee2cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553394724 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.553394724
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4207156423
Short name T594
Test name
Test status
Simulation time 22642324 ps
CPU time 0.83 seconds
Started May 09 01:03:11 PM PDT 24
Finished May 09 01:03:15 PM PDT 24
Peak memory 199340 kb
Host smart-080d842f-87c5-491e-9939-eca9c25519a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207156423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.4207156423
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3928911948
Short name T82
Test name
Test status
Simulation time 142738232 ps
CPU time 0.62 seconds
Started May 09 01:03:13 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 194764 kb
Host smart-84afe7f5-2469-496e-9b56-9b4db44f987d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928911948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3928911948
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1261264270
Short name T62
Test name
Test status
Simulation time 42028458 ps
CPU time 2.04 seconds
Started May 09 01:03:13 PM PDT 24
Finished May 09 01:03:17 PM PDT 24
Peak memory 199928 kb
Host smart-ea409ef3-c402-464a-aab0-eaafaabbd27c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261264270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1261264270
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2063352520
Short name T68
Test name
Test status
Simulation time 70513893 ps
CPU time 3.39 seconds
Started May 09 01:03:14 PM PDT 24
Finished May 09 01:03:20 PM PDT 24
Peak memory 199944 kb
Host smart-590c7442-d7eb-440b-9ee7-127a93c33a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063352520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2063352520
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2559068529
Short name T132
Test name
Test status
Simulation time 86067502 ps
CPU time 2.78 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 200088 kb
Host smart-b39b6a96-036f-431c-9e86-7fa44a87f1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559068529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2559068529
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1709720290
Short name T557
Test name
Test status
Simulation time 40859659759 ps
CPU time 623.9 seconds
Started May 09 01:03:11 PM PDT 24
Finished May 09 01:13:38 PM PDT 24
Peak memory 216688 kb
Host smart-a0378121-2ea9-4eb4-aa39-8b05c1aa7ecb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709720290 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1709720290
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3337113247
Short name T95
Test name
Test status
Simulation time 32687036 ps
CPU time 0.88 seconds
Started May 09 01:03:13 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 199384 kb
Host smart-3fb5f9a9-975e-43bb-acb9-2783799d6bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337113247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3337113247
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1878392117
Short name T512
Test name
Test status
Simulation time 16966062 ps
CPU time 0.59 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 194832 kb
Host smart-bbfed59a-857f-44c5-8cc4-7c25c6f92b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878392117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1878392117
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1543494235
Short name T543
Test name
Test status
Simulation time 102207844 ps
CPU time 1.96 seconds
Started May 09 01:03:17 PM PDT 24
Finished May 09 01:03:20 PM PDT 24
Peak memory 200040 kb
Host smart-a7dd2d40-c2d6-4c81-9441-24a5bdf02fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543494235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1543494235
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2704567932
Short name T514
Test name
Test status
Simulation time 1734089145 ps
CPU time 2.2 seconds
Started May 09 01:03:12 PM PDT 24
Finished May 09 01:03:17 PM PDT 24
Peak memory 200084 kb
Host smart-3a225e6b-1367-4858-9d71-a05ea1466249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704567932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2704567932
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1292059852
Short name T131
Test name
Test status
Simulation time 98551265 ps
CPU time 1.87 seconds
Started May 09 01:03:18 PM PDT 24
Finished May 09 01:03:20 PM PDT 24
Peak memory 200024 kb
Host smart-744009e2-0034-43db-88b5-1e67e0ef2a59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292059852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1292059852
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.405564892
Short name T515
Test name
Test status
Simulation time 67129493 ps
CPU time 1.85 seconds
Started May 09 01:03:19 PM PDT 24
Finished May 09 01:03:23 PM PDT 24
Peak memory 200096 kb
Host smart-7a71cbbe-343f-46e0-a643-95396f9dc8c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405564892 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.405564892
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2883387508
Short name T566
Test name
Test status
Simulation time 72220328 ps
CPU time 0.7 seconds
Started May 09 01:03:13 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 198072 kb
Host smart-62a9c262-bc48-418d-b46c-d3b14f93140d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883387508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2883387508
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2862782449
Short name T550
Test name
Test status
Simulation time 26411150 ps
CPU time 0.63 seconds
Started May 09 01:03:11 PM PDT 24
Finished May 09 01:03:15 PM PDT 24
Peak memory 195028 kb
Host smart-74c6e257-8655-455a-b382-a8cc24087f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862782449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2862782449
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1841533358
Short name T544
Test name
Test status
Simulation time 425255937 ps
CPU time 1.83 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 199180 kb
Host smart-cddfc352-4823-4103-bfb7-195a0f7923ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841533358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1841533358
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3622941230
Short name T523
Test name
Test status
Simulation time 69178026 ps
CPU time 2.6 seconds
Started May 09 01:03:16 PM PDT 24
Finished May 09 01:03:20 PM PDT 24
Peak memory 200104 kb
Host smart-2855b5b8-b14a-4b2e-8f04-6c04813ce2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622941230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3622941230
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2251878341
Short name T598
Test name
Test status
Simulation time 355608219 ps
CPU time 3.18 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 200060 kb
Host smart-96da530c-ec1e-4c0c-85f9-2e6b0bc52e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251878341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2251878341
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2985606580
Short name T64
Test name
Test status
Simulation time 104669521 ps
CPU time 3.7 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:30 PM PDT 24
Peak memory 208320 kb
Host smart-b2eeb009-1a6f-451e-8751-d23fe4234ea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985606580 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2985606580
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3026255319
Short name T561
Test name
Test status
Simulation time 47064397 ps
CPU time 0.79 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:23 PM PDT 24
Peak memory 199044 kb
Host smart-9fee1ed3-ad30-4764-aabc-607b8514300b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026255319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3026255319
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.708408282
Short name T559
Test name
Test status
Simulation time 14720860 ps
CPU time 0.63 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194868 kb
Host smart-938c8b90-375f-4f81-b4da-6d9523acd630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708408282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.708408282
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4169387422
Short name T492
Test name
Test status
Simulation time 129979070 ps
CPU time 1.14 seconds
Started May 09 01:03:19 PM PDT 24
Finished May 09 01:03:21 PM PDT 24
Peak memory 198476 kb
Host smart-5cd7a457-6ba7-48d8-b3f2-f218957f31ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169387422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.4169387422
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1736541669
Short name T595
Test name
Test status
Simulation time 89727875 ps
CPU time 2.31 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:24 PM PDT 24
Peak memory 200160 kb
Host smart-3c51ac36-73ab-43bd-8b26-52fb3cd69017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736541669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1736541669
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2750531070
Short name T66
Test name
Test status
Simulation time 87432573 ps
CPU time 1.24 seconds
Started May 09 01:03:19 PM PDT 24
Finished May 09 01:03:22 PM PDT 24
Peak memory 199900 kb
Host smart-da62f52a-7025-4241-8966-6618ce17cabb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750531070 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2750531070
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2692212078
Short name T585
Test name
Test status
Simulation time 248235957 ps
CPU time 0.83 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:23 PM PDT 24
Peak memory 199524 kb
Host smart-6010c964-30ba-401e-b838-fb8e6c106ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692212078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2692212078
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2175034608
Short name T519
Test name
Test status
Simulation time 13292789 ps
CPU time 0.59 seconds
Started May 09 01:03:25 PM PDT 24
Finished May 09 01:03:29 PM PDT 24
Peak memory 194928 kb
Host smart-6f6c87f3-7509-412b-829f-2fecf48334b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175034608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2175034608
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.259563605
Short name T63
Test name
Test status
Simulation time 104975402 ps
CPU time 1.89 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 200044 kb
Host smart-547bf66d-6add-4b8e-9c93-bc0fbfc650de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259563605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.259563605
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3862342248
Short name T541
Test name
Test status
Simulation time 164527391 ps
CPU time 2.3 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 200060 kb
Host smart-fa1ef468-12bc-4c09-8ae3-597afc65ca9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862342248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3862342248
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1010809318
Short name T124
Test name
Test status
Simulation time 232584796 ps
CPU time 4.41 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:31 PM PDT 24
Peak memory 200100 kb
Host smart-f2c677c2-72ae-4f16-9406-1cfadf622432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010809318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1010809318
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2455798635
Short name T599
Test name
Test status
Simulation time 41654074 ps
CPU time 1.78 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 200152 kb
Host smart-726767fb-75ff-40ec-98b2-fd312d7c6104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455798635 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2455798635
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2308947453
Short name T567
Test name
Test status
Simulation time 17846302 ps
CPU time 0.71 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 197900 kb
Host smart-dd55e1e3-8892-483c-82a7-f5c88196692e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308947453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2308947453
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2180170827
Short name T531
Test name
Test status
Simulation time 15045897 ps
CPU time 0.59 seconds
Started May 09 01:03:21 PM PDT 24
Finished May 09 01:03:24 PM PDT 24
Peak memory 194836 kb
Host smart-2bbf5254-4a02-4c52-b6cd-553b845ae716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180170827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2180170827
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2441461434
Short name T551
Test name
Test status
Simulation time 308246739 ps
CPU time 1.74 seconds
Started May 09 01:03:21 PM PDT 24
Finished May 09 01:03:25 PM PDT 24
Peak memory 200072 kb
Host smart-34b5f5f3-254c-46d3-b397-55e7449202c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441461434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2441461434
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4220612631
Short name T522
Test name
Test status
Simulation time 309598613 ps
CPU time 3.03 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:29 PM PDT 24
Peak memory 200024 kb
Host smart-6f8c0db9-6be8-4d5d-9599-9d950891916c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220612631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4220612631
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.910132439
Short name T525
Test name
Test status
Simulation time 100194849 ps
CPU time 1.92 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:24 PM PDT 24
Peak memory 200084 kb
Host smart-69f90726-fa53-4a97-87cc-fbefeaf1d53c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910132439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.910132439
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3742156881
Short name T496
Test name
Test status
Simulation time 46617309 ps
CPU time 2.71 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:29 PM PDT 24
Peak memory 200188 kb
Host smart-a4dee08b-4485-414a-80f5-0994ab809aa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742156881 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3742156881
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1046616393
Short name T506
Test name
Test status
Simulation time 85849134 ps
CPU time 0.69 seconds
Started May 09 01:03:21 PM PDT 24
Finished May 09 01:03:23 PM PDT 24
Peak memory 197572 kb
Host smart-fbab2ca5-d481-4059-b4c8-0734306c7872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046616393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1046616393
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1662443119
Short name T568
Test name
Test status
Simulation time 101379405 ps
CPU time 0.6 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:22 PM PDT 24
Peak memory 194888 kb
Host smart-409470b8-db89-4377-b7e8-1d061a0b892c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662443119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1662443119
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1372006583
Short name T569
Test name
Test status
Simulation time 735458269 ps
CPU time 2.4 seconds
Started May 09 01:03:21 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 200088 kb
Host smart-c639b303-f6bf-4ffd-ab14-578b058a659d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372006583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1372006583
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4273280212
Short name T92
Test name
Test status
Simulation time 172178187 ps
CPU time 1.37 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 200068 kb
Host smart-3278209a-bab0-48dd-bfad-c75803ebf6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273280212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.4273280212
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1854726669
Short name T128
Test name
Test status
Simulation time 189586036 ps
CPU time 3.01 seconds
Started May 09 01:03:25 PM PDT 24
Finished May 09 01:03:31 PM PDT 24
Peak memory 200072 kb
Host smart-0269559e-39e7-4f1a-b69c-6cf3a04220de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854726669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1854726669
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.182218950
Short name T560
Test name
Test status
Simulation time 437059190 ps
CPU time 7.83 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 199764 kb
Host smart-3cd909f9-2e4c-4b54-a305-f4847f4ad9a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182218950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.182218950
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.67291130
Short name T102
Test name
Test status
Simulation time 1067084414 ps
CPU time 11.49 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:18 PM PDT 24
Peak memory 199936 kb
Host smart-ded73f1e-a507-4f76-bde6-97fff9ae99ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67291130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.67291130
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2093196583
Short name T78
Test name
Test status
Simulation time 157399060 ps
CPU time 1.01 seconds
Started May 09 01:02:59 PM PDT 24
Finished May 09 01:03:01 PM PDT 24
Peak memory 199336 kb
Host smart-05bae0d3-3aa6-46db-a31e-92be170af79f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093196583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2093196583
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.136216070
Short name T554
Test name
Test status
Simulation time 168894058 ps
CPU time 2.49 seconds
Started May 09 01:03:02 PM PDT 24
Finished May 09 01:03:06 PM PDT 24
Peak memory 208280 kb
Host smart-e64500e7-c458-47f6-aa3f-2f2710e5af21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136216070 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.136216070
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2765776008
Short name T516
Test name
Test status
Simulation time 55330465 ps
CPU time 0.69 seconds
Started May 09 01:03:03 PM PDT 24
Finished May 09 01:03:05 PM PDT 24
Peak memory 197924 kb
Host smart-27b20056-07c0-4901-b116-3b98f0e7782d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765776008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2765776008
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1852107240
Short name T81
Test name
Test status
Simulation time 13241857 ps
CPU time 0.59 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:06 PM PDT 24
Peak memory 194920 kb
Host smart-595f81f5-73d9-44d6-97bf-b07b9f475309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852107240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1852107240
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2289882097
Short name T487
Test name
Test status
Simulation time 98724409 ps
CPU time 1.52 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:09 PM PDT 24
Peak memory 200036 kb
Host smart-ed559ab5-693f-41dc-967c-828d7949a640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289882097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2289882097
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2880584238
Short name T546
Test name
Test status
Simulation time 190888837 ps
CPU time 3.67 seconds
Started May 09 01:02:58 PM PDT 24
Finished May 09 01:03:03 PM PDT 24
Peak memory 200044 kb
Host smart-86349dd7-1f75-4c3f-bed0-3b80db9c044c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880584238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2880584238
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2481231043
Short name T125
Test name
Test status
Simulation time 96727283 ps
CPU time 2.78 seconds
Started May 09 01:02:58 PM PDT 24
Finished May 09 01:03:02 PM PDT 24
Peak memory 200076 kb
Host smart-0ae0be68-8b64-4b0d-b0a0-f45c00a3c912
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481231043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2481231043
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3092972920
Short name T509
Test name
Test status
Simulation time 32644449 ps
CPU time 0.58 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:28 PM PDT 24
Peak memory 194856 kb
Host smart-5c63debd-617e-418c-97fa-3e54ecb25f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092972920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3092972920
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2606665311
Short name T500
Test name
Test status
Simulation time 12463776 ps
CPU time 0.61 seconds
Started May 09 01:03:24 PM PDT 24
Finished May 09 01:03:28 PM PDT 24
Peak memory 194972 kb
Host smart-9c07c41d-305c-414a-8cbf-e7ef975644db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606665311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2606665311
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.4020336923
Short name T540
Test name
Test status
Simulation time 35135126 ps
CPU time 0.62 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:23 PM PDT 24
Peak memory 194872 kb
Host smart-8b90aff7-3dab-4640-b8db-e2a31b132850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020336923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4020336923
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2266008281
Short name T582
Test name
Test status
Simulation time 11234312 ps
CPU time 0.59 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:28 PM PDT 24
Peak memory 194788 kb
Host smart-094461cf-ca4e-488c-a6b0-5f4c476f5b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266008281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2266008281
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1163978423
Short name T480
Test name
Test status
Simulation time 13014993 ps
CPU time 0.66 seconds
Started May 09 01:03:24 PM PDT 24
Finished May 09 01:03:29 PM PDT 24
Peak memory 194976 kb
Host smart-db797138-2790-4841-98b2-79263c0d9614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163978423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1163978423
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1931995691
Short name T597
Test name
Test status
Simulation time 12121699 ps
CPU time 0.56 seconds
Started May 09 01:03:25 PM PDT 24
Finished May 09 01:03:29 PM PDT 24
Peak memory 194516 kb
Host smart-541934a9-d654-4458-96e3-8ccf6160c4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931995691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1931995691
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1404701746
Short name T552
Test name
Test status
Simulation time 25805342 ps
CPU time 0.61 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194940 kb
Host smart-e269fbd9-3948-438e-8eb6-75f3f9068dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404701746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1404701746
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2239409411
Short name T502
Test name
Test status
Simulation time 18526181 ps
CPU time 0.57 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194800 kb
Host smart-36e72e22-811c-4517-8321-2eb8cfecba98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239409411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2239409411
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3258053420
Short name T600
Test name
Test status
Simulation time 12334819 ps
CPU time 0.59 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 194884 kb
Host smart-033970c3-a317-46be-a330-d8e2b3ef4874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258053420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3258053420
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1972934174
Short name T528
Test name
Test status
Simulation time 13329264 ps
CPU time 0.6 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194900 kb
Host smart-97c18ce6-4150-4c44-a187-224b4d7e5c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972934174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1972934174
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1825087928
Short name T99
Test name
Test status
Simulation time 332854449 ps
CPU time 3.3 seconds
Started May 09 01:02:56 PM PDT 24
Finished May 09 01:03:00 PM PDT 24
Peak memory 200020 kb
Host smart-bda26f3c-ee66-4c6a-ac07-c25302ce9b23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825087928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1825087928
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3357582568
Short name T549
Test name
Test status
Simulation time 1100658246 ps
CPU time 15.84 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:22 PM PDT 24
Peak memory 199988 kb
Host smart-9785e9b6-238b-40c9-939c-59caf8370b2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357582568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3357582568
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2730118030
Short name T495
Test name
Test status
Simulation time 37083735 ps
CPU time 1 seconds
Started May 09 01:02:57 PM PDT 24
Finished May 09 01:02:59 PM PDT 24
Peak memory 199828 kb
Host smart-740ea4f6-a5c1-473d-a2b6-a4b27a5645a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730118030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2730118030
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.558337638
Short name T518
Test name
Test status
Simulation time 288389460 ps
CPU time 2.09 seconds
Started May 09 01:03:02 PM PDT 24
Finished May 09 01:03:05 PM PDT 24
Peak memory 200060 kb
Host smart-2f6edcba-4bd4-4416-aeba-0d3b842f5654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558337638 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.558337638
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.444999807
Short name T507
Test name
Test status
Simulation time 119862471 ps
CPU time 0.94 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:22 PM PDT 24
Peak memory 199788 kb
Host smart-16ba7089-bdb5-4596-a7ff-0b05c9aec1de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444999807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.444999807
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.594575303
Short name T532
Test name
Test status
Simulation time 17064676 ps
CPU time 0.65 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:06 PM PDT 24
Peak memory 194948 kb
Host smart-945c42af-f615-447d-9057-522056e972cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594575303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.594575303
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4209510853
Short name T513
Test name
Test status
Simulation time 255207231 ps
CPU time 2.24 seconds
Started May 09 01:03:06 PM PDT 24
Finished May 09 01:03:11 PM PDT 24
Peak memory 200156 kb
Host smart-6b4a68c8-22e4-4fe9-99d7-44880bc3498e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209510853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4209510853
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4282440142
Short name T588
Test name
Test status
Simulation time 269692005 ps
CPU time 2.52 seconds
Started May 09 01:03:01 PM PDT 24
Finished May 09 01:03:05 PM PDT 24
Peak memory 200100 kb
Host smart-cbcf7cbd-90e2-40b5-8c63-a9e815bb4b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282440142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4282440142
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3745203036
Short name T580
Test name
Test status
Simulation time 617277008 ps
CPU time 2.96 seconds
Started May 09 01:02:58 PM PDT 24
Finished May 09 01:03:02 PM PDT 24
Peak memory 200072 kb
Host smart-cead9015-cee7-4403-8d66-52244f053056
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745203036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3745203036
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1511605580
Short name T584
Test name
Test status
Simulation time 26766178 ps
CPU time 0.6 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:25 PM PDT 24
Peak memory 194988 kb
Host smart-701c7e45-42f1-4516-9827-a3a622e2a7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511605580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1511605580
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.616698616
Short name T501
Test name
Test status
Simulation time 64626164 ps
CPU time 0.62 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 194848 kb
Host smart-91eb4d5f-01d0-4d1f-ad19-b390bd4af650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616698616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.616698616
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1458261490
Short name T538
Test name
Test status
Simulation time 26039668 ps
CPU time 0.59 seconds
Started May 09 01:03:21 PM PDT 24
Finished May 09 01:03:24 PM PDT 24
Peak memory 194924 kb
Host smart-49d2c32e-62cf-45bf-acdb-38daa8890593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458261490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1458261490
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.806178057
Short name T556
Test name
Test status
Simulation time 32410965 ps
CPU time 0.6 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194864 kb
Host smart-b2d62e11-eb88-4594-92c1-6529f9c8b011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806178057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.806178057
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3588582508
Short name T536
Test name
Test status
Simulation time 29191253 ps
CPU time 0.6 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 194896 kb
Host smart-5935d13c-5796-42b1-8eb1-909bb7732da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588582508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3588582508
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2077413525
Short name T483
Test name
Test status
Simulation time 20834706 ps
CPU time 0.64 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194976 kb
Host smart-15ee1860-72d0-476d-a802-eacdf140a6dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077413525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2077413525
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2431938393
Short name T578
Test name
Test status
Simulation time 53350983 ps
CPU time 0.66 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:23 PM PDT 24
Peak memory 194932 kb
Host smart-e7a8723f-5730-4e47-b65b-b474ef6fe359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431938393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2431938393
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3341789202
Short name T527
Test name
Test status
Simulation time 43363286 ps
CPU time 0.61 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:28 PM PDT 24
Peak memory 194852 kb
Host smart-2aa3969a-84c0-4d34-bc46-5dae3417c8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341789202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3341789202
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2846510427
Short name T481
Test name
Test status
Simulation time 20842167 ps
CPU time 0.58 seconds
Started May 09 01:03:21 PM PDT 24
Finished May 09 01:03:25 PM PDT 24
Peak memory 194860 kb
Host smart-e28508ef-1530-4882-9ef7-9844146b47c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846510427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2846510427
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.362031420
Short name T486
Test name
Test status
Simulation time 11367392 ps
CPU time 0.6 seconds
Started May 09 01:03:20 PM PDT 24
Finished May 09 01:03:23 PM PDT 24
Peak memory 194980 kb
Host smart-2e1f33a0-5a28-46af-a68e-716eb29fd4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362031420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.362031420
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3567639638
Short name T96
Test name
Test status
Simulation time 304265291 ps
CPU time 3.18 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:11 PM PDT 24
Peak memory 198868 kb
Host smart-385273c2-6e11-4459-ab72-c0829c7e91ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567639638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3567639638
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.448152983
Short name T94
Test name
Test status
Simulation time 309473001 ps
CPU time 13.74 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:20 PM PDT 24
Peak memory 198968 kb
Host smart-97efd73a-72ea-43df-8b76-33b078620eba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448152983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.448152983
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3210391219
Short name T100
Test name
Test status
Simulation time 100504567 ps
CPU time 0.91 seconds
Started May 09 01:03:02 PM PDT 24
Finished May 09 01:03:05 PM PDT 24
Peak memory 199144 kb
Host smart-addd7037-ec74-434e-8793-c7548df6b0db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210391219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3210391219
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.29840079
Short name T591
Test name
Test status
Simulation time 96273775 ps
CPU time 2.26 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:09 PM PDT 24
Peak memory 200016 kb
Host smart-7bcdde94-cf88-410a-8fa4-0ef41ca623cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29840079 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.29840079
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.334895817
Short name T537
Test name
Test status
Simulation time 61162096 ps
CPU time 0.94 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:12 PM PDT 24
Peak memory 199640 kb
Host smart-123c41c6-43ac-40c3-9ac0-73d28b10e485
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334895817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.334895817
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4060186346
Short name T534
Test name
Test status
Simulation time 16939352 ps
CPU time 0.59 seconds
Started May 09 01:03:03 PM PDT 24
Finished May 09 01:03:04 PM PDT 24
Peak memory 194880 kb
Host smart-3b3e7709-8fd9-4e47-a1ee-318c9ed72e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060186346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4060186346
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3923829825
Short name T574
Test name
Test status
Simulation time 396255201 ps
CPU time 1.13 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:12 PM PDT 24
Peak memory 198496 kb
Host smart-25f9056f-37c9-4946-8c9e-227b7c62fb9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923829825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3923829825
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2888228708
Short name T547
Test name
Test status
Simulation time 91496352 ps
CPU time 2.16 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:09 PM PDT 24
Peak memory 199972 kb
Host smart-442b2fa5-0b20-443e-980a-b678ccbc8118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888228708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2888228708
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3373781757
Short name T530
Test name
Test status
Simulation time 478656845 ps
CPU time 3.85 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:10 PM PDT 24
Peak memory 200112 kb
Host smart-44b49ae9-d196-455e-ae6c-f02365639fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373781757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3373781757
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.390925788
Short name T521
Test name
Test status
Simulation time 28507571 ps
CPU time 0.62 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:25 PM PDT 24
Peak memory 194972 kb
Host smart-1c1c0eb4-a340-497c-aeb4-d544d16c7f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390925788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.390925788
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3922111193
Short name T529
Test name
Test status
Simulation time 45658325 ps
CPU time 0.6 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:25 PM PDT 24
Peak memory 194860 kb
Host smart-1123339b-41b8-476b-ad5c-a5c5133b4f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922111193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3922111193
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3404388353
Short name T586
Test name
Test status
Simulation time 41354494 ps
CPU time 0.56 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194796 kb
Host smart-d39aa40b-da09-4d40-9eef-20a5c8b2095c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404388353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3404388353
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1061164469
Short name T491
Test name
Test status
Simulation time 100366225 ps
CPU time 0.57 seconds
Started May 09 01:03:24 PM PDT 24
Finished May 09 01:03:29 PM PDT 24
Peak memory 194872 kb
Host smart-43e1f00e-4b52-4089-b1ec-8c144589f2f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061164469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1061164469
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2787637408
Short name T490
Test name
Test status
Simulation time 56992711 ps
CPU time 0.61 seconds
Started May 09 01:03:25 PM PDT 24
Finished May 09 01:03:29 PM PDT 24
Peak memory 194540 kb
Host smart-f024b17b-4196-4bda-9dff-88822be9b996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787637408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2787637408
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2212766177
Short name T499
Test name
Test status
Simulation time 15488196 ps
CPU time 0.63 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 195008 kb
Host smart-86b8dcac-a305-42e3-9419-585374dbdf43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212766177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2212766177
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3689961130
Short name T493
Test name
Test status
Simulation time 42138721 ps
CPU time 0.61 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194872 kb
Host smart-b1e16ce3-d340-4f57-bed2-c5dce4a2933b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689961130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3689961130
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3807052704
Short name T122
Test name
Test status
Simulation time 12216676 ps
CPU time 0.6 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:26 PM PDT 24
Peak memory 194884 kb
Host smart-a8c1fc29-88fc-496f-9a1b-362bbde1358d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807052704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3807052704
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4266626680
Short name T510
Test name
Test status
Simulation time 14219013 ps
CPU time 0.58 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:27 PM PDT 24
Peak memory 194944 kb
Host smart-42836a59-4822-4137-b973-a6a1ee3c722b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266626680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4266626680
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2288271948
Short name T581
Test name
Test status
Simulation time 27151752 ps
CPU time 0.59 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:28 PM PDT 24
Peak memory 194908 kb
Host smart-6534b986-9948-4f0a-82d9-d1b59b51eb58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288271948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2288271948
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2075038909
Short name T504
Test name
Test status
Simulation time 257213021 ps
CPU time 1.8 seconds
Started May 09 01:03:07 PM PDT 24
Finished May 09 01:03:11 PM PDT 24
Peak memory 200116 kb
Host smart-6bb79c12-7b91-4c2b-9729-7e88bf2cee59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075038909 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2075038909
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1913486712
Short name T105
Test name
Test status
Simulation time 148271780 ps
CPU time 0.82 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:08 PM PDT 24
Peak memory 199252 kb
Host smart-f3d610f2-c35a-4d7d-b8b7-b3618490925f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913486712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1913486712
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1739506131
Short name T577
Test name
Test status
Simulation time 41641981 ps
CPU time 0.61 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:07 PM PDT 24
Peak memory 194836 kb
Host smart-7a92b2f4-f429-402a-9837-4b667f8bc530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739506131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1739506131
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3873500195
Short name T572
Test name
Test status
Simulation time 48074540 ps
CPU time 1.09 seconds
Started May 09 01:03:06 PM PDT 24
Finished May 09 01:03:09 PM PDT 24
Peak memory 199792 kb
Host smart-7b7bb0cb-c907-4069-b5c9-2f4f29fe4972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873500195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3873500195
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2432184564
Short name T571
Test name
Test status
Simulation time 160330192 ps
CPU time 2.92 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:10 PM PDT 24
Peak memory 200048 kb
Host smart-1ce80a08-bb61-48e9-a5c2-edeab9a501d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432184564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2432184564
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3966180469
Short name T130
Test name
Test status
Simulation time 92144938 ps
CPU time 1.71 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:09 PM PDT 24
Peak memory 200116 kb
Host smart-d35f0051-45b0-4f27-b8b3-fcb0951318f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966180469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3966180469
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.498771344
Short name T592
Test name
Test status
Simulation time 164110903 ps
CPU time 1.18 seconds
Started May 09 01:03:06 PM PDT 24
Finished May 09 01:03:10 PM PDT 24
Peak memory 199808 kb
Host smart-c77a66c6-3751-4fd4-bc09-13f9e2213749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498771344 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.498771344
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2158788892
Short name T83
Test name
Test status
Simulation time 60847120 ps
CPU time 0.75 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:08 PM PDT 24
Peak memory 197876 kb
Host smart-fcb2b2e4-a047-480e-a87d-4dc97dc3d181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158788892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2158788892
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3940939450
Short name T564
Test name
Test status
Simulation time 16132376 ps
CPU time 0.6 seconds
Started May 09 01:03:03 PM PDT 24
Finished May 09 01:03:04 PM PDT 24
Peak memory 194872 kb
Host smart-4403e239-8d0b-4b37-891a-4cb14fe4bb25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940939450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3940939450
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1012038793
Short name T542
Test name
Test status
Simulation time 34275416 ps
CPU time 1.59 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 200092 kb
Host smart-c149b8e7-d437-4377-ae22-cf96dc87067e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012038793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1012038793
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1367511125
Short name T587
Test name
Test status
Simulation time 273024901 ps
CPU time 3.83 seconds
Started May 09 01:03:07 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 200036 kb
Host smart-d771e299-5fd7-41b1-a0af-7c50a58faf05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367511125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1367511125
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.561422528
Short name T123
Test name
Test status
Simulation time 351384030 ps
CPU time 2.91 seconds
Started May 09 01:03:07 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 199996 kb
Host smart-2333228e-f648-4210-8444-169090484ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561422528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.561422528
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1898504753
Short name T545
Test name
Test status
Simulation time 168438662 ps
CPU time 2.37 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:13 PM PDT 24
Peak memory 200172 kb
Host smart-38eaced6-0758-4fd5-bd16-60286c4d5a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898504753 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1898504753
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3842916343
Short name T505
Test name
Test status
Simulation time 26715845 ps
CPU time 0.84 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:08 PM PDT 24
Peak memory 199872 kb
Host smart-c82f9b25-77f9-40d7-aafb-9676d99fa0a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842916343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3842916343
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1856877776
Short name T565
Test name
Test status
Simulation time 146962802 ps
CPU time 0.59 seconds
Started May 09 01:03:05 PM PDT 24
Finished May 09 01:03:08 PM PDT 24
Peak memory 194984 kb
Host smart-e64b1427-bf5d-4dfe-9994-fdbfe780da6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856877776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1856877776
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2584045448
Short name T488
Test name
Test status
Simulation time 69982296 ps
CPU time 1.62 seconds
Started May 09 01:03:07 PM PDT 24
Finished May 09 01:03:12 PM PDT 24
Peak memory 200132 kb
Host smart-428bc167-f1d0-4a24-850b-10cf1b645dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584045448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2584045448
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.940358334
Short name T65
Test name
Test status
Simulation time 204644742 ps
CPU time 2.49 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 200076 kb
Host smart-41174f85-f29d-444d-b7bf-2cfd403231ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940358334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.940358334
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2742426747
Short name T126
Test name
Test status
Simulation time 413264444 ps
CPU time 1.73 seconds
Started May 09 01:03:04 PM PDT 24
Finished May 09 01:03:07 PM PDT 24
Peak memory 200044 kb
Host smart-d7486378-0ab8-456b-9d7e-38fee650ceb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742426747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2742426747
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.183499694
Short name T494
Test name
Test status
Simulation time 98527282 ps
CPU time 1.64 seconds
Started May 09 01:03:07 PM PDT 24
Finished May 09 01:03:11 PM PDT 24
Peak memory 200100 kb
Host smart-234cf5b4-1aca-4fc6-88ac-a317886ac909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183499694 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.183499694
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1598694934
Short name T98
Test name
Test status
Simulation time 19382726 ps
CPU time 0.9 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 199552 kb
Host smart-c93aa024-2ccf-45ab-999b-af74d4bf80db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598694934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1598694934
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2686862767
Short name T482
Test name
Test status
Simulation time 111780587 ps
CPU time 0.6 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:12 PM PDT 24
Peak memory 194936 kb
Host smart-56af3878-f30d-475d-8de7-36f5f48a1a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686862767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2686862767
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.324392709
Short name T573
Test name
Test status
Simulation time 307740443 ps
CPU time 1.71 seconds
Started May 09 01:03:09 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 200052 kb
Host smart-de8b93f4-1ed5-4a08-9f76-acc35fcfc6c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324392709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.324392709
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1822387709
Short name T576
Test name
Test status
Simulation time 671432522 ps
CPU time 3.75 seconds
Started May 09 01:03:06 PM PDT 24
Finished May 09 01:03:12 PM PDT 24
Peak memory 200092 kb
Host smart-48a2a079-5e46-448c-9aeb-49233dc409ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822387709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1822387709
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.157160884
Short name T129
Test name
Test status
Simulation time 722933920 ps
CPU time 4.1 seconds
Started May 09 01:03:06 PM PDT 24
Finished May 09 01:03:12 PM PDT 24
Peak memory 200004 kb
Host smart-2c23dc21-da68-4c62-8875-f63eb2f46325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157160884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.157160884
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1808372207
Short name T511
Test name
Test status
Simulation time 74854672 ps
CPU time 1.88 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:15 PM PDT 24
Peak memory 200124 kb
Host smart-6dbf3b61-f046-4d0d-bb0d-3589a0ac05c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808372207 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1808372207
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1060363691
Short name T489
Test name
Test status
Simulation time 37705086 ps
CPU time 0.8 seconds
Started May 09 01:03:17 PM PDT 24
Finished May 09 01:03:19 PM PDT 24
Peak memory 199160 kb
Host smart-3eb7eef8-2a14-4b29-923a-1b9c6144d304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060363691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1060363691
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1912237079
Short name T533
Test name
Test status
Simulation time 16364735 ps
CPU time 0.66 seconds
Started May 09 01:03:14 PM PDT 24
Finished May 09 01:03:17 PM PDT 24
Peak memory 194768 kb
Host smart-ddd618bb-dba3-4771-9d10-322387115095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912237079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1912237079
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1729635607
Short name T590
Test name
Test status
Simulation time 1018235112 ps
CPU time 1.64 seconds
Started May 09 01:03:11 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 200116 kb
Host smart-ba99f1c0-5684-4ed7-8e2d-965f6efc0583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729635607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1729635607
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2661724457
Short name T593
Test name
Test status
Simulation time 39606492 ps
CPU time 2.03 seconds
Started May 09 01:03:08 PM PDT 24
Finished May 09 01:03:14 PM PDT 24
Peak memory 200104 kb
Host smart-78bd090e-8796-49cf-ac84-5a03dceab224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661724457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2661724457
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4132384782
Short name T601
Test name
Test status
Simulation time 604496787 ps
CPU time 2.96 seconds
Started May 09 01:03:10 PM PDT 24
Finished May 09 01:03:16 PM PDT 24
Peak memory 200180 kb
Host smart-7f899a72-54b8-4321-9df0-a7f41bb7a776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132384782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4132384782
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1572314397
Short name T261
Test name
Test status
Simulation time 88546874 ps
CPU time 0.59 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:03:39 PM PDT 24
Peak memory 196328 kb
Host smart-4bf52e06-fc93-4525-8591-acdfa045c952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572314397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1572314397
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1747010786
Short name T48
Test name
Test status
Simulation time 1788248090 ps
CPU time 23.65 seconds
Started May 09 01:03:24 PM PDT 24
Finished May 09 01:03:51 PM PDT 24
Peak memory 223124 kb
Host smart-4161da03-9e08-4d0d-856f-60bf1fd18bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747010786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1747010786
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2680643584
Short name T323
Test name
Test status
Simulation time 857510026 ps
CPU time 18.22 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:45 PM PDT 24
Peak memory 200640 kb
Host smart-e1554850-924e-4f8e-bf5f-a80053691eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680643584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2680643584
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3203064820
Short name T139
Test name
Test status
Simulation time 10313860742 ps
CPU time 592.21 seconds
Started May 09 01:03:26 PM PDT 24
Finished May 09 01:13:21 PM PDT 24
Peak memory 691312 kb
Host smart-f4d45e8c-3c2e-4213-a203-c9bd14969813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203064820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3203064820
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3816051631
Short name T429
Test name
Test status
Simulation time 849423430 ps
CPU time 13.09 seconds
Started May 09 01:03:22 PM PDT 24
Finished May 09 01:03:39 PM PDT 24
Peak memory 200548 kb
Host smart-f23fa4dc-aeee-4620-a0f3-3d5371be6d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816051631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3816051631
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2143952211
Short name T433
Test name
Test status
Simulation time 213674303 ps
CPU time 4 seconds
Started May 09 01:03:23 PM PDT 24
Finished May 09 01:03:31 PM PDT 24
Peak memory 200632 kb
Host smart-191fdf57-577e-4dde-a756-3069c92df867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143952211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2143952211
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3656588217
Short name T405
Test name
Test status
Simulation time 29110361 ps
CPU time 1.01 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:03:39 PM PDT 24
Peak memory 200060 kb
Host smart-466785b2-07cb-4774-861d-8cab9a312fa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656588217 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3656588217
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1711382634
Short name T471
Test name
Test status
Simulation time 400710195059 ps
CPU time 498.72 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:11:55 PM PDT 24
Peak memory 200672 kb
Host smart-584a073f-1400-4e34-90f3-67c608e6cfc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711382634 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1711382634
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3599964426
Short name T194
Test name
Test status
Simulation time 80098511 ps
CPU time 0.62 seconds
Started May 09 01:03:30 PM PDT 24
Finished May 09 01:03:34 PM PDT 24
Peak memory 196268 kb
Host smart-515ef1e5-55f2-4487-ae72-28a2847756ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599964426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3599964426
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1622818933
Short name T327
Test name
Test status
Simulation time 792510568 ps
CPU time 40.46 seconds
Started May 09 01:03:31 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 229148 kb
Host smart-a6807aec-3c0e-4e47-8ceb-4c9e6ec6db4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622818933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1622818933
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3313970885
Short name T308
Test name
Test status
Simulation time 327464474 ps
CPU time 16.89 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:03:52 PM PDT 24
Peak memory 200540 kb
Host smart-eca7aede-7897-4a07-97f4-ddc76e0a0e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313970885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3313970885
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3324575912
Short name T163
Test name
Test status
Simulation time 4551896654 ps
CPU time 122.91 seconds
Started May 09 01:03:31 PM PDT 24
Finished May 09 01:05:38 PM PDT 24
Peak memory 442608 kb
Host smart-748a0bc3-917d-447a-8b28-c65ac014e1e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324575912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3324575912
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2516139028
Short name T153
Test name
Test status
Simulation time 977999960 ps
CPU time 56.24 seconds
Started May 09 01:03:33 PM PDT 24
Finished May 09 01:04:33 PM PDT 24
Peak memory 200616 kb
Host smart-b94329bb-0ba3-437d-b2d9-40ceff22691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516139028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2516139028
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2876636807
Short name T37
Test name
Test status
Simulation time 140014547 ps
CPU time 0.8 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:03:37 PM PDT 24
Peak memory 218908 kb
Host smart-f13f33e5-c792-4ece-ac92-6bf54681e894
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876636807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2876636807
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.705438269
Short name T54
Test name
Test status
Simulation time 484631012 ps
CPU time 2.96 seconds
Started May 09 01:03:33 PM PDT 24
Finished May 09 01:03:39 PM PDT 24
Peak memory 200592 kb
Host smart-260cafe4-9d16-49e4-88c2-a1906e04a959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705438269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.705438269
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2324377053
Short name T149
Test name
Test status
Simulation time 64897331 ps
CPU time 1 seconds
Started May 09 01:03:34 PM PDT 24
Finished May 09 01:03:38 PM PDT 24
Peak memory 199228 kb
Host smart-e62bd0c6-d1eb-4ea7-a608-6eb2aaf9c4db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324377053 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2324377053
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2257032260
Short name T184
Test name
Test status
Simulation time 7578228172 ps
CPU time 432.05 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:10:48 PM PDT 24
Peak memory 200744 kb
Host smart-aed9ba98-084a-4b92-9ce0-4e3e0ea46fab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257032260 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2257032260
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1427115708
Short name T395
Test name
Test status
Simulation time 26654878 ps
CPU time 0.62 seconds
Started May 09 01:03:59 PM PDT 24
Finished May 09 01:04:02 PM PDT 24
Peak memory 195240 kb
Host smart-78bd33ed-be80-4766-b4c3-19e8b92bb85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427115708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1427115708
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3850512774
Short name T179
Test name
Test status
Simulation time 286101960 ps
CPU time 14.93 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:12 PM PDT 24
Peak memory 203716 kb
Host smart-c5208600-54ac-4845-903e-e77c3e400196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850512774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3850512774
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2992258559
Short name T285
Test name
Test status
Simulation time 2610486927 ps
CPU time 50.11 seconds
Started May 09 01:03:56 PM PDT 24
Finished May 09 01:04:50 PM PDT 24
Peak memory 200656 kb
Host smart-2fab1817-9cb8-41ca-b2fe-7249a792bb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992258559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2992258559
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4103427534
Short name T150
Test name
Test status
Simulation time 113886069 ps
CPU time 1.26 seconds
Started May 09 01:03:55 PM PDT 24
Finished May 09 01:03:59 PM PDT 24
Peak memory 200492 kb
Host smart-218648c6-3108-423b-afbf-ab83cf63fa02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103427534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4103427534
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2860769423
Short name T468
Test name
Test status
Simulation time 4938998694 ps
CPU time 43.69 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:40 PM PDT 24
Peak memory 200548 kb
Host smart-5d8e323b-d8fb-4d95-8a58-47ddab66a838
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860769423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2860769423
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3712227562
Short name T447
Test name
Test status
Simulation time 1252184372 ps
CPU time 58.96 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:57 PM PDT 24
Peak memory 200568 kb
Host smart-7fd40c09-dd50-46d0-812d-3cfc537f445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712227562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3712227562
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3284757009
Short name T286
Test name
Test status
Simulation time 540189338 ps
CPU time 6.4 seconds
Started May 09 01:04:00 PM PDT 24
Finished May 09 01:04:08 PM PDT 24
Peak memory 200596 kb
Host smart-b8b0c0a8-fa05-4207-9388-f97c058edd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284757009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3284757009
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.179308682
Short name T33
Test name
Test status
Simulation time 99037623 ps
CPU time 0.94 seconds
Started May 09 01:03:53 PM PDT 24
Finished May 09 01:03:57 PM PDT 24
Peak memory 199032 kb
Host smart-385f75a4-6783-466d-94cb-addf3df9c59d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179308682 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.179308682
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2097177432
Short name T77
Test name
Test status
Simulation time 87849990888 ps
CPU time 573 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:13:30 PM PDT 24
Peak memory 200604 kb
Host smart-42828be3-fdb9-4289-9ba5-78aeaf251d51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097177432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.2097177432
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2508831567
Short name T201
Test name
Test status
Simulation time 19293146 ps
CPU time 0.59 seconds
Started May 09 01:03:57 PM PDT 24
Finished May 09 01:04:00 PM PDT 24
Peak memory 195220 kb
Host smart-da1e4780-be29-44fd-b9ca-76040f509353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508831567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2508831567
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.953048609
Short name T49
Test name
Test status
Simulation time 2428505581 ps
CPU time 29.36 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:27 PM PDT 24
Peak memory 217140 kb
Host smart-56b23200-916d-4175-8b1d-a56f206230e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953048609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.953048609
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2388649083
Short name T370
Test name
Test status
Simulation time 8159096213 ps
CPU time 37.91 seconds
Started May 09 01:04:00 PM PDT 24
Finished May 09 01:04:39 PM PDT 24
Peak memory 200760 kb
Host smart-6deef2c7-9eba-4016-9dc9-68c001a58330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388649083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2388649083
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1099842877
Short name T69
Test name
Test status
Simulation time 647109508 ps
CPU time 25.95 seconds
Started May 09 01:03:56 PM PDT 24
Finished May 09 01:04:25 PM PDT 24
Peak memory 299840 kb
Host smart-9def5c0f-799c-440e-a917-c5f8236c39aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099842877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1099842877
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1212605225
Short name T347
Test name
Test status
Simulation time 4349583435 ps
CPU time 16.61 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:14 PM PDT 24
Peak memory 200672 kb
Host smart-a1931e61-b4fa-490e-989b-601cc1deebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212605225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1212605225
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.533881498
Short name T230
Test name
Test status
Simulation time 1271442125 ps
CPU time 6.62 seconds
Started May 09 01:03:57 PM PDT 24
Finished May 09 01:04:07 PM PDT 24
Peak memory 200508 kb
Host smart-91d031b4-2994-498a-8376-953a266b0c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533881498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.533881498
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.4246557029
Short name T157
Test name
Test status
Simulation time 28616650 ps
CPU time 1 seconds
Started May 09 01:03:55 PM PDT 24
Finished May 09 01:03:59 PM PDT 24
Peak memory 200080 kb
Host smart-e3b64c76-158d-4e2d-90b5-f15faef1e768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246557029 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.4246557029
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2748002254
Short name T76
Test name
Test status
Simulation time 102589778267 ps
CPU time 458.01 seconds
Started May 09 01:03:53 PM PDT 24
Finished May 09 01:11:34 PM PDT 24
Peak memory 200660 kb
Host smart-afec12e9-c36b-4f14-a024-c4ea209d2ea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748002254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2748002254
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.928928658
Short name T28
Test name
Test status
Simulation time 6234035199 ps
CPU time 278.23 seconds
Started May 09 01:05:44 PM PDT 24
Finished May 09 01:10:24 PM PDT 24
Peak memory 605692 kb
Host smart-3ab728c0-0232-44cd-9568-d093999ac94a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928928658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.928928658
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4079828609
Short name T383
Test name
Test status
Simulation time 94864257 ps
CPU time 0.58 seconds
Started May 09 01:03:58 PM PDT 24
Finished May 09 01:04:01 PM PDT 24
Peak memory 196916 kb
Host smart-52f89b07-b52d-4cb9-90e4-99b87179b40a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079828609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4079828609
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1202076614
Short name T313
Test name
Test status
Simulation time 386548489 ps
CPU time 10 seconds
Started May 09 01:03:53 PM PDT 24
Finished May 09 01:04:05 PM PDT 24
Peak memory 200584 kb
Host smart-ad6ab024-8dcc-4cac-86e0-31742d34eb79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202076614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1202076614
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3705100680
Short name T328
Test name
Test status
Simulation time 18245812853 ps
CPU time 28.29 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:25 PM PDT 24
Peak memory 200732 kb
Host smart-f0a0050b-a1a1-43fd-9f7e-1ef6ca5dba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705100680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3705100680
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.617875074
Short name T136
Test name
Test status
Simulation time 6393403510 ps
CPU time 745.59 seconds
Started May 09 01:03:55 PM PDT 24
Finished May 09 01:16:23 PM PDT 24
Peak memory 668184 kb
Host smart-64f2dee3-5f22-410b-a666-cf73afbc5cf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617875074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.617875074
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2631291035
Short name T42
Test name
Test status
Simulation time 5492467721 ps
CPU time 37.18 seconds
Started May 09 01:03:56 PM PDT 24
Finished May 09 01:04:36 PM PDT 24
Peak memory 200608 kb
Host smart-de829bc3-210c-4c15-b095-2445a96a56f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631291035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2631291035
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1491784335
Short name T207
Test name
Test status
Simulation time 1454042522 ps
CPU time 4.93 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:03 PM PDT 24
Peak memory 200544 kb
Host smart-5b8fc765-0ab5-49b1-984a-916791f97b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491784335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1491784335
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2804994102
Short name T461
Test name
Test status
Simulation time 178151814 ps
CPU time 1.05 seconds
Started May 09 01:04:00 PM PDT 24
Finished May 09 01:04:03 PM PDT 24
Peak memory 200112 kb
Host smart-e2641b62-41f0-487a-819f-888d9f2b6a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804994102 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2804994102
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1095950513
Short name T398
Test name
Test status
Simulation time 8880434959 ps
CPU time 535.75 seconds
Started May 09 01:03:57 PM PDT 24
Finished May 09 01:12:56 PM PDT 24
Peak memory 200600 kb
Host smart-427a3b39-c011-41e5-97dd-3ef61578eb8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095950513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1095950513
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1126217578
Short name T391
Test name
Test status
Simulation time 15802901 ps
CPU time 0.62 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:03:57 PM PDT 24
Peak memory 196312 kb
Host smart-52280d7e-acaa-4a9c-bf00-8ea003982f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126217578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1126217578
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1779520634
Short name T288
Test name
Test status
Simulation time 1198002458 ps
CPU time 8.42 seconds
Started May 09 01:03:59 PM PDT 24
Finished May 09 01:04:10 PM PDT 24
Peak memory 208724 kb
Host smart-9b32b5ea-68ba-4680-bb03-59fc7de0d777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779520634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1779520634
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2591212833
Short name T382
Test name
Test status
Simulation time 120106051 ps
CPU time 6.68 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:04 PM PDT 24
Peak memory 200676 kb
Host smart-03d0da2f-198e-4d79-b303-7baf7f499ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591212833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2591212833
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.955686233
Short name T349
Test name
Test status
Simulation time 1763563585 ps
CPU time 341.98 seconds
Started May 09 01:03:58 PM PDT 24
Finished May 09 01:09:43 PM PDT 24
Peak memory 498420 kb
Host smart-a93ebc4e-ba10-4c4c-a510-c425dc0619e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955686233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.955686233
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_smoke.3216767046
Short name T265
Test name
Test status
Simulation time 732461773 ps
CPU time 5.93 seconds
Started May 09 01:03:59 PM PDT 24
Finished May 09 01:04:07 PM PDT 24
Peak memory 200540 kb
Host smart-8038203e-6c6f-4e1e-a994-d255f5176300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216767046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3216767046
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2130330557
Short name T411
Test name
Test status
Simulation time 218553333 ps
CPU time 1.38 seconds
Started May 09 01:03:58 PM PDT 24
Finished May 09 01:04:02 PM PDT 24
Peak memory 200424 kb
Host smart-6f77224a-9df7-497d-9cc9-b5c4c1bf4a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130330557 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2130330557
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2039931520
Short name T197
Test name
Test status
Simulation time 14970908605 ps
CPU time 435.73 seconds
Started May 09 01:04:01 PM PDT 24
Finished May 09 01:11:18 PM PDT 24
Peak memory 200636 kb
Host smart-bf00e91e-1400-444e-b412-1814cc2c3585
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039931520 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.2039931520
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.4108064293
Short name T463
Test name
Test status
Simulation time 93548140 ps
CPU time 1.53 seconds
Started May 09 01:04:05 PM PDT 24
Finished May 09 01:04:12 PM PDT 24
Peak memory 200436 kb
Host smart-52d62eb3-883f-4a4f-9756-6dff9d59ffb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108064293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4108064293
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3241168079
Short name T199
Test name
Test status
Simulation time 12838585942 ps
CPU time 40.69 seconds
Started May 09 01:04:05 PM PDT 24
Finished May 09 01:04:50 PM PDT 24
Peak memory 200760 kb
Host smart-3216ef7b-2e52-44b4-ac54-f5ac7f764ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241168079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3241168079
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3585083474
Short name T281
Test name
Test status
Simulation time 6307373516 ps
CPU time 786.17 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:17:20 PM PDT 24
Peak memory 689112 kb
Host smart-c2b35d95-f689-47dc-983d-522ffde9c846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585083474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3585083474
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1361353233
Short name T269
Test name
Test status
Simulation time 2183594867 ps
CPU time 38.44 seconds
Started May 09 01:04:04 PM PDT 24
Finished May 09 01:04:47 PM PDT 24
Peak memory 200644 kb
Host smart-f98fc9d2-3725-4263-9ee0-50cb94aa348e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361353233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1361353233
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.5889982
Short name T89
Test name
Test status
Simulation time 30758209661 ps
CPU time 100.92 seconds
Started May 09 01:03:55 PM PDT 24
Finished May 09 01:05:39 PM PDT 24
Peak memory 200552 kb
Host smart-6d4f36ac-74c6-452b-8957-c96505da08e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5889982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.5889982
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1306684278
Short name T247
Test name
Test status
Simulation time 1729947403 ps
CPU time 6.98 seconds
Started May 09 01:03:56 PM PDT 24
Finished May 09 01:04:06 PM PDT 24
Peak memory 200628 kb
Host smart-133fd301-e7de-460d-bce8-84c84073d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306684278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1306684278
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.767457708
Short name T146
Test name
Test status
Simulation time 307139308 ps
CPU time 1.4 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:14 PM PDT 24
Peak memory 199424 kb
Host smart-c9fd8050-0fc6-4987-9410-179eaf8acca9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767457708 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.767457708
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2996205737
Short name T229
Test name
Test status
Simulation time 443445167623 ps
CPU time 495.01 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:12:28 PM PDT 24
Peak memory 200604 kb
Host smart-8f241e16-4772-4be4-807d-196005fa8a13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996205737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2996205737
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2265084056
Short name T291
Test name
Test status
Simulation time 27342899 ps
CPU time 0.62 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:14 PM PDT 24
Peak memory 196316 kb
Host smart-d4a95967-8e0f-4c05-81c9-40e2354901a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265084056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2265084056
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3346396781
Short name T303
Test name
Test status
Simulation time 201519538 ps
CPU time 11.19 seconds
Started May 09 01:04:03 PM PDT 24
Finished May 09 01:04:18 PM PDT 24
Peak memory 208784 kb
Host smart-7e9ffc60-83a3-4f97-bbaa-313a87da2a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346396781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3346396781
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.643268331
Short name T431
Test name
Test status
Simulation time 1274146459 ps
CPU time 34.52 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:48 PM PDT 24
Peak memory 200516 kb
Host smart-d28b665f-7ce7-4249-befe-0712afce491b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643268331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.643268331
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.218832619
Short name T177
Test name
Test status
Simulation time 6969405994 ps
CPU time 898.4 seconds
Started May 09 01:04:04 PM PDT 24
Finished May 09 01:19:07 PM PDT 24
Peak memory 745032 kb
Host smart-43b589a8-3d9e-41b1-9868-bb503f6c5229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218832619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.218832619
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2125302742
Short name T458
Test name
Test status
Simulation time 1909498317 ps
CPU time 105.68 seconds
Started May 09 01:04:04 PM PDT 24
Finished May 09 01:05:54 PM PDT 24
Peak memory 200600 kb
Host smart-92c4003a-8c61-4c71-b3f0-fb04d5b531d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125302742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2125302742
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3168600664
Short name T290
Test name
Test status
Simulation time 8970319317 ps
CPU time 42.74 seconds
Started May 09 01:04:06 PM PDT 24
Finished May 09 01:04:53 PM PDT 24
Peak memory 200656 kb
Host smart-b35e8965-745e-4190-95cb-2dd3935bfccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168600664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3168600664
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2817235537
Short name T449
Test name
Test status
Simulation time 884375717 ps
CPU time 4.72 seconds
Started May 09 01:04:04 PM PDT 24
Finished May 09 01:04:13 PM PDT 24
Peak memory 200672 kb
Host smart-44f34c74-fb02-491b-924b-d08cc4e4f84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817235537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2817235537
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2506774781
Short name T380
Test name
Test status
Simulation time 52904093 ps
CPU time 1.11 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:14 PM PDT 24
Peak memory 200052 kb
Host smart-1e35f531-b29e-4d51-9dcc-f552635b3fe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506774781 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2506774781
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.159946153
Short name T237
Test name
Test status
Simulation time 8794502298 ps
CPU time 468.68 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:12:03 PM PDT 24
Peak memory 200712 kb
Host smart-7b8cb53f-ab54-420a-b042-1287d2777b66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159946153 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.159946153
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2107939978
Short name T322
Test name
Test status
Simulation time 24893271 ps
CPU time 0.6 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:13 PM PDT 24
Peak memory 195312 kb
Host smart-c2722546-31c1-47bb-bf64-788602a543b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107939978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2107939978
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1817991541
Short name T401
Test name
Test status
Simulation time 528828567 ps
CPU time 22.41 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:35 PM PDT 24
Peak memory 215856 kb
Host smart-372f4a40-bc0a-4724-be0a-caea30bb14a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817991541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1817991541
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.890158411
Short name T182
Test name
Test status
Simulation time 627252310 ps
CPU time 7.85 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:21 PM PDT 24
Peak memory 200476 kb
Host smart-f76d8f7f-162f-43f7-9f46-9b3ec6e3534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890158411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.890158411
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1291084158
Short name T166
Test name
Test status
Simulation time 127889550 ps
CPU time 7.45 seconds
Started May 09 01:04:06 PM PDT 24
Finished May 09 01:04:18 PM PDT 24
Peak memory 200648 kb
Host smart-fdea99bb-012f-49c6-9356-934cdb904ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291084158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1291084158
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.468971841
Short name T180
Test name
Test status
Simulation time 418261438 ps
CPU time 1.17 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 200500 kb
Host smart-8dae38af-ad6f-4a94-85a9-a56cd152b899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468971841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.468971841
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3616965455
Short name T326
Test name
Test status
Simulation time 27364673 ps
CPU time 1.03 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 199932 kb
Host smart-d020de8c-0ff4-475a-83b5-c0097ead10e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616965455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3616965455
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2767435277
Short name T464
Test name
Test status
Simulation time 121910317386 ps
CPU time 437.34 seconds
Started May 09 01:04:06 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 200600 kb
Host smart-b9a274ea-0847-4ab2-b76d-2c573b2aa898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767435277 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2767435277
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3313458673
Short name T319
Test name
Test status
Simulation time 38234927 ps
CPU time 0.59 seconds
Started May 09 01:04:03 PM PDT 24
Finished May 09 01:04:08 PM PDT 24
Peak memory 195980 kb
Host smart-52d67622-74a9-4c82-99fa-ed2f38aec122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313458673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3313458673
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4034237119
Short name T371
Test name
Test status
Simulation time 45001148 ps
CPU time 1.36 seconds
Started May 09 01:04:04 PM PDT 24
Finished May 09 01:04:09 PM PDT 24
Peak memory 200420 kb
Host smart-a45fb83d-6451-4fc6-b7b2-f25eadd5b0f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034237119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4034237119
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3179391435
Short name T357
Test name
Test status
Simulation time 1157101745 ps
CPU time 59.47 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:05:12 PM PDT 24
Peak memory 200564 kb
Host smart-a00db614-c6b1-4d8b-ae43-3acaac3c817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179391435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3179391435
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2705938598
Short name T263
Test name
Test status
Simulation time 15569407899 ps
CPU time 933.6 seconds
Started May 09 01:04:06 PM PDT 24
Finished May 09 01:19:44 PM PDT 24
Peak memory 739516 kb
Host smart-5a7ea245-9adf-4cf7-ab93-1a6eac7f175d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705938598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2705938598
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1650305989
Short name T305
Test name
Test status
Simulation time 502676396 ps
CPU time 6.76 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:20 PM PDT 24
Peak memory 200380 kb
Host smart-074dc061-e10e-4df1-9a4d-fee706810aa3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650305989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1650305989
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.533425789
Short name T264
Test name
Test status
Simulation time 3426218133 ps
CPU time 50.04 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:05:04 PM PDT 24
Peak memory 200656 kb
Host smart-2cfe8807-be16-456c-9687-8466394a72af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533425789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.533425789
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1892994986
Short name T320
Test name
Test status
Simulation time 499904503 ps
CPU time 5.88 seconds
Started May 09 01:04:06 PM PDT 24
Finished May 09 01:04:16 PM PDT 24
Peak memory 200564 kb
Host smart-2a2c8416-730a-44d5-80d0-8084ba8da3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892994986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1892994986
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3539530615
Short name T334
Test name
Test status
Simulation time 76910285 ps
CPU time 1 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 199628 kb
Host smart-dc324d88-75f3-426d-a6d6-2b0ff3c18352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539530615 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3539530615
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3317711740
Short name T212
Test name
Test status
Simulation time 31381505442 ps
CPU time 448.39 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 200668 kb
Host smart-fe47b210-e71e-48ff-bdf2-84ed22418e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317711740 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3317711740
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_alert_test.510609398
Short name T452
Test name
Test status
Simulation time 41545848 ps
CPU time 0.56 seconds
Started May 09 01:04:05 PM PDT 24
Finished May 09 01:04:11 PM PDT 24
Peak memory 196332 kb
Host smart-17918aa7-e50b-4ead-ae4d-9c90cc25e2f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510609398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.510609398
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3329889090
Short name T356
Test name
Test status
Simulation time 4624869455 ps
CPU time 59.56 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:05:13 PM PDT 24
Peak memory 231332 kb
Host smart-f2dfe539-3857-4a9e-b208-a60d0427a6ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329889090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3329889090
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.40325733
Short name T270
Test name
Test status
Simulation time 1829564159 ps
CPU time 14.1 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:28 PM PDT 24
Peak memory 200468 kb
Host smart-a77d793f-eb83-4a58-a8dd-1d1abd2c7243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40325733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.40325733
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1570682481
Short name T217
Test name
Test status
Simulation time 1197739765 ps
CPU time 286.73 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:09:00 PM PDT 24
Peak memory 654608 kb
Host smart-9d9c4fb6-fbe1-4005-af0a-9f5da757388e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570682481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1570682481
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3154091475
Short name T422
Test name
Test status
Simulation time 408594516 ps
CPU time 14 seconds
Started May 09 01:04:05 PM PDT 24
Finished May 09 01:04:24 PM PDT 24
Peak memory 200592 kb
Host smart-67121526-78b1-46e8-a1e8-c059aabd940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154091475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3154091475
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3955589736
Short name T373
Test name
Test status
Simulation time 52833588 ps
CPU time 0.92 seconds
Started May 09 01:04:09 PM PDT 24
Finished May 09 01:04:16 PM PDT 24
Peak memory 199416 kb
Host smart-3d1efc58-532f-4846-9e39-bc7bac3730ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955589736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3955589736
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3280193659
Short name T171
Test name
Test status
Simulation time 168214876 ps
CPU time 1.25 seconds
Started May 09 01:04:05 PM PDT 24
Finished May 09 01:04:11 PM PDT 24
Peak memory 200328 kb
Host smart-e1942362-ebd7-4f88-aad8-f28b02ba4811
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280193659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3280193659
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1355974910
Short name T209
Test name
Test status
Simulation time 29032051010 ps
CPU time 542.73 seconds
Started May 09 01:04:03 PM PDT 24
Finished May 09 01:13:10 PM PDT 24
Peak memory 200644 kb
Host smart-1167ca7a-5564-43b9-9dcf-94e8aa914b8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355974910 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.1355974910
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2003556537
Short name T340
Test name
Test status
Simulation time 45103558 ps
CPU time 0.58 seconds
Started May 09 01:04:13 PM PDT 24
Finished May 09 01:04:18 PM PDT 24
Peak memory 196256 kb
Host smart-a5575042-3a19-4604-817a-ac299978653f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003556537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2003556537
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3906377175
Short name T47
Test name
Test status
Simulation time 512776463 ps
CPU time 25.15 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:39 PM PDT 24
Peak memory 219004 kb
Host smart-c22c7524-38a6-4373-b7c8-b0238dc10218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906377175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3906377175
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1175591091
Short name T363
Test name
Test status
Simulation time 950659670 ps
CPU time 24.02 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:37 PM PDT 24
Peak memory 200604 kb
Host smart-1a9ba0e0-3f71-4432-ab88-69d342307c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175591091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1175591091
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4150005776
Short name T188
Test name
Test status
Simulation time 1652185257 ps
CPU time 357.11 seconds
Started May 09 01:04:13 PM PDT 24
Finished May 09 01:10:14 PM PDT 24
Peak memory 592900 kb
Host smart-b5d75814-8f24-4cac-8b01-143327f4cc56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150005776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4150005776
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3179817630
Short name T338
Test name
Test status
Simulation time 1830876974 ps
CPU time 19.25 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:32 PM PDT 24
Peak memory 200604 kb
Host smart-8eff5347-7563-4b63-bef8-3723211b2e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179817630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3179817630
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.11003742
Short name T279
Test name
Test status
Simulation time 923757348 ps
CPU time 1.93 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 200560 kb
Host smart-597b18a5-10d7-4595-9016-8734b0f0fc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11003742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.11003742
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.625339951
Short name T262
Test name
Test status
Simulation time 217791369 ps
CPU time 1.25 seconds
Started May 09 01:04:09 PM PDT 24
Finished May 09 01:04:16 PM PDT 24
Peak memory 200580 kb
Host smart-cc10d4bc-ecda-4f64-a1da-dc47cdf778ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625339951 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.625339951
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.919693596
Short name T202
Test name
Test status
Simulation time 15563004789 ps
CPU time 436.26 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 200632 kb
Host smart-116a5820-fc10-49d8-9ba9-8e22007b5c7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919693596 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.919693596
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1228434657
Short name T441
Test name
Test status
Simulation time 18319260 ps
CPU time 0.58 seconds
Started May 09 01:03:31 PM PDT 24
Finished May 09 01:03:34 PM PDT 24
Peak memory 196104 kb
Host smart-52ba3a07-a382-479a-a2aa-7b11b94851ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228434657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1228434657
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1507744630
Short name T427
Test name
Test status
Simulation time 1014844831 ps
CPU time 53.7 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:04:32 PM PDT 24
Peak memory 222156 kb
Host smart-cd728686-da0d-48e7-9119-8799d3fc3195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507744630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1507744630
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.541263020
Short name T107
Test name
Test status
Simulation time 9107798968 ps
CPU time 13.75 seconds
Started May 09 01:03:31 PM PDT 24
Finished May 09 01:03:48 PM PDT 24
Peak memory 200708 kb
Host smart-8024bdcf-a3c4-47a6-9505-f797e147e75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541263020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.541263020
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3715666011
Short name T151
Test name
Test status
Simulation time 1295660293 ps
CPU time 294.45 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:08:33 PM PDT 24
Peak memory 678592 kb
Host smart-0bc16b97-626b-4812-9eca-cf8a2d2289ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715666011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3715666011
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2451085522
Short name T231
Test name
Test status
Simulation time 2109554185 ps
CPU time 72.34 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:04:48 PM PDT 24
Peak memory 200604 kb
Host smart-68e4a1e0-6f47-4b94-8159-f7764984d31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451085522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2451085522
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3332471431
Short name T35
Test name
Test status
Simulation time 111832017 ps
CPU time 0.82 seconds
Started May 09 01:03:34 PM PDT 24
Finished May 09 01:03:38 PM PDT 24
Peak memory 218880 kb
Host smart-1cb2754c-0288-4168-bf30-31166a9666b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332471431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3332471431
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1754209194
Short name T271
Test name
Test status
Simulation time 2423949887 ps
CPU time 3.86 seconds
Started May 09 01:03:36 PM PDT 24
Finished May 09 01:03:43 PM PDT 24
Peak memory 200744 kb
Host smart-6323e890-8584-4fea-9b4b-c8e797eb3a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754209194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1754209194
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1390573184
Short name T342
Test name
Test status
Simulation time 316210522 ps
CPU time 1.01 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:03:36 PM PDT 24
Peak memory 200116 kb
Host smart-c5156b8e-12a0-4235-a61b-5a2d9c97c686
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390573184 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1390573184
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.986683310
Short name T296
Test name
Test status
Simulation time 148012519917 ps
CPU time 481.11 seconds
Started May 09 01:03:30 PM PDT 24
Finished May 09 01:11:33 PM PDT 24
Peak memory 200568 kb
Host smart-e1fe7689-55bc-46c4-b186-e81a4f774b88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986683310 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.986683310
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2810646844
Short name T167
Test name
Test status
Simulation time 12000620 ps
CPU time 0.61 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:04:20 PM PDT 24
Peak memory 196056 kb
Host smart-cf80d4a5-4299-41ae-a5e4-ce00b634cb1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810646844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2810646844
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1582701088
Short name T440
Test name
Test status
Simulation time 72149080 ps
CPU time 1.9 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 200568 kb
Host smart-7062cdc0-1a55-4252-bf2a-3b7cdd0233d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582701088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1582701088
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1218969471
Short name T59
Test name
Test status
Simulation time 2046764874 ps
CPU time 6.52 seconds
Started May 09 01:04:10 PM PDT 24
Finished May 09 01:04:22 PM PDT 24
Peak memory 200484 kb
Host smart-dbf05b67-f3a8-412d-9e3a-0f1fbbe9c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218969471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1218969471
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3788900754
Short name T141
Test name
Test status
Simulation time 1445990177 ps
CPU time 60.93 seconds
Started May 09 01:04:07 PM PDT 24
Finished May 09 01:05:14 PM PDT 24
Peak memory 397924 kb
Host smart-6cfba43d-c0d7-4432-8e3b-ce2fc935977b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788900754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3788900754
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3179206624
Short name T378
Test name
Test status
Simulation time 7613689698 ps
CPU time 93.1 seconds
Started May 09 01:04:10 PM PDT 24
Finished May 09 01:05:48 PM PDT 24
Peak memory 200672 kb
Host smart-0e1cfb6e-7181-49be-9514-adc90c4c7b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179206624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3179206624
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1995396341
Short name T142
Test name
Test status
Simulation time 388906651 ps
CPU time 6.34 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:04:20 PM PDT 24
Peak memory 200572 kb
Host smart-0f3c2518-9f47-439e-a9f5-84f366c74681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995396341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1995396341
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1697441304
Short name T454
Test name
Test status
Simulation time 71894249 ps
CPU time 1.2 seconds
Started May 09 01:04:15 PM PDT 24
Finished May 09 01:04:20 PM PDT 24
Peak memory 200556 kb
Host smart-e126e7f6-e9b1-4b59-8c89-d10519898ed4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697441304 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1697441304
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3274699956
Short name T426
Test name
Test status
Simulation time 28942371337 ps
CPU time 414.25 seconds
Started May 09 01:04:08 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 200656 kb
Host smart-4a47de86-d876-4c69-a27a-b78922530d49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274699956 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3274699956
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.42605710
Short name T175
Test name
Test status
Simulation time 14774938 ps
CPU time 0.63 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:04:20 PM PDT 24
Peak memory 196336 kb
Host smart-5c209c44-dbd0-4572-b803-caefa4f11701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42605710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.42605710
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1620651611
Short name T470
Test name
Test status
Simulation time 4715745338 ps
CPU time 29.11 seconds
Started May 09 01:04:17 PM PDT 24
Finished May 09 01:04:50 PM PDT 24
Peak memory 208972 kb
Host smart-50793a9c-5d9c-4d8e-8286-2d57f2e9541e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620651611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1620651611
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3559085814
Short name T375
Test name
Test status
Simulation time 16829886449 ps
CPU time 17.48 seconds
Started May 09 01:04:15 PM PDT 24
Finished May 09 01:04:37 PM PDT 24
Peak memory 200736 kb
Host smart-0fe8ca46-6cf5-4e29-9f57-d97aa019cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559085814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3559085814
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2619824274
Short name T439
Test name
Test status
Simulation time 4190695361 ps
CPU time 825.12 seconds
Started May 09 01:04:14 PM PDT 24
Finished May 09 01:18:04 PM PDT 24
Peak memory 701012 kb
Host smart-53418707-475c-46d1-9af5-049148f8d8f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2619824274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2619824274
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1259539357
Short name T214
Test name
Test status
Simulation time 13199458 ps
CPU time 0.66 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:04:23 PM PDT 24
Peak memory 196776 kb
Host smart-3f6c8fe3-1672-4f98-b6d3-802de6304738
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259539357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1259539357
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2997457917
Short name T436
Test name
Test status
Simulation time 3118210162 ps
CPU time 12.81 seconds
Started May 09 01:04:14 PM PDT 24
Finished May 09 01:04:31 PM PDT 24
Peak memory 200640 kb
Host smart-b348970e-2736-41db-b710-c3c9a5c16d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997457917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2997457917
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3549687858
Short name T359
Test name
Test status
Simulation time 2628125644 ps
CPU time 4.73 seconds
Started May 09 01:04:14 PM PDT 24
Finished May 09 01:04:23 PM PDT 24
Peak memory 200704 kb
Host smart-a4731396-2b9d-4138-9e1c-e38114da438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549687858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3549687858
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2626235222
Short name T160
Test name
Test status
Simulation time 322195107 ps
CPU time 1.08 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:04:20 PM PDT 24
Peak memory 200132 kb
Host smart-43991693-3ac6-47aa-a81b-1b01e90d2aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626235222 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2626235222
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3542649937
Short name T200
Test name
Test status
Simulation time 42837512776 ps
CPU time 513.68 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:12:55 PM PDT 24
Peak memory 200716 kb
Host smart-f324e40e-36ae-4da1-9bd1-b4d0b7a3620e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542649937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3542649937
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1929528673
Short name T20
Test name
Test status
Simulation time 14071945 ps
CPU time 0.6 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:04:21 PM PDT 24
Peak memory 196340 kb
Host smart-7428cedf-e175-4d29-a78e-35d8a306a9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929528673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1929528673
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.4290909622
Short name T456
Test name
Test status
Simulation time 458685508 ps
CPU time 7.59 seconds
Started May 09 01:04:21 PM PDT 24
Finished May 09 01:04:31 PM PDT 24
Peak memory 216980 kb
Host smart-72de0250-d973-416d-a760-ebdff4987fa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290909622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4290909622
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2890944330
Short name T134
Test name
Test status
Simulation time 2931447922 ps
CPU time 36.68 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:04:57 PM PDT 24
Peak memory 200620 kb
Host smart-5c791be8-8589-41df-8c49-8a2d4961d502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890944330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2890944330
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1772761903
Short name T243
Test name
Test status
Simulation time 1275010745 ps
CPU time 286.14 seconds
Started May 09 01:04:15 PM PDT 24
Finished May 09 01:09:05 PM PDT 24
Peak memory 615876 kb
Host smart-5d94c314-035a-4936-bba7-2f2b4420b458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772761903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1772761903
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1142210483
Short name T467
Test name
Test status
Simulation time 4500189712 ps
CPU time 80.47 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:05:40 PM PDT 24
Peak memory 200700 kb
Host smart-d7c65d28-5345-4f53-abef-0cc8a726155b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142210483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1142210483
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1896431000
Short name T414
Test name
Test status
Simulation time 5622758912 ps
CPU time 65.8 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:05:27 PM PDT 24
Peak memory 200728 kb
Host smart-84c1cbb0-4508-4504-96cf-c33072e3a7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896431000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1896431000
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.567738665
Short name T144
Test name
Test status
Simulation time 703971623 ps
CPU time 4.29 seconds
Started May 09 01:04:14 PM PDT 24
Finished May 09 01:04:22 PM PDT 24
Peak memory 200604 kb
Host smart-f094ff69-1bfd-4161-a04f-d4d63aff9e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567738665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.567738665
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.619760602
Short name T365
Test name
Test status
Simulation time 33534010 ps
CPU time 1.33 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:04:21 PM PDT 24
Peak memory 200600 kb
Host smart-08ba2c22-c8eb-464b-91e7-d3b357fe4361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619760602 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.619760602
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2368468079
Short name T211
Test name
Test status
Simulation time 39038690622 ps
CPU time 543.84 seconds
Started May 09 01:04:15 PM PDT 24
Finished May 09 01:13:23 PM PDT 24
Peak memory 200716 kb
Host smart-07af1f84-c7bc-4869-9edd-01fc73e7a610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368468079 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2368468079
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.15209450
Short name T181
Test name
Test status
Simulation time 47741449 ps
CPU time 0.6 seconds
Started May 09 01:04:20 PM PDT 24
Finished May 09 01:04:24 PM PDT 24
Peak memory 195264 kb
Host smart-8f7613cf-a777-4126-8658-3eaa8f140c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15209450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.15209450
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2496964451
Short name T389
Test name
Test status
Simulation time 1545784879 ps
CPU time 17.25 seconds
Started May 09 01:04:17 PM PDT 24
Finished May 09 01:04:38 PM PDT 24
Peak memory 209740 kb
Host smart-46ba23bc-a54f-4468-ab1d-416fa18e7309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496964451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2496964451
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3996441342
Short name T1
Test name
Test status
Simulation time 12648794486 ps
CPU time 42.69 seconds
Started May 09 01:04:17 PM PDT 24
Finished May 09 01:05:03 PM PDT 24
Peak memory 200784 kb
Host smart-94cf92b9-ffeb-47ae-964e-a482927b2a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996441342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3996441342
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2749333391
Short name T206
Test name
Test status
Simulation time 28956017519 ps
CPU time 1246.05 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:25:08 PM PDT 24
Peak memory 700216 kb
Host smart-d75f29f5-eae1-4485-bc4b-2091ff9e0f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749333391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2749333391
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2164714338
Short name T16
Test name
Test status
Simulation time 4472523428 ps
CPU time 16.04 seconds
Started May 09 01:04:19 PM PDT 24
Finished May 09 01:04:38 PM PDT 24
Peak memory 200688 kb
Host smart-8ebf1b27-04ca-4957-bac6-4262abe53480
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164714338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2164714338
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2270405509
Short name T364
Test name
Test status
Simulation time 2909253228 ps
CPU time 59.38 seconds
Started May 09 01:04:17 PM PDT 24
Finished May 09 01:05:20 PM PDT 24
Peak memory 200696 kb
Host smart-06f08cb8-1cff-4e80-b752-f43e6c122b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270405509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2270405509
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3764018557
Short name T362
Test name
Test status
Simulation time 389321877 ps
CPU time 5.84 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:04:28 PM PDT 24
Peak memory 200544 kb
Host smart-4b9b818c-fef9-489f-98a0-c815ad4bd00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764018557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3764018557
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3819816588
Short name T106
Test name
Test status
Simulation time 19778604832 ps
CPU time 47.46 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:05:09 PM PDT 24
Peak memory 200768 kb
Host smart-eb8c2a43-1e72-4193-8fdc-05e623cee182
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819816588 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3819816588
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.4119502301
Short name T415
Test name
Test status
Simulation time 284276625 ps
CPU time 1.07 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:04:23 PM PDT 24
Peak memory 199888 kb
Host smart-8ba78337-e01f-49eb-8e81-4f28f23954cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119502301 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.4119502301
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2621101813
Short name T379
Test name
Test status
Simulation time 8044117964 ps
CPU time 458.21 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:12:00 PM PDT 24
Peak memory 200600 kb
Host smart-083b36bc-1aba-4a7d-9886-9e3d2abf8b38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621101813 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.2621101813
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1806009286
Short name T473
Test name
Test status
Simulation time 30573304 ps
CPU time 0.59 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:04:22 PM PDT 24
Peak memory 197032 kb
Host smart-b3ad23e6-c3cf-4144-b14d-af01dfd13bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806009286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1806009286
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2699671944
Short name T404
Test name
Test status
Simulation time 2106913685 ps
CPU time 28.79 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:04:51 PM PDT 24
Peak memory 219092 kb
Host smart-677c75c1-42de-4713-8779-4370053b96a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699671944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2699671944
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3842749226
Short name T161
Test name
Test status
Simulation time 3021665457 ps
CPU time 14.73 seconds
Started May 09 01:04:18 PM PDT 24
Finished May 09 01:04:36 PM PDT 24
Peak memory 200660 kb
Host smart-5eb648d2-14bc-47d9-9274-8777dfe5ba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842749226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3842749226
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1405659037
Short name T276
Test name
Test status
Simulation time 8425395913 ps
CPU time 1158.47 seconds
Started May 09 01:04:16 PM PDT 24
Finished May 09 01:23:39 PM PDT 24
Peak memory 756528 kb
Host smart-7b96ddc7-3a68-40d5-b1be-a6eba5a4b454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405659037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1405659037
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4241026425
Short name T72
Test name
Test status
Simulation time 4200406476 ps
CPU time 59.37 seconds
Started May 09 01:04:20 PM PDT 24
Finished May 09 01:05:22 PM PDT 24
Peak memory 200712 kb
Host smart-41c6a4b2-b28c-4557-8e9c-ff0c5fdcf925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241026425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4241026425
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.548686341
Short name T165
Test name
Test status
Simulation time 292450609 ps
CPU time 2.75 seconds
Started May 09 01:04:21 PM PDT 24
Finished May 09 01:04:26 PM PDT 24
Peak memory 200540 kb
Host smart-9c092064-5164-49b8-958e-70781fea45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548686341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.548686341
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2250787996
Short name T444
Test name
Test status
Simulation time 343064816 ps
CPU time 1.07 seconds
Started May 09 01:04:27 PM PDT 24
Finished May 09 01:04:30 PM PDT 24
Peak memory 200008 kb
Host smart-bda376a7-6922-46cd-b453-6e6f937058b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250787996 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2250787996
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1679488718
Short name T277
Test name
Test status
Simulation time 32066311033 ps
CPU time 445.94 seconds
Started May 09 01:04:19 PM PDT 24
Finished May 09 01:11:48 PM PDT 24
Peak memory 200660 kb
Host smart-eb8b5e79-5b42-4e44-bb44-6cdf07684db8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679488718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1679488718
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2512929894
Short name T394
Test name
Test status
Simulation time 16758053 ps
CPU time 0.62 seconds
Started May 09 01:04:31 PM PDT 24
Finished May 09 01:04:34 PM PDT 24
Peak memory 196356 kb
Host smart-2a38f71b-e5f4-4a21-ac52-a79db47dd0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512929894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2512929894
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3441113577
Short name T51
Test name
Test status
Simulation time 554859483 ps
CPU time 34.81 seconds
Started May 09 01:04:27 PM PDT 24
Finished May 09 01:05:04 PM PDT 24
Peak memory 222064 kb
Host smart-494050fd-a2e5-4070-aaf4-b8eb11cefa31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441113577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3441113577
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2652941220
Short name T475
Test name
Test status
Simulation time 3549943095 ps
CPU time 33.54 seconds
Started May 09 01:04:31 PM PDT 24
Finished May 09 01:05:07 PM PDT 24
Peak memory 200732 kb
Host smart-fa94e538-aadf-470a-8f9b-cca8eae26bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652941220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2652941220
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3837596798
Short name T213
Test name
Test status
Simulation time 406435582 ps
CPU time 10.18 seconds
Started May 09 01:04:33 PM PDT 24
Finished May 09 01:04:45 PM PDT 24
Peak memory 226412 kb
Host smart-8ab082a4-ec4f-4d1a-a4b4-6ccafb62e332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837596798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3837596798
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3604056376
Short name T321
Test name
Test status
Simulation time 1602438884 ps
CPU time 22.48 seconds
Started May 09 01:04:27 PM PDT 24
Finished May 09 01:04:52 PM PDT 24
Peak memory 200544 kb
Host smart-d7988dbb-776b-4f14-931c-53f578f300c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604056376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3604056376
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1959852914
Short name T185
Test name
Test status
Simulation time 1658158373 ps
CPU time 6.23 seconds
Started May 09 01:04:24 PM PDT 24
Finished May 09 01:04:32 PM PDT 24
Peak memory 200516 kb
Host smart-773802d1-da41-4082-956a-bd5791631209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959852914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1959852914
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3766486220
Short name T38
Test name
Test status
Simulation time 44669996 ps
CPU time 1.04 seconds
Started May 09 01:04:28 PM PDT 24
Finished May 09 01:04:30 PM PDT 24
Peak memory 199084 kb
Host smart-5be69b65-23fa-4728-8ef4-159f13b2ddf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766486220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3766486220
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3134871854
Short name T295
Test name
Test status
Simulation time 78679726 ps
CPU time 1.24 seconds
Started May 09 01:04:25 PM PDT 24
Finished May 09 01:04:28 PM PDT 24
Peak memory 200580 kb
Host smart-e63d48cd-abb5-4f26-814b-9281bd4a3383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134871854 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3134871854
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1158822361
Short name T372
Test name
Test status
Simulation time 34893893971 ps
CPU time 481.52 seconds
Started May 09 01:04:31 PM PDT 24
Finished May 09 01:12:33 PM PDT 24
Peak memory 200532 kb
Host smart-967fdc64-4c2e-4e20-855e-141f48b7113b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158822361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1158822361
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2730378138
Short name T85
Test name
Test status
Simulation time 37862844 ps
CPU time 0.63 seconds
Started May 09 01:04:26 PM PDT 24
Finished May 09 01:04:29 PM PDT 24
Peak memory 195860 kb
Host smart-d3f78a49-c207-4e63-82d7-087328e8baed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730378138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2730378138
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.886375215
Short name T344
Test name
Test status
Simulation time 428236707 ps
CPU time 18.55 seconds
Started May 09 01:04:28 PM PDT 24
Finished May 09 01:04:48 PM PDT 24
Peak memory 200644 kb
Host smart-0bb59281-3604-4a75-bff4-afa7abe7707b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886375215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.886375215
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3945920704
Short name T418
Test name
Test status
Simulation time 4587445865 ps
CPU time 39.28 seconds
Started May 09 01:04:32 PM PDT 24
Finished May 09 01:05:14 PM PDT 24
Peak memory 200644 kb
Host smart-a3faa3a8-c790-4e31-a5af-33295e9c6b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945920704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3945920704
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3667946381
Short name T154
Test name
Test status
Simulation time 5452705771 ps
CPU time 582.25 seconds
Started May 09 01:04:30 PM PDT 24
Finished May 09 01:14:13 PM PDT 24
Peak memory 623592 kb
Host smart-d54cab33-e599-462d-ae30-1c3e2f51219d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667946381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3667946381
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3469622778
Short name T164
Test name
Test status
Simulation time 6999227544 ps
CPU time 88.51 seconds
Started May 09 01:04:33 PM PDT 24
Finished May 09 01:06:04 PM PDT 24
Peak memory 200696 kb
Host smart-b8e6da74-4fef-4bc3-a89b-72b0e10b94f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469622778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3469622778
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2354681536
Short name T304
Test name
Test status
Simulation time 609939848 ps
CPU time 5.3 seconds
Started May 09 01:04:26 PM PDT 24
Finished May 09 01:04:34 PM PDT 24
Peak memory 200620 kb
Host smart-614d5ae9-cbd5-4f8b-8895-4d6e60f3880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354681536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2354681536
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3889075730
Short name T73
Test name
Test status
Simulation time 107235882 ps
CPU time 1.11 seconds
Started May 09 01:04:31 PM PDT 24
Finished May 09 01:04:33 PM PDT 24
Peak memory 200368 kb
Host smart-840731c7-a32e-4eb9-94ea-4ae8a34c0d90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889075730 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3889075730
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.4017510146
Short name T457
Test name
Test status
Simulation time 50219880173 ps
CPU time 446.86 seconds
Started May 09 01:04:33 PM PDT 24
Finished May 09 01:12:02 PM PDT 24
Peak memory 200520 kb
Host smart-5adb358c-2bda-4e21-b463-275cb190ff18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017510146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.4017510146
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3186738377
Short name T44
Test name
Test status
Simulation time 45174705 ps
CPU time 0.59 seconds
Started May 09 01:04:26 PM PDT 24
Finished May 09 01:04:29 PM PDT 24
Peak memory 196336 kb
Host smart-d2601773-512b-4877-a792-55b282a34fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186738377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3186738377
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.207715695
Short name T210
Test name
Test status
Simulation time 355550270 ps
CPU time 20.2 seconds
Started May 09 01:04:32 PM PDT 24
Finished May 09 01:04:55 PM PDT 24
Peak memory 218896 kb
Host smart-99d8392e-a2f1-43b8-a2d3-8e76ec8846ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207715695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.207715695
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1935297532
Short name T169
Test name
Test status
Simulation time 4585122306 ps
CPU time 35.73 seconds
Started May 09 01:04:25 PM PDT 24
Finished May 09 01:05:03 PM PDT 24
Peak memory 200708 kb
Host smart-192f62fe-dee8-40be-93e8-2623256e1351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935297532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1935297532
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.565861079
Short name T392
Test name
Test status
Simulation time 388544272 ps
CPU time 2.2 seconds
Started May 09 01:04:27 PM PDT 24
Finished May 09 01:04:31 PM PDT 24
Peak memory 200604 kb
Host smart-7875fbca-048c-48e2-a7ef-2bafd1b41b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565861079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.565861079
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1658579411
Short name T311
Test name
Test status
Simulation time 250665778 ps
CPU time 1.27 seconds
Started May 09 01:04:25 PM PDT 24
Finished May 09 01:04:28 PM PDT 24
Peak memory 200540 kb
Host smart-58f37235-f834-44e5-8dc0-4fb31c5955ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658579411 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1658579411
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.947474907
Short name T299
Test name
Test status
Simulation time 29243034129 ps
CPU time 532.67 seconds
Started May 09 01:04:26 PM PDT 24
Finished May 09 01:13:20 PM PDT 24
Peak memory 200712 kb
Host smart-ebc69fc2-0bef-41a7-9222-1baab360dddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947474907 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.947474907
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1107335485
Short name T178
Test name
Test status
Simulation time 40894125 ps
CPU time 0.62 seconds
Started May 09 01:04:38 PM PDT 24
Finished May 09 01:04:41 PM PDT 24
Peak memory 195304 kb
Host smart-c47ab7fb-7bb6-4131-b1b2-4ff9977fe392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107335485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1107335485
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3136569794
Short name T252
Test name
Test status
Simulation time 410022868 ps
CPU time 5.7 seconds
Started May 09 01:04:26 PM PDT 24
Finished May 09 01:04:34 PM PDT 24
Peak memory 216108 kb
Host smart-f0c32444-9b5e-484d-8436-105d02e8798d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136569794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3136569794
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3435724471
Short name T29
Test name
Test status
Simulation time 693414246 ps
CPU time 37 seconds
Started May 09 01:04:32 PM PDT 24
Finished May 09 01:05:12 PM PDT 24
Peak memory 200572 kb
Host smart-786a4ba4-b1b7-4cf5-92cc-3c3bf1f283fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435724471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3435724471
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.484502635
Short name T43
Test name
Test status
Simulation time 3237633861 ps
CPU time 520.14 seconds
Started May 09 01:04:33 PM PDT 24
Finished May 09 01:13:15 PM PDT 24
Peak memory 690516 kb
Host smart-de71bec0-e9b5-4741-8390-459c6ce833a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484502635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.484502635
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1500361573
Short name T216
Test name
Test status
Simulation time 586540053 ps
CPU time 10.73 seconds
Started May 09 01:04:31 PM PDT 24
Finished May 09 01:04:44 PM PDT 24
Peak memory 200568 kb
Host smart-7a5982e6-50f9-4800-a47d-497c5f70c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500361573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1500361573
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.881434681
Short name T246
Test name
Test status
Simulation time 519619582 ps
CPU time 5.8 seconds
Started May 09 01:04:31 PM PDT 24
Finished May 09 01:04:37 PM PDT 24
Peak memory 200424 kb
Host smart-9796851e-8c65-432a-877e-ebd00ff13423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881434681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.881434681
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4187938324
Short name T466
Test name
Test status
Simulation time 2778543681 ps
CPU time 72.25 seconds
Started May 09 01:04:33 PM PDT 24
Finished May 09 01:05:47 PM PDT 24
Peak memory 200548 kb
Host smart-f6f1ba8f-efd8-44a1-b559-6cd09ec94887
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187938324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4187938324
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.698948982
Short name T408
Test name
Test status
Simulation time 34431017 ps
CPU time 0.96 seconds
Started May 09 01:04:33 PM PDT 24
Finished May 09 01:04:36 PM PDT 24
Peak memory 199208 kb
Host smart-cd507741-304a-4beb-8f50-16198f33b651
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698948982 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.698948982
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1468001011
Short name T215
Test name
Test status
Simulation time 154835191933 ps
CPU time 511.72 seconds
Started May 09 01:04:25 PM PDT 24
Finished May 09 01:12:59 PM PDT 24
Peak memory 200580 kb
Host smart-b31246d3-5b0e-4bc5-99d8-720155357a82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468001011 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1468001011
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3815873501
Short name T162
Test name
Test status
Simulation time 13453557 ps
CPU time 0.62 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:04:39 PM PDT 24
Peak memory 195220 kb
Host smart-6373d30b-2292-4199-8def-4fb26256802f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815873501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3815873501
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3075587273
Short name T410
Test name
Test status
Simulation time 442921665 ps
CPU time 17.21 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:04:57 PM PDT 24
Peak memory 228080 kb
Host smart-b92e7684-e611-4771-b11b-a2185daee9da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075587273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3075587273
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1496154305
Short name T88
Test name
Test status
Simulation time 4573239581 ps
CPU time 81.07 seconds
Started May 09 01:04:42 PM PDT 24
Finished May 09 01:06:04 PM PDT 24
Peak memory 200716 kb
Host smart-1ecb4e2a-6d10-40e4-a285-8b4409c7265d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496154305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1496154305
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4293896025
Short name T396
Test name
Test status
Simulation time 5535268985 ps
CPU time 115 seconds
Started May 09 01:04:43 PM PDT 24
Finished May 09 01:06:38 PM PDT 24
Peak memory 347236 kb
Host smart-9401cdd1-8b62-47e0-befc-cf3571b4d211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293896025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4293896025
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4278542422
Short name T448
Test name
Test status
Simulation time 462272927 ps
CPU time 4.74 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:04:43 PM PDT 24
Peak memory 200568 kb
Host smart-91f2eb87-f894-4e0a-98d4-823d57741604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278542422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4278542422
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.680838792
Short name T451
Test name
Test status
Simulation time 163653274 ps
CPU time 4.91 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:04:43 PM PDT 24
Peak memory 200584 kb
Host smart-81b52c38-0d70-4aa4-895c-b503245b4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680838792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.680838792
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.714061964
Short name T227
Test name
Test status
Simulation time 75387045 ps
CPU time 1.41 seconds
Started May 09 01:04:35 PM PDT 24
Finished May 09 01:04:38 PM PDT 24
Peak memory 200568 kb
Host smart-845df57b-1664-43be-8f54-2001dae50236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714061964 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.714061964
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2037481001
Short name T393
Test name
Test status
Simulation time 319132862947 ps
CPU time 518.81 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:13:18 PM PDT 24
Peak memory 200712 kb
Host smart-266a241e-2b6c-41cc-b620-2939e92fd742
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037481001 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2037481001
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1958916890
Short name T87
Test name
Test status
Simulation time 13848414 ps
CPU time 0.6 seconds
Started May 09 01:03:33 PM PDT 24
Finished May 09 01:03:37 PM PDT 24
Peak memory 196020 kb
Host smart-19161be7-aa29-450e-82a3-5d611d5f8260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958916890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1958916890
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.488787598
Short name T260
Test name
Test status
Simulation time 844306261 ps
CPU time 42.61 seconds
Started May 09 01:03:34 PM PDT 24
Finished May 09 01:04:20 PM PDT 24
Peak memory 216932 kb
Host smart-0ba7977d-edde-42d4-807a-e476665e4c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488787598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.488787598
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1954851746
Short name T255
Test name
Test status
Simulation time 12052471067 ps
CPU time 45.2 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:04:23 PM PDT 24
Peak memory 200724 kb
Host smart-febd8c75-d447-4a4a-a10d-4c393ebfab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954851746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1954851746
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.4177546510
Short name T186
Test name
Test status
Simulation time 2407661648 ps
CPU time 526.48 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 631360 kb
Host smart-f4a86306-5691-4f14-a8b1-7b34359de024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177546510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4177546510
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1824158130
Short name T282
Test name
Test status
Simulation time 463764460 ps
CPU time 27.78 seconds
Started May 09 01:03:36 PM PDT 24
Finished May 09 01:04:07 PM PDT 24
Peak memory 200540 kb
Host smart-a2b7cd2e-18f5-4c15-b57b-bbd759e77927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824158130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1824158130
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2680203034
Short name T36
Test name
Test status
Simulation time 253814712 ps
CPU time 0.92 seconds
Started May 09 01:03:33 PM PDT 24
Finished May 09 01:03:37 PM PDT 24
Peak memory 218900 kb
Host smart-4cca2774-1097-4005-a02b-b96acae0362e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680203034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2680203034
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3955824619
Short name T219
Test name
Test status
Simulation time 2505663168 ps
CPU time 4.21 seconds
Started May 09 01:03:34 PM PDT 24
Finished May 09 01:03:42 PM PDT 24
Peak memory 200592 kb
Host smart-6ff975f7-f733-4958-821b-4a00033bc4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955824619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3955824619
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1639300547
Short name T438
Test name
Test status
Simulation time 34477837 ps
CPU time 1.04 seconds
Started May 09 01:03:30 PM PDT 24
Finished May 09 01:03:34 PM PDT 24
Peak memory 200080 kb
Host smart-5ed9fa5c-0270-4820-a70d-2876359ea39d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639300547 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1639300547
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.4186175456
Short name T249
Test name
Test status
Simulation time 7320096569 ps
CPU time 412.65 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:10:31 PM PDT 24
Peak memory 200512 kb
Host smart-71c75d4f-f734-4894-a14d-f9ac8d214f04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186175456 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.4186175456
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.4070857712
Short name T267
Test name
Test status
Simulation time 15529233 ps
CPU time 0.63 seconds
Started May 09 01:04:39 PM PDT 24
Finished May 09 01:04:42 PM PDT 24
Peak memory 197076 kb
Host smart-99aed90b-7081-41f5-a71c-a6e5a788e729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070857712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4070857712
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2504519172
Short name T287
Test name
Test status
Simulation time 932224348 ps
CPU time 43.9 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:05:23 PM PDT 24
Peak memory 217072 kb
Host smart-83f6d2ca-c76e-4020-b06d-3c049494f3ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504519172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2504519172
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.846799406
Short name T158
Test name
Test status
Simulation time 10513871707 ps
CPU time 52.21 seconds
Started May 09 01:04:38 PM PDT 24
Finished May 09 01:05:33 PM PDT 24
Peak memory 200648 kb
Host smart-668cb3e0-6578-4ca3-b8d5-c335d54a17e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846799406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.846799406
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3772426947
Short name T53
Test name
Test status
Simulation time 10418575996 ps
CPU time 255.63 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:08:55 PM PDT 24
Peak memory 601520 kb
Host smart-d280975f-a3bf-4bcb-a1ee-0092306348df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772426947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3772426947
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3850913808
Short name T266
Test name
Test status
Simulation time 9002633932 ps
CPU time 115.52 seconds
Started May 09 01:04:36 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 200752 kb
Host smart-34b59cb1-11d7-41a0-9572-f5092ea5acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850913808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3850913808
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.428175004
Short name T273
Test name
Test status
Simulation time 313592286 ps
CPU time 5.01 seconds
Started May 09 01:04:45 PM PDT 24
Finished May 09 01:04:51 PM PDT 24
Peak memory 200640 kb
Host smart-5aaef07e-cee3-4672-98be-3afecfc14995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428175004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.428175004
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1747065231
Short name T446
Test name
Test status
Simulation time 18976230614 ps
CPU time 518.4 seconds
Started May 09 01:04:38 PM PDT 24
Finished May 09 01:13:19 PM PDT 24
Peak memory 208848 kb
Host smart-7297621d-a542-45be-a137-f02546f0e9f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747065231 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1747065231
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3073274447
Short name T421
Test name
Test status
Simulation time 118338401 ps
CPU time 1.01 seconds
Started May 09 01:04:36 PM PDT 24
Finished May 09 01:04:38 PM PDT 24
Peak memory 200252 kb
Host smart-1271318d-c673-4e72-8145-48475a7b48d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073274447 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3073274447
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3008396457
Short name T351
Test name
Test status
Simulation time 8143395830 ps
CPU time 432.59 seconds
Started May 09 01:04:40 PM PDT 24
Finished May 09 01:11:54 PM PDT 24
Peak memory 200620 kb
Host smart-877fd1de-dcf7-43bc-b10f-69f61f363e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008396457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3008396457
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.111721001
Short name T74
Test name
Test status
Simulation time 21210063 ps
CPU time 0.59 seconds
Started May 09 01:04:40 PM PDT 24
Finished May 09 01:04:42 PM PDT 24
Peak memory 195976 kb
Host smart-5a4c7e44-aeae-47e1-a8fa-ce58d9f726b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111721001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.111721001
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3224932577
Short name T173
Test name
Test status
Simulation time 3972740640 ps
CPU time 36.48 seconds
Started May 09 01:04:44 PM PDT 24
Finished May 09 01:05:22 PM PDT 24
Peak memory 249528 kb
Host smart-e46125a5-e01a-46b8-9be5-f6d2aac3155f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224932577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3224932577
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3309117581
Short name T420
Test name
Test status
Simulation time 9373930817 ps
CPU time 717.07 seconds
Started May 09 01:04:38 PM PDT 24
Finished May 09 01:16:38 PM PDT 24
Peak memory 663724 kb
Host smart-db4539c1-e4a3-45a3-8aa4-bc6542d75b71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309117581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3309117581
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3361330633
Short name T135
Test name
Test status
Simulation time 6780417830 ps
CPU time 98.03 seconds
Started May 09 01:04:39 PM PDT 24
Finished May 09 01:06:20 PM PDT 24
Peak memory 200796 kb
Host smart-d10cb6b8-5f39-4e77-90bf-2de10d53dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361330633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3361330633
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1427426860
Short name T192
Test name
Test status
Simulation time 370194380 ps
CPU time 1.83 seconds
Started May 09 01:04:44 PM PDT 24
Finished May 09 01:04:47 PM PDT 24
Peak memory 200596 kb
Host smart-02bfe01f-7274-4c65-bef1-37a8d89d4d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427426860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1427426860
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.250933378
Short name T195
Test name
Test status
Simulation time 105538640 ps
CPU time 1 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:04:40 PM PDT 24
Peak memory 199500 kb
Host smart-b9a1a988-da16-4afa-8c57-fbf1f9655f83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250933378 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.250933378
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3920250706
Short name T241
Test name
Test status
Simulation time 31859620421 ps
CPU time 463.38 seconds
Started May 09 01:04:37 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 200528 kb
Host smart-34b2b982-3c2d-43c9-ba1e-7a589478189d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920250706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3920250706
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.909111655
Short name T336
Test name
Test status
Simulation time 120053002 ps
CPU time 0.65 seconds
Started May 09 01:04:48 PM PDT 24
Finished May 09 01:04:50 PM PDT 24
Peak memory 195976 kb
Host smart-cd7e715a-a0a5-4d4f-aa88-2390446afff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909111655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.909111655
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.844955403
Short name T40
Test name
Test status
Simulation time 939796408 ps
CPU time 14.55 seconds
Started May 09 01:04:38 PM PDT 24
Finished May 09 01:04:55 PM PDT 24
Peak memory 216564 kb
Host smart-b46fc2ee-c753-451e-a927-6864993904bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844955403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.844955403
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1058777147
Short name T224
Test name
Test status
Simulation time 4191084322 ps
CPU time 20.86 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:05:08 PM PDT 24
Peak memory 200636 kb
Host smart-27b313d7-a169-4be7-8d92-ff9ff40d7b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058777147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1058777147
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3089093440
Short name T109
Test name
Test status
Simulation time 9754059624 ps
CPU time 807.88 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:18:15 PM PDT 24
Peak memory 730084 kb
Host smart-0d97cd94-01c4-44cb-9cb1-58f85f8105af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089093440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3089093440
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3565113542
Short name T170
Test name
Test status
Simulation time 3321108814 ps
CPU time 65.73 seconds
Started May 09 01:04:45 PM PDT 24
Finished May 09 01:05:51 PM PDT 24
Peak memory 200620 kb
Host smart-5be2d13c-3d66-49b7-94d1-98ffeb2b8e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565113542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3565113542
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3301108348
Short name T172
Test name
Test status
Simulation time 1555126624 ps
CPU time 4.62 seconds
Started May 09 01:04:39 PM PDT 24
Finished May 09 01:04:46 PM PDT 24
Peak memory 200608 kb
Host smart-96c6c1a6-c5b3-4748-9505-8d5b6d147ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301108348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3301108348
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2347128163
Short name T244
Test name
Test status
Simulation time 108351054 ps
CPU time 1.02 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:04:49 PM PDT 24
Peak memory 199972 kb
Host smart-5ee44e35-fcfc-4c40-ab4e-313acb8c9c08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347128163 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2347128163
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3185703327
Short name T366
Test name
Test status
Simulation time 40560845745 ps
CPU time 554.97 seconds
Started May 09 01:04:47 PM PDT 24
Finished May 09 01:14:04 PM PDT 24
Peak memory 200680 kb
Host smart-14462821-8fa0-4a87-8009-15cdbe0658b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185703327 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.3185703327
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_alert_test.30760883
Short name T332
Test name
Test status
Simulation time 141116080 ps
CPU time 0.56 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:04:48 PM PDT 24
Peak memory 196020 kb
Host smart-33212ef7-55ec-481e-962d-01e49c41b13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.30760883
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.529144369
Short name T50
Test name
Test status
Simulation time 175629025 ps
CPU time 11.41 seconds
Started May 09 01:04:54 PM PDT 24
Finished May 09 01:05:06 PM PDT 24
Peak memory 219036 kb
Host smart-6e05936f-6156-49c3-a28e-929b64ad8ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529144369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.529144369
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.839885542
Short name T256
Test name
Test status
Simulation time 2822697890 ps
CPU time 30.8 seconds
Started May 09 01:04:54 PM PDT 24
Finished May 09 01:05:26 PM PDT 24
Peak memory 200728 kb
Host smart-445f6191-4f88-4546-a133-2735373a8ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839885542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.839885542
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1180193272
Short name T460
Test name
Test status
Simulation time 310565404 ps
CPU time 44.05 seconds
Started May 09 01:04:47 PM PDT 24
Finished May 09 01:05:32 PM PDT 24
Peak memory 250708 kb
Host smart-7f0ddcf2-4763-415d-a506-cb14bcb8f5de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180193272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1180193272
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.770262347
Short name T112
Test name
Test status
Simulation time 2099739563 ps
CPU time 29.55 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:05:18 PM PDT 24
Peak memory 200636 kb
Host smart-6b22ce43-e4a8-4d47-9e3a-169a0a33fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770262347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.770262347
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3879530473
Short name T250
Test name
Test status
Simulation time 720498722 ps
CPU time 5.86 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:04:54 PM PDT 24
Peak memory 200700 kb
Host smart-1abbe5e4-a2bf-42cc-80a0-ecf223727cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879530473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3879530473
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.738554941
Short name T121
Test name
Test status
Simulation time 32548911277 ps
CPU time 1702.57 seconds
Started May 09 01:04:47 PM PDT 24
Finished May 09 01:33:11 PM PDT 24
Peak memory 801428 kb
Host smart-55fdf100-ce92-4005-9014-e6d1e7f3488d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738554941 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.738554941
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3971925636
Short name T294
Test name
Test status
Simulation time 56869196 ps
CPU time 1.29 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:04:49 PM PDT 24
Peak memory 200592 kb
Host smart-09668358-1302-4c86-83e5-039702ddf6c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971925636 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3971925636
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2462835973
Short name T360
Test name
Test status
Simulation time 215117561068 ps
CPU time 381.62 seconds
Started May 09 01:04:49 PM PDT 24
Finished May 09 01:11:13 PM PDT 24
Peak memory 200724 kb
Host smart-29cafd45-1937-4ef1-936d-0b6acaa6e7c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462835973 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2462835973
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1108823072
Short name T189
Test name
Test status
Simulation time 22912740 ps
CPU time 0.61 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:04:48 PM PDT 24
Peak memory 196300 kb
Host smart-c75fc76e-7303-4067-845d-14ae82516828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108823072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1108823072
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4234459598
Short name T196
Test name
Test status
Simulation time 4225361372 ps
CPU time 50.62 seconds
Started May 09 01:04:49 PM PDT 24
Finished May 09 01:05:41 PM PDT 24
Peak memory 220212 kb
Host smart-3ef14108-1dab-470e-baeb-fe692a757fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234459598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4234459598
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3547967292
Short name T75
Test name
Test status
Simulation time 4056953657 ps
CPU time 58.42 seconds
Started May 09 01:04:49 PM PDT 24
Finished May 09 01:05:49 PM PDT 24
Peak memory 200756 kb
Host smart-5bae351b-2ff4-4e19-90c3-ad7cbedc3853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547967292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3547967292
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3933363397
Short name T245
Test name
Test status
Simulation time 10286376441 ps
CPU time 613.96 seconds
Started May 09 01:04:48 PM PDT 24
Finished May 09 01:15:04 PM PDT 24
Peak memory 717328 kb
Host smart-4dc65e95-cdc1-41ef-af1f-9e40adb31488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933363397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3933363397
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.4084620304
Short name T306
Test name
Test status
Simulation time 3983651536 ps
CPU time 17.21 seconds
Started May 09 01:04:45 PM PDT 24
Finished May 09 01:05:03 PM PDT 24
Peak memory 200564 kb
Host smart-c31250b1-5ab5-402f-8922-f554c44f2d4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084620304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4084620304
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4288598525
Short name T455
Test name
Test status
Simulation time 8258806942 ps
CPU time 60.44 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:05:47 PM PDT 24
Peak memory 200708 kb
Host smart-0d917ea8-5e5f-4f4b-8bd4-dc436f4186b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288598525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4288598525
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2056531101
Short name T325
Test name
Test status
Simulation time 4032911380 ps
CPU time 6.35 seconds
Started May 09 01:05:19 PM PDT 24
Finished May 09 01:05:27 PM PDT 24
Peak memory 200772 kb
Host smart-3ace65f3-6304-4f41-8783-1f5226fc12ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056531101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2056531101
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1572787015
Short name T24
Test name
Test status
Simulation time 7958172518 ps
CPU time 435.3 seconds
Started May 09 01:04:48 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 200696 kb
Host smart-e3fe95f6-6235-4785-9730-096a2d541ec2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572787015 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1572787015
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4254658033
Short name T21
Test name
Test status
Simulation time 40070301 ps
CPU time 0.58 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:00 PM PDT 24
Peak memory 195320 kb
Host smart-69131267-8580-4266-9c40-2d7d8461bcf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254658033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4254658033
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2304247521
Short name T388
Test name
Test status
Simulation time 303381066 ps
CPU time 3.79 seconds
Started May 09 01:04:54 PM PDT 24
Finished May 09 01:04:59 PM PDT 24
Peak memory 200468 kb
Host smart-c12fa768-66aa-4d74-9460-299b768bbf53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304247521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2304247521
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.888156852
Short name T226
Test name
Test status
Simulation time 256877871 ps
CPU time 3.53 seconds
Started May 09 01:04:47 PM PDT 24
Finished May 09 01:04:53 PM PDT 24
Peak memory 200520 kb
Host smart-1d2f7de6-f167-489f-94a8-97b5dea233d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888156852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.888156852
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.201873977
Short name T368
Test name
Test status
Simulation time 11198827723 ps
CPU time 483.67 seconds
Started May 09 01:04:46 PM PDT 24
Finished May 09 01:12:51 PM PDT 24
Peak memory 711708 kb
Host smart-969155d1-d353-4208-8e6c-d7a4404b0366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201873977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.201873977
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3460316043
Short name T402
Test name
Test status
Simulation time 15253065465 ps
CPU time 130.29 seconds
Started May 09 01:04:49 PM PDT 24
Finished May 09 01:07:01 PM PDT 24
Peak memory 200752 kb
Host smart-79cbe4b2-04d1-45f0-9ce2-ddaea02fb17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460316043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3460316043
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.859582838
Short name T60
Test name
Test status
Simulation time 137178593 ps
CPU time 4.37 seconds
Started May 09 01:04:49 PM PDT 24
Finished May 09 01:04:55 PM PDT 24
Peak memory 200624 kb
Host smart-65ddb641-52d8-416e-8748-fc14be4a19ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859582838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.859582838
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2023373305
Short name T423
Test name
Test status
Simulation time 194876101 ps
CPU time 1.27 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:05:03 PM PDT 24
Peak memory 200508 kb
Host smart-4740fa99-0b49-4eab-ba6d-ea4a3c1cfadf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023373305 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2023373305
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.4148662420
Short name T190
Test name
Test status
Simulation time 8736070667 ps
CPU time 443.95 seconds
Started May 09 01:04:49 PM PDT 24
Finished May 09 01:12:14 PM PDT 24
Peak memory 200680 kb
Host smart-029bc7fc-fcbd-4489-b323-ca44c03ed4a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148662420 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.4148662420
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3849229476
Short name T152
Test name
Test status
Simulation time 62100376 ps
CPU time 0.57 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:00 PM PDT 24
Peak memory 196040 kb
Host smart-8c9e8480-4eca-4853-9057-18860e8eefde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849229476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3849229476
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4064512388
Short name T376
Test name
Test status
Simulation time 443156846 ps
CPU time 11.16 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:05:13 PM PDT 24
Peak memory 215992 kb
Host smart-0fe669bf-916b-4304-9aba-f8d461e71d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064512388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4064512388
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.4223232068
Short name T435
Test name
Test status
Simulation time 162810563 ps
CPU time 8.25 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:08 PM PDT 24
Peak memory 200652 kb
Host smart-0b1be67b-4380-4264-af30-b26de0f5a57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223232068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.4223232068
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2704140753
Short name T465
Test name
Test status
Simulation time 5718879985 ps
CPU time 716.06 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:16:57 PM PDT 24
Peak memory 729660 kb
Host smart-c455ffdf-d8ac-4885-b63f-36ee7c5ec0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704140753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2704140753
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2015573217
Short name T257
Test name
Test status
Simulation time 4049494961 ps
CPU time 76.64 seconds
Started May 09 01:05:02 PM PDT 24
Finished May 09 01:06:20 PM PDT 24
Peak memory 200748 kb
Host smart-e398b847-1e2e-428f-ab0d-36a3f716d10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015573217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2015573217
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3608468551
Short name T358
Test name
Test status
Simulation time 2943624684 ps
CPU time 6.54 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:05:08 PM PDT 24
Peak memory 200688 kb
Host smart-d29fdea5-654e-4ac4-a1e6-b4f8c131c974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608468551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3608468551
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2988091976
Short name T450
Test name
Test status
Simulation time 3118674909 ps
CPU time 15.98 seconds
Started May 09 01:05:00 PM PDT 24
Finished May 09 01:05:18 PM PDT 24
Peak memory 200564 kb
Host smart-f62af76d-63c5-4f94-8b11-75e752f6eaa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988091976 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2988091976
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.999313106
Short name T225
Test name
Test status
Simulation time 29689549 ps
CPU time 0.96 seconds
Started May 09 01:05:00 PM PDT 24
Finished May 09 01:05:04 PM PDT 24
Peak memory 199552 kb
Host smart-267a91c6-bce9-4544-b180-183cda8377ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999313106 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.999313106
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3835316600
Short name T385
Test name
Test status
Simulation time 38407769893 ps
CPU time 507.46 seconds
Started May 09 01:04:57 PM PDT 24
Finished May 09 01:13:25 PM PDT 24
Peak memory 200644 kb
Host smart-bfdb9676-afe5-4d1f-96f5-4db270d03543
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835316600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3835316600
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1659763662
Short name T232
Test name
Test status
Simulation time 48077032 ps
CPU time 0.59 seconds
Started May 09 01:04:57 PM PDT 24
Finished May 09 01:04:58 PM PDT 24
Peak memory 196224 kb
Host smart-ea0a2395-5447-4ba2-9dc7-9bc2f1d1be18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659763662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1659763662
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1886699635
Short name T52
Test name
Test status
Simulation time 357708055 ps
CPU time 8.35 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:09 PM PDT 24
Peak memory 200564 kb
Host smart-3f8e4405-2fbb-4af9-b5c0-d0010991f3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886699635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1886699635
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2268258294
Short name T419
Test name
Test status
Simulation time 928164672 ps
CPU time 12.26 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:13 PM PDT 24
Peak memory 200560 kb
Host smart-c555e6c7-5166-450a-9dce-12c94bf78039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268258294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2268258294
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4117359301
Short name T462
Test name
Test status
Simulation time 2006955625 ps
CPU time 9.35 seconds
Started May 09 01:05:00 PM PDT 24
Finished May 09 01:05:12 PM PDT 24
Peak memory 200540 kb
Host smart-e1dbf2f3-8840-4b85-a92b-832d84b28079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117359301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4117359301
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2583771656
Short name T27
Test name
Test status
Simulation time 365452272 ps
CPU time 5.65 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:05 PM PDT 24
Peak memory 200604 kb
Host smart-f6ab5f40-76ff-49ef-89da-3caa5430eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583771656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2583771656
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.929312256
Short name T472
Test name
Test status
Simulation time 26385237591 ps
CPU time 489.39 seconds
Started May 09 01:04:57 PM PDT 24
Finished May 09 01:13:07 PM PDT 24
Peak memory 200628 kb
Host smart-f18ed3f0-e79a-4e43-b5f0-2c446b914eae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929312256 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.929312256
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.468208702
Short name T221
Test name
Test status
Simulation time 192430026 ps
CPU time 1.1 seconds
Started May 09 01:05:03 PM PDT 24
Finished May 09 01:05:05 PM PDT 24
Peak memory 200348 kb
Host smart-40131e5a-1e40-4717-b34e-68ac729b5c2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468208702 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.468208702
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3456254307
Short name T239
Test name
Test status
Simulation time 32429230174 ps
CPU time 429.68 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:12:10 PM PDT 24
Peak memory 200668 kb
Host smart-ee456811-23af-4fc7-973d-c0a1dc9c03b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456254307 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.3456254307
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2279697922
Short name T387
Test name
Test status
Simulation time 40839355 ps
CPU time 0.61 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:01 PM PDT 24
Peak memory 196352 kb
Host smart-b211377c-7b1b-4f09-b887-93b65d2e2ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279697922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2279697922
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.153087539
Short name T222
Test name
Test status
Simulation time 3819191136 ps
CPU time 50.12 seconds
Started May 09 01:05:05 PM PDT 24
Finished May 09 01:05:56 PM PDT 24
Peak memory 200704 kb
Host smart-117e99b7-3ef6-4f19-8581-7210c9d3ed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153087539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.153087539
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.831671321
Short name T352
Test name
Test status
Simulation time 25265419978 ps
CPU time 867.53 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:19:29 PM PDT 24
Peak memory 730392 kb
Host smart-f86d90a5-6cd1-4487-b158-57016f541805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831671321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.831671321
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3588188737
Short name T3
Test name
Test status
Simulation time 15070286352 ps
CPU time 107.09 seconds
Started May 09 01:05:00 PM PDT 24
Finished May 09 01:06:49 PM PDT 24
Peak memory 200680 kb
Host smart-e8e94262-e77e-41a7-a14c-8a76e8777859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588188737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3588188737
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3892495412
Short name T268
Test name
Test status
Simulation time 141961857 ps
CPU time 2.11 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:05:03 PM PDT 24
Peak memory 200592 kb
Host smart-4da21fee-2a54-4df5-bd60-b15030171b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892495412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3892495412
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3156439341
Short name T417
Test name
Test status
Simulation time 262098280 ps
CPU time 1.12 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:05:03 PM PDT 24
Peak memory 200224 kb
Host smart-eadd9eea-116f-42e9-a2c3-f662035c0cab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156439341 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3156439341
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.901656637
Short name T409
Test name
Test status
Simulation time 27096297748 ps
CPU time 496.65 seconds
Started May 09 01:04:57 PM PDT 24
Finished May 09 01:13:15 PM PDT 24
Peak memory 200604 kb
Host smart-a49b5d9a-2c28-42b0-8475-5abed431ed44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901656637 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.901656637
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3166626669
Short name T309
Test name
Test status
Simulation time 33195567 ps
CPU time 0.59 seconds
Started May 09 01:05:02 PM PDT 24
Finished May 09 01:05:04 PM PDT 24
Peak memory 195328 kb
Host smart-ecca1327-7f07-479c-b9b8-28df5eba58d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166626669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3166626669
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.409881300
Short name T259
Test name
Test status
Simulation time 43006812 ps
CPU time 3.96 seconds
Started May 09 01:05:02 PM PDT 24
Finished May 09 01:05:08 PM PDT 24
Peak memory 224988 kb
Host smart-58339519-2225-4da9-8c6d-f55ca315022f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409881300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.409881300
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3633768837
Short name T119
Test name
Test status
Simulation time 2148146098 ps
CPU time 57.52 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:05:59 PM PDT 24
Peak memory 200772 kb
Host smart-61b3f813-8df4-44a4-b403-5c2313108102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633768837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3633768837
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.438621107
Short name T115
Test name
Test status
Simulation time 9831260033 ps
CPU time 508.19 seconds
Started May 09 01:05:02 PM PDT 24
Finished May 09 01:13:32 PM PDT 24
Peak memory 701200 kb
Host smart-15dbb760-2c17-416c-8897-cd48a04409d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438621107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.438621107
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1138005634
Short name T137
Test name
Test status
Simulation time 1383477220 ps
CPU time 13.52 seconds
Started May 09 01:05:00 PM PDT 24
Finished May 09 01:05:16 PM PDT 24
Peak memory 200496 kb
Host smart-e6d69d30-8e8d-49c8-9f1d-25c25f6c7d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138005634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1138005634
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.319747896
Short name T298
Test name
Test status
Simulation time 535975659 ps
CPU time 4.57 seconds
Started May 09 01:04:59 PM PDT 24
Finished May 09 01:05:06 PM PDT 24
Peak memory 200624 kb
Host smart-707ca524-411c-404e-8ce1-0457184e363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319747896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.319747896
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.4256376084
Short name T174
Test name
Test status
Simulation time 73716725 ps
CPU time 1.12 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:05:02 PM PDT 24
Peak memory 200016 kb
Host smart-7665749e-993d-49f7-ac5d-0f1485e44134
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256376084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.4256376084
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1315171645
Short name T317
Test name
Test status
Simulation time 74055733457 ps
CPU time 476.85 seconds
Started May 09 01:04:58 PM PDT 24
Finished May 09 01:12:56 PM PDT 24
Peak memory 200644 kb
Host smart-9640c117-4c82-4df2-b3c6-294e199fb1a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315171645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1315171645
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3582819857
Short name T335
Test name
Test status
Simulation time 136617925 ps
CPU time 0.63 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:03:47 PM PDT 24
Peak memory 196292 kb
Host smart-aea749bb-84a9-4bf1-a01e-f7bab02c67ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582819857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3582819857
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1449089042
Short name T477
Test name
Test status
Simulation time 1724645301 ps
CPU time 37.28 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:04:15 PM PDT 24
Peak memory 208816 kb
Host smart-7a38fc7e-3453-4737-aebc-9ce870870c8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449089042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1449089042
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2917197052
Short name T204
Test name
Test status
Simulation time 4396474141 ps
CPU time 17.61 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:03:56 PM PDT 24
Peak memory 200744 kb
Host smart-69e94708-ee31-4f18-870f-f4a2c0ea2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917197052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2917197052
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.912800514
Short name T140
Test name
Test status
Simulation time 1038970668 ps
CPU time 249.3 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:07:48 PM PDT 24
Peak memory 491052 kb
Host smart-90597dab-a2e9-423c-be14-918ca0ea1e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912800514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.912800514
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.243325239
Short name T251
Test name
Test status
Simulation time 609945606 ps
CPU time 34.16 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:04:12 PM PDT 24
Peak memory 200580 kb
Host smart-5159f3d0-7ca4-465b-b596-9336e1c64bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243325239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.243325239
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3554711605
Short name T34
Test name
Test status
Simulation time 83334348 ps
CPU time 0.99 seconds
Started May 09 01:03:45 PM PDT 24
Finished May 09 01:03:50 PM PDT 24
Peak memory 219964 kb
Host smart-f5fff318-96a1-4164-a98f-1b9232b5e8a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554711605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3554711605
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1464194414
Short name T355
Test name
Test status
Simulation time 118447414 ps
CPU time 1.16 seconds
Started May 09 01:03:35 PM PDT 24
Finished May 09 01:03:39 PM PDT 24
Peak memory 200560 kb
Host smart-e71c0de4-1784-47ae-bbbf-77d8b8b556cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464194414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1464194414
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.4067429003
Short name T253
Test name
Test status
Simulation time 139292754 ps
CPU time 1.3 seconds
Started May 09 01:03:34 PM PDT 24
Finished May 09 01:03:39 PM PDT 24
Peak memory 200516 kb
Host smart-71a3b8c3-fded-4f9a-acb3-de89a4079bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067429003 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.4067429003
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3038573406
Short name T350
Test name
Test status
Simulation time 57567958291 ps
CPU time 526.05 seconds
Started May 09 01:03:32 PM PDT 24
Finished May 09 01:12:21 PM PDT 24
Peak memory 200636 kb
Host smart-689e5122-f062-4c73-ab8a-587d6eb5f918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038573406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3038573406
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4139081700
Short name T406
Test name
Test status
Simulation time 13668676 ps
CPU time 0.57 seconds
Started May 09 01:05:13 PM PDT 24
Finished May 09 01:05:17 PM PDT 24
Peak memory 196304 kb
Host smart-aa0e03b9-cad1-4a72-ac77-8a1f7c4449e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139081700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4139081700
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.175656984
Short name T353
Test name
Test status
Simulation time 226798767 ps
CPU time 3.09 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:05:14 PM PDT 24
Peak memory 200576 kb
Host smart-a6a44184-81a6-4c7d-bf1a-674ed39c8305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175656984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.175656984
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3698791492
Short name T312
Test name
Test status
Simulation time 2027755071 ps
CPU time 10.18 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:05:25 PM PDT 24
Peak memory 200548 kb
Host smart-f314021c-07e9-4428-8c91-c5c9d4f7a340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698791492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3698791492
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1217725568
Short name T476
Test name
Test status
Simulation time 17749715453 ps
CPU time 1222.15 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:25:35 PM PDT 24
Peak memory 782368 kb
Host smart-7d04b82c-5ea4-4048-8862-bf0412c39a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217725568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1217725568
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2654218596
Short name T205
Test name
Test status
Simulation time 1627313855 ps
CPU time 48.86 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:06:01 PM PDT 24
Peak memory 200604 kb
Host smart-23e30252-c0aa-4c2a-9d14-df15f884fdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654218596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2654218596
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2638396653
Short name T453
Test name
Test status
Simulation time 96711942 ps
CPU time 1.87 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:05:15 PM PDT 24
Peak memory 200476 kb
Host smart-8257c4af-1019-4890-bbf2-8d3b7c11425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638396653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2638396653
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.423371557
Short name T235
Test name
Test status
Simulation time 63204555 ps
CPU time 1.37 seconds
Started May 09 01:05:12 PM PDT 24
Finished May 09 01:05:17 PM PDT 24
Peak memory 200488 kb
Host smart-e5518e4d-86b3-4f0b-b837-9514741a5a5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423371557 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.423371557
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1808562335
Short name T17
Test name
Test status
Simulation time 722105435681 ps
CPU time 568.97 seconds
Started May 09 01:05:13 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 200720 kb
Host smart-76382d7a-9c2a-4df0-bf91-2c1d3f0b3ab6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808562335 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1808562335
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2059057607
Short name T377
Test name
Test status
Simulation time 17597956 ps
CPU time 0.58 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:05:11 PM PDT 24
Peak memory 195304 kb
Host smart-89d6443a-62c2-41b8-9031-1b33eef61585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059057607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2059057607
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2875532511
Short name T133
Test name
Test status
Simulation time 1027576734 ps
CPU time 32.29 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:05:47 PM PDT 24
Peak memory 208824 kb
Host smart-2f0ef397-ef8d-46a3-bec0-fdfa6e72627b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875532511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2875532511
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3323791072
Short name T155
Test name
Test status
Simulation time 8896983281 ps
CPU time 58.01 seconds
Started May 09 01:05:12 PM PDT 24
Finished May 09 01:06:13 PM PDT 24
Peak memory 200772 kb
Host smart-2607784a-9585-4646-8f31-2e320f826224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323791072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3323791072
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2355705213
Short name T116
Test name
Test status
Simulation time 13498865674 ps
CPU time 829.73 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:19:03 PM PDT 24
Peak memory 681668 kb
Host smart-077aaf1d-9134-4388-b592-396442368dfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355705213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2355705213
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3882375790
Short name T412
Test name
Test status
Simulation time 6544902410 ps
CPU time 97.84 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:06:53 PM PDT 24
Peak memory 200764 kb
Host smart-e74b409c-9c61-4d7f-b961-1773a9969663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882375790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3882375790
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.938025130
Short name T397
Test name
Test status
Simulation time 614833444 ps
CPU time 7 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:05:21 PM PDT 24
Peak memory 200480 kb
Host smart-219a932d-1e74-4204-b3da-92fe0c9913ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938025130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.938025130
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.650098555
Short name T425
Test name
Test status
Simulation time 376339076 ps
CPU time 1.23 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:05:11 PM PDT 24
Peak memory 200568 kb
Host smart-c1714576-4174-4b09-99dc-0de21fa1bdc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650098555 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.650098555
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1352538909
Short name T384
Test name
Test status
Simulation time 14389649997 ps
CPU time 390.02 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:11:45 PM PDT 24
Peak memory 200672 kb
Host smart-9de880c8-664e-4487-a6e4-9d2c06e2a067
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352538909 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1352538909
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3255108122
Short name T367
Test name
Test status
Simulation time 44283003 ps
CPU time 0.59 seconds
Started May 09 01:05:12 PM PDT 24
Finished May 09 01:05:16 PM PDT 24
Peak memory 196336 kb
Host smart-ea6ba5d6-8b70-4e8b-baaf-69e588395448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255108122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3255108122
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.803733916
Short name T292
Test name
Test status
Simulation time 777489047 ps
CPU time 18.05 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:05:29 PM PDT 24
Peak memory 219912 kb
Host smart-187e2619-1d97-49ea-9526-c09598fad7ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803733916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.803733916
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2519909400
Short name T413
Test name
Test status
Simulation time 579053629 ps
CPU time 9.01 seconds
Started May 09 01:05:16 PM PDT 24
Finished May 09 01:05:27 PM PDT 24
Peak memory 200636 kb
Host smart-68ea623a-1907-48cb-9263-8e8f4ffe14d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519909400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2519909400
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1118684997
Short name T238
Test name
Test status
Simulation time 23529059549 ps
CPU time 807.81 seconds
Started May 09 01:05:08 PM PDT 24
Finished May 09 01:18:37 PM PDT 24
Peak memory 747020 kb
Host smart-1eb6c759-28cf-45e8-819b-02beaf25c942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118684997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1118684997
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1480932064
Short name T333
Test name
Test status
Simulation time 1180279572 ps
CPU time 18.19 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:05:30 PM PDT 24
Peak memory 200628 kb
Host smart-9373d9ca-6035-47e6-aae7-801c50be16f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480932064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1480932064
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3357174122
Short name T274
Test name
Test status
Simulation time 1973606945 ps
CPU time 10.51 seconds
Started May 09 01:05:08 PM PDT 24
Finished May 09 01:05:20 PM PDT 24
Peak memory 200600 kb
Host smart-7ee36455-ecf9-47fe-a29d-e8ed82a28e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357174122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3357174122
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3474103126
Short name T302
Test name
Test status
Simulation time 137371928 ps
CPU time 2.63 seconds
Started May 09 01:05:14 PM PDT 24
Finished May 09 01:05:20 PM PDT 24
Peak memory 200568 kb
Host smart-1710b76b-604e-46c0-990f-2839d1384dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474103126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3474103126
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3248624121
Short name T318
Test name
Test status
Simulation time 94184737 ps
CPU time 0.95 seconds
Started May 09 01:05:12 PM PDT 24
Finished May 09 01:05:17 PM PDT 24
Peak memory 199212 kb
Host smart-43ae8f60-0827-4af8-a8e8-2f4a6da1bee8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248624121 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3248624121
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.396360645
Short name T442
Test name
Test status
Simulation time 74414840670 ps
CPU time 489.2 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:13:25 PM PDT 24
Peak memory 200676 kb
Host smart-b28dbd7a-27c9-4923-9ac2-4c69cea54dcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396360645 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.396360645
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3039351572
Short name T445
Test name
Test status
Simulation time 13490352 ps
CPU time 0.64 seconds
Started May 09 01:05:14 PM PDT 24
Finished May 09 01:05:18 PM PDT 24
Peak memory 196296 kb
Host smart-7ea5147c-f94e-45f5-8baf-d60cda435e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039351572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3039351572
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4195956110
Short name T191
Test name
Test status
Simulation time 614322148 ps
CPU time 9.19 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:05:23 PM PDT 24
Peak memory 200628 kb
Host smart-83b16ec0-4c28-4c82-8904-9053855d661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195956110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4195956110
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4077874781
Short name T343
Test name
Test status
Simulation time 2423611071 ps
CPU time 649.22 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:16:02 PM PDT 24
Peak memory 711620 kb
Host smart-39ab08c6-b9fe-49fc-bee0-bbb34079dad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077874781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4077874781
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1964713465
Short name T248
Test name
Test status
Simulation time 398801888 ps
CPU time 8.06 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:05:23 PM PDT 24
Peak memory 200372 kb
Host smart-9c5830f5-2a6e-4397-bf5c-b174eff48828
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964713465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1964713465
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3220533041
Short name T234
Test name
Test status
Simulation time 1255176084 ps
CPU time 76.98 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:06:27 PM PDT 24
Peak memory 200656 kb
Host smart-d67adf8e-39c7-4cb6-b549-aeb11e4981e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220533041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3220533041
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3853558677
Short name T91
Test name
Test status
Simulation time 53819390 ps
CPU time 1.77 seconds
Started May 09 01:05:12 PM PDT 24
Finished May 09 01:05:17 PM PDT 24
Peak memory 200528 kb
Host smart-d457e274-5aae-4f93-ab0f-e8f135ca120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853558677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3853558677
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1293913622
Short name T156
Test name
Test status
Simulation time 57710883 ps
CPU time 1.32 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:05:14 PM PDT 24
Peak memory 200668 kb
Host smart-a9c3c61a-0c8b-4bc7-b978-9ac464c63670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293913622 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1293913622
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2846916821
Short name T46
Test name
Test status
Simulation time 7960558175 ps
CPU time 430.49 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:12:21 PM PDT 24
Peak memory 200688 kb
Host smart-772a6067-8da5-44cc-9a00-a4cede6d2318
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846916821 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2846916821
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3104420955
Short name T159
Test name
Test status
Simulation time 32334904 ps
CPU time 0.57 seconds
Started May 09 01:05:13 PM PDT 24
Finished May 09 01:05:17 PM PDT 24
Peak memory 195956 kb
Host smart-9cb09139-8b25-44a8-a213-043c1db415c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104420955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3104420955
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3019104357
Short name T8
Test name
Test status
Simulation time 3734960959 ps
CPU time 22.24 seconds
Started May 09 01:05:12 PM PDT 24
Finished May 09 01:05:38 PM PDT 24
Peak memory 208964 kb
Host smart-34d9144a-2ba6-42e1-9dcd-bba246a4e6bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019104357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3019104357
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3315890488
Short name T314
Test name
Test status
Simulation time 1063917681 ps
CPU time 53.34 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:06:06 PM PDT 24
Peak memory 200548 kb
Host smart-1a929165-b9e0-42ba-b288-99607b7ec2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315890488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3315890488
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2509992038
Short name T346
Test name
Test status
Simulation time 8442812006 ps
CPU time 1077 seconds
Started May 09 01:05:09 PM PDT 24
Finished May 09 01:23:09 PM PDT 24
Peak memory 739348 kb
Host smart-a5a49592-eafb-4806-8025-51d6690bf8d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509992038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2509992038
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2286685853
Short name T236
Test name
Test status
Simulation time 3926112787 ps
CPU time 30.29 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:05:45 PM PDT 24
Peak memory 200620 kb
Host smart-c66b9008-70c2-4d2b-9d71-151d94d91bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286685853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2286685853
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2216026680
Short name T474
Test name
Test status
Simulation time 1173750566 ps
CPU time 3.78 seconds
Started May 09 01:05:11 PM PDT 24
Finished May 09 01:05:19 PM PDT 24
Peak memory 200500 kb
Host smart-12c69a7e-85dc-489b-861e-f59c1441c64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216026680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2216026680
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.976293870
Short name T293
Test name
Test status
Simulation time 42829886 ps
CPU time 0.97 seconds
Started May 09 01:05:15 PM PDT 24
Finished May 09 01:05:18 PM PDT 24
Peak memory 198736 kb
Host smart-5a71c579-2b4f-4281-9990-9b7f118249dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976293870 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.976293870
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2855808167
Short name T331
Test name
Test status
Simulation time 81695120768 ps
CPU time 523.59 seconds
Started May 09 01:05:10 PM PDT 24
Finished May 09 01:13:58 PM PDT 24
Peak memory 200648 kb
Host smart-2af5f66a-4781-4267-b653-7823d6301875
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855808167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2855808167
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2967445226
Short name T459
Test name
Test status
Simulation time 41037817 ps
CPU time 0.59 seconds
Started May 09 01:05:22 PM PDT 24
Finished May 09 01:05:25 PM PDT 24
Peak memory 195220 kb
Host smart-3fc99ef9-1cdf-4393-94f6-b28c9784aa74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967445226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2967445226
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1589513592
Short name T428
Test name
Test status
Simulation time 378112327 ps
CPU time 20.56 seconds
Started May 09 01:05:22 PM PDT 24
Finished May 09 01:05:45 PM PDT 24
Peak memory 214920 kb
Host smart-bf6fdffa-8d59-46e4-bebc-9ce603888717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589513592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1589513592
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2587074483
Short name T2
Test name
Test status
Simulation time 1591069034 ps
CPU time 30.76 seconds
Started May 09 01:05:25 PM PDT 24
Finished May 09 01:05:57 PM PDT 24
Peak memory 200600 kb
Host smart-f4ea62dc-370e-4390-9f6a-1c5a44f28707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587074483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2587074483
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3761607366
Short name T118
Test name
Test status
Simulation time 9732627091 ps
CPU time 631.46 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:15:53 PM PDT 24
Peak memory 690676 kb
Host smart-eeccce9e-26c0-4a74-9703-b041900e0199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761607366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3761607366
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2441808109
Short name T337
Test name
Test status
Simulation time 5594216051 ps
CPU time 31.93 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:05:56 PM PDT 24
Peak memory 200804 kb
Host smart-bf5b6ba7-c234-4a4b-b499-15835304c7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441808109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2441808109
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3327830787
Short name T424
Test name
Test status
Simulation time 146094550 ps
CPU time 4.8 seconds
Started May 09 01:05:22 PM PDT 24
Finished May 09 01:05:30 PM PDT 24
Peak memory 200568 kb
Host smart-2e6be7f6-52a5-4325-a0a2-05e9c56752b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327830787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3327830787
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1982933109
Short name T145
Test name
Test status
Simulation time 42355214 ps
CPU time 1.01 seconds
Started May 09 01:05:23 PM PDT 24
Finished May 09 01:05:26 PM PDT 24
Peak memory 199188 kb
Host smart-424d50f9-6a7c-4771-83b5-fc3935ee0904
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982933109 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1982933109
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.671862969
Short name T233
Test name
Test status
Simulation time 36211363143 ps
CPU time 509.29 seconds
Started May 09 01:05:23 PM PDT 24
Finished May 09 01:13:54 PM PDT 24
Peak memory 200648 kb
Host smart-4d600bc3-1eae-416e-b60b-9a708f2b33e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671862969 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.671862969
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.615511883
Short name T218
Test name
Test status
Simulation time 22859760 ps
CPU time 0.55 seconds
Started May 09 01:05:34 PM PDT 24
Finished May 09 01:05:37 PM PDT 24
Peak memory 195304 kb
Host smart-17530d38-61e3-45c7-bcb0-b75f8edff815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615511883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.615511883
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2149159437
Short name T407
Test name
Test status
Simulation time 16289376468 ps
CPU time 44.46 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:06:07 PM PDT 24
Peak memory 221132 kb
Host smart-b047c373-2238-4ec8-bc15-40eb29611b35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149159437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2149159437
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1510095717
Short name T120
Test name
Test status
Simulation time 759011441 ps
CPU time 35.94 seconds
Started May 09 01:05:35 PM PDT 24
Finished May 09 01:06:13 PM PDT 24
Peak memory 200632 kb
Host smart-b6ce322b-7028-420a-bc6d-34f5c6a7dbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510095717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1510095717
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1021380972
Short name T297
Test name
Test status
Simulation time 1410346039 ps
CPU time 314.76 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:10:37 PM PDT 24
Peak memory 494816 kb
Host smart-79a56160-b000-4628-acc8-725bc837e7bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021380972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1021380972
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2798113793
Short name T324
Test name
Test status
Simulation time 7278557943 ps
CPU time 110.61 seconds
Started May 09 01:05:24 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 200712 kb
Host smart-13685fbe-1bb2-4da8-989c-f97c4ef27c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798113793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2798113793
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2616939779
Short name T341
Test name
Test status
Simulation time 182959737 ps
CPU time 3.02 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:05:25 PM PDT 24
Peak memory 200516 kb
Host smart-52373bf6-7999-4a39-958e-ffabaecb2034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616939779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2616939779
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1551736310
Short name T280
Test name
Test status
Simulation time 51532052164 ps
CPU time 1134.15 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:24:17 PM PDT 24
Peak memory 763972 kb
Host smart-ce2ef36a-dc9b-464c-a0d7-356b880e6926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551736310 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1551736310
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.811483949
Short name T310
Test name
Test status
Simulation time 33776063 ps
CPU time 1.34 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:05:24 PM PDT 24
Peak memory 200376 kb
Host smart-f22127d3-a7d3-4f20-a473-8c328d24eddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811483949 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.811483949
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1284078062
Short name T278
Test name
Test status
Simulation time 32363821286 ps
CPU time 476.43 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:13:20 PM PDT 24
Peak memory 200716 kb
Host smart-1156eb75-cc7a-47d4-bb04-543d39110265
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284078062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1284078062
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4080349774
Short name T208
Test name
Test status
Simulation time 14116250 ps
CPU time 0.57 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:05:25 PM PDT 24
Peak memory 195248 kb
Host smart-710610a7-c5f1-48f1-97e6-3380c56fff6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080349774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4080349774
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1301846665
Short name T220
Test name
Test status
Simulation time 1069480035 ps
CPU time 53.65 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:06:17 PM PDT 24
Peak memory 241532 kb
Host smart-95b587ee-33c0-46f8-8d09-98c0502e638f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301846665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1301846665
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2697168878
Short name T9
Test name
Test status
Simulation time 35361626691 ps
CPU time 57.41 seconds
Started May 09 01:05:34 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 200716 kb
Host smart-dd4c13d9-289e-426c-9ae3-45531ca2eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697168878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2697168878
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4080622792
Short name T469
Test name
Test status
Simulation time 3927796244 ps
CPU time 669.78 seconds
Started May 09 01:05:34 PM PDT 24
Finished May 09 01:16:46 PM PDT 24
Peak memory 735660 kb
Host smart-3438f4f0-afce-4e8f-8d28-9d80914b6ea6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080622792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4080622792
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3218491093
Short name T187
Test name
Test status
Simulation time 1017445331 ps
CPU time 29.5 seconds
Started May 09 01:05:19 PM PDT 24
Finished May 09 01:05:50 PM PDT 24
Peak memory 200572 kb
Host smart-c30ea7d8-8e97-4773-907e-6e7ff6c98e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218491093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3218491093
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3479633475
Short name T361
Test name
Test status
Simulation time 322661811 ps
CPU time 2.78 seconds
Started May 09 01:05:24 PM PDT 24
Finished May 09 01:05:29 PM PDT 24
Peak memory 200572 kb
Host smart-bdb4df84-c66a-40cf-be20-29adf85fd20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479633475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3479633475
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.82848650
Short name T289
Test name
Test status
Simulation time 1492412828 ps
CPU time 18.21 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:05:42 PM PDT 24
Peak memory 200624 kb
Host smart-929617a8-c42a-4574-aa9d-2e2abb879c2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82848650 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.82848650
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2973004609
Short name T345
Test name
Test status
Simulation time 49596290 ps
CPU time 1.03 seconds
Started May 09 01:05:24 PM PDT 24
Finished May 09 01:05:27 PM PDT 24
Peak memory 199204 kb
Host smart-9be92e41-6aa6-4baf-8261-48b5e673a239
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973004609 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2973004609
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3119433585
Short name T272
Test name
Test status
Simulation time 115713538990 ps
CPU time 501.8 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:13:46 PM PDT 24
Peak memory 200624 kb
Host smart-e3e01484-a398-4f1e-bb1b-70edc905cde9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119433585 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3119433585
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1451957697
Short name T32
Test name
Test status
Simulation time 662997897 ps
CPU time 9.41 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:05:32 PM PDT 24
Peak memory 200444 kb
Host smart-cba81a77-5396-4699-9146-116b231fae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451957697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1451957697
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2102555775
Short name T148
Test name
Test status
Simulation time 29280931 ps
CPU time 0.56 seconds
Started May 09 01:05:25 PM PDT 24
Finished May 09 01:05:27 PM PDT 24
Peak memory 195300 kb
Host smart-adca4e30-01bf-4477-a1c8-8db1aa474333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102555775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2102555775
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3615742753
Short name T443
Test name
Test status
Simulation time 891934422 ps
CPU time 11.91 seconds
Started May 09 01:05:23 PM PDT 24
Finished May 09 01:05:37 PM PDT 24
Peak memory 200660 kb
Host smart-71307df3-07d7-4a6e-b605-545d77f91623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615742753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3615742753
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.866824495
Short name T110
Test name
Test status
Simulation time 3206844190 ps
CPU time 11.38 seconds
Started May 09 01:05:23 PM PDT 24
Finished May 09 01:05:37 PM PDT 24
Peak memory 200744 kb
Host smart-bd1482a7-6f01-4c95-89e9-3dd50b85271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866824495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.866824495
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2360740331
Short name T354
Test name
Test status
Simulation time 50251811868 ps
CPU time 584.51 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:15:08 PM PDT 24
Peak memory 527060 kb
Host smart-79a7832a-1c07-4557-ad00-3719a9cb3e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360740331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2360740331
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1976111811
Short name T223
Test name
Test status
Simulation time 6619772598 ps
CPU time 34.97 seconds
Started May 09 01:05:23 PM PDT 24
Finished May 09 01:06:00 PM PDT 24
Peak memory 200724 kb
Host smart-d045ae1e-7fa5-422f-b648-5421fc77025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976111811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1976111811
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1828531923
Short name T13
Test name
Test status
Simulation time 263914896 ps
CPU time 4.33 seconds
Started May 09 01:05:34 PM PDT 24
Finished May 09 01:05:41 PM PDT 24
Peak memory 200576 kb
Host smart-410423c9-0008-4f04-977f-beafdaf87a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828531923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1828531923
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.850813468
Short name T316
Test name
Test status
Simulation time 104772788 ps
CPU time 1.06 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:05:25 PM PDT 24
Peak memory 199924 kb
Host smart-665bbe10-faa2-4010-ab9c-cd5931fe1324
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850813468 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.850813468
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1596254372
Short name T307
Test name
Test status
Simulation time 29490198649 ps
CPU time 505.61 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:13:47 PM PDT 24
Peak memory 200636 kb
Host smart-36ba0d0b-9981-4063-bc7e-7b42fdf8cbe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596254372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1596254372
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_alert_test.921208011
Short name T301
Test name
Test status
Simulation time 14849024 ps
CPU time 0.63 seconds
Started May 09 01:05:33 PM PDT 24
Finished May 09 01:05:36 PM PDT 24
Peak memory 195304 kb
Host smart-369d098e-7d7b-45ca-ada0-f43933ef413a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921208011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.921208011
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2410997558
Short name T19
Test name
Test status
Simulation time 101415049 ps
CPU time 5.37 seconds
Started May 09 01:05:23 PM PDT 24
Finished May 09 01:05:31 PM PDT 24
Peak memory 200508 kb
Host smart-c56ccae5-00ed-43d6-8dd1-14b68b2be670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410997558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2410997558
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1133787657
Short name T284
Test name
Test status
Simulation time 371871255 ps
CPU time 19.13 seconds
Started May 09 01:05:35 PM PDT 24
Finished May 09 01:05:56 PM PDT 24
Peak memory 200600 kb
Host smart-584537b7-ac5e-4595-a6ed-5b93fcdf916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133787657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1133787657
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4129428470
Short name T70
Test name
Test status
Simulation time 3759805148 ps
CPU time 859.18 seconds
Started May 09 01:05:21 PM PDT 24
Finished May 09 01:19:43 PM PDT 24
Peak memory 738972 kb
Host smart-a6c65688-2ccb-43db-b6b2-e2593eb76b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129428470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4129428470
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2367121997
Short name T41
Test name
Test status
Simulation time 1860424008 ps
CPU time 31.49 seconds
Started May 09 01:05:23 PM PDT 24
Finished May 09 01:05:57 PM PDT 24
Peak memory 200608 kb
Host smart-804b0c94-290c-4259-aef8-85a15a9db7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367121997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2367121997
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2655751991
Short name T183
Test name
Test status
Simulation time 124097233 ps
CPU time 3.95 seconds
Started May 09 01:05:20 PM PDT 24
Finished May 09 01:05:26 PM PDT 24
Peak memory 200544 kb
Host smart-be9a9806-fdc6-497c-9908-01f889584251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655751991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2655751991
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2499815973
Short name T203
Test name
Test status
Simulation time 71676297 ps
CPU time 1.31 seconds
Started May 09 01:05:35 PM PDT 24
Finished May 09 01:05:38 PM PDT 24
Peak memory 199524 kb
Host smart-04c2471c-3861-4ffc-a761-ca86dfd3ebb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499815973 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2499815973
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.921935428
Short name T6
Test name
Test status
Simulation time 7090709182 ps
CPU time 407.2 seconds
Started May 09 01:05:34 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 200604 kb
Host smart-95204397-49c8-4455-8e9c-eb6b05018b33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921935428 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.921935428
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3307128089
Short name T30
Test name
Test status
Simulation time 67574394 ps
CPU time 3.45 seconds
Started May 09 01:05:32 PM PDT 24
Finished May 09 01:05:37 PM PDT 24
Peak memory 200552 kb
Host smart-2538b6b4-843f-4ecd-a837-759c6de23698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307128089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3307128089
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.777659909
Short name T275
Test name
Test status
Simulation time 23642584 ps
CPU time 0.66 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:03:48 PM PDT 24
Peak memory 196176 kb
Host smart-e3d258c2-6572-4132-87af-38761a1478ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777659909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.777659909
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1422331526
Short name T176
Test name
Test status
Simulation time 555274496 ps
CPU time 18.68 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:04:04 PM PDT 24
Peak memory 208772 kb
Host smart-65fda458-ab89-4405-a946-2a86226b2be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422331526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1422331526
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3178346191
Short name T416
Test name
Test status
Simulation time 3338052636 ps
CPU time 48.28 seconds
Started May 09 01:03:46 PM PDT 24
Finished May 09 01:04:38 PM PDT 24
Peak memory 200720 kb
Host smart-a99fc8fb-9647-4099-9b95-e7722056bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178346191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3178346191
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2700088318
Short name T198
Test name
Test status
Simulation time 7073824459 ps
CPU time 375.07 seconds
Started May 09 01:03:41 PM PDT 24
Finished May 09 01:10:00 PM PDT 24
Peak memory 631528 kb
Host smart-65af35ce-cce6-47ef-9261-2b3e6389b81b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700088318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2700088318
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2597153206
Short name T15
Test name
Test status
Simulation time 6992009018 ps
CPU time 52.46 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:04:39 PM PDT 24
Peak memory 200704 kb
Host smart-4cb37c50-33fc-4994-95b2-03f07090118d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597153206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2597153206
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4132931565
Short name T45
Test name
Test status
Simulation time 16868263376 ps
CPU time 48.99 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:04:36 PM PDT 24
Peak memory 200660 kb
Host smart-b664b6ec-ea1c-4ace-afa3-1d86c6c70cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132931565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4132931565
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2585839992
Short name T432
Test name
Test status
Simulation time 47087618 ps
CPU time 0.79 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:03:49 PM PDT 24
Peak memory 197860 kb
Host smart-dc4fb69b-d93d-4318-89bb-afdea9019aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585839992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2585839992
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3232978713
Short name T390
Test name
Test status
Simulation time 76485489 ps
CPU time 0.98 seconds
Started May 09 01:03:41 PM PDT 24
Finished May 09 01:03:45 PM PDT 24
Peak memory 199300 kb
Host smart-d5274db8-b435-460f-8ced-cfce26c50ea7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232978713 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3232978713
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.360058222
Short name T283
Test name
Test status
Simulation time 34807013017 ps
CPU time 484.09 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 200668 kb
Host smart-932aa4ed-e0fa-4888-ac20-952ad463fa28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360058222 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.360058222
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2289613146
Short name T147
Test name
Test status
Simulation time 26394586 ps
CPU time 0.58 seconds
Started May 09 01:03:45 PM PDT 24
Finished May 09 01:03:50 PM PDT 24
Peak memory 195296 kb
Host smart-9b2f6913-c43b-4dab-8a6e-bcf02bfa6d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289613146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2289613146
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2426060646
Short name T315
Test name
Test status
Simulation time 928313774 ps
CPU time 52.31 seconds
Started May 09 01:03:43 PM PDT 24
Finished May 09 01:04:39 PM PDT 24
Peak memory 241116 kb
Host smart-5c310953-c89a-41de-a452-b41f87123d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426060646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2426060646
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1446499283
Short name T369
Test name
Test status
Simulation time 2774246655 ps
CPU time 52.95 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:04:41 PM PDT 24
Peak memory 200764 kb
Host smart-b30f081e-7b3d-4538-9465-25ab25be8c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446499283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1446499283
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1543723937
Short name T330
Test name
Test status
Simulation time 3144467099 ps
CPU time 675.08 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:15:01 PM PDT 24
Peak memory 673964 kb
Host smart-fe6c1ad8-c3e9-4176-8393-cd1f45c148ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543723937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1543723937
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1529268516
Short name T23
Test name
Test status
Simulation time 6583683894 ps
CPU time 111.84 seconds
Started May 09 01:03:43 PM PDT 24
Finished May 09 01:05:39 PM PDT 24
Peak memory 200628 kb
Host smart-03536a0f-2504-4407-90d6-0648d94fdecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529268516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1529268516
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3324508324
Short name T240
Test name
Test status
Simulation time 297487684 ps
CPU time 3.6 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:03:51 PM PDT 24
Peak memory 200556 kb
Host smart-d0d35925-c574-4099-b55c-c58b64e62866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324508324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3324508324
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2122781004
Short name T93
Test name
Test status
Simulation time 62928857 ps
CPU time 1.24 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:03:46 PM PDT 24
Peak memory 200456 kb
Host smart-f0641ef7-8fa8-4da7-8301-b0e192805f92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122781004 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2122781004
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3208371028
Short name T143
Test name
Test status
Simulation time 98740599716 ps
CPU time 478.73 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:11:47 PM PDT 24
Peak memory 200656 kb
Host smart-5a3082c8-8190-4d66-a6f8-850f22c77852
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208371028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3208371028
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3488383668
Short name T300
Test name
Test status
Simulation time 58376016 ps
CPU time 0.61 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:03:49 PM PDT 24
Peak memory 196300 kb
Host smart-2f2097a9-da72-4eaa-b4d2-c7ef36b24108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488383668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3488383668
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1962120232
Short name T386
Test name
Test status
Simulation time 247087026 ps
CPU time 10.92 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:03:56 PM PDT 24
Peak memory 216872 kb
Host smart-7eeada5f-f792-4898-a6b7-def661c9cd25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1962120232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1962120232
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1979767199
Short name T339
Test name
Test status
Simulation time 1831432623 ps
CPU time 24.89 seconds
Started May 09 01:03:43 PM PDT 24
Finished May 09 01:04:11 PM PDT 24
Peak memory 200580 kb
Host smart-fcb7aa66-c74e-46c6-9724-b680975b2147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979767199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1979767199
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3997138601
Short name T168
Test name
Test status
Simulation time 2906878806 ps
CPU time 823.35 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:17:29 PM PDT 24
Peak memory 737184 kb
Host smart-577706a7-5adb-40a5-b5e7-4008cad21f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997138601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3997138601
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3507518133
Short name T381
Test name
Test status
Simulation time 1091193651 ps
CPU time 62.31 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:04:49 PM PDT 24
Peak memory 200612 kb
Host smart-b5f2f5f0-0a27-4d4c-8b86-4e34d28c47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507518133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3507518133
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2104590466
Short name T400
Test name
Test status
Simulation time 551797105 ps
CPU time 4.39 seconds
Started May 09 01:03:43 PM PDT 24
Finished May 09 01:03:52 PM PDT 24
Peak memory 200604 kb
Host smart-c49750c7-eb3a-447b-95ba-20e767f50dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104590466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2104590466
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3248112909
Short name T18
Test name
Test status
Simulation time 114144235 ps
CPU time 1.09 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:03:49 PM PDT 24
Peak memory 200456 kb
Host smart-72194a58-bd3e-4383-979e-c40d9e58df0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248112909 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3248112909
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2398275811
Short name T71
Test name
Test status
Simulation time 155449519013 ps
CPU time 511.46 seconds
Started May 09 01:03:42 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 200660 kb
Host smart-625ae3e5-40dd-4424-9023-c5caa40ce472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398275811 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2398275811
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3921238750
Short name T329
Test name
Test status
Simulation time 14624480 ps
CPU time 0.57 seconds
Started May 09 01:03:55 PM PDT 24
Finished May 09 01:03:59 PM PDT 24
Peak memory 195308 kb
Host smart-f566c326-a09d-482c-b997-5fe90e8c5ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921238750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3921238750
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3458833360
Short name T193
Test name
Test status
Simulation time 7442751386 ps
CPU time 41.52 seconds
Started May 09 01:03:50 PM PDT 24
Finished May 09 01:04:33 PM PDT 24
Peak memory 218000 kb
Host smart-9c54ff7a-12b9-4606-8d1d-add63f536854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458833360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3458833360
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1988255297
Short name T403
Test name
Test status
Simulation time 1328140893 ps
CPU time 34.97 seconds
Started May 09 01:03:46 PM PDT 24
Finished May 09 01:04:25 PM PDT 24
Peak memory 200588 kb
Host smart-a3bf8965-3dea-44e2-b428-2f914770faca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988255297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1988255297
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2110460421
Short name T430
Test name
Test status
Simulation time 21882801 ps
CPU time 0.89 seconds
Started May 09 01:03:44 PM PDT 24
Finished May 09 01:03:48 PM PDT 24
Peak memory 208680 kb
Host smart-b68ce1c2-74e5-416d-89b7-8ad99bc0f263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110460421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2110460421
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3786635824
Short name T374
Test name
Test status
Simulation time 9382067702 ps
CPU time 34.92 seconds
Started May 09 01:03:43 PM PDT 24
Finished May 09 01:04:22 PM PDT 24
Peak memory 200724 kb
Host smart-5b380b47-d39b-4d9b-8f6e-80321673e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786635824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3786635824
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2622474932
Short name T90
Test name
Test status
Simulation time 349477757 ps
CPU time 3.62 seconds
Started May 09 01:03:43 PM PDT 24
Finished May 09 01:03:51 PM PDT 24
Peak memory 200548 kb
Host smart-78ca4ca6-ba00-47b9-a439-bf47913a1ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622474932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2622474932
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3567940972
Short name T61
Test name
Test status
Simulation time 32203594 ps
CPU time 0.73 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:03:58 PM PDT 24
Peak memory 195964 kb
Host smart-918ffa3d-a722-4a91-9881-62763d089bb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567940972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3567940972
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1433261821
Short name T242
Test name
Test status
Simulation time 329011702 ps
CPU time 1.3 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:03:59 PM PDT 24
Peak memory 200400 kb
Host smart-bf454a1f-744b-40c7-87c6-cc6df009167a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433261821 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1433261821
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.541053068
Short name T39
Test name
Test status
Simulation time 74266393209 ps
CPU time 526.26 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:12:44 PM PDT 24
Peak memory 200580 kb
Host smart-8b357ef5-bafd-4ce3-9a5a-3e85f420eea4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541053068 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.541053068
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3514285800
Short name T31
Test name
Test status
Simulation time 298311351 ps
CPU time 12.1 seconds
Started May 09 01:03:55 PM PDT 24
Finished May 09 01:04:11 PM PDT 24
Peak memory 200628 kb
Host smart-9432ce01-2319-4725-9f93-4caef48efbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514285800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3514285800
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.754898466
Short name T254
Test name
Test status
Simulation time 20792271 ps
CPU time 0.64 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:03:57 PM PDT 24
Peak memory 195272 kb
Host smart-e2d57283-3e7f-4bc5-bb3a-83713a0a0bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754898466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.754898466
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2144982465
Short name T399
Test name
Test status
Simulation time 210740786 ps
CPU time 3.88 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:01 PM PDT 24
Peak memory 200548 kb
Host smart-bbe56dbd-10ba-4ee6-9dca-ea250fee3ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144982465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2144982465
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3161837275
Short name T228
Test name
Test status
Simulation time 534835434 ps
CPU time 14.37 seconds
Started May 09 01:03:54 PM PDT 24
Finished May 09 01:04:11 PM PDT 24
Peak memory 200572 kb
Host smart-b1ff9dfc-6e8a-4689-944a-8da1de291127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161837275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3161837275
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4036370535
Short name T348
Test name
Test status
Simulation time 1833454794 ps
CPU time 107.39 seconds
Started May 09 01:03:57 PM PDT 24
Finished May 09 01:05:47 PM PDT 24
Peak memory 550184 kb
Host smart-e22f8863-75a3-4691-92d6-f54cf1899968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036370535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4036370535
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.856374168
Short name T14
Test name
Test status
Simulation time 37703083940 ps
CPU time 131.69 seconds
Started May 09 01:03:55 PM PDT 24
Finished May 09 01:06:09 PM PDT 24
Peak memory 200740 kb
Host smart-e2cc75d6-e208-4ad5-9668-eb12ee18ec36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856374168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.856374168
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.566662666
Short name T55
Test name
Test status
Simulation time 6065293341 ps
CPU time 56.14 seconds
Started May 09 01:03:59 PM PDT 24
Finished May 09 01:04:58 PM PDT 24
Peak memory 200740 kb
Host smart-43afc2ed-bb34-4728-b8af-56c63c63565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566662666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.566662666
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.556472283
Short name T434
Test name
Test status
Simulation time 1637025092 ps
CPU time 6.16 seconds
Started May 09 01:03:53 PM PDT 24
Finished May 09 01:04:02 PM PDT 24
Peak memory 200564 kb
Host smart-fe80c1c0-0c0b-46da-b84a-d62ce583135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556472283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.556472283
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2532726152
Short name T138
Test name
Test status
Simulation time 32442530 ps
CPU time 1.2 seconds
Started May 09 01:03:57 PM PDT 24
Finished May 09 01:04:01 PM PDT 24
Peak memory 200412 kb
Host smart-ce296b18-42aa-4b02-aa03-9a9641f3efe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532726152 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2532726152
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3721630433
Short name T258
Test name
Test status
Simulation time 7437828130 ps
CPU time 432.33 seconds
Started May 09 01:03:59 PM PDT 24
Finished May 09 01:11:14 PM PDT 24
Peak memory 200656 kb
Host smart-acac361d-7a49-4dd0-ab4c-3ed85c8926b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721630433 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3721630433
Directory /workspace/9.hmac_test_sha_vectors/latest
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