Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5438224	1			T1	319		T2	479		T4	469
all_values[1]	5438224	1			T1	319		T2	479		T4	469
all_values[2]	5438224	1			T1	319		T2	479		T4	469

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43208

1

T1

24

T2

153

T4

2

auto[1]

16271464

1

T1

933

T2

1284

T4

1405

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14846836

1

T1

955

T2

1404

T4

1315

auto[1]

1467836

1

T1

2

T2

33

T4

92

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	16249	1			T2	151		T7	233		T17	47
all_values[0]	auto[0]	auto[1]	157	1			T2	2		T17	2		T47	2
all_values[0]	auto[1]	auto[0]	5407869	1			T1	317		T2	309		T4	432
all_values[0]	auto[1]	auto[1]	13949	1			T1	2		T2	17		T4	37
all_values[1]	auto[0]	auto[0]	17319	1			T4	2		T12	2		T17	49
all_values[1]	auto[0]	auto[1]	73	1			T60	2		T61	2		T68	3
all_values[1]	auto[1]	auto[0]	5420745	1			T1	319		T2	479		T4	467
all_values[1]	auto[1]	auto[1]	87	1			T31	2		T106	2		T107	2
all_values[2]	auto[0]	auto[0]	3688	1			T1	24		T5	278		T16	1
all_values[2]	auto[0]	auto[1]	5722	1			T16	304		T22	2		T88	2
all_values[2]	auto[1]	auto[0]	3980966	1			T1	295		T2	465		T4	414
all_values[2]	auto[1]	auto[1]	1447848	1			T2	14		T4	55		T7	7271