Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2741217

1

T1

316

T2

18

T4

134

auto[1]

822399

1

T2

10

T4

22

T7

8262

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

830415

1

T1

316

T2

14

T4

20

auto[1]

2733201

1

T2

14

T4

136

T7

3306

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2252799

1

T1

316

T2

16

T4

17

auto[1]

1310817

1

T2

12

T4

139

T7

6705

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	2978387	1			T1	312		T2	13		T4	63
fifo_depth[1]	111720	1			T1	2		T4	16		T7	199
fifo_depth[2]	86837	1			T1	1		T4	13		T7	207
fifo_depth[3]	66744	1			T4	6		T7	235		T5	19
fifo_depth[4]	53124	1			T4	12		T7	232		T5	24
fifo_depth[5]	44805	1			T1	1		T4	7		T7	222
fifo_depth[6]	41814	1			T4	8		T7	222		T5	18
fifo_depth[7]	34475	1			T4	4		T7	195		T5	19

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

585229

1

T1

4

T2

15

T4

93

auto[1]

2978387

1

T1

312

T2

13

T4

63

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3560850

1

T1

316

T2

27

T4

156

auto[1]

2766

1

T2

1

T6

2

T14

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

17120

1

T1

4

T2

3

T4

3

auto[0]

auto[0]

auto[0]

auto[1]

19883

1

T2

2

T4

2

T7

911

auto[0]

auto[0]

auto[1]

auto[0]

350867

1

T2

3

T4

3

T7

384

auto[0]

auto[0]

auto[1]

auto[1]

16099

1

T2

2

T4

2

T5

178

auto[0]

auto[1]

auto[0]

auto[0]

40964

1

T2

2

T4

2

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

41278

1

T2

1

T4

1

T7

492

auto[0]

auto[1]

auto[1]

auto[0]

50850

1

T2

1

T4

77

T24

5

auto[0]

auto[1]

auto[1]

auto[1]

48168

1

T2

1

T4

3

T7

259

auto[1]

auto[0]

auto[0]

auto[0]

69560

1

T1

312

T2

2

T4

2

auto[1]

auto[0]

auto[0]

auto[1]

69511

1

T4

3

T7

2490

T6

2

auto[1]

auto[0]

auto[1]

auto[0]

1640654

1

T2

3

T7

766

T10

23785

auto[1]

auto[0]

auto[1]

auto[1]

69105

1

T2

1

T4

2

T7

634

auto[1]

auto[1]

auto[0]

auto[0]

285073

1

T2

2

T4

4

T7

2046

auto[1]

auto[1]

auto[0]

auto[1]

287026

1

T2

2

T4

3

T7

2645

auto[1]

auto[1]

auto[1]

auto[0]

286129

1

T2

2

T4

43

T7

432

auto[1]

auto[1]

auto[1]

auto[1]

271329

1

T2

1

T4

6

T7

831

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

86569

1

T1

316

T2

5

T4

5

auto[0]

auto[0]

auto[0]

auto[1]

88792

1

T2

2

T4

5

T7

3401

auto[0]

auto[0]

auto[1]

auto[0]

1990979

1

T2

6

T4

3

T7

1150

auto[0]

auto[0]

auto[1]

auto[1]

84719

1

T2

3

T4

4

T7

634

auto[0]

auto[1]

auto[0]

auto[0]

325855

1

T2

3

T4

6

T7

2046

auto[0]

auto[1]

auto[0]

auto[1]

328175

1

T2

3

T4

4

T7

3137

auto[0]

auto[1]

auto[1]

auto[0]

336665

1

T2

3

T4

120

T7

432

auto[0]

auto[1]

auto[1]

auto[1]

319096

1

T2

2

T4

9

T7

1090

auto[1]

auto[0]

auto[0]

auto[0]

111

1

T29

1

T51

2

T30

5

auto[1]

auto[0]

auto[0]

auto[1]

602

1

T6

2

T14

2

T22

2

auto[1]

auto[0]

auto[1]

auto[0]

542

1

T125

1

T30

6

T126

1

auto[1]

auto[0]

auto[1]

auto[1]

485

1

T22

1

T46

1

T39

65

auto[1]

auto[1]

auto[0]

auto[0]

182

1

T2

1

T29

6

T127

1

auto[1]

auto[1]

auto[0]

auto[1]

129

1

T47

1

T128

1

T104

6

auto[1]

auto[1]

auto[1]

auto[0]

314

1

T46

1

T129

1

T51

1

auto[1]

auto[1]

auto[1]

auto[1]

401

1

T14

1

T46

1

T130

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	69560	1			T1	312		T2	2		T4	2
fifo_depth[0]	auto[0]	auto[0]	auto[1]	69511	1			T4	3		T7	2490		T6	2
fifo_depth[0]	auto[0]	auto[1]	auto[0]	1640654	1			T2	3		T7	766		T10	23785
fifo_depth[0]	auto[0]	auto[1]	auto[1]	69105	1			T2	1		T4	2		T7	634
fifo_depth[0]	auto[1]	auto[0]	auto[0]	285073	1			T2	2		T4	4		T7	2046
fifo_depth[0]	auto[1]	auto[0]	auto[1]	287026	1			T2	2		T4	3		T7	2645
fifo_depth[0]	auto[1]	auto[1]	auto[0]	286129	1			T2	2		T4	43		T7	432
fifo_depth[0]	auto[1]	auto[1]	auto[1]	271329	1			T2	1		T4	6		T7	831
fifo_depth[1]	auto[0]	auto[0]	auto[0]	1275	1			T1	2		T16	39		T131	2
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1283	1			T7	82		T16	10		T131	42
fifo_depth[1]	auto[0]	auto[1]	auto[0]	89939	1			T7	41		T10	2538		T15	1503
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1335	1			T5	21		T16	22		T132	22
fifo_depth[1]	auto[1]	auto[0]	auto[0]	4026	1			T16	47		T131	2		T29	26
fifo_depth[1]	auto[1]	auto[0]	auto[1]	4318	1			T7	50		T132	23		T133	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	4879	1			T4	16		T24	3		T12	139
fifo_depth[1]	auto[1]	auto[1]	auto[1]	4665	1			T7	26		T12	139		T16	10
fifo_depth[2]	auto[0]	auto[0]	auto[0]	1207	1			T1	1		T16	33		T29	6
fifo_depth[2]	auto[0]	auto[0]	auto[1]	1281	1			T7	103		T16	15		T131	35
fifo_depth[2]	auto[0]	auto[1]	auto[0]	65645	1			T7	27		T10	2433		T15	676
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1330	1			T5	23		T16	23		T132	29
fifo_depth[2]	auto[1]	auto[0]	auto[0]	3857	1			T16	41		T131	1		T29	1
fifo_depth[2]	auto[1]	auto[0]	auto[1]	4209	1			T7	56		T50	1		T132	16
fifo_depth[2]	auto[1]	auto[1]	auto[0]	4811	1			T4	13		T24	2		T12	148
fifo_depth[2]	auto[1]	auto[1]	auto[1]	4497	1			T7	21		T12	127		T16	13
fifo_depth[3]	auto[0]	auto[0]	auto[0]	875	1			T16	21		T131	1		T29	6
fifo_depth[3]	auto[0]	auto[0]	auto[1]	806	1			T7	103		T16	16		T131	13
fifo_depth[3]	auto[0]	auto[1]	auto[0]	47601	1			T7	55		T10	1903		T15	301
fifo_depth[3]	auto[0]	auto[1]	auto[1]	818	1			T5	19		T16	25		T132	20
fifo_depth[3]	auto[1]	auto[0]	auto[0]	3710	1			T16	38		T29	23		T132	105
fifo_depth[3]	auto[1]	auto[0]	auto[1]	4068	1			T7	55		T132	16		T105	104
fifo_depth[3]	auto[1]	auto[1]	auto[0]	4433	1			T4	6		T12	129		T16	92
fifo_depth[3]	auto[1]	auto[1]	auto[1]	4433	1			T7	22		T12	126		T16	13
fifo_depth[4]	auto[0]	auto[0]	auto[0]	1015	1			T16	26		T29	6		T134	1
fifo_depth[4]	auto[0]	auto[0]	auto[1]	959	1			T7	93		T16	12		T131	4
fifo_depth[4]	auto[0]	auto[1]	auto[0]	33714	1			T7	47		T10	1384		T15	105
fifo_depth[4]	auto[0]	auto[1]	auto[1]	819	1			T5	24		T16	21		T132	20
fifo_depth[4]	auto[1]	auto[0]	auto[0]	3678	1			T16	33		T29	1		T132	109
fifo_depth[4]	auto[1]	auto[0]	auto[1]	4028	1			T7	67		T50	1		T132	19
fifo_depth[4]	auto[1]	auto[1]	auto[0]	4507	1			T4	12		T12	135		T16	99
fifo_depth[4]	auto[1]	auto[1]	auto[1]	4404	1			T7	25		T12	151		T16	14
fifo_depth[5]	auto[0]	auto[0]	auto[0]	732	1			T1	1		T16	25		T29	5
fifo_depth[5]	auto[0]	auto[0]	auto[1]	731	1			T7	96		T16	21		T131	3
fifo_depth[5]	auto[0]	auto[1]	auto[0]	26867	1			T7	38		T10	1236		T15	36
fifo_depth[5]	auto[0]	auto[1]	auto[1]	556	1			T5	16		T16	11		T132	24
fifo_depth[5]	auto[1]	auto[0]	auto[0]	3535	1			T16	45		T29	22		T132	101
fifo_depth[5]	auto[1]	auto[0]	auto[1]	3828	1			T7	56		T132	19		T133	3
fifo_depth[5]	auto[1]	auto[1]	auto[0]	4292	1			T4	7		T12	123		T16	95
fifo_depth[5]	auto[1]	auto[1]	auto[1]	4264	1			T7	32		T12	127		T16	15
fifo_depth[6]	auto[0]	auto[0]	auto[0]	959	1			T16	30		T29	37		T135	16
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1216	1			T7	102		T16	9		T131	3
fifo_depth[6]	auto[0]	auto[1]	auto[0]	22858	1			T7	36		T10	1047		T15	6
fifo_depth[6]	auto[0]	auto[1]	auto[1]	907	1			T5	18		T16	15		T132	24
fifo_depth[6]	auto[1]	auto[0]	auto[0]	3556	1			T16	34		T29	2		T132	108
fifo_depth[6]	auto[1]	auto[0]	auto[1]	3899	1			T7	56		T132	23		T133	2
fifo_depth[6]	auto[1]	auto[1]	auto[0]	4358	1			T4	8		T12	135		T16	99
fifo_depth[6]	auto[1]	auto[1]	auto[1]	4061	1			T7	28		T12	134		T16	9
fifo_depth[7]	auto[0]	auto[0]	auto[0]	690	1			T16	34		T29	6		T135	12
fifo_depth[7]	auto[0]	auto[0]	auto[1]	644	1			T7	85		T16	16		T29	7
fifo_depth[7]	auto[0]	auto[1]	auto[0]	18217	1			T7	38		T10	936		T76	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	424	1			T5	19		T16	19		T132	23
fifo_depth[7]	auto[1]	auto[0]	auto[0]	3198	1			T16	34		T29	22		T132	100
fifo_depth[7]	auto[1]	auto[0]	auto[1]	3417	1			T7	51		T132	14		T105	63
fifo_depth[7]	auto[1]	auto[1]	auto[0]	4092	1			T4	4		T12	136		T16	96
fifo_depth[7]	auto[1]	auto[1]	auto[1]	3793	1			T7	21		T12	117		T16	12