Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5438224	1			T1	319		T2	479		T4	469
all_pins[1]	5438224	1			T1	319		T2	479		T4	469
all_pins[2]	5438224	1			T1	319		T2	479		T4	469

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	14852595	1			T1	955		T2	1403		T4	1313
values[0x1]	1462077	1			T1	2		T2	34		T4	94
transitions[0x0=>0x1]	1462013	1			T1	2		T2	34		T4	94
transitions[0x1=>0x0]	1462022	1			T1	2		T2	34		T4	94

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5424082	1			T1	317		T2	459		T4	430
all_pins[0]	values[0x1]	14142	1			T1	2		T2	20		T4	39
all_pins[0]	transitions[0x0=>0x1]	14113	1			T1	2		T2	20		T4	39
all_pins[0]	transitions[0x1=>0x0]	1447828	1			T2	14		T4	55		T7	7271
all_pins[1]	values[0x0]	5438137	1			T1	319		T2	479		T4	469
all_pins[1]	values[0x1]	87	1			T31	2		T106	2		T107	2
all_pins[1]	transitions[0x0=>0x1]	66	1			T31	1		T106	2		T107	2
all_pins[1]	transitions[0x1=>0x0]	14121	1			T1	2		T2	20		T4	39
all_pins[2]	values[0x0]	3990376	1			T1	319		T2	465		T4	414
all_pins[2]	values[0x1]	1447848	1			T2	14		T4	55		T7	7271
all_pins[2]	transitions[0x0=>0x1]	1447834	1			T2	14		T4	55		T7	7271
all_pins[2]	transitions[0x1=>0x0]	73	1			T31	2		T106	2		T107	2