Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 361 1 T31 7 T60 7 T61 10
all_values[1] 361 1 T31 7 T60 7 T61 10
all_values[2] 361 1 T31 7 T60 7 T61 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 561 1 T31 8 T60 5 T61 12
auto[1] 522 1 T31 13 T60 16 T61 18


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 376 1 T31 7 T60 2 T61 8
auto[1] 707 1 T31 14 T60 19 T61 22


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 605 1 T31 11 T60 9 T61 14
auto[1] 478 1 T31 10 T60 12 T61 16


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 72 1 T31 2 T61 1 T108 1
all_values[0] auto[0] auto[0] auto[1] 29 1 T60 2 T61 1 T108 1
all_values[0] auto[0] auto[1] auto[0] 55 1 T60 2 T61 2 T108 1
all_values[0] auto[0] auto[1] auto[1] 32 1 T31 2 T60 1 T108 1
all_values[0] auto[1] auto[0] auto[1] 92 1 T31 2 T61 2 T108 2
all_values[0] auto[1] auto[1] auto[1] 81 1 T31 1 T60 2 T61 4
all_values[1] auto[0] auto[0] auto[0] 60 1 T31 1 T108 2 T68 1
all_values[1] auto[0] auto[0] auto[1] 48 1 T31 1 T60 1 T61 1
all_values[1] auto[0] auto[1] auto[0] 58 1 T31 3 T61 5 T108 2
all_values[1] auto[0] auto[1] auto[1] 46 1 T60 2 T108 3 T68 1
all_values[1] auto[1] auto[0] auto[1] 81 1 T60 2 T61 1 T68 3
all_values[1] auto[1] auto[1] auto[1] 68 1 T31 2 T60 2 T61 3
all_values[2] auto[0] auto[0] auto[0] 70 1 T31 1 T108 2 T71 5
all_values[2] auto[0] auto[0] auto[1] 38 1 T61 3 T108 1 T68 1
all_values[2] auto[0] auto[1] auto[0] 61 1 T108 3 T109 2 T110 1
all_values[2] auto[0] auto[1] auto[1] 36 1 T31 1 T60 1 T61 1
all_values[2] auto[1] auto[0] auto[1] 71 1 T31 1 T61 3 T108 1
all_values[2] auto[1] auto[1] auto[1] 85 1 T31 4 T60 6 T61 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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