Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.66 95.66 92.61 100.00 63.16 91.21 99.49 71.47


Total test records in report: 602
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T516 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1775957640 May 19 01:28:34 PM PDT 24 May 19 01:28:36 PM PDT 24 40427306 ps
T517 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3931104086 May 19 01:28:06 PM PDT 24 May 19 01:28:13 PM PDT 24 32430412 ps
T518 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.347824217 May 19 01:28:35 PM PDT 24 May 19 01:28:40 PM PDT 24 148041823 ps
T519 /workspace/coverage/cover_reg_top/35.hmac_intr_test.829167916 May 19 01:28:36 PM PDT 24 May 19 01:28:39 PM PDT 24 30864997 ps
T520 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1770772105 May 19 01:28:36 PM PDT 24 May 19 01:28:39 PM PDT 24 44056050 ps
T521 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1451625183 May 19 01:28:12 PM PDT 24 May 19 01:28:18 PM PDT 24 88529503 ps
T522 /workspace/coverage/cover_reg_top/0.hmac_intr_test.167327229 May 19 01:27:58 PM PDT 24 May 19 01:28:02 PM PDT 24 35541882 ps
T523 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3144474286 May 19 01:28:35 PM PDT 24 May 19 01:28:40 PM PDT 24 171908169 ps
T524 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3744400209 May 19 01:28:12 PM PDT 24 May 19 01:28:18 PM PDT 24 65456712 ps
T121 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3125930239 May 19 01:28:08 PM PDT 24 May 19 01:28:18 PM PDT 24 301070523 ps
T525 /workspace/coverage/cover_reg_top/25.hmac_intr_test.105268334 May 19 01:28:36 PM PDT 24 May 19 01:28:39 PM PDT 24 14924032 ps
T526 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3872539367 May 19 01:28:34 PM PDT 24 May 19 01:28:39 PM PDT 24 437159947 ps
T527 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2944156980 May 19 01:28:13 PM PDT 24 May 19 01:28:20 PM PDT 24 161382579 ps
T528 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1537042194 May 19 01:28:38 PM PDT 24 May 19 01:28:41 PM PDT 24 11927260 ps
T529 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2039671704 May 19 01:28:37 PM PDT 24 May 19 01:28:41 PM PDT 24 15323895 ps
T530 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4223859320 May 19 01:28:03 PM PDT 24 May 19 01:28:10 PM PDT 24 27053466 ps
T531 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1199584650 May 19 01:28:22 PM PDT 24 May 19 01:28:25 PM PDT 24 386861174 ps
T532 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3178602175 May 19 01:28:25 PM PDT 24 May 19 01:28:29 PM PDT 24 42336018 ps
T533 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2469590251 May 19 01:28:06 PM PDT 24 May 19 01:28:15 PM PDT 24 81169483 ps
T534 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2435450487 May 19 01:28:35 PM PDT 24 May 19 01:28:39 PM PDT 24 41727599 ps
T535 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.41900216 May 19 01:28:11 PM PDT 24 May 19 01:28:17 PM PDT 24 40334762 ps
T536 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3758645884 May 19 01:28:22 PM PDT 24 May 19 01:28:26 PM PDT 24 60310623 ps
T537 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2371971741 May 19 01:27:58 PM PDT 24 May 19 01:28:04 PM PDT 24 101669019 ps
T538 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1043389605 May 19 01:28:22 PM PDT 24 May 19 01:28:27 PM PDT 24 673276507 ps
T539 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2760714259 May 19 01:28:06 PM PDT 24 May 19 01:28:13 PM PDT 24 43442305 ps
T540 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1796704590 May 19 01:28:25 PM PDT 24 May 19 01:28:30 PM PDT 24 135486968 ps
T120 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3290884243 May 19 01:28:23 PM PDT 24 May 19 01:28:26 PM PDT 24 99275698 ps
T541 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1973511875 May 19 01:28:14 PM PDT 24 May 19 01:28:18 PM PDT 24 13090696 ps
T542 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1087613434 May 19 01:28:34 PM PDT 24 May 19 01:28:40 PM PDT 24 885399193 ps
T113 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.162907432 May 19 01:28:34 PM PDT 24 May 19 01:28:40 PM PDT 24 85740173 ps
T543 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2046246852 May 19 01:28:41 PM PDT 24 May 19 01:28:45 PM PDT 24 18369116 ps
T544 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2877142645 May 19 01:28:02 PM PDT 24 May 19 01:28:08 PM PDT 24 42458867 ps
T545 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.244085217 May 19 01:28:13 PM PDT 24 May 19 01:28:19 PM PDT 24 41917046 ps
T114 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2483501766 May 19 01:28:22 PM PDT 24 May 19 01:28:26 PM PDT 24 338461591 ps
T546 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3667067734 May 19 01:28:33 PM PDT 24 May 19 01:28:35 PM PDT 24 49569520 ps
T547 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3949862941 May 19 01:28:26 PM PDT 24 May 19 01:37:32 PM PDT 24 136385551091 ps
T116 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1193841539 May 19 01:28:28 PM PDT 24 May 19 01:28:33 PM PDT 24 779223041 ps
T548 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1855805291 May 19 01:28:13 PM PDT 24 May 19 01:28:18 PM PDT 24 20234396 ps
T549 /workspace/coverage/cover_reg_top/13.hmac_intr_test.670572430 May 19 01:28:24 PM PDT 24 May 19 01:28:27 PM PDT 24 42194588 ps
T82 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2341380905 May 19 01:28:23 PM PDT 24 May 19 01:28:25 PM PDT 24 66067085 ps
T550 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1425087589 May 19 01:28:40 PM PDT 24 May 19 01:28:43 PM PDT 24 46198355 ps
T551 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3895083039 May 19 01:28:11 PM PDT 24 May 19 01:28:18 PM PDT 24 342754370 ps
T552 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1518750521 May 19 01:28:23 PM PDT 24 May 19 01:28:25 PM PDT 24 31949839 ps
T112 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4206225482 May 19 01:27:59 PM PDT 24 May 19 01:28:04 PM PDT 24 88159130 ps
T553 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3915233007 May 19 01:28:36 PM PDT 24 May 19 01:28:40 PM PDT 24 16154350 ps
T554 /workspace/coverage/cover_reg_top/12.hmac_intr_test.276793525 May 19 01:28:25 PM PDT 24 May 19 01:28:28 PM PDT 24 21640452 ps
T555 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3040062073 May 19 01:28:04 PM PDT 24 May 19 01:28:12 PM PDT 24 149935468 ps
T115 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3393023824 May 19 01:28:04 PM PDT 24 May 19 01:28:13 PM PDT 24 760881003 ps
T556 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2958745695 May 19 01:28:35 PM PDT 24 May 19 01:28:38 PM PDT 24 21896593 ps
T557 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.819922758 May 19 01:28:26 PM PDT 24 May 19 01:28:29 PM PDT 24 82691887 ps
T558 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1842883904 May 19 01:28:16 PM PDT 24 May 19 01:28:21 PM PDT 24 180845689 ps
T559 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1518247443 May 19 01:28:05 PM PDT 24 May 19 01:28:13 PM PDT 24 89891189 ps
T560 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3786642787 May 19 01:28:37 PM PDT 24 May 19 01:28:42 PM PDT 24 184201923 ps
T122 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1246494876 May 19 01:28:24 PM PDT 24 May 19 01:28:31 PM PDT 24 1359315891 ps
T561 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.585881749 May 19 01:28:28 PM PDT 24 May 19 01:28:31 PM PDT 24 218681860 ps
T117 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3087901307 May 19 01:28:08 PM PDT 24 May 19 01:28:18 PM PDT 24 144807676 ps
T562 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3595211563 May 19 01:28:34 PM PDT 24 May 19 01:28:39 PM PDT 24 86972904 ps
T563 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2996900278 May 19 01:28:06 PM PDT 24 May 19 01:28:14 PM PDT 24 42140468 ps
T83 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1689614731 May 19 01:28:15 PM PDT 24 May 19 01:28:19 PM PDT 24 27864536 ps
T564 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2781012935 May 19 01:28:08 PM PDT 24 May 19 01:28:16 PM PDT 24 399513837 ps
T565 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1804303096 May 19 01:28:10 PM PDT 24 May 19 01:28:16 PM PDT 24 29474632 ps
T566 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2753806848 May 19 01:28:06 PM PDT 24 May 19 01:28:16 PM PDT 24 177077016 ps
T85 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3581556895 May 19 01:28:05 PM PDT 24 May 19 01:28:17 PM PDT 24 3304120749 ps
T86 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3093395341 May 19 01:28:27 PM PDT 24 May 19 01:28:29 PM PDT 24 94236332 ps
T567 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3033780287 May 19 01:28:02 PM PDT 24 May 19 01:28:08 PM PDT 24 125185303 ps
T568 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.401206278 May 19 01:28:11 PM PDT 24 May 19 01:28:16 PM PDT 24 12958187 ps
T569 /workspace/coverage/cover_reg_top/5.hmac_intr_test.644374452 May 19 01:28:12 PM PDT 24 May 19 01:28:17 PM PDT 24 147939400 ps
T570 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1700898915 May 19 01:28:03 PM PDT 24 May 19 01:28:12 PM PDT 24 145652283 ps
T571 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3930980493 May 19 01:28:27 PM PDT 24 May 19 01:28:29 PM PDT 24 34739294 ps
T572 /workspace/coverage/cover_reg_top/26.hmac_intr_test.760657343 May 19 01:28:36 PM PDT 24 May 19 01:28:39 PM PDT 24 39362813 ps
T573 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.82102185 May 19 01:28:33 PM PDT 24 May 19 01:28:36 PM PDT 24 122137313 ps
T574 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2057393745 May 19 01:28:23 PM PDT 24 May 19 01:28:26 PM PDT 24 13135989 ps
T575 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.982335369 May 19 01:28:10 PM PDT 24 May 19 01:28:19 PM PDT 24 489724309 ps
T576 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3871527746 May 19 01:28:27 PM PDT 24 May 19 01:28:31 PM PDT 24 302516441 ps
T577 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1706637566 May 19 01:28:34 PM PDT 24 May 19 01:28:38 PM PDT 24 154848302 ps
T578 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3721033304 May 19 01:28:36 PM PDT 24 May 19 01:28:39 PM PDT 24 59002210 ps
T579 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2275734639 May 19 01:28:34 PM PDT 24 May 19 01:28:37 PM PDT 24 46741008 ps
T580 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1130804344 May 19 01:28:12 PM PDT 24 May 19 01:28:17 PM PDT 24 62028153 ps
T581 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3045261075 May 19 01:28:35 PM PDT 24 May 19 01:28:38 PM PDT 24 37133434 ps
T582 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.264680873 May 19 01:28:15 PM PDT 24 May 19 01:28:20 PM PDT 24 212764240 ps
T583 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1078593258 May 19 01:28:16 PM PDT 24 May 19 01:28:19 PM PDT 24 19203730 ps
T584 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3894022603 May 19 01:28:33 PM PDT 24 May 19 01:28:36 PM PDT 24 384966067 ps
T585 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1858095706 May 19 01:28:23 PM PDT 24 May 19 01:28:26 PM PDT 24 79377672 ps
T586 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.945075304 May 19 01:28:07 PM PDT 24 May 19 01:28:17 PM PDT 24 123647879 ps
T587 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1143754702 May 19 01:28:40 PM PDT 24 May 19 01:28:43 PM PDT 24 105434264 ps
T588 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3003085759 May 19 01:28:07 PM PDT 24 May 19 01:28:22 PM PDT 24 836487864 ps
T589 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.336752343 May 19 01:28:15 PM PDT 24 May 19 01:28:20 PM PDT 24 93606912 ps
T590 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3711720699 May 19 01:28:21 PM PDT 24 May 19 01:28:24 PM PDT 24 317186338 ps
T118 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3874420058 May 19 01:28:26 PM PDT 24 May 19 01:28:30 PM PDT 24 119701443 ps
T591 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4273987560 May 19 01:28:39 PM PDT 24 May 19 01:28:42 PM PDT 24 29407693 ps
T592 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2760493629 May 19 01:28:33 PM PDT 24 May 19 01:28:34 PM PDT 24 198125405 ps
T593 /workspace/coverage/cover_reg_top/23.hmac_intr_test.701157757 May 19 01:28:32 PM PDT 24 May 19 01:28:34 PM PDT 24 40059925 ps
T594 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2710173773 May 19 01:28:06 PM PDT 24 May 19 01:28:14 PM PDT 24 35375672 ps
T595 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3788225043 May 19 01:28:24 PM PDT 24 May 19 01:28:27 PM PDT 24 14426785 ps
T596 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2707828195 May 19 01:28:07 PM PDT 24 May 19 01:28:21 PM PDT 24 159127185 ps
T119 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2455238479 May 19 01:28:34 PM PDT 24 May 19 01:28:42 PM PDT 24 284258317 ps
T597 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1362684236 May 19 01:28:26 PM PDT 24 May 19 01:28:29 PM PDT 24 44636142 ps
T598 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.496062864 May 19 01:28:22 PM PDT 24 May 19 01:28:24 PM PDT 24 112954750 ps
T599 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.403191397 May 19 01:28:00 PM PDT 24 May 19 01:28:09 PM PDT 24 956715349 ps
T600 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.191721288 May 19 01:28:02 PM PDT 24 May 19 01:28:10 PM PDT 24 203726667 ps
T601 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2807441724 May 19 01:28:38 PM PDT 24 May 19 01:28:41 PM PDT 24 36404645 ps
T602 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.891609474 May 19 01:28:04 PM PDT 24 May 19 01:28:12 PM PDT 24 15589059 ps

Test location /workspace/coverage/default/6.hmac_back_pressure.1324712836
Short name T2
Test name
Test status
Simulation time 2698469784 ps
CPU time 27.21 seconds
Started May 19 01:15:13 PM PDT 24
Finished May 19 01:15:58 PM PDT 24
Peak memory 210024 kb
Host smart-ac67af2f-10e0-4415-98b6-de9312fb1b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324712836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1324712836
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1551922770
Short name T52
Test name
Test status
Simulation time 390705374703 ps
CPU time 757.18 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:41:11 PM PDT 24
Peak memory 216580 kb
Host smart-ca1aae2d-0a64-4760-b09a-e9b3fe08b6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551922770 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1551922770
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3775410519
Short name T16
Test name
Test status
Simulation time 1532066937 ps
CPU time 89.99 seconds
Started May 19 01:15:28 PM PDT 24
Finished May 19 01:17:10 PM PDT 24
Peak memory 200320 kb
Host smart-60da30fb-06ef-4dce-8afb-0315454d9751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775410519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3775410519
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2603802409
Short name T25
Test name
Test status
Simulation time 101542242 ps
CPU time 0.83 seconds
Started May 19 01:15:10 PM PDT 24
Finished May 19 01:15:28 PM PDT 24
Peak memory 218736 kb
Host smart-8e2cd673-4c1d-4dad-ab8e-13b3a9593a18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603802409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2603802409
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2576468290
Short name T60
Test name
Test status
Simulation time 96187667842 ps
CPU time 1421.09 seconds
Started May 19 01:15:44 PM PDT 24
Finished May 19 01:39:28 PM PDT 24
Peak memory 786044 kb
Host smart-d792da7a-7393-4281-8809-3550f73f28a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576468290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2576468290
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3290884243
Short name T120
Test name
Test status
Simulation time 99275698 ps
CPU time 1.95 seconds
Started May 19 01:28:23 PM PDT 24
Finished May 19 01:28:26 PM PDT 24
Peak memory 199960 kb
Host smart-5c5e5909-a7b4-4a0d-88e2-3eb84feba906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290884243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3290884243
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2941871891
Short name T7
Test name
Test status
Simulation time 1326552195 ps
CPU time 76.18 seconds
Started May 19 01:15:22 PM PDT 24
Finished May 19 01:16:53 PM PDT 24
Peak memory 200440 kb
Host smart-4732d7ec-35f2-41f3-8a27-bf6fac6074ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941871891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2941871891
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3712218087
Short name T73
Test name
Test status
Simulation time 164393687 ps
CPU time 1.03 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:13 PM PDT 24
Peak memory 199760 kb
Host smart-046bc884-4325-4d37-a0a9-46625a19c93b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712218087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3712218087
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/39.hmac_error.428933848
Short name T19
Test name
Test status
Simulation time 810308163 ps
CPU time 43.75 seconds
Started May 19 01:16:34 PM PDT 24
Finished May 19 01:17:19 PM PDT 24
Peak memory 200616 kb
Host smart-57f1e477-ace8-47de-b7a9-57a09a1a4a8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428933848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.428933848
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3066239007
Short name T39
Test name
Test status
Simulation time 864442020 ps
CPU time 22.35 seconds
Started May 19 01:16:34 PM PDT 24
Finished May 19 01:16:57 PM PDT 24
Peak memory 200628 kb
Host smart-b686ea72-c601-4578-9447-4319fb2e618f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066239007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3066239007
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2601209578
Short name T10
Test name
Test status
Simulation time 8735610556 ps
CPU time 446.71 seconds
Started May 19 01:15:05 PM PDT 24
Finished May 19 01:22:51 PM PDT 24
Peak memory 200640 kb
Host smart-889732fe-738c-4c12-bc40-a67bbab22e8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601209578 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2601209578
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3632252294
Short name T108
Test name
Test status
Simulation time 62872810 ps
CPU time 0.6 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194928 kb
Host smart-3079a37c-2eb1-4a79-9636-ef5b1576552c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632252294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3632252294
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.717772628
Short name T33
Test name
Test status
Simulation time 134662028 ps
CPU time 3.31 seconds
Started May 19 01:15:26 PM PDT 24
Finished May 19 01:15:43 PM PDT 24
Peak memory 200624 kb
Host smart-a6acdb5b-8d50-44f3-8a35-4c8800cbf0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717772628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.717772628
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.585718268
Short name T375
Test name
Test status
Simulation time 945753691 ps
CPU time 53.43 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:17:06 PM PDT 24
Peak memory 200580 kb
Host smart-1fa1f0d4-1307-4b7b-933e-1247783a6ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585718268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.585718268
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_alert_test.107091915
Short name T9
Test name
Test status
Simulation time 14114287 ps
CPU time 0.61 seconds
Started May 19 01:15:44 PM PDT 24
Finished May 19 01:15:48 PM PDT 24
Peak memory 196240 kb
Host smart-5b803482-1226-451e-a036-1d04a81f5ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107091915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.107091915
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3481748849
Short name T90
Test name
Test status
Simulation time 10439564650 ps
CPU time 473.71 seconds
Started May 19 01:15:43 PM PDT 24
Finished May 19 01:23:41 PM PDT 24
Peak memory 664980 kb
Host smart-2a4324a6-303b-4b31-a312-a55b8de7423e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481748849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3481748849
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3115890476
Short name T22
Test name
Test status
Simulation time 3893618501 ps
CPU time 38.76 seconds
Started May 19 01:15:26 PM PDT 24
Finished May 19 01:16:18 PM PDT 24
Peak memory 230460 kb
Host smart-9820bfa7-112f-4717-a264-cd59b91f514e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115890476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3115890476
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.191721288
Short name T600
Test name
Test status
Simulation time 203726667 ps
CPU time 1.69 seconds
Started May 19 01:28:02 PM PDT 24
Finished May 19 01:28:10 PM PDT 24
Peak memory 199960 kb
Host smart-dd5b5fb2-0008-4155-92cb-1bbca99114a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191721288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.191721288
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3874420058
Short name T118
Test name
Test status
Simulation time 119701443 ps
CPU time 1.89 seconds
Started May 19 01:28:26 PM PDT 24
Finished May 19 01:28:30 PM PDT 24
Peak memory 199836 kb
Host smart-11e82b29-a2c2-42a0-9f3b-8e96e7171aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874420058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3874420058
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2515990034
Short name T57
Test name
Test status
Simulation time 52858635 ps
CPU time 1.81 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:14 PM PDT 24
Peak memory 200260 kb
Host smart-437012a9-db94-4a5e-a388-24585d9f4c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515990034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2515990034
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2608909788
Short name T87
Test name
Test status
Simulation time 1184173536 ps
CPU time 61.83 seconds
Started May 19 01:16:00 PM PDT 24
Finished May 19 01:17:03 PM PDT 24
Peak memory 200572 kb
Host smart-8947ccf7-0b80-4763-89b9-647dd297c5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608909788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2608909788
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_stress_all.4232714617
Short name T17
Test name
Test status
Simulation time 335287325 ps
CPU time 14.41 seconds
Started May 19 01:16:33 PM PDT 24
Finished May 19 01:16:48 PM PDT 24
Peak memory 200664 kb
Host smart-189f1c89-30de-4d1a-a591-1c86a7277db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232714617 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4232714617
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3299619747
Short name T13
Test name
Test status
Simulation time 590625696 ps
CPU time 83.27 seconds
Started May 19 01:15:42 PM PDT 24
Finished May 19 01:17:09 PM PDT 24
Peak memory 469536 kb
Host smart-9f2efd7d-7eaa-44e1-b6b9-4b2637ee353a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3299619747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3299619747
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1327227892
Short name T23
Test name
Test status
Simulation time 591685784 ps
CPU time 8.05 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:15:47 PM PDT 24
Peak memory 200356 kb
Host smart-1080f8f5-906e-4ff5-925c-69ce11f89e4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327227892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1327227892
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3038106824
Short name T102
Test name
Test status
Simulation time 2227499312 ps
CPU time 58.04 seconds
Started May 19 01:15:35 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 200940 kb
Host smart-68434c49-b23e-404d-b643-5c537107a2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038106824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3038106824
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4261440634
Short name T91
Test name
Test status
Simulation time 2616150891 ps
CPU time 32.59 seconds
Started May 19 01:15:42 PM PDT 24
Finished May 19 01:16:19 PM PDT 24
Peak memory 223740 kb
Host smart-0eba0cce-e80e-489d-806f-6843b1f5aa30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261440634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4261440634
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.879893900
Short name T107
Test name
Test status
Simulation time 2496427230 ps
CPU time 33.36 seconds
Started May 19 01:15:51 PM PDT 24
Finished May 19 01:16:25 PM PDT 24
Peak memory 200748 kb
Host smart-f966be2a-22d7-4686-af4c-d1b46ec5d577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879893900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.879893900
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2919928289
Short name T65
Test name
Test status
Simulation time 385422603 ps
CPU time 1.95 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:37 PM PDT 24
Peak memory 200000 kb
Host smart-51d0b773-5c91-463c-9c01-a75ddd87c143
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919928289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2919928289
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.485841906
Short name T78
Test name
Test status
Simulation time 416036035 ps
CPU time 5.41 seconds
Started May 19 01:27:59 PM PDT 24
Finished May 19 01:28:08 PM PDT 24
Peak memory 199904 kb
Host smart-5a10abf7-45fb-4490-b2af-46374c9c4d05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485841906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.485841906
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.403191397
Short name T599
Test name
Test status
Simulation time 956715349 ps
CPU time 5.62 seconds
Started May 19 01:28:00 PM PDT 24
Finished May 19 01:28:09 PM PDT 24
Peak memory 199144 kb
Host smart-5a8fd4c9-9531-4736-924c-bbd28426401e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403191397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.403191397
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2969644073
Short name T504
Test name
Test status
Simulation time 69566845 ps
CPU time 0.75 seconds
Started May 19 01:27:59 PM PDT 24
Finished May 19 01:28:03 PM PDT 24
Peak memory 197576 kb
Host smart-c805e22d-c057-4db3-b092-59e8caa4b813
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969644073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2969644073
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2371971741
Short name T537
Test name
Test status
Simulation time 101669019 ps
CPU time 3.57 seconds
Started May 19 01:27:58 PM PDT 24
Finished May 19 01:28:04 PM PDT 24
Peak memory 215436 kb
Host smart-26b63f40-482f-4537-86a5-168561fc5f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371971741 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2371971741
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2877142645
Short name T544
Test name
Test status
Simulation time 42458867 ps
CPU time 0.86 seconds
Started May 19 01:28:02 PM PDT 24
Finished May 19 01:28:08 PM PDT 24
Peak memory 199432 kb
Host smart-dd8e4d17-7b5c-45ac-9ad5-84166168cbaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877142645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2877142645
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.167327229
Short name T522
Test name
Test status
Simulation time 35541882 ps
CPU time 0.61 seconds
Started May 19 01:27:58 PM PDT 24
Finished May 19 01:28:02 PM PDT 24
Peak memory 194972 kb
Host smart-c04e8a27-ba59-41da-904f-e00b27b7cb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167327229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.167327229
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1399714417
Short name T70
Test name
Test status
Simulation time 161269745 ps
CPU time 1.08 seconds
Started May 19 01:28:01 PM PDT 24
Finished May 19 01:28:08 PM PDT 24
Peak memory 199828 kb
Host smart-b924e8d9-433e-4355-be8e-c67703b933ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399714417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1399714417
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3597170727
Short name T62
Test name
Test status
Simulation time 37063294 ps
CPU time 1.78 seconds
Started May 19 01:28:05 PM PDT 24
Finished May 19 01:28:14 PM PDT 24
Peak memory 200052 kb
Host smart-36d1c9bc-041b-481a-8992-0688cf73ffb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597170727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3597170727
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4206225482
Short name T112
Test name
Test status
Simulation time 88159130 ps
CPU time 1.72 seconds
Started May 19 01:27:59 PM PDT 24
Finished May 19 01:28:04 PM PDT 24
Peak memory 200036 kb
Host smart-fcb379ca-098b-429d-b8f5-1b33a33783fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206225482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4206225482
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2707828195
Short name T596
Test name
Test status
Simulation time 159127185 ps
CPU time 8.14 seconds
Started May 19 01:28:07 PM PDT 24
Finished May 19 01:28:21 PM PDT 24
Peak memory 200012 kb
Host smart-a22b9836-ec1f-4687-b486-594f4f2e1e41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707828195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2707828195
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3003085759
Short name T588
Test name
Test status
Simulation time 836487864 ps
CPU time 9.87 seconds
Started May 19 01:28:07 PM PDT 24
Finished May 19 01:28:22 PM PDT 24
Peak memory 199892 kb
Host smart-9e7f4387-2c8a-489d-831f-b433631ccc93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003085759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3003085759
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3033780287
Short name T567
Test name
Test status
Simulation time 125185303 ps
CPU time 0.88 seconds
Started May 19 01:28:02 PM PDT 24
Finished May 19 01:28:08 PM PDT 24
Peak memory 199372 kb
Host smart-51c4aeba-fb8e-4294-81fa-4451fbfd9b0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033780287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3033780287
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.597149867
Short name T66
Test name
Test status
Simulation time 212552167 ps
CPU time 1.26 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:14 PM PDT 24
Peak memory 200016 kb
Host smart-78f5232a-fe05-4e64-a218-bca56135317c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597149867 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.597149867
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.891609474
Short name T602
Test name
Test status
Simulation time 15589059 ps
CPU time 0.81 seconds
Started May 19 01:28:04 PM PDT 24
Finished May 19 01:28:12 PM PDT 24
Peak memory 199496 kb
Host smart-a9273417-0735-4aab-9a29-e9f8471dbe97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891609474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.891609474
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4223859320
Short name T530
Test name
Test status
Simulation time 27053466 ps
CPU time 0.63 seconds
Started May 19 01:28:03 PM PDT 24
Finished May 19 01:28:10 PM PDT 24
Peak memory 194908 kb
Host smart-5de014d5-b848-4d79-a6fd-3845db04947a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223859320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4223859320
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3040062073
Short name T555
Test name
Test status
Simulation time 149935468 ps
CPU time 1.75 seconds
Started May 19 01:28:04 PM PDT 24
Finished May 19 01:28:12 PM PDT 24
Peak memory 200036 kb
Host smart-d681136f-c1d2-4878-bb2c-4366cb1c9427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040062073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3040062073
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4272225779
Short name T513
Test name
Test status
Simulation time 129446589 ps
CPU time 3.31 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:15 PM PDT 24
Peak memory 200316 kb
Host smart-01c16b98-013c-496d-b861-f7ba6ab72a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272225779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4272225779
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.987155430
Short name T506
Test name
Test status
Simulation time 238061452 ps
CPU time 1.67 seconds
Started May 19 01:28:25 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 199980 kb
Host smart-9d947ed1-fb49-4c12-ac5a-103c1a351421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987155430 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.987155430
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1662090905
Short name T491
Test name
Test status
Simulation time 74053397 ps
CPU time 0.85 seconds
Started May 19 01:28:24 PM PDT 24
Finished May 19 01:28:27 PM PDT 24
Peak memory 199812 kb
Host smart-6d74c272-f34b-4300-bb8b-e2b6ad046432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662090905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1662090905
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1518750521
Short name T552
Test name
Test status
Simulation time 31949839 ps
CPU time 0.64 seconds
Started May 19 01:28:23 PM PDT 24
Finished May 19 01:28:25 PM PDT 24
Peak memory 194904 kb
Host smart-aa319dfb-42ef-4a66-8281-bd0b6bae574c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518750521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1518750521
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1199584650
Short name T531
Test name
Test status
Simulation time 386861174 ps
CPU time 1.66 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:25 PM PDT 24
Peak memory 200032 kb
Host smart-315406d2-06d3-4cd9-bebd-a1fb310cdcb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199584650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1199584650
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1842883904
Short name T558
Test name
Test status
Simulation time 180845689 ps
CPU time 2.46 seconds
Started May 19 01:28:16 PM PDT 24
Finished May 19 01:28:21 PM PDT 24
Peak memory 199932 kb
Host smart-885c26ac-cc0e-4f6d-8753-3780ac0e1b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842883904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1842883904
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3711720699
Short name T590
Test name
Test status
Simulation time 317186338 ps
CPU time 1.95 seconds
Started May 19 01:28:21 PM PDT 24
Finished May 19 01:28:24 PM PDT 24
Peak memory 200032 kb
Host smart-37ae5137-6215-4f24-9473-6e5279825eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711720699 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3711720699
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.496062864
Short name T598
Test name
Test status
Simulation time 112954750 ps
CPU time 0.95 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:24 PM PDT 24
Peak memory 199240 kb
Host smart-9d498fdb-fc54-4189-a775-e769f6ff4585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496062864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.496062864
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1362684236
Short name T597
Test name
Test status
Simulation time 44636142 ps
CPU time 0.6 seconds
Started May 19 01:28:26 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 194668 kb
Host smart-648f3b06-3972-4203-a8fb-1456d11f2f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362684236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1362684236
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3758645884
Short name T536
Test name
Test status
Simulation time 60310623 ps
CPU time 2.17 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:26 PM PDT 24
Peak memory 199940 kb
Host smart-e94bcd44-7f2f-49e7-924b-538be67582b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758645884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3758645884
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1043389605
Short name T538
Test name
Test status
Simulation time 673276507 ps
CPU time 3.12 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:27 PM PDT 24
Peak memory 200136 kb
Host smart-cc91d541-739c-4b0f-aa38-d2bbf9c42490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043389605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1043389605
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1464225441
Short name T55
Test name
Test status
Simulation time 20933323 ps
CPU time 1.25 seconds
Started May 19 01:28:23 PM PDT 24
Finished May 19 01:28:27 PM PDT 24
Peak memory 200004 kb
Host smart-6229d9d9-4122-4596-9a92-df220fdc4593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464225441 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1464225441
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4223358571
Short name T489
Test name
Test status
Simulation time 28782205 ps
CPU time 0.94 seconds
Started May 19 01:28:28 PM PDT 24
Finished May 19 01:28:30 PM PDT 24
Peak memory 199792 kb
Host smart-eb5bafcf-f6c8-4403-8882-3d6473207635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223358571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4223358571
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.276793525
Short name T554
Test name
Test status
Simulation time 21640452 ps
CPU time 0.65 seconds
Started May 19 01:28:25 PM PDT 24
Finished May 19 01:28:28 PM PDT 24
Peak memory 194880 kb
Host smart-039a7dcd-da41-4fa5-baa7-faa4965d9ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276793525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.276793525
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1858095706
Short name T585
Test name
Test status
Simulation time 79377672 ps
CPU time 1.63 seconds
Started May 19 01:28:23 PM PDT 24
Finished May 19 01:28:26 PM PDT 24
Peak memory 200008 kb
Host smart-51a9d384-508f-416c-ace9-5ec54d5b3b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858095706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1858095706
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1678209807
Short name T53
Test name
Test status
Simulation time 69755668 ps
CPU time 3.76 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:27 PM PDT 24
Peak memory 199920 kb
Host smart-3255cafc-16f9-430c-b4e8-9a8746ac75ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678209807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1678209807
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2483501766
Short name T114
Test name
Test status
Simulation time 338461591 ps
CPU time 1.86 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:26 PM PDT 24
Peak memory 200028 kb
Host smart-92ecc72d-8207-424f-a316-b50acd599e00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483501766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2483501766
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1796704590
Short name T540
Test name
Test status
Simulation time 135486968 ps
CPU time 2.45 seconds
Started May 19 01:28:25 PM PDT 24
Finished May 19 01:28:30 PM PDT 24
Peak memory 207560 kb
Host smart-52345e8e-d5cc-46f3-8d25-c75c48c555c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796704590 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1796704590
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.332205088
Short name T79
Test name
Test status
Simulation time 29995040 ps
CPU time 0.72 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:24 PM PDT 24
Peak memory 197968 kb
Host smart-76497dc7-8663-4fae-bce4-572dd953d24a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332205088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.332205088
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.670572430
Short name T549
Test name
Test status
Simulation time 42194588 ps
CPU time 0.62 seconds
Started May 19 01:28:24 PM PDT 24
Finished May 19 01:28:27 PM PDT 24
Peak memory 194844 kb
Host smart-093b4f65-a152-43d2-a4a8-81dc740f135d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670572430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.670572430
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3185512783
Short name T508
Test name
Test status
Simulation time 92531932 ps
CPU time 1.21 seconds
Started May 19 01:28:25 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 199596 kb
Host smart-84c9abc0-930f-46bd-b494-4c62cee448f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185512783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3185512783
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2675627537
Short name T502
Test name
Test status
Simulation time 1040749995 ps
CPU time 3.09 seconds
Started May 19 01:28:24 PM PDT 24
Finished May 19 01:28:30 PM PDT 24
Peak memory 200108 kb
Host smart-7f18d26c-7910-409a-83ca-a021bbb006c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675627537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2675627537
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1246494876
Short name T122
Test name
Test status
Simulation time 1359315891 ps
CPU time 4.32 seconds
Started May 19 01:28:24 PM PDT 24
Finished May 19 01:28:31 PM PDT 24
Peak memory 199940 kb
Host smart-1f190e79-1bc6-4483-9108-07ab43869ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246494876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1246494876
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1769916260
Short name T28
Test name
Test status
Simulation time 75446160 ps
CPU time 1.84 seconds
Started May 19 01:28:28 PM PDT 24
Finished May 19 01:28:31 PM PDT 24
Peak memory 200088 kb
Host smart-4f032584-368c-4135-8d72-8c5cc817d5c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769916260 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1769916260
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3780563402
Short name T505
Test name
Test status
Simulation time 158173434 ps
CPU time 0.85 seconds
Started May 19 01:28:27 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 199220 kb
Host smart-5b1bbb89-19f0-4fe2-b49c-3761a0601c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780563402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3780563402
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3930980493
Short name T571
Test name
Test status
Simulation time 34739294 ps
CPU time 0.59 seconds
Started May 19 01:28:27 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 194888 kb
Host smart-72e64a50-a755-41f2-a29e-ee6dbf49b51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930980493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3930980493
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.819922758
Short name T557
Test name
Test status
Simulation time 82691887 ps
CPU time 1.1 seconds
Started May 19 01:28:26 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 200000 kb
Host smart-fb0371fb-88ed-44e9-b613-86e0a3b94cc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819922758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.819922758
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3584665659
Short name T510
Test name
Test status
Simulation time 101433325 ps
CPU time 1.44 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:37 PM PDT 24
Peak memory 200056 kb
Host smart-acd87154-94d2-4898-88ef-0a41d38a8448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584665659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3584665659
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3449206554
Short name T58
Test name
Test status
Simulation time 152594011 ps
CPU time 3.29 seconds
Started May 19 01:28:27 PM PDT 24
Finished May 19 01:28:32 PM PDT 24
Peak memory 200324 kb
Host smart-6a797f25-7f54-4b2b-a768-f7641153a0e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449206554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3449206554
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3949862941
Short name T547
Test name
Test status
Simulation time 136385551091 ps
CPU time 543.93 seconds
Started May 19 01:28:26 PM PDT 24
Finished May 19 01:37:32 PM PDT 24
Peak memory 216416 kb
Host smart-b8d70726-614e-4c81-9812-3693fdbab30a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949862941 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3949862941
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3093395341
Short name T86
Test name
Test status
Simulation time 94236332 ps
CPU time 0.72 seconds
Started May 19 01:28:27 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 197952 kb
Host smart-3d015a57-989e-4562-8c69-c2086b4d9775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093395341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3093395341
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3788225043
Short name T595
Test name
Test status
Simulation time 14426785 ps
CPU time 0.6 seconds
Started May 19 01:28:24 PM PDT 24
Finished May 19 01:28:27 PM PDT 24
Peak memory 194816 kb
Host smart-5c4741d5-b28e-4a97-b595-8da1d083b7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788225043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3788225043
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3871527746
Short name T576
Test name
Test status
Simulation time 302516441 ps
CPU time 2.62 seconds
Started May 19 01:28:27 PM PDT 24
Finished May 19 01:28:31 PM PDT 24
Peak memory 199972 kb
Host smart-4f13df48-f39d-41c2-9ae4-ab5615f47fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871527746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3871527746
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3178602175
Short name T532
Test name
Test status
Simulation time 42336018 ps
CPU time 1.24 seconds
Started May 19 01:28:25 PM PDT 24
Finished May 19 01:28:29 PM PDT 24
Peak memory 199344 kb
Host smart-06f113d7-a3c8-45f7-89c7-942a9bd86a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178602175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3178602175
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2455238479
Short name T119
Test name
Test status
Simulation time 284258317 ps
CPU time 4.68 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:42 PM PDT 24
Peak memory 199916 kb
Host smart-761f6bdc-d2fa-45fd-8b1b-0ba323def249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455238479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2455238479
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.347824217
Short name T518
Test name
Test status
Simulation time 148041823 ps
CPU time 1.2 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 199836 kb
Host smart-813c1b79-486f-4d96-8923-860fc1d6dcb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347824217 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.347824217
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.990107980
Short name T64
Test name
Test status
Simulation time 18650453 ps
CPU time 0.92 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:34 PM PDT 24
Peak memory 199796 kb
Host smart-cf6774e5-03ee-4acb-a9d4-f2f2654205f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990107980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.990107980
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2882744854
Short name T503
Test name
Test status
Simulation time 38156658 ps
CPU time 0.62 seconds
Started May 19 01:28:24 PM PDT 24
Finished May 19 01:28:26 PM PDT 24
Peak memory 194956 kb
Host smart-46b00460-58a4-472e-a711-f41ba81ad59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882744854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2882744854
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3144474286
Short name T523
Test name
Test status
Simulation time 171908169 ps
CPU time 2.21 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 199864 kb
Host smart-83f28170-91b8-4f86-a56b-a306fcf75932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144474286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3144474286
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.585881749
Short name T561
Test name
Test status
Simulation time 218681860 ps
CPU time 1.54 seconds
Started May 19 01:28:28 PM PDT 24
Finished May 19 01:28:31 PM PDT 24
Peak memory 200048 kb
Host smart-a541be99-3636-45b4-b19a-6d81ae91e202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585881749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.585881749
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1193841539
Short name T116
Test name
Test status
Simulation time 779223041 ps
CPU time 3.41 seconds
Started May 19 01:28:28 PM PDT 24
Finished May 19 01:28:33 PM PDT 24
Peak memory 199976 kb
Host smart-cced8340-0bb2-467b-ac65-71948e902099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193841539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1193841539
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2848234411
Short name T495
Test name
Test status
Simulation time 136867947 ps
CPU time 1.82 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 200004 kb
Host smart-3f60aa76-0cda-494a-afb8-fe6436a82e08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848234411 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2848234411
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4119730384
Short name T80
Test name
Test status
Simulation time 79802980 ps
CPU time 0.82 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:36 PM PDT 24
Peak memory 199144 kb
Host smart-a7e0da8a-96b9-4e05-997b-08494e8a6687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119730384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.4119730384
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1775957640
Short name T516
Test name
Test status
Simulation time 40427306 ps
CPU time 0.6 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:36 PM PDT 24
Peak memory 194944 kb
Host smart-ed766d28-4fac-459d-8610-fca1c7320923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775957640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1775957640
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.82102185
Short name T573
Test name
Test status
Simulation time 122137313 ps
CPU time 1.61 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:36 PM PDT 24
Peak memory 199760 kb
Host smart-0b518505-ff29-481c-9d33-9a4d933b42cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82102185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_
outstanding.82102185
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.416827482
Short name T54
Test name
Test status
Simulation time 53773899 ps
CPU time 1.37 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:36 PM PDT 24
Peak memory 200008 kb
Host smart-e1a92cf7-ae70-4302-97d1-7f5eeaa8e7c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416827482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.416827482
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1706637566
Short name T577
Test name
Test status
Simulation time 154848302 ps
CPU time 1.92 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:38 PM PDT 24
Peak memory 199976 kb
Host smart-a2d0e0dc-bb3f-4597-af82-9be71f468864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706637566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1706637566
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4054216179
Short name T507
Test name
Test status
Simulation time 59597802 ps
CPU time 0.73 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:38 PM PDT 24
Peak memory 197796 kb
Host smart-760e8e5f-dd42-44ac-ad16-7a2cef42eb12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054216179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4054216179
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2275734639
Short name T579
Test name
Test status
Simulation time 46741008 ps
CPU time 0.58 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:37 PM PDT 24
Peak memory 194856 kb
Host smart-09feb2a0-67b8-4a7a-a704-f8f6f533842c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275734639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2275734639
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3894022603
Short name T584
Test name
Test status
Simulation time 384966067 ps
CPU time 1.82 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:36 PM PDT 24
Peak memory 200040 kb
Host smart-f9f33199-4ff4-4e2b-aa62-71d81aea7171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894022603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3894022603
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1087613434
Short name T542
Test name
Test status
Simulation time 885399193 ps
CPU time 4.06 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 200288 kb
Host smart-13166f7f-095b-49b5-a97c-c8fafc6087b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087613434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1087613434
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.162907432
Short name T113
Test name
Test status
Simulation time 85740173 ps
CPU time 2.81 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 199996 kb
Host smart-1c5c69f2-50ea-45f3-bf57-15a1ce0b67a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162907432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.162907432
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3872539367
Short name T526
Test name
Test status
Simulation time 437159947 ps
CPU time 2.47 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 200012 kb
Host smart-ad2591d1-c818-4f83-84c8-3a33fad11f0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872539367 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3872539367
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3667067734
Short name T546
Test name
Test status
Simulation time 49569520 ps
CPU time 0.71 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:35 PM PDT 24
Peak memory 197624 kb
Host smart-e2ca6880-1c31-40ab-bc90-d975ac435e86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667067734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3667067734
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2313195500
Short name T71
Test name
Test status
Simulation time 28734036 ps
CPU time 0.59 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:36 PM PDT 24
Peak memory 195104 kb
Host smart-7c79e128-85b0-4f18-99cf-a3da912294c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313195500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2313195500
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3786642787
Short name T560
Test name
Test status
Simulation time 184201923 ps
CPU time 2.32 seconds
Started May 19 01:28:37 PM PDT 24
Finished May 19 01:28:42 PM PDT 24
Peak memory 199804 kb
Host smart-b5c0ae61-e894-40af-ace0-12cbd770a649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786642787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3786642787
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3595211563
Short name T562
Test name
Test status
Simulation time 86972904 ps
CPU time 1.91 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 200080 kb
Host smart-1a4a89d4-67c6-49bd-b4f0-80ac713071c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595211563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3595211563
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3499875087
Short name T63
Test name
Test status
Simulation time 158597252 ps
CPU time 7.74 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:20 PM PDT 24
Peak memory 200052 kb
Host smart-c5ba3e69-eaa2-49ea-b81f-358f3548f82d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499875087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3499875087
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3008925726
Short name T84
Test name
Test status
Simulation time 468558762 ps
CPU time 5.67 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 199288 kb
Host smart-f848017c-819a-43fe-a9d3-0c36e8562cd2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008925726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3008925726
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2996900278
Short name T563
Test name
Test status
Simulation time 42140468 ps
CPU time 1.38 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:14 PM PDT 24
Peak memory 200084 kb
Host smart-03c47bc1-4f95-4e81-8a0d-16fb6455e418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996900278 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2996900278
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.220000209
Short name T72
Test name
Test status
Simulation time 20384563 ps
CPU time 0.73 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:13 PM PDT 24
Peak memory 197644 kb
Host smart-bebf7208-dc9b-4c8d-b7d4-4b0b4328d0ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220000209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.220000209
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.990103065
Short name T61
Test name
Test status
Simulation time 59098051 ps
CPU time 0.64 seconds
Started May 19 01:28:05 PM PDT 24
Finished May 19 01:28:12 PM PDT 24
Peak memory 194876 kb
Host smart-7e8dd276-f84d-4927-a043-f8bfc962e656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990103065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.990103065
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2710173773
Short name T594
Test name
Test status
Simulation time 35375672 ps
CPU time 1.56 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:14 PM PDT 24
Peak memory 199952 kb
Host smart-d34e0db4-5690-4bfa-8c80-d0103d73b9a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710173773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2710173773
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3799455029
Short name T27
Test name
Test status
Simulation time 407410953 ps
CPU time 2.61 seconds
Started May 19 01:28:04 PM PDT 24
Finished May 19 01:28:13 PM PDT 24
Peak memory 200036 kb
Host smart-a6aca290-395c-4e24-8cc6-a71fb1655f64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799455029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3799455029
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3393023824
Short name T115
Test name
Test status
Simulation time 760881003 ps
CPU time 3.1 seconds
Started May 19 01:28:04 PM PDT 24
Finished May 19 01:28:13 PM PDT 24
Peak memory 199932 kb
Host smart-b1700faf-77ac-4d68-bd1b-6cdb02139ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393023824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3393023824
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2760493629
Short name T592
Test name
Test status
Simulation time 198125405 ps
CPU time 0.61 seconds
Started May 19 01:28:33 PM PDT 24
Finished May 19 01:28:34 PM PDT 24
Peak memory 194860 kb
Host smart-4e15fcad-b3ed-4068-9a82-65d49de1d571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760493629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2760493629
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2958745695
Short name T556
Test name
Test status
Simulation time 21896593 ps
CPU time 0.64 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:38 PM PDT 24
Peak memory 194868 kb
Host smart-1b8425d6-4b06-4860-b401-9bb8fa5a9f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958745695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2958745695
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.656457022
Short name T74
Test name
Test status
Simulation time 54197620 ps
CPU time 0.62 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:38 PM PDT 24
Peak memory 194884 kb
Host smart-c05974b2-997a-4e9f-a1b3-5434185ae99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656457022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.656457022
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.701157757
Short name T593
Test name
Test status
Simulation time 40059925 ps
CPU time 0.58 seconds
Started May 19 01:28:32 PM PDT 24
Finished May 19 01:28:34 PM PDT 24
Peak memory 194812 kb
Host smart-00fd1853-c0fa-4ea5-89f3-0adcf393ae96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701157757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.701157757
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.277091543
Short name T110
Test name
Test status
Simulation time 14200030 ps
CPU time 0.61 seconds
Started May 19 01:28:34 PM PDT 24
Finished May 19 01:28:38 PM PDT 24
Peak memory 194960 kb
Host smart-a6969165-1676-4bbf-9c10-1902674310ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277091543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.277091543
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.105268334
Short name T525
Test name
Test status
Simulation time 14924032 ps
CPU time 0.6 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194828 kb
Host smart-48e466f5-a783-4c67-ada2-610084a771eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105268334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.105268334
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.760657343
Short name T572
Test name
Test status
Simulation time 39362813 ps
CPU time 0.57 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194856 kb
Host smart-b82eacbe-fe87-4512-86b3-0d52e6f75c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760657343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.760657343
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.497830440
Short name T68
Test name
Test status
Simulation time 16870162 ps
CPU time 0.62 seconds
Started May 19 01:28:37 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 194944 kb
Host smart-98e1ec4b-2982-4da7-8e4c-a3d041ab5a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497830440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.497830440
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1419669660
Short name T493
Test name
Test status
Simulation time 21217324 ps
CPU time 0.58 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194816 kb
Host smart-dca4f823-68b2-492c-9410-0f42d88dd7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419669660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1419669660
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1143754702
Short name T587
Test name
Test status
Simulation time 105434264 ps
CPU time 0.58 seconds
Started May 19 01:28:40 PM PDT 24
Finished May 19 01:28:43 PM PDT 24
Peak memory 194852 kb
Host smart-2a917aca-6ba0-456b-92dc-d0b4440e0ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143754702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1143754702
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3353501344
Short name T487
Test name
Test status
Simulation time 426204992 ps
CPU time 5.52 seconds
Started May 19 01:28:05 PM PDT 24
Finished May 19 01:28:17 PM PDT 24
Peak memory 200232 kb
Host smart-bad640bb-c79d-44fb-bea1-8a9ef558c42f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353501344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3353501344
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3581556895
Short name T85
Test name
Test status
Simulation time 3304120749 ps
CPU time 5.9 seconds
Started May 19 01:28:05 PM PDT 24
Finished May 19 01:28:17 PM PDT 24
Peak memory 199584 kb
Host smart-73caf4ab-f2f3-4b63-a663-3609d1f34a38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581556895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3581556895
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2760714259
Short name T539
Test name
Test status
Simulation time 43442305 ps
CPU time 0.91 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:13 PM PDT 24
Peak memory 199772 kb
Host smart-3075ee73-f35a-4fac-8780-6a915794777d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760714259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2760714259
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2469590251
Short name T533
Test name
Test status
Simulation time 81169483 ps
CPU time 2.92 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:15 PM PDT 24
Peak memory 200000 kb
Host smart-512f6ab2-84b9-48cc-abad-9e7daa08d3bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469590251 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2469590251
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1518247443
Short name T559
Test name
Test status
Simulation time 89891189 ps
CPU time 0.82 seconds
Started May 19 01:28:05 PM PDT 24
Finished May 19 01:28:13 PM PDT 24
Peak memory 199108 kb
Host smart-4bdeade8-706c-4a59-a292-411ed8a9dea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518247443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1518247443
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3931104086
Short name T517
Test name
Test status
Simulation time 32430412 ps
CPU time 0.71 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:13 PM PDT 24
Peak memory 194952 kb
Host smart-60c2a251-3d19-4cf2-a8f0-b52ba4d120ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931104086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3931104086
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1700898915
Short name T570
Test name
Test status
Simulation time 145652283 ps
CPU time 2.39 seconds
Started May 19 01:28:03 PM PDT 24
Finished May 19 01:28:12 PM PDT 24
Peak memory 199996 kb
Host smart-6f99a0e4-149d-409e-8ca4-04a8a8074d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700898915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1700898915
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2753806848
Short name T566
Test name
Test status
Simulation time 177077016 ps
CPU time 3.74 seconds
Started May 19 01:28:06 PM PDT 24
Finished May 19 01:28:16 PM PDT 24
Peak memory 199996 kb
Host smart-ccfd2925-fdfe-4bc5-814e-266862c904aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753806848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2753806848
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3915233007
Short name T553
Test name
Test status
Simulation time 16154350 ps
CPU time 0.65 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 194968 kb
Host smart-5c757faa-3da1-4ef7-85f6-e57eb61dc760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915233007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3915233007
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.4231101785
Short name T109
Test name
Test status
Simulation time 14356050 ps
CPU time 0.6 seconds
Started May 19 01:28:40 PM PDT 24
Finished May 19 01:28:43 PM PDT 24
Peak memory 194788 kb
Host smart-96128dba-76ed-48ad-9de6-c7ea1be2fceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231101785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4231101785
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.348405840
Short name T492
Test name
Test status
Simulation time 50796056 ps
CPU time 0.62 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 194876 kb
Host smart-ad3f202d-74c3-42a9-bf82-ae99286fcd5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348405840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.348405840
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3721033304
Short name T578
Test name
Test status
Simulation time 59002210 ps
CPU time 0.63 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194876 kb
Host smart-6502479b-ca8c-47cb-8e25-fdea8645ef00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721033304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3721033304
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.829167916
Short name T519
Test name
Test status
Simulation time 30864997 ps
CPU time 0.67 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194872 kb
Host smart-7567fac6-0869-47b4-a112-f19096c7d4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829167916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.829167916
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1537042194
Short name T528
Test name
Test status
Simulation time 11927260 ps
CPU time 0.59 seconds
Started May 19 01:28:38 PM PDT 24
Finished May 19 01:28:41 PM PDT 24
Peak memory 194880 kb
Host smart-97e08455-08bf-42d3-bdbf-fa90d09ee618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537042194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1537042194
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1770772105
Short name T520
Test name
Test status
Simulation time 44056050 ps
CPU time 0.63 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194944 kb
Host smart-c3af140d-ad21-4e2f-b21d-2e6530afd331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770772105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1770772105
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1541165254
Short name T514
Test name
Test status
Simulation time 12664270 ps
CPU time 0.6 seconds
Started May 19 01:28:37 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 194888 kb
Host smart-d74aa791-8435-4ec2-8706-7954df6e6e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541165254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1541165254
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4273987560
Short name T591
Test name
Test status
Simulation time 29407693 ps
CPU time 0.6 seconds
Started May 19 01:28:39 PM PDT 24
Finished May 19 01:28:42 PM PDT 24
Peak memory 194856 kb
Host smart-78c90296-fae0-407c-8e58-d72d94cab6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273987560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4273987560
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.982335369
Short name T575
Test name
Test status
Simulation time 489724309 ps
CPU time 3.23 seconds
Started May 19 01:28:10 PM PDT 24
Finished May 19 01:28:19 PM PDT 24
Peak memory 199976 kb
Host smart-40650e26-c443-4045-bec5-c1e632dbcb43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982335369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.982335369
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.474609938
Short name T488
Test name
Test status
Simulation time 779851005 ps
CPU time 5.88 seconds
Started May 19 01:28:10 PM PDT 24
Finished May 19 01:28:21 PM PDT 24
Peak memory 199912 kb
Host smart-dea829af-8e90-490e-8eac-55a0bde1b6e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474609938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.474609938
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.446530043
Short name T81
Test name
Test status
Simulation time 64227831 ps
CPU time 0.85 seconds
Started May 19 01:28:09 PM PDT 24
Finished May 19 01:28:16 PM PDT 24
Peak memory 199304 kb
Host smart-b3387ef0-6656-49ca-9bb6-16741401e063
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446530043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.446530043
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3895083039
Short name T551
Test name
Test status
Simulation time 342754370 ps
CPU time 2.41 seconds
Started May 19 01:28:11 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 199928 kb
Host smart-a984d06b-e177-4e45-889b-7056a9fae55a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895083039 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3895083039
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1130804344
Short name T580
Test name
Test status
Simulation time 62028153 ps
CPU time 0.73 seconds
Started May 19 01:28:12 PM PDT 24
Finished May 19 01:28:17 PM PDT 24
Peak memory 197912 kb
Host smart-23adf9c5-a91a-42c3-8174-4ee9cafa103c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130804344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1130804344
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1804303096
Short name T565
Test name
Test status
Simulation time 29474632 ps
CPU time 0.61 seconds
Started May 19 01:28:10 PM PDT 24
Finished May 19 01:28:16 PM PDT 24
Peak memory 194912 kb
Host smart-9e47d3ca-8383-4791-805d-38127cc8f7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804303096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1804303096
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.41900216
Short name T535
Test name
Test status
Simulation time 40334762 ps
CPU time 1.16 seconds
Started May 19 01:28:11 PM PDT 24
Finished May 19 01:28:17 PM PDT 24
Peak memory 199680 kb
Host smart-09a2dcf4-8fba-4ebf-98d7-9d6e69f21ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41900216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_o
utstanding.41900216
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3744400209
Short name T524
Test name
Test status
Simulation time 65456712 ps
CPU time 1.8 seconds
Started May 19 01:28:12 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 200060 kb
Host smart-6eeeebc0-bfcd-4c8a-838f-099ec4227b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744400209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3744400209
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3125930239
Short name T121
Test name
Test status
Simulation time 301070523 ps
CPU time 4.37 seconds
Started May 19 01:28:08 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 200036 kb
Host smart-9fbf0512-81b8-47f8-9af9-4d83349e6bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125930239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3125930239
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2435450487
Short name T534
Test name
Test status
Simulation time 41727599 ps
CPU time 0.58 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194912 kb
Host smart-fce6d0f5-772f-433e-adb9-e8ed3e38e82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435450487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2435450487
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3081423745
Short name T494
Test name
Test status
Simulation time 44276095 ps
CPU time 0.61 seconds
Started May 19 01:28:37 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 194852 kb
Host smart-b24e8342-dbf8-4b94-8eaa-f945db32e89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081423745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3081423745
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3045261075
Short name T581
Test name
Test status
Simulation time 37133434 ps
CPU time 0.6 seconds
Started May 19 01:28:35 PM PDT 24
Finished May 19 01:28:38 PM PDT 24
Peak memory 194788 kb
Host smart-7d3ec24c-e03f-42a7-a97a-91ad204c54a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045261075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3045261075
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2039671704
Short name T529
Test name
Test status
Simulation time 15323895 ps
CPU time 0.65 seconds
Started May 19 01:28:37 PM PDT 24
Finished May 19 01:28:41 PM PDT 24
Peak memory 194952 kb
Host smart-b8c12ce6-c833-4c09-9520-a862f528900f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039671704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2039671704
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2030818177
Short name T496
Test name
Test status
Simulation time 13550163 ps
CPU time 0.6 seconds
Started May 19 01:28:37 PM PDT 24
Finished May 19 01:28:40 PM PDT 24
Peak memory 194876 kb
Host smart-0b33430a-2c78-474d-8c38-f5c8a6a88917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030818177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2030818177
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1425087589
Short name T550
Test name
Test status
Simulation time 46198355 ps
CPU time 0.62 seconds
Started May 19 01:28:40 PM PDT 24
Finished May 19 01:28:43 PM PDT 24
Peak memory 194796 kb
Host smart-d163813e-a255-4446-a367-c5b3ce42207e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425087589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1425087589
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2807441724
Short name T601
Test name
Test status
Simulation time 36404645 ps
CPU time 0.61 seconds
Started May 19 01:28:38 PM PDT 24
Finished May 19 01:28:41 PM PDT 24
Peak memory 194968 kb
Host smart-ecd1f72c-cc1c-430f-b51a-d3d772eaafc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807441724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2807441724
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.315696860
Short name T511
Test name
Test status
Simulation time 57365119 ps
CPU time 0.63 seconds
Started May 19 01:28:36 PM PDT 24
Finished May 19 01:28:39 PM PDT 24
Peak memory 194884 kb
Host smart-e12cc8c0-c242-401e-86d5-53800471c9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315696860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.315696860
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3504501263
Short name T509
Test name
Test status
Simulation time 38252094 ps
CPU time 0.57 seconds
Started May 19 01:28:45 PM PDT 24
Finished May 19 01:28:49 PM PDT 24
Peak memory 194872 kb
Host smart-cddab913-1d54-4fcd-9bba-ee2bb966e556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504501263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3504501263
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2046246852
Short name T543
Test name
Test status
Simulation time 18369116 ps
CPU time 0.56 seconds
Started May 19 01:28:41 PM PDT 24
Finished May 19 01:28:45 PM PDT 24
Peak memory 194912 kb
Host smart-d5ca6fd9-cd97-4bbe-92fd-20a47ed38bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046246852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2046246852
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4086940712
Short name T500
Test name
Test status
Simulation time 344662613 ps
CPU time 3.54 seconds
Started May 19 01:28:12 PM PDT 24
Finished May 19 01:28:20 PM PDT 24
Peak memory 216392 kb
Host smart-6e9eff97-911a-48ec-aea8-bf1a54ca1e26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086940712 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4086940712
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.401206278
Short name T568
Test name
Test status
Simulation time 12958187 ps
CPU time 0.71 seconds
Started May 19 01:28:11 PM PDT 24
Finished May 19 01:28:16 PM PDT 24
Peak memory 197364 kb
Host smart-d9fba49d-0ba8-4585-9f07-de295d476c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401206278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.401206278
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.644374452
Short name T569
Test name
Test status
Simulation time 147939400 ps
CPU time 0.62 seconds
Started May 19 01:28:12 PM PDT 24
Finished May 19 01:28:17 PM PDT 24
Peak memory 194908 kb
Host smart-1da13b00-3b94-4ce6-8fe7-5203ba18143c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644374452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.644374452
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.930061844
Short name T499
Test name
Test status
Simulation time 49495495 ps
CPU time 1.14 seconds
Started May 19 01:28:08 PM PDT 24
Finished May 19 01:28:15 PM PDT 24
Peak memory 199928 kb
Host smart-83c3304b-1f0f-45f9-b865-ce694ec52cfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930061844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.930061844
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.945075304
Short name T586
Test name
Test status
Simulation time 123647879 ps
CPU time 3.43 seconds
Started May 19 01:28:07 PM PDT 24
Finished May 19 01:28:17 PM PDT 24
Peak memory 200024 kb
Host smart-7934f4a7-26bf-4b79-b4a2-296120327ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945075304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.945075304
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2781012935
Short name T564
Test name
Test status
Simulation time 399513837 ps
CPU time 1.88 seconds
Started May 19 01:28:08 PM PDT 24
Finished May 19 01:28:16 PM PDT 24
Peak memory 200012 kb
Host smart-201af36f-a7f4-46bb-b3f3-d223d984324f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781012935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2781012935
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3273210123
Short name T515
Test name
Test status
Simulation time 279704476 ps
CPU time 1.9 seconds
Started May 19 01:28:14 PM PDT 24
Finished May 19 01:28:19 PM PDT 24
Peak memory 200064 kb
Host smart-95d7bffd-17f0-4fd3-806b-fde4e5606559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273210123 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3273210123
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1689614731
Short name T83
Test name
Test status
Simulation time 27864536 ps
CPU time 0.91 seconds
Started May 19 01:28:15 PM PDT 24
Finished May 19 01:28:19 PM PDT 24
Peak memory 199800 kb
Host smart-8a760da3-52c1-45df-9f1f-bcb24f34b2c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689614731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1689614731
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3094474589
Short name T497
Test name
Test status
Simulation time 27161197 ps
CPU time 0.63 seconds
Started May 19 01:28:10 PM PDT 24
Finished May 19 01:28:16 PM PDT 24
Peak memory 194904 kb
Host smart-4178d2cd-0a1a-4bc7-b7b1-6df05b9d9055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094474589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3094474589
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2917388119
Short name T498
Test name
Test status
Simulation time 2310491233 ps
CPU time 2.37 seconds
Started May 19 01:28:16 PM PDT 24
Finished May 19 01:28:21 PM PDT 24
Peak memory 200088 kb
Host smart-234e8607-9012-4a5e-88fa-ac7f6b478609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917388119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2917388119
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1419653016
Short name T501
Test name
Test status
Simulation time 1583648314 ps
CPU time 4.78 seconds
Started May 19 01:28:11 PM PDT 24
Finished May 19 01:28:20 PM PDT 24
Peak memory 200088 kb
Host smart-f1333b45-c001-419f-9a83-0f495d4229f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419653016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1419653016
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3087901307
Short name T117
Test name
Test status
Simulation time 144807676 ps
CPU time 4.08 seconds
Started May 19 01:28:08 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 200000 kb
Host smart-20198680-81d4-421c-9d75-a1f7cec40799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087901307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3087901307
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3931912821
Short name T26
Test name
Test status
Simulation time 65774684 ps
CPU time 2.1 seconds
Started May 19 01:28:14 PM PDT 24
Finished May 19 01:28:19 PM PDT 24
Peak memory 200020 kb
Host smart-a6ca43ed-6870-4a68-9af6-95a73b701169
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931912821 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3931912821
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1078593258
Short name T583
Test name
Test status
Simulation time 19203730 ps
CPU time 0.73 seconds
Started May 19 01:28:16 PM PDT 24
Finished May 19 01:28:19 PM PDT 24
Peak memory 197668 kb
Host smart-2d198c5a-e35c-4946-bf37-65e9b0c1a6d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078593258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1078593258
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1855805291
Short name T548
Test name
Test status
Simulation time 20234396 ps
CPU time 0.68 seconds
Started May 19 01:28:13 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 195196 kb
Host smart-57bed374-571d-4fef-83eb-1f75111c9354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855805291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1855805291
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.150903893
Short name T490
Test name
Test status
Simulation time 85373174 ps
CPU time 1.08 seconds
Started May 19 01:28:13 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 198540 kb
Host smart-172d1b9e-4240-495d-9d72-7cf0b108ace8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150903893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.150903893
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2944156980
Short name T527
Test name
Test status
Simulation time 161382579 ps
CPU time 3.49 seconds
Started May 19 01:28:13 PM PDT 24
Finished May 19 01:28:20 PM PDT 24
Peak memory 200040 kb
Host smart-82c44cc4-4282-443d-aa54-ba5f0622444c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944156980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2944156980
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2411344724
Short name T111
Test name
Test status
Simulation time 92511213 ps
CPU time 2.81 seconds
Started May 19 01:28:16 PM PDT 24
Finished May 19 01:28:21 PM PDT 24
Peak memory 200028 kb
Host smart-19577969-ecef-45e6-a5ae-522c083a751c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411344724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2411344724
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.336752343
Short name T589
Test name
Test status
Simulation time 93606912 ps
CPU time 2.43 seconds
Started May 19 01:28:15 PM PDT 24
Finished May 19 01:28:20 PM PDT 24
Peak memory 200024 kb
Host smart-020b7a4c-afe9-4c22-892d-e2d9e3a3937e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336752343 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.336752343
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2600908583
Short name T69
Test name
Test status
Simulation time 49784842 ps
CPU time 0.85 seconds
Started May 19 01:28:21 PM PDT 24
Finished May 19 01:28:23 PM PDT 24
Peak memory 199424 kb
Host smart-252dafd4-18b7-4222-844c-d6bbeb76c0bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600908583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2600908583
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1973511875
Short name T541
Test name
Test status
Simulation time 13090696 ps
CPU time 0.62 seconds
Started May 19 01:28:14 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 194784 kb
Host smart-60747969-ff1b-452c-a43a-44f1639f401c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973511875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1973511875
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1529172771
Short name T67
Test name
Test status
Simulation time 324112048 ps
CPU time 1.18 seconds
Started May 19 01:28:22 PM PDT 24
Finished May 19 01:28:25 PM PDT 24
Peak memory 199828 kb
Host smart-1579e787-4145-4abc-bab7-a6a3c0bc1ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529172771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1529172771
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3394378245
Short name T59
Test name
Test status
Simulation time 110051979 ps
CPU time 3.01 seconds
Started May 19 01:28:21 PM PDT 24
Finished May 19 01:28:25 PM PDT 24
Peak memory 199984 kb
Host smart-2dba46a5-5f88-4d45-b85d-3bd679302d19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394378245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3394378245
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1451625183
Short name T521
Test name
Test status
Simulation time 88529503 ps
CPU time 1.84 seconds
Started May 19 01:28:12 PM PDT 24
Finished May 19 01:28:18 PM PDT 24
Peak memory 200012 kb
Host smart-83df3efc-f5b4-4033-8ba8-aca4eb50dfe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451625183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1451625183
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.244085217
Short name T545
Test name
Test status
Simulation time 41917046 ps
CPU time 2.62 seconds
Started May 19 01:28:13 PM PDT 24
Finished May 19 01:28:19 PM PDT 24
Peak memory 200204 kb
Host smart-f8941435-504e-4e6b-b02f-456ddb17499b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244085217 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.244085217
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2341380905
Short name T82
Test name
Test status
Simulation time 66067085 ps
CPU time 0.69 seconds
Started May 19 01:28:23 PM PDT 24
Finished May 19 01:28:25 PM PDT 24
Peak memory 197980 kb
Host smart-788fca36-1990-4693-83a8-ba9779895bd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341380905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2341380905
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2057393745
Short name T574
Test name
Test status
Simulation time 13135989 ps
CPU time 0.65 seconds
Started May 19 01:28:23 PM PDT 24
Finished May 19 01:28:26 PM PDT 24
Peak memory 194964 kb
Host smart-07a6c5cb-341f-4454-9071-6170abd934be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057393745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2057393745
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.264680873
Short name T582
Test name
Test status
Simulation time 212764240 ps
CPU time 2.36 seconds
Started May 19 01:28:15 PM PDT 24
Finished May 19 01:28:20 PM PDT 24
Peak memory 200056 kb
Host smart-64868763-33af-4938-8868-4a6e539e333d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264680873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.264680873
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1750858927
Short name T512
Test name
Test status
Simulation time 63874368 ps
CPU time 3.37 seconds
Started May 19 01:28:13 PM PDT 24
Finished May 19 01:28:20 PM PDT 24
Peak memory 199984 kb
Host smart-814b47f5-0cf9-44aa-a2a1-e1bbc5f5a2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750858927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1750858927
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.868535125
Short name T56
Test name
Test status
Simulation time 355621546 ps
CPU time 3.12 seconds
Started May 19 01:28:15 PM PDT 24
Finished May 19 01:28:21 PM PDT 24
Peak memory 200012 kb
Host smart-7baca128-b3f6-4bad-8cc6-87ab6f443adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868535125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.868535125
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.594221919
Short name T348
Test name
Test status
Simulation time 17078111 ps
CPU time 0.64 seconds
Started May 19 01:14:59 PM PDT 24
Finished May 19 01:15:19 PM PDT 24
Peak memory 196232 kb
Host smart-19872794-d1de-4569-bb5e-744b2889cb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594221919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.594221919
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1240106382
Short name T14
Test name
Test status
Simulation time 15319884381 ps
CPU time 57.53 seconds
Started May 19 01:14:58 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 229376 kb
Host smart-0807638e-8492-41ca-bbc5-2e53a0b75cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240106382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1240106382
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3270921274
Short name T352
Test name
Test status
Simulation time 38349334 ps
CPU time 1.99 seconds
Started May 19 01:14:57 PM PDT 24
Finished May 19 01:15:18 PM PDT 24
Peak memory 200356 kb
Host smart-b8927e83-a731-4ec6-90a5-edb932e909d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270921274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3270921274
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.4059418894
Short name T211
Test name
Test status
Simulation time 1914724594 ps
CPU time 92.07 seconds
Started May 19 01:14:58 PM PDT 24
Finished May 19 01:16:49 PM PDT 24
Peak memory 411148 kb
Host smart-e50b1a31-f133-4065-94e2-4e62fb0d44a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059418894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4059418894
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1586879919
Short name T382
Test name
Test status
Simulation time 20534507133 ps
CPU time 84.79 seconds
Started May 19 01:14:57 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 200956 kb
Host smart-4db83137-c9d7-4f96-b035-d7c66a24ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586879919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1586879919
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2185251295
Short name T36
Test name
Test status
Simulation time 201726382 ps
CPU time 0.88 seconds
Started May 19 01:14:58 PM PDT 24
Finished May 19 01:15:19 PM PDT 24
Peak memory 218856 kb
Host smart-19ff1a61-541c-4489-8be8-df697341a624
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185251295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2185251295
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3991640687
Short name T408
Test name
Test status
Simulation time 1816070547 ps
CPU time 6.83 seconds
Started May 19 01:15:00 PM PDT 24
Finished May 19 01:15:26 PM PDT 24
Peak memory 200592 kb
Host smart-7ee933a8-dd5c-4466-b715-ba9357bfe7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991640687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3991640687
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3959584561
Short name T293
Test name
Test status
Simulation time 130018492 ps
CPU time 1.01 seconds
Started May 19 01:15:01 PM PDT 24
Finished May 19 01:15:20 PM PDT 24
Peak memory 199240 kb
Host smart-1b2cc490-3944-48bd-9708-bad2510d07c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959584561 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3959584561
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1121362414
Short name T151
Test name
Test status
Simulation time 28193425818 ps
CPU time 406.86 seconds
Started May 19 01:14:58 PM PDT 24
Finished May 19 01:22:04 PM PDT 24
Peak memory 200584 kb
Host smart-b503463e-b14b-4958-84fa-fe1ad8633235
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121362414 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1121362414
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3144692303
Short name T376
Test name
Test status
Simulation time 95834498 ps
CPU time 0.56 seconds
Started May 19 01:15:02 PM PDT 24
Finished May 19 01:15:22 PM PDT 24
Peak memory 195984 kb
Host smart-194721a0-2f20-44ac-a68d-11ee86e4bb61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144692303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3144692303
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1282321541
Short name T445
Test name
Test status
Simulation time 621344332 ps
CPU time 16.46 seconds
Started May 19 01:14:56 PM PDT 24
Finished May 19 01:15:31 PM PDT 24
Peak memory 216400 kb
Host smart-022f89f0-1a25-4539-b06a-d782602f3cc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282321541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1282321541
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1411745851
Short name T101
Test name
Test status
Simulation time 2643850306 ps
CPU time 48.42 seconds
Started May 19 01:14:58 PM PDT 24
Finished May 19 01:16:06 PM PDT 24
Peak memory 200712 kb
Host smart-718af41b-ebfc-4a0b-8377-54701a322e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411745851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1411745851
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.614246827
Short name T181
Test name
Test status
Simulation time 3580620939 ps
CPU time 377.08 seconds
Started May 19 01:15:00 PM PDT 24
Finished May 19 01:21:36 PM PDT 24
Peak memory 640448 kb
Host smart-54ee5794-56f6-47ec-b4c0-3645a7dbb15b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614246827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.614246827
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1496265153
Short name T300
Test name
Test status
Simulation time 1054152580 ps
CPU time 7.01 seconds
Started May 19 01:15:00 PM PDT 24
Finished May 19 01:15:26 PM PDT 24
Peak memory 200596 kb
Host smart-be92a5f7-5e3c-4102-a360-fe59bd86df4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496265153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1496265153
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3410076387
Short name T37
Test name
Test status
Simulation time 62724611 ps
CPU time 0.84 seconds
Started May 19 01:14:59 PM PDT 24
Finished May 19 01:15:19 PM PDT 24
Peak memory 218948 kb
Host smart-515f21da-05d0-4bc6-870b-00ce3296051f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410076387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3410076387
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3121234910
Short name T305
Test name
Test status
Simulation time 72234145 ps
CPU time 2.47 seconds
Started May 19 01:15:00 PM PDT 24
Finished May 19 01:15:22 PM PDT 24
Peak memory 200924 kb
Host smart-6d44a7fc-354f-4e03-94f8-d81b5777bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121234910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3121234910
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1650232304
Short name T145
Test name
Test status
Simulation time 66881358 ps
CPU time 1.24 seconds
Started May 19 01:15:04 PM PDT 24
Finished May 19 01:15:24 PM PDT 24
Peak memory 200316 kb
Host smart-55e6a52b-9517-404e-8c59-b14af85bf188
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650232304 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1650232304
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2583827360
Short name T240
Test name
Test status
Simulation time 29958436341 ps
CPU time 533.19 seconds
Started May 19 01:14:59 PM PDT 24
Finished May 19 01:24:11 PM PDT 24
Peak memory 200628 kb
Host smart-b140f761-7262-425b-bae4-bdbc485c137b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583827360 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2583827360
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2567847705
Short name T364
Test name
Test status
Simulation time 21650209 ps
CPU time 0.58 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:15:35 PM PDT 24
Peak memory 197108 kb
Host smart-84328be5-3830-4082-a543-68d6e836e3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567847705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2567847705
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.269764040
Short name T182
Test name
Test status
Simulation time 365575239 ps
CPU time 13.22 seconds
Started May 19 01:15:21 PM PDT 24
Finished May 19 01:15:49 PM PDT 24
Peak memory 225752 kb
Host smart-0cd79a15-eeeb-47ab-afca-c003cffd9bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=269764040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.269764040
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2183522501
Short name T231
Test name
Test status
Simulation time 331679522 ps
CPU time 2.14 seconds
Started May 19 01:15:22 PM PDT 24
Finished May 19 01:15:38 PM PDT 24
Peak memory 200484 kb
Host smart-244a09f5-12bc-48a1-8b8f-83d9d1108ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183522501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2183522501
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1931869180
Short name T410
Test name
Test status
Simulation time 9319994159 ps
CPU time 377.13 seconds
Started May 19 01:15:19 PM PDT 24
Finished May 19 01:21:52 PM PDT 24
Peak memory 695208 kb
Host smart-180d0bb3-47b3-4069-a7ef-6dd807837f9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931869180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1931869180
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2243870668
Short name T291
Test name
Test status
Simulation time 808083379 ps
CPU time 44.51 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:16:18 PM PDT 24
Peak memory 200512 kb
Host smart-d933eaaf-c996-45a3-9846-1679ef2c2aef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243870668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2243870668
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2729331656
Short name T135
Test name
Test status
Simulation time 6941392196 ps
CPU time 59.49 seconds
Started May 19 01:15:19 PM PDT 24
Finished May 19 01:16:35 PM PDT 24
Peak memory 200704 kb
Host smart-8a57a637-36a6-4b5f-84dd-01daaa4fbd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729331656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2729331656
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1650103194
Short name T202
Test name
Test status
Simulation time 192950725 ps
CPU time 1.14 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:15:40 PM PDT 24
Peak memory 200488 kb
Host smart-69686d4b-2436-45fa-86c4-b64b12990183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650103194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1650103194
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2142028294
Short name T313
Test name
Test status
Simulation time 147127368 ps
CPU time 1.05 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:15:35 PM PDT 24
Peak memory 200184 kb
Host smart-89fc31e1-c541-45d6-b179-b70d9ace6e0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142028294 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2142028294
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.4239622435
Short name T455
Test name
Test status
Simulation time 16845759274 ps
CPU time 455.85 seconds
Started May 19 01:15:19 PM PDT 24
Finished May 19 01:23:10 PM PDT 24
Peak memory 200660 kb
Host smart-342ec069-8794-451b-b200-c1be29123375
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239622435 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.4239622435
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_alert_test.924060245
Short name T486
Test name
Test status
Simulation time 12536540 ps
CPU time 0.58 seconds
Started May 19 01:15:22 PM PDT 24
Finished May 19 01:15:37 PM PDT 24
Peak memory 196228 kb
Host smart-e1476256-c49d-4384-939e-d04d99f3f894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924060245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.924060245
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.594418974
Short name T358
Test name
Test status
Simulation time 1567099772 ps
CPU time 39.55 seconds
Started May 19 01:15:22 PM PDT 24
Finished May 19 01:16:16 PM PDT 24
Peak memory 208720 kb
Host smart-6cdc3cf1-9c07-457f-ac7a-2515002bf6d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594418974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.594418974
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.229684471
Short name T100
Test name
Test status
Simulation time 3759181932 ps
CPU time 52.3 seconds
Started May 19 01:15:20 PM PDT 24
Finished May 19 01:16:28 PM PDT 24
Peak memory 200752 kb
Host smart-3f8d9109-c78e-4a7d-a590-80f1ce00a883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229684471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.229684471
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.781596144
Short name T387
Test name
Test status
Simulation time 14763138414 ps
CPU time 892.58 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:30:31 PM PDT 24
Peak memory 711312 kb
Host smart-c31e7118-fbbf-4b65-a6fd-b6eb7f961116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781596144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.781596144
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3427934311
Short name T189
Test name
Test status
Simulation time 6592564447 ps
CPU time 90.39 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:17:04 PM PDT 24
Peak memory 200676 kb
Host smart-68bf7230-d10b-4f72-9af2-66c866f80c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427934311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3427934311
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3722939509
Short name T370
Test name
Test status
Simulation time 164222783 ps
CPU time 5.17 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:15:39 PM PDT 24
Peak memory 200556 kb
Host smart-0659a9c7-9533-4b16-be15-760ef3f95c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722939509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3722939509
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2524917718
Short name T44
Test name
Test status
Simulation time 230132000 ps
CPU time 1.03 seconds
Started May 19 01:15:24 PM PDT 24
Finished May 19 01:15:38 PM PDT 24
Peak memory 200388 kb
Host smart-41bc23cd-2066-4241-bdcc-160a6a700f82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524917718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2524917718
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3298271098
Short name T185
Test name
Test status
Simulation time 409053013208 ps
CPU time 524.47 seconds
Started May 19 01:15:22 PM PDT 24
Finished May 19 01:24:21 PM PDT 24
Peak memory 200644 kb
Host smart-f7f68024-6e6e-434e-b892-7845d297a089
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298271098 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3298271098
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1178428714
Short name T480
Test name
Test status
Simulation time 145393767 ps
CPU time 0.57 seconds
Started May 19 01:15:24 PM PDT 24
Finished May 19 01:15:39 PM PDT 24
Peak memory 195352 kb
Host smart-570dd7eb-a0e9-485f-84e9-217e72adf40a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178428714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1178428714
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1121481835
Short name T49
Test name
Test status
Simulation time 306303998 ps
CPU time 13.3 seconds
Started May 19 01:15:24 PM PDT 24
Finished May 19 01:15:51 PM PDT 24
Peak memory 208860 kb
Host smart-86b7665b-6154-41f7-9996-ece887d04e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121481835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1121481835
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3310119488
Short name T261
Test name
Test status
Simulation time 6102903741 ps
CPU time 23.77 seconds
Started May 19 01:15:24 PM PDT 24
Finished May 19 01:16:01 PM PDT 24
Peak memory 200752 kb
Host smart-ea8172a5-eefe-4aa6-8ee1-3179be475889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310119488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3310119488
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1555206604
Short name T88
Test name
Test status
Simulation time 1215719765 ps
CPU time 134.68 seconds
Started May 19 01:15:26 PM PDT 24
Finished May 19 01:17:53 PM PDT 24
Peak memory 465436 kb
Host smart-e708b77d-c04c-4da8-bbd9-f72f2bd97d18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555206604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1555206604
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1249605689
Short name T430
Test name
Test status
Simulation time 22099349215 ps
CPU time 75.12 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:16:54 PM PDT 24
Peak memory 200660 kb
Host smart-b93ef34b-1922-4f7d-bb7c-a207ac114734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249605689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1249605689
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.10863552
Short name T386
Test name
Test status
Simulation time 1192859722 ps
CPU time 6.63 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:15:45 PM PDT 24
Peak memory 200596 kb
Host smart-ea41cd1b-b94d-4e3a-a476-60ae540d395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10863552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.10863552
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.904348836
Short name T271
Test name
Test status
Simulation time 50414191 ps
CPU time 1.02 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:15:39 PM PDT 24
Peak memory 200072 kb
Host smart-09f3328a-68fd-4121-85b3-f0c271411bf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904348836 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.904348836
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3732792760
Short name T398
Test name
Test status
Simulation time 24851586086 ps
CPU time 450.12 seconds
Started May 19 01:15:22 PM PDT 24
Finished May 19 01:23:07 PM PDT 24
Peak memory 200664 kb
Host smart-b40b6e2d-be25-4cde-bc3b-c4896173886a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732792760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3732792760
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2335017329
Short name T157
Test name
Test status
Simulation time 20053903 ps
CPU time 0.58 seconds
Started May 19 01:15:24 PM PDT 24
Finished May 19 01:15:38 PM PDT 24
Peak memory 196392 kb
Host smart-d2c99e2b-9479-4435-92eb-a458ff2d32a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335017329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2335017329
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1405248452
Short name T249
Test name
Test status
Simulation time 573735645 ps
CPU time 11.48 seconds
Started May 19 01:15:26 PM PDT 24
Finished May 19 01:15:51 PM PDT 24
Peak memory 200600 kb
Host smart-1d3be534-88c0-4ba9-a788-e5b5ebf26f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405248452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1405248452
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.994598818
Short name T228
Test name
Test status
Simulation time 725209748 ps
CPU time 150.94 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:18:09 PM PDT 24
Peak memory 611012 kb
Host smart-e9fb1f4e-d807-4008-9b06-37f5debc285c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994598818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.994598818
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1191974695
Short name T423
Test name
Test status
Simulation time 2035999098 ps
CPU time 59.51 seconds
Started May 19 01:15:27 PM PDT 24
Finished May 19 01:16:39 PM PDT 24
Peak memory 200576 kb
Host smart-5e8517f9-7718-4b2e-bc56-c5c4cc4f230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191974695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1191974695
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3971494925
Short name T280
Test name
Test status
Simulation time 1436155838 ps
CPU time 3.65 seconds
Started May 19 01:15:24 PM PDT 24
Finished May 19 01:15:41 PM PDT 24
Peak memory 200604 kb
Host smart-96419c38-437c-485a-a2a2-90a3fadbcdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971494925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3971494925
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.737118962
Short name T373
Test name
Test status
Simulation time 80633651 ps
CPU time 1.07 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:15:39 PM PDT 24
Peak memory 200372 kb
Host smart-8f4ecc1c-f4ab-48d6-be2c-823a21888e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737118962 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.737118962
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1666822583
Short name T343
Test name
Test status
Simulation time 32690148733 ps
CPU time 463.01 seconds
Started May 19 01:15:24 PM PDT 24
Finished May 19 01:23:21 PM PDT 24
Peak memory 200628 kb
Host smart-0e6dc957-b3a2-45eb-a0ca-cf1b91e94aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666822583 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1666822583
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.967414232
Short name T265
Test name
Test status
Simulation time 31296805 ps
CPU time 0.56 seconds
Started May 19 01:15:32 PM PDT 24
Finished May 19 01:15:42 PM PDT 24
Peak memory 195336 kb
Host smart-8b190655-9818-4e3e-a274-69970cbd3f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967414232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.967414232
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.116589862
Short name T456
Test name
Test status
Simulation time 2320634377 ps
CPU time 31.55 seconds
Started May 19 01:15:29 PM PDT 24
Finished May 19 01:16:12 PM PDT 24
Peak memory 228204 kb
Host smart-d353f0e3-8fd3-4670-8b81-bd07016d8000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116589862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.116589862
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4269385915
Short name T162
Test name
Test status
Simulation time 110621295 ps
CPU time 2.33 seconds
Started May 19 01:15:31 PM PDT 24
Finished May 19 01:15:44 PM PDT 24
Peak memory 200572 kb
Host smart-f4c0c29b-ac6d-4ffd-a675-042e386e906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269385915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4269385915
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.627811116
Short name T417
Test name
Test status
Simulation time 2090662610 ps
CPU time 106.92 seconds
Started May 19 01:15:28 PM PDT 24
Finished May 19 01:17:27 PM PDT 24
Peak memory 410692 kb
Host smart-f8669150-6376-42a8-b4f6-1c36f2e3a8a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627811116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.627811116
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_long_msg.478451886
Short name T1
Test name
Test status
Simulation time 1348057095 ps
CPU time 3.05 seconds
Started May 19 01:15:30 PM PDT 24
Finished May 19 01:15:44 PM PDT 24
Peak memory 200508 kb
Host smart-1afaa02e-d9ae-47e4-b56c-bd5f5f864e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478451886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.478451886
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2018036292
Short name T309
Test name
Test status
Simulation time 501204262 ps
CPU time 5.67 seconds
Started May 19 01:15:29 PM PDT 24
Finished May 19 01:15:46 PM PDT 24
Peak memory 200592 kb
Host smart-1f07e2a6-bbdc-4abc-bd23-cb11ce32b07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018036292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2018036292
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.99247003
Short name T354
Test name
Test status
Simulation time 171251127 ps
CPU time 1.02 seconds
Started May 19 01:15:28 PM PDT 24
Finished May 19 01:15:42 PM PDT 24
Peak memory 200112 kb
Host smart-406993b8-3fd6-4a45-a59d-8e026db78606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99247003 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.hmac_test_hmac_vectors.99247003
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.638256248
Short name T366
Test name
Test status
Simulation time 39968837262 ps
CPU time 459.66 seconds
Started May 19 01:15:29 PM PDT 24
Finished May 19 01:23:20 PM PDT 24
Peak memory 200400 kb
Host smart-27b2aef2-8475-482c-b960-a7fa85e5950a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638256248 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.638256248
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2575437604
Short name T32
Test name
Test status
Simulation time 189369442 ps
CPU time 3.17 seconds
Started May 19 01:15:30 PM PDT 24
Finished May 19 01:15:44 PM PDT 24
Peak memory 200552 kb
Host smart-ec914fc7-758f-494e-8198-d2a505fa5369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575437604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2575437604
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.268943895
Short name T219
Test name
Test status
Simulation time 19962205 ps
CPU time 0.57 seconds
Started May 19 01:15:33 PM PDT 24
Finished May 19 01:15:43 PM PDT 24
Peak memory 196300 kb
Host smart-e505d4bc-8197-433b-a374-d74085ae5947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268943895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.268943895
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3597780137
Short name T320
Test name
Test status
Simulation time 4568798679 ps
CPU time 30.83 seconds
Started May 19 01:15:28 PM PDT 24
Finished May 19 01:16:11 PM PDT 24
Peak memory 208808 kb
Host smart-c698d39e-c269-4261-9edd-46b3d6b83b19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597780137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3597780137
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2897565900
Short name T482
Test name
Test status
Simulation time 1123794696 ps
CPU time 191.47 seconds
Started May 19 01:15:33 PM PDT 24
Finished May 19 01:18:54 PM PDT 24
Peak memory 447196 kb
Host smart-df232678-f39f-403e-a8ac-9ccaf9a61c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897565900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2897565900
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3728775519
Short name T416
Test name
Test status
Simulation time 5755621551 ps
CPU time 70.11 seconds
Started May 19 01:15:33 PM PDT 24
Finished May 19 01:16:52 PM PDT 24
Peak memory 200892 kb
Host smart-d7e1c14e-902a-49dd-b9d1-62cdf55a3022
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728775519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3728775519
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_smoke.2437093755
Short name T192
Test name
Test status
Simulation time 159894856 ps
CPU time 4.91 seconds
Started May 19 01:15:28 PM PDT 24
Finished May 19 01:15:45 PM PDT 24
Peak memory 200652 kb
Host smart-a9e3c159-2328-43a8-8673-424445bd6508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437093755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2437093755
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.935738193
Short name T385
Test name
Test status
Simulation time 51622775 ps
CPU time 0.97 seconds
Started May 19 01:15:36 PM PDT 24
Finished May 19 01:15:44 PM PDT 24
Peak memory 199184 kb
Host smart-130744e1-b4bb-4a3a-92c4-354dc958f31d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935738193 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.935738193
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.489739529
Short name T465
Test name
Test status
Simulation time 7488598338 ps
CPU time 464.78 seconds
Started May 19 01:15:36 PM PDT 24
Finished May 19 01:23:28 PM PDT 24
Peak memory 200604 kb
Host smart-10520b5e-ac4e-47d9-ac72-f218cc16066a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489739529 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.489739529
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.721450241
Short name T184
Test name
Test status
Simulation time 12353672 ps
CPU time 0.55 seconds
Started May 19 01:15:44 PM PDT 24
Finished May 19 01:15:48 PM PDT 24
Peak memory 196368 kb
Host smart-90d2f29e-d268-40fe-8c52-e7c6aea658b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721450241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.721450241
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.129569930
Short name T207
Test name
Test status
Simulation time 1694453872 ps
CPU time 47.7 seconds
Started May 19 01:15:37 PM PDT 24
Finished May 19 01:16:31 PM PDT 24
Peak memory 232856 kb
Host smart-ad03367b-08db-4540-b2ed-c1014d1dfdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129569930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.129569930
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1214227961
Short name T450
Test name
Test status
Simulation time 1758175468 ps
CPU time 24.99 seconds
Started May 19 01:15:39 PM PDT 24
Finished May 19 01:16:09 PM PDT 24
Peak memory 200564 kb
Host smart-5a157485-e1bb-4e6c-8ceb-6b0aba59085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214227961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1214227961
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3411884202
Short name T217
Test name
Test status
Simulation time 2298978839 ps
CPU time 536.34 seconds
Started May 19 01:15:43 PM PDT 24
Finished May 19 01:24:43 PM PDT 24
Peak memory 723756 kb
Host smart-b3077245-eae6-49da-b745-32c0aa2ee1fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411884202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3411884202
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2589381321
Short name T146
Test name
Test status
Simulation time 24478783896 ps
CPU time 75.4 seconds
Started May 19 01:15:44 PM PDT 24
Finished May 19 01:17:03 PM PDT 24
Peak memory 200588 kb
Host smart-ecbf9d20-9215-41b1-9eff-80561556b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589381321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2589381321
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2539860782
Short name T50
Test name
Test status
Simulation time 1009015585 ps
CPU time 4.18 seconds
Started May 19 01:15:35 PM PDT 24
Finished May 19 01:15:47 PM PDT 24
Peak memory 200652 kb
Host smart-05b8b281-5771-44cc-959b-ac964b42e90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539860782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2539860782
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3347343079
Short name T413
Test name
Test status
Simulation time 382587470 ps
CPU time 0.99 seconds
Started May 19 01:15:33 PM PDT 24
Finished May 19 01:15:43 PM PDT 24
Peak memory 199928 kb
Host smart-796ae5e4-569c-47c2-93b1-6c1135ff44c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347343079 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3347343079
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1942631036
Short name T345
Test name
Test status
Simulation time 114501475830 ps
CPU time 485.81 seconds
Started May 19 01:15:40 PM PDT 24
Finished May 19 01:23:50 PM PDT 24
Peak memory 200624 kb
Host smart-3ee2501a-7ecc-4319-9387-0c8907f735fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942631036 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1942631036
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2908781519
Short name T288
Test name
Test status
Simulation time 98790815 ps
CPU time 0.59 seconds
Started May 19 01:15:40 PM PDT 24
Finished May 19 01:15:45 PM PDT 24
Peak memory 195328 kb
Host smart-597daf7a-98d0-4d93-bafe-58c2db580960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908781519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2908781519
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2349493960
Short name T278
Test name
Test status
Simulation time 370828072 ps
CPU time 4.98 seconds
Started May 19 01:15:33 PM PDT 24
Finished May 19 01:15:47 PM PDT 24
Peak memory 200520 kb
Host smart-1cb7a4c5-5399-4364-8e6d-420fbda0b2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349493960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2349493960
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1482376937
Short name T298
Test name
Test status
Simulation time 3911529000 ps
CPU time 281.9 seconds
Started May 19 01:15:39 PM PDT 24
Finished May 19 01:20:26 PM PDT 24
Peak memory 471044 kb
Host smart-5f511577-c86e-4ceb-874c-49b8fa2b761d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482376937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1482376937
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.15061330
Short name T462
Test name
Test status
Simulation time 6865742115 ps
CPU time 31.77 seconds
Started May 19 01:15:36 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 200700 kb
Host smart-ba94c1ce-6340-4d31-8f26-e33340695f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15061330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.15061330
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.4294563822
Short name T353
Test name
Test status
Simulation time 1460414725 ps
CPU time 5.4 seconds
Started May 19 01:15:39 PM PDT 24
Finished May 19 01:15:50 PM PDT 24
Peak memory 200568 kb
Host smart-5b066b4a-7de8-4e97-867a-ea79439c6fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294563822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.4294563822
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3893576320
Short name T333
Test name
Test status
Simulation time 118067576 ps
CPU time 1.26 seconds
Started May 19 01:15:35 PM PDT 24
Finished May 19 01:15:44 PM PDT 24
Peak memory 200516 kb
Host smart-b8ea9093-01e9-4aea-9774-8dfac4438b06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893576320 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3893576320
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2258217112
Short name T175
Test name
Test status
Simulation time 138724516492 ps
CPU time 513.75 seconds
Started May 19 01:15:36 PM PDT 24
Finished May 19 01:24:17 PM PDT 24
Peak memory 200828 kb
Host smart-b25daa57-850a-40ea-b1e5-da2f4b27ce52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258217112 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2258217112
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1246291819
Short name T258
Test name
Test status
Simulation time 74019743 ps
CPU time 0.59 seconds
Started May 19 01:15:38 PM PDT 24
Finished May 19 01:15:44 PM PDT 24
Peak memory 196388 kb
Host smart-de8b1744-5895-40aa-9dce-1e02c9dd2af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246291819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1246291819
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3169401871
Short name T277
Test name
Test status
Simulation time 64315350 ps
CPU time 1.18 seconds
Started May 19 01:15:40 PM PDT 24
Finished May 19 01:15:46 PM PDT 24
Peak memory 200328 kb
Host smart-7ab6253c-f8e4-4194-8433-d7272a95627a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169401871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3169401871
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4095649463
Short name T103
Test name
Test status
Simulation time 36205076 ps
CPU time 1.13 seconds
Started May 19 01:15:39 PM PDT 24
Finished May 19 01:15:45 PM PDT 24
Peak memory 200592 kb
Host smart-2ee3cffe-9f88-4064-9626-bf5b250988db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095649463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4095649463
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3133116643
Short name T193
Test name
Test status
Simulation time 597949502 ps
CPU time 175.81 seconds
Started May 19 01:15:39 PM PDT 24
Finished May 19 01:18:40 PM PDT 24
Peak memory 618912 kb
Host smart-7053a16a-a089-4a8e-8a1a-8c82d645a595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133116643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3133116643
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3867093427
Short name T21
Test name
Test status
Simulation time 8678114961 ps
CPU time 24.63 seconds
Started May 19 01:15:42 PM PDT 24
Finished May 19 01:16:10 PM PDT 24
Peak memory 200668 kb
Host smart-b7b7a407-9853-4dc4-868d-d7ee55bce63e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867093427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3867093427
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2917822709
Short name T155
Test name
Test status
Simulation time 32377453140 ps
CPU time 91.31 seconds
Started May 19 01:15:41 PM PDT 24
Finished May 19 01:17:17 PM PDT 24
Peak memory 200568 kb
Host smart-76ef8bb5-d04c-4886-9de6-49e5c5afbd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917822709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2917822709
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2100296992
Short name T176
Test name
Test status
Simulation time 3144962008 ps
CPU time 4.19 seconds
Started May 19 01:15:40 PM PDT 24
Finished May 19 01:15:49 PM PDT 24
Peak memory 200676 kb
Host smart-7c3f4f10-7a50-4fe6-963f-1929e5b4d728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100296992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2100296992
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.847293010
Short name T463
Test name
Test status
Simulation time 49111450 ps
CPU time 1.04 seconds
Started May 19 01:15:43 PM PDT 24
Finished May 19 01:15:48 PM PDT 24
Peak memory 200272 kb
Host smart-f4cd9fa6-a0cc-4c34-9165-83498ea0bd3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847293010 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.847293010
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3783155907
Short name T312
Test name
Test status
Simulation time 47952232630 ps
CPU time 524.08 seconds
Started May 19 01:15:39 PM PDT 24
Finished May 19 01:24:28 PM PDT 24
Peak memory 200684 kb
Host smart-4607e6e6-569f-4e27-9139-01ccd8b418d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783155907 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3783155907
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1614092775
Short name T426
Test name
Test status
Simulation time 2002186527 ps
CPU time 19.81 seconds
Started May 19 01:15:39 PM PDT 24
Finished May 19 01:16:04 PM PDT 24
Peak memory 227732 kb
Host smart-e9afff77-cda5-4ebb-a499-0b83ab448e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614092775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1614092775
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2442773151
Short name T392
Test name
Test status
Simulation time 1763726771 ps
CPU time 46.91 seconds
Started May 19 01:15:41 PM PDT 24
Finished May 19 01:16:32 PM PDT 24
Peak memory 200636 kb
Host smart-7529c3ce-72ae-40c2-b81d-fa8789c5df28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442773151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2442773151
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_error.3487302787
Short name T440
Test name
Test status
Simulation time 758611920 ps
CPU time 11.35 seconds
Started May 19 01:15:47 PM PDT 24
Finished May 19 01:16:00 PM PDT 24
Peak memory 200460 kb
Host smart-621edb59-ed54-48ce-bca2-b256118d43b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487302787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3487302787
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2753445594
Short name T5
Test name
Test status
Simulation time 310191291 ps
CPU time 2.55 seconds
Started May 19 01:15:38 PM PDT 24
Finished May 19 01:15:46 PM PDT 24
Peak memory 200536 kb
Host smart-3dc67665-3980-45aa-95cb-a19b92c2caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753445594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2753445594
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3692913108
Short name T216
Test name
Test status
Simulation time 1326076660 ps
CPU time 1.45 seconds
Started May 19 01:15:38 PM PDT 24
Finished May 19 01:15:45 PM PDT 24
Peak memory 200528 kb
Host smart-73f70bd6-dc6c-49be-8f21-41f95e09e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692913108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3692913108
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1757688464
Short name T136
Test name
Test status
Simulation time 111046331706 ps
CPU time 801.26 seconds
Started May 19 01:15:46 PM PDT 24
Finished May 19 01:29:09 PM PDT 24
Peak memory 653960 kb
Host smart-92336e18-b726-4b6f-81ae-7494970036d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757688464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1757688464
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3310434967
Short name T140
Test name
Test status
Simulation time 55264730 ps
CPU time 0.98 seconds
Started May 19 01:15:43 PM PDT 24
Finished May 19 01:15:48 PM PDT 24
Peak memory 199728 kb
Host smart-9f61ddc4-2e0f-4abe-966d-71785eb88620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310434967 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3310434967
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1864955301
Short name T77
Test name
Test status
Simulation time 31221235141 ps
CPU time 565.99 seconds
Started May 19 01:15:44 PM PDT 24
Finished May 19 01:25:13 PM PDT 24
Peak memory 200612 kb
Host smart-b7e91883-2a5b-4db0-8176-e4e913b72531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864955301 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1864955301
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2353451780
Short name T453
Test name
Test status
Simulation time 446308062 ps
CPU time 7.62 seconds
Started May 19 01:15:46 PM PDT 24
Finished May 19 01:15:56 PM PDT 24
Peak memory 200468 kb
Host smart-f2a8f6c1-555f-4006-a0b0-aa7b926b036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353451780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2353451780
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.13690019
Short name T396
Test name
Test status
Simulation time 51806463 ps
CPU time 0.57 seconds
Started May 19 01:15:05 PM PDT 24
Finished May 19 01:15:24 PM PDT 24
Peak memory 196040 kb
Host smart-456f8190-09c0-4b83-8b77-335922d6831b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13690019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.13690019
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3455706763
Short name T51
Test name
Test status
Simulation time 464450001 ps
CPU time 23.4 seconds
Started May 19 01:15:04 PM PDT 24
Finished May 19 01:15:46 PM PDT 24
Peak memory 210192 kb
Host smart-2bc82016-f228-4966-9bd5-c108c0d16535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455706763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3455706763
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3659480374
Short name T362
Test name
Test status
Simulation time 3191423573 ps
CPU time 58.18 seconds
Started May 19 01:14:58 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 200668 kb
Host smart-27b9b830-6b3f-481d-9ad2-a52bd915f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659480374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3659480374
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1862293424
Short name T351
Test name
Test status
Simulation time 1810049639 ps
CPU time 493.94 seconds
Started May 19 01:15:00 PM PDT 24
Finished May 19 01:23:32 PM PDT 24
Peak memory 666080 kb
Host smart-b0838a0d-ef71-4e7d-a28b-953c14c2902a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862293424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1862293424
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.4181832009
Short name T419
Test name
Test status
Simulation time 1428649894 ps
CPU time 5.45 seconds
Started May 19 01:15:04 PM PDT 24
Finished May 19 01:15:28 PM PDT 24
Peak memory 200536 kb
Host smart-77174302-3a84-4df6-89c6-a9c6859bd5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181832009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.4181832009
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1883125888
Short name T35
Test name
Test status
Simulation time 58036371 ps
CPU time 0.92 seconds
Started May 19 01:15:02 PM PDT 24
Finished May 19 01:15:22 PM PDT 24
Peak memory 218784 kb
Host smart-2aba60cb-7331-409f-9427-1bd9e5a7b9a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883125888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1883125888
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2392947910
Short name T314
Test name
Test status
Simulation time 242868375 ps
CPU time 2.28 seconds
Started May 19 01:15:01 PM PDT 24
Finished May 19 01:15:22 PM PDT 24
Peak memory 200592 kb
Host smart-1d79c2e0-19fc-4e25-8d41-ed9e4481e3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392947910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2392947910
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.157810916
Short name T272
Test name
Test status
Simulation time 46343196 ps
CPU time 1.03 seconds
Started May 19 01:14:59 PM PDT 24
Finished May 19 01:15:19 PM PDT 24
Peak memory 200308 kb
Host smart-b5c52325-0642-49ea-8eb6-0632f80d82ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157810916 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.157810916
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2723533025
Short name T282
Test name
Test status
Simulation time 25256921 ps
CPU time 0.56 seconds
Started May 19 01:15:51 PM PDT 24
Finished May 19 01:15:53 PM PDT 24
Peak memory 196372 kb
Host smart-b1dd9fcb-f574-4394-b217-d148cb29ad59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723533025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2723533025
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3979133863
Short name T234
Test name
Test status
Simulation time 4687804364 ps
CPU time 47.16 seconds
Started May 19 01:15:46 PM PDT 24
Finished May 19 01:16:35 PM PDT 24
Peak memory 216320 kb
Host smart-d6abc020-7675-4d38-bcc3-61e3b3fc9243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979133863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3979133863
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2794518532
Short name T92
Test name
Test status
Simulation time 4017831720 ps
CPU time 39.13 seconds
Started May 19 01:15:44 PM PDT 24
Finished May 19 01:16:27 PM PDT 24
Peak memory 200980 kb
Host smart-cc560017-c7a2-4dc5-b022-8e877467c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794518532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2794518532
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1488910354
Short name T215
Test name
Test status
Simulation time 260111817 ps
CPU time 15.65 seconds
Started May 19 01:15:46 PM PDT 24
Finished May 19 01:16:04 PM PDT 24
Peak memory 200548 kb
Host smart-f177a17b-084b-434c-996b-ec3b40143266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488910354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1488910354
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1794495461
Short name T197
Test name
Test status
Simulation time 492863088 ps
CPU time 4.11 seconds
Started May 19 01:15:45 PM PDT 24
Finished May 19 01:15:52 PM PDT 24
Peak memory 200620 kb
Host smart-53570a8d-c164-4c57-9e7e-b0746fffeb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794495461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1794495461
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2792805681
Short name T137
Test name
Test status
Simulation time 176207732 ps
CPU time 0.99 seconds
Started May 19 01:15:45 PM PDT 24
Finished May 19 01:15:49 PM PDT 24
Peak memory 200028 kb
Host smart-d48f34b5-7710-4411-be29-797f4e530dc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792805681 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2792805681
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.869679191
Short name T15
Test name
Test status
Simulation time 52757306547 ps
CPU time 489.49 seconds
Started May 19 01:15:48 PM PDT 24
Finished May 19 01:23:59 PM PDT 24
Peak memory 200676 kb
Host smart-c731b0db-d180-4605-9d05-44dd8393e596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869679191 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.869679191
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1879978002
Short name T226
Test name
Test status
Simulation time 36794506 ps
CPU time 0.58 seconds
Started May 19 01:15:50 PM PDT 24
Finished May 19 01:15:51 PM PDT 24
Peak memory 196076 kb
Host smart-eff01107-f074-4a57-b51e-39add97213c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879978002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1879978002
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4075180976
Short name T267
Test name
Test status
Simulation time 9165676599 ps
CPU time 48.81 seconds
Started May 19 01:15:49 PM PDT 24
Finished May 19 01:16:38 PM PDT 24
Peak memory 235528 kb
Host smart-5853b496-e841-4b36-9234-2bf90c274f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075180976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4075180976
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1393770454
Short name T332
Test name
Test status
Simulation time 3454383393 ps
CPU time 877.09 seconds
Started May 19 01:15:50 PM PDT 24
Finished May 19 01:30:28 PM PDT 24
Peak memory 738024 kb
Host smart-a405a30f-6b5d-4175-b3df-a6466cb389ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393770454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1393770454
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.22146602
Short name T302
Test name
Test status
Simulation time 4176255511 ps
CPU time 27.42 seconds
Started May 19 01:15:50 PM PDT 24
Finished May 19 01:16:18 PM PDT 24
Peak memory 200668 kb
Host smart-9aff7888-0f57-40b6-97a1-c148582a9c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22146602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.22146602
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.227179178
Short name T471
Test name
Test status
Simulation time 27865063 ps
CPU time 1.17 seconds
Started May 19 01:15:49 PM PDT 24
Finished May 19 01:15:51 PM PDT 24
Peak memory 200440 kb
Host smart-a15aefc8-1c9d-48f6-8391-4d4548578b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227179178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.227179178
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3519357700
Short name T443
Test name
Test status
Simulation time 277988510 ps
CPU time 1.49 seconds
Started May 19 01:15:50 PM PDT 24
Finished May 19 01:15:52 PM PDT 24
Peak memory 200672 kb
Host smart-5321a544-1577-417c-87c9-4af243641597
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519357700 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3519357700
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2283617057
Short name T476
Test name
Test status
Simulation time 164391844461 ps
CPU time 481.77 seconds
Started May 19 01:15:49 PM PDT 24
Finished May 19 01:23:51 PM PDT 24
Peak memory 200896 kb
Host smart-e8dc0db2-c20f-4769-9bca-01f13483e56e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283617057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2283617057
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2268104620
Short name T460
Test name
Test status
Simulation time 11854817 ps
CPU time 0.6 seconds
Started May 19 01:16:01 PM PDT 24
Finished May 19 01:16:04 PM PDT 24
Peak memory 196068 kb
Host smart-18d272cf-2e18-4d6c-8e4b-7dbf150f9d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268104620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2268104620
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.696013997
Short name T48
Test name
Test status
Simulation time 190573399 ps
CPU time 10.18 seconds
Started May 19 01:15:50 PM PDT 24
Finished May 19 01:16:01 PM PDT 24
Peak memory 208748 kb
Host smart-85b4febe-07e3-4e1c-bca1-13fbba278bbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696013997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.696013997
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2434943747
Short name T483
Test name
Test status
Simulation time 4231578286 ps
CPU time 50.94 seconds
Started May 19 01:16:03 PM PDT 24
Finished May 19 01:16:55 PM PDT 24
Peak memory 200708 kb
Host smart-c0b6348c-b83f-4727-8729-477ddddbf81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434943747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2434943747
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1732615155
Short name T448
Test name
Test status
Simulation time 199837574 ps
CPU time 18.64 seconds
Started May 19 01:16:03 PM PDT 24
Finished May 19 01:16:23 PM PDT 24
Peak memory 227940 kb
Host smart-f4f2cbc6-8a83-4a76-bdba-0dd85aa7ad25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732615155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1732615155
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_long_msg.505878908
Short name T328
Test name
Test status
Simulation time 2058637037 ps
CPU time 41.18 seconds
Started May 19 01:15:49 PM PDT 24
Finished May 19 01:16:31 PM PDT 24
Peak memory 200608 kb
Host smart-ced3bf1a-2105-47f5-9e6e-ab267cc96e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505878908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.505878908
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2730919928
Short name T359
Test name
Test status
Simulation time 1536428718 ps
CPU time 5.4 seconds
Started May 19 01:15:49 PM PDT 24
Finished May 19 01:15:55 PM PDT 24
Peak memory 200644 kb
Host smart-da7cfc57-c6ed-4057-b3f1-b27144d3a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730919928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2730919928
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3559169236
Short name T31
Test name
Test status
Simulation time 39306136 ps
CPU time 0.62 seconds
Started May 19 01:15:56 PM PDT 24
Finished May 19 01:15:58 PM PDT 24
Peak memory 195904 kb
Host smart-6e5b989b-40ca-4996-83bf-ad972b27b44f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559169236 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3559169236
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.869838563
Short name T485
Test name
Test status
Simulation time 95974639 ps
CPU time 1.06 seconds
Started May 19 01:15:55 PM PDT 24
Finished May 19 01:15:58 PM PDT 24
Peak memory 199844 kb
Host smart-fb5b01d5-26d2-467f-8111-2a57983188c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869838563 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.869838563
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1802311061
Short name T235
Test name
Test status
Simulation time 67699157509 ps
CPU time 464.11 seconds
Started May 19 01:15:53 PM PDT 24
Finished May 19 01:23:38 PM PDT 24
Peak memory 200596 kb
Host smart-1874fe29-7ec9-4d70-9f68-47b408cce617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802311061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1802311061
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.535035964
Short name T164
Test name
Test status
Simulation time 102692223 ps
CPU time 0.63 seconds
Started May 19 01:16:01 PM PDT 24
Finished May 19 01:16:04 PM PDT 24
Peak memory 197092 kb
Host smart-edbf6610-3b0f-4e2e-9f99-992afff8e27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535035964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.535035964
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3490497690
Short name T46
Test name
Test status
Simulation time 4567380143 ps
CPU time 63.24 seconds
Started May 19 01:16:01 PM PDT 24
Finished May 19 01:17:06 PM PDT 24
Peak memory 227336 kb
Host smart-3dc66a87-bbdb-4fc5-8ff9-3cd72c629fb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490497690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3490497690
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.514063706
Short name T97
Test name
Test status
Simulation time 4551401044 ps
CPU time 35.49 seconds
Started May 19 01:15:58 PM PDT 24
Finished May 19 01:16:35 PM PDT 24
Peak memory 200940 kb
Host smart-cc392819-0741-40d2-aec7-13de4a95432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514063706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.514063706
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1971175045
Short name T160
Test name
Test status
Simulation time 4858342099 ps
CPU time 591.58 seconds
Started May 19 01:15:54 PM PDT 24
Finished May 19 01:25:47 PM PDT 24
Peak memory 651460 kb
Host smart-963506c9-81bd-4aae-884a-b97ef20e2f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971175045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1971175045
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2850551999
Short name T169
Test name
Test status
Simulation time 183908497 ps
CPU time 3.34 seconds
Started May 19 01:15:56 PM PDT 24
Finished May 19 01:16:01 PM PDT 24
Peak memory 200400 kb
Host smart-fcd2b027-4e7a-4fc0-b987-3c143b7a6b5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850551999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2850551999
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4168867204
Short name T337
Test name
Test status
Simulation time 334522820 ps
CPU time 4.74 seconds
Started May 19 01:15:57 PM PDT 24
Finished May 19 01:16:03 PM PDT 24
Peak memory 200552 kb
Host smart-8c975de9-723b-4c6d-8d84-6c1dff7d61d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168867204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4168867204
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.112866101
Short name T340
Test name
Test status
Simulation time 491202910 ps
CPU time 5.87 seconds
Started May 19 01:15:53 PM PDT 24
Finished May 19 01:16:00 PM PDT 24
Peak memory 200536 kb
Host smart-7ae3c623-de6c-4475-8940-93c9449cd19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112866101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.112866101
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1381050367
Short name T391
Test name
Test status
Simulation time 44229789 ps
CPU time 1.08 seconds
Started May 19 01:15:57 PM PDT 24
Finished May 19 01:16:00 PM PDT 24
Peak memory 199924 kb
Host smart-a3bc96a4-bf51-467e-a718-ee30060a37df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381050367 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1381050367
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2962651607
Short name T161
Test name
Test status
Simulation time 51481849725 ps
CPU time 486.17 seconds
Started May 19 01:16:03 PM PDT 24
Finished May 19 01:24:11 PM PDT 24
Peak memory 200644 kb
Host smart-fe3fa42d-feb7-4dcc-b565-2d4b4a41d21c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962651607 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.2962651607
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.657547299
Short name T245
Test name
Test status
Simulation time 75681672 ps
CPU time 4.32 seconds
Started May 19 01:15:59 PM PDT 24
Finished May 19 01:16:05 PM PDT 24
Peak memory 200628 kb
Host smart-a0806f8c-5673-4c3a-92c3-e59e38b9182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657547299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.657547299
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3541294832
Short name T75
Test name
Test status
Simulation time 27447337 ps
CPU time 0.63 seconds
Started May 19 01:16:00 PM PDT 24
Finished May 19 01:16:02 PM PDT 24
Peak memory 197100 kb
Host smart-c4b52b15-bc69-4365-b931-e23ec1d7e826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541294832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3541294832
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2511861509
Short name T208
Test name
Test status
Simulation time 2036909321 ps
CPU time 33.61 seconds
Started May 19 01:15:59 PM PDT 24
Finished May 19 01:16:35 PM PDT 24
Peak memory 232936 kb
Host smart-0bb9c5e1-cd9c-447c-a052-c0f65f27d311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511861509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2511861509
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3956353015
Short name T270
Test name
Test status
Simulation time 2129641526 ps
CPU time 39.45 seconds
Started May 19 01:15:59 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 200500 kb
Host smart-e50dc202-9216-4d41-bc4b-423de138881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956353015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3956353015
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2430917504
Short name T339
Test name
Test status
Simulation time 1520692076 ps
CPU time 208.34 seconds
Started May 19 01:16:01 PM PDT 24
Finished May 19 01:19:31 PM PDT 24
Peak memory 657256 kb
Host smart-275af2f4-851d-47e8-bf9d-c787731af544
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430917504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2430917504
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3403715317
Short name T335
Test name
Test status
Simulation time 94079045 ps
CPU time 2.92 seconds
Started May 19 01:16:02 PM PDT 24
Finished May 19 01:16:07 PM PDT 24
Peak memory 200436 kb
Host smart-c722e11b-2b90-42f7-b140-66b451636fd2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403715317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3403715317
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2420526956
Short name T223
Test name
Test status
Simulation time 2712000666 ps
CPU time 27.25 seconds
Started May 19 01:16:03 PM PDT 24
Finished May 19 01:16:31 PM PDT 24
Peak memory 200704 kb
Host smart-1d628a89-1090-41f7-8337-7def24d16fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420526956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2420526956
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1702314638
Short name T222
Test name
Test status
Simulation time 2783401367 ps
CPU time 6.59 seconds
Started May 19 01:15:57 PM PDT 24
Finished May 19 01:16:05 PM PDT 24
Peak memory 200708 kb
Host smart-2fd06468-c818-4372-90ef-5a5dc35268eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702314638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1702314638
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1073066806
Short name T477
Test name
Test status
Simulation time 189648499 ps
CPU time 1.12 seconds
Started May 19 01:15:59 PM PDT 24
Finished May 19 01:16:02 PM PDT 24
Peak memory 200376 kb
Host smart-2251f5ee-445c-45ef-84e1-50db0639d911
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073066806 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1073066806
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2220106937
Short name T457
Test name
Test status
Simulation time 32348816305 ps
CPU time 410.72 seconds
Started May 19 01:16:02 PM PDT 24
Finished May 19 01:22:55 PM PDT 24
Peak memory 200604 kb
Host smart-be4bea36-15fa-4cda-bd2c-3c8981ff059a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220106937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.2220106937
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2195109566
Short name T425
Test name
Test status
Simulation time 46004278 ps
CPU time 0.63 seconds
Started May 19 01:16:10 PM PDT 24
Finished May 19 01:16:12 PM PDT 24
Peak memory 196584 kb
Host smart-51af38e0-1eec-4680-b2f0-8cb721cccbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195109566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2195109566
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.677550282
Short name T381
Test name
Test status
Simulation time 1459292312 ps
CPU time 45.63 seconds
Started May 19 01:16:00 PM PDT 24
Finished May 19 01:16:48 PM PDT 24
Peak memory 248276 kb
Host smart-d30b11d9-d489-45f0-9d2f-b8f9a07804db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677550282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.677550282
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3724389657
Short name T174
Test name
Test status
Simulation time 4247395009 ps
CPU time 304.92 seconds
Started May 19 01:16:04 PM PDT 24
Finished May 19 01:21:10 PM PDT 24
Peak memory 695664 kb
Host smart-f0855dfc-5eeb-4f41-80b2-c446ce7fb5e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724389657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3724389657
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_long_msg.152895554
Short name T131
Test name
Test status
Simulation time 10539509859 ps
CPU time 33.78 seconds
Started May 19 01:16:01 PM PDT 24
Finished May 19 01:16:37 PM PDT 24
Peak memory 200716 kb
Host smart-cd18b939-954c-402e-bd4d-c9d7b7c7225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152895554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.152895554
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2618323400
Short name T247
Test name
Test status
Simulation time 187347915 ps
CPU time 3.01 seconds
Started May 19 01:16:00 PM PDT 24
Finished May 19 01:16:05 PM PDT 24
Peak memory 200628 kb
Host smart-97968bd6-8ccf-4d7e-8a2c-bb4adb3eada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618323400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2618323400
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.25932450
Short name T308
Test name
Test status
Simulation time 74527021 ps
CPU time 1.39 seconds
Started May 19 01:16:02 PM PDT 24
Finished May 19 01:16:05 PM PDT 24
Peak memory 200852 kb
Host smart-f418d0dc-a967-4fd9-8dfc-055eb39092c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25932450 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.hmac_test_hmac_vectors.25932450
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2641736706
Short name T124
Test name
Test status
Simulation time 26270770256 ps
CPU time 484.48 seconds
Started May 19 01:16:01 PM PDT 24
Finished May 19 01:24:08 PM PDT 24
Peak memory 200900 kb
Host smart-abab7fcf-4761-4636-b6b6-48541d7f8a10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641736706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2641736706
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_alert_test.242030204
Short name T422
Test name
Test status
Simulation time 14890058 ps
CPU time 0.58 seconds
Started May 19 01:16:05 PM PDT 24
Finished May 19 01:16:06 PM PDT 24
Peak memory 195304 kb
Host smart-44d60de8-6aef-465d-825c-7bd6fd4d9239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242030204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.242030204
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3085506307
Short name T6
Test name
Test status
Simulation time 4027460336 ps
CPU time 34.5 seconds
Started May 19 01:16:08 PM PDT 24
Finished May 19 01:16:43 PM PDT 24
Peak memory 232192 kb
Host smart-91daeff3-c79a-4fad-a771-b9b1022d24ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085506307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3085506307
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.664615212
Short name T106
Test name
Test status
Simulation time 1888675838 ps
CPU time 24.3 seconds
Started May 19 01:16:07 PM PDT 24
Finished May 19 01:16:32 PM PDT 24
Peak memory 200636 kb
Host smart-d82e9ce4-1d0b-444c-99e3-b663e39f1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664615212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.664615212
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3614541426
Short name T250
Test name
Test status
Simulation time 1694188766 ps
CPU time 405.91 seconds
Started May 19 01:16:08 PM PDT 24
Finished May 19 01:22:55 PM PDT 24
Peak memory 478708 kb
Host smart-173fb834-90cf-4244-9962-8c43a59d1947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614541426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3614541426
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1765219737
Short name T252
Test name
Test status
Simulation time 3469721623 ps
CPU time 46.75 seconds
Started May 19 01:16:06 PM PDT 24
Finished May 19 01:16:54 PM PDT 24
Peak memory 200736 kb
Host smart-392f8468-e28b-4450-b73e-f8b151b91f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765219737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1765219737
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1341561699
Short name T195
Test name
Test status
Simulation time 128503983 ps
CPU time 1.38 seconds
Started May 19 01:16:08 PM PDT 24
Finished May 19 01:16:10 PM PDT 24
Peak memory 200640 kb
Host smart-454df869-ee05-4852-89be-f7437f51298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341561699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1341561699
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3861544260
Short name T429
Test name
Test status
Simulation time 2136753245 ps
CPU time 517.01 seconds
Started May 19 01:16:06 PM PDT 24
Finished May 19 01:24:44 PM PDT 24
Peak memory 685680 kb
Host smart-a609721d-c97d-46b3-9e5f-23170ead21e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861544260 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3861544260
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1827381999
Short name T466
Test name
Test status
Simulation time 52579779 ps
CPU time 1.28 seconds
Started May 19 01:16:08 PM PDT 24
Finished May 19 01:16:09 PM PDT 24
Peak memory 200612 kb
Host smart-da9a0b17-9bf4-44b5-983b-bea981926b78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827381999 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1827381999
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1210547949
Short name T363
Test name
Test status
Simulation time 7845131819 ps
CPU time 482.67 seconds
Started May 19 01:16:07 PM PDT 24
Finished May 19 01:24:11 PM PDT 24
Peak memory 200972 kb
Host smart-6b5ac301-dcf5-4293-a84e-ecbc0b238670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210547949 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1210547949
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3829099300
Short name T254
Test name
Test status
Simulation time 21027110 ps
CPU time 0.59 seconds
Started May 19 01:16:14 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 196344 kb
Host smart-4d9263ab-1e65-4de3-8a7f-6b304a4bb304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829099300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3829099300
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1674154774
Short name T214
Test name
Test status
Simulation time 388209115 ps
CPU time 16.74 seconds
Started May 19 01:16:03 PM PDT 24
Finished May 19 01:16:22 PM PDT 24
Peak memory 202712 kb
Host smart-6902ed9b-b351-4af7-bc39-f7296fcbbc4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674154774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1674154774
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1943845984
Short name T41
Test name
Test status
Simulation time 5513876929 ps
CPU time 21.84 seconds
Started May 19 01:16:07 PM PDT 24
Finished May 19 01:16:30 PM PDT 24
Peak memory 200584 kb
Host smart-1d9287dc-7a4e-4c15-8ae1-abf60e190c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943845984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1943845984
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3924138054
Short name T190
Test name
Test status
Simulation time 6414252722 ps
CPU time 386.31 seconds
Started May 19 01:16:06 PM PDT 24
Finished May 19 01:22:33 PM PDT 24
Peak memory 684968 kb
Host smart-1e8a153f-bf09-411a-b5cf-18d651a1d16f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924138054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3924138054
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1431654192
Short name T347
Test name
Test status
Simulation time 6690290562 ps
CPU time 95.01 seconds
Started May 19 01:16:06 PM PDT 24
Finished May 19 01:17:42 PM PDT 24
Peak memory 200704 kb
Host smart-791b44a8-91e8-47ba-9af3-181cc9a0c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431654192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1431654192
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1552687067
Short name T403
Test name
Test status
Simulation time 64261331 ps
CPU time 1.33 seconds
Started May 19 01:16:05 PM PDT 24
Finished May 19 01:16:07 PM PDT 24
Peak memory 200540 kb
Host smart-5848250d-40d2-4140-abae-ecfd8a1b6de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552687067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1552687067
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.188971373
Short name T464
Test name
Test status
Simulation time 59398546 ps
CPU time 1.3 seconds
Started May 19 01:16:15 PM PDT 24
Finished May 19 01:16:17 PM PDT 24
Peak memory 200552 kb
Host smart-0e7fabfd-a685-4e49-83bd-7978b9f47f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188971373 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.188971373
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1801549634
Short name T170
Test name
Test status
Simulation time 39713868350 ps
CPU time 535.72 seconds
Started May 19 01:16:14 PM PDT 24
Finished May 19 01:25:11 PM PDT 24
Peak memory 200612 kb
Host smart-1a528b3e-9838-4099-a3c7-4aea2b6819c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801549634 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1801549634
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1338017357
Short name T389
Test name
Test status
Simulation time 60690632 ps
CPU time 0.56 seconds
Started May 19 01:16:12 PM PDT 24
Finished May 19 01:16:14 PM PDT 24
Peak memory 196300 kb
Host smart-934d950e-2285-4bf5-bdbb-ac46c2f8bb0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338017357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1338017357
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1016376349
Short name T236
Test name
Test status
Simulation time 2998789532 ps
CPU time 33.2 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 241512 kb
Host smart-7c5ec641-9bce-42ca-830c-bf5468670fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016376349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1016376349
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2284598139
Short name T292
Test name
Test status
Simulation time 9532181553 ps
CPU time 32.51 seconds
Started May 19 01:16:13 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 200684 kb
Host smart-f7331b99-1809-4766-b755-87d32c6478f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284598139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2284598139
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3665415355
Short name T355
Test name
Test status
Simulation time 1986456848 ps
CPU time 556.55 seconds
Started May 19 01:16:13 PM PDT 24
Finished May 19 01:25:31 PM PDT 24
Peak memory 702712 kb
Host smart-0eafdffd-c880-4185-8e19-2745af1aab09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665415355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3665415355
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3186846438
Short name T123
Test name
Test status
Simulation time 410376661 ps
CPU time 23.1 seconds
Started May 19 01:16:13 PM PDT 24
Finished May 19 01:16:37 PM PDT 24
Peak memory 200400 kb
Host smart-b5eea98e-d76e-4649-814f-7e456efb247a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186846438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3186846438
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3959008653
Short name T180
Test name
Test status
Simulation time 5061544564 ps
CPU time 81.1 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:17:43 PM PDT 24
Peak memory 200672 kb
Host smart-279c4ea6-7018-469b-9a14-d22349e8850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959008653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3959008653
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3715935494
Short name T439
Test name
Test status
Simulation time 439003416 ps
CPU time 6.02 seconds
Started May 19 01:16:15 PM PDT 24
Finished May 19 01:16:22 PM PDT 24
Peak memory 200556 kb
Host smart-592ce50d-6986-47aa-a1fb-e10fc5e95420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715935494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3715935494
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2093795890
Short name T401
Test name
Test status
Simulation time 132538265 ps
CPU time 1.23 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:22 PM PDT 24
Peak memory 200516 kb
Host smart-8f208364-459b-40e1-96a9-6bea583b7577
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093795890 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2093795890
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3251782880
Short name T210
Test name
Test status
Simulation time 15824653745 ps
CPU time 432.94 seconds
Started May 19 01:16:13 PM PDT 24
Finished May 19 01:23:27 PM PDT 24
Peak memory 200660 kb
Host smart-b5838595-dcb1-4612-9ac4-25a2a669b104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251782880 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3251782880
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3386946399
Short name T263
Test name
Test status
Simulation time 461288232 ps
CPU time 8.13 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:16:20 PM PDT 24
Peak memory 200552 kb
Host smart-8568632b-1052-4611-ad86-3580e5480a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386946399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3386946399
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2451620714
Short name T325
Test name
Test status
Simulation time 11746534 ps
CPU time 0.6 seconds
Started May 19 01:16:13 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 196336 kb
Host smart-5d601862-0db8-4542-b654-26e99dc1608c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451620714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2451620714
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3508033087
Short name T304
Test name
Test status
Simulation time 997651510 ps
CPU time 53.67 seconds
Started May 19 01:16:10 PM PDT 24
Finished May 19 01:17:04 PM PDT 24
Peak memory 232120 kb
Host smart-fbcf603e-883a-484b-a57d-3c4d5271a3c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508033087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3508033087
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3300177978
Short name T361
Test name
Test status
Simulation time 8586823705 ps
CPU time 504.38 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:24:37 PM PDT 24
Peak memory 715248 kb
Host smart-81ad62f4-23e3-4123-8930-79d8cf233cec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300177978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3300177978
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3352108977
Short name T20
Test name
Test status
Simulation time 9068031265 ps
CPU time 72.62 seconds
Started May 19 01:16:12 PM PDT 24
Finished May 19 01:17:26 PM PDT 24
Peak memory 200696 kb
Host smart-814ca1cd-3aef-4721-b774-becd65d11807
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352108977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3352108977
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2689040051
Short name T317
Test name
Test status
Simulation time 15868712 ps
CPU time 0.85 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:16:13 PM PDT 24
Peak memory 199072 kb
Host smart-1110e032-099a-4856-bf07-11733e2e1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689040051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2689040051
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1711042512
Short name T178
Test name
Test status
Simulation time 197274640 ps
CPU time 6.43 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:29 PM PDT 24
Peak memory 200560 kb
Host smart-dc97d837-4dc1-4fb9-bdb6-dc36ea0a38e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711042512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1711042512
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2303303249
Short name T243
Test name
Test status
Simulation time 44527131 ps
CPU time 1.09 seconds
Started May 19 01:16:13 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 200344 kb
Host smart-0f3795bf-a61e-4940-b199-20b15bbc73f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303303249 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2303303249
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.4004644099
Short name T76
Test name
Test status
Simulation time 29406113127 ps
CPU time 542.4 seconds
Started May 19 01:16:15 PM PDT 24
Finished May 19 01:25:18 PM PDT 24
Peak memory 200660 kb
Host smart-9dc13a5d-600d-4a6a-b31b-8ce4f27d2204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004644099 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.4004644099
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.476766692
Short name T139
Test name
Test status
Simulation time 12581549 ps
CPU time 0.57 seconds
Started May 19 01:15:13 PM PDT 24
Finished May 19 01:15:32 PM PDT 24
Peak memory 196336 kb
Host smart-1498f6f7-8b23-4753-a0b4-a75d835e6c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476766692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.476766692
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1814216730
Short name T171
Test name
Test status
Simulation time 2776999298 ps
CPU time 41.83 seconds
Started May 19 01:15:10 PM PDT 24
Finished May 19 01:16:09 PM PDT 24
Peak memory 220192 kb
Host smart-ffc1c422-621e-42b5-ae5c-c4731797ad72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814216730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1814216730
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3887207442
Short name T458
Test name
Test status
Simulation time 5015087484 ps
CPU time 16.84 seconds
Started May 19 01:15:13 PM PDT 24
Finished May 19 01:15:48 PM PDT 24
Peak memory 200632 kb
Host smart-bf29e2a1-58ce-4775-adf4-a8c614e3af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887207442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3887207442
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3926344584
Short name T299
Test name
Test status
Simulation time 3092276218 ps
CPU time 386.41 seconds
Started May 19 01:15:13 PM PDT 24
Finished May 19 01:21:57 PM PDT 24
Peak memory 657224 kb
Host smart-ad670473-1a43-43a3-951c-546050e2209b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926344584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3926344584
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.4292314048
Short name T336
Test name
Test status
Simulation time 5801275358 ps
CPU time 118.35 seconds
Started May 19 01:15:10 PM PDT 24
Finished May 19 01:17:25 PM PDT 24
Peak memory 200688 kb
Host smart-120baccf-a54d-4ceb-b855-112fa5330593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292314048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.4292314048
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2524175696
Short name T38
Test name
Test status
Simulation time 63252953 ps
CPU time 0.85 seconds
Started May 19 01:15:09 PM PDT 24
Finished May 19 01:15:27 PM PDT 24
Peak memory 218720 kb
Host smart-fcddf2ee-5b8d-4add-9a8c-244eb5664486
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524175696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2524175696
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4127903858
Short name T452
Test name
Test status
Simulation time 97277755 ps
CPU time 1.19 seconds
Started May 19 01:15:10 PM PDT 24
Finished May 19 01:15:28 PM PDT 24
Peak memory 200584 kb
Host smart-4bf30b66-b11b-41e3-a850-94261c1a1ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127903858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4127903858
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.494910511
Short name T342
Test name
Test status
Simulation time 576078714 ps
CPU time 1.33 seconds
Started May 19 01:15:03 PM PDT 24
Finished May 19 01:15:23 PM PDT 24
Peak memory 200436 kb
Host smart-1022dc83-d64c-4a03-be1c-17668968185a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494910511 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.494910511
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2946459271
Short name T239
Test name
Test status
Simulation time 27747819584 ps
CPU time 411.17 seconds
Started May 19 01:15:03 PM PDT 24
Finished May 19 01:22:13 PM PDT 24
Peak memory 200576 kb
Host smart-d7fc854a-32d4-4043-aea0-bb2527e554a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946459271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2946459271
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.867781449
Short name T34
Test name
Test status
Simulation time 179841034 ps
CPU time 4.86 seconds
Started May 19 01:15:05 PM PDT 24
Finished May 19 01:15:28 PM PDT 24
Peak memory 200584 kb
Host smart-f8f6ad62-3ce4-4c78-85f0-206b9ce51aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867781449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.867781449
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.826986633
Short name T310
Test name
Test status
Simulation time 17444150 ps
CPU time 0.58 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:23 PM PDT 24
Peak memory 197020 kb
Host smart-763e4875-1aef-4eab-984b-68066a77c83e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826986633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.826986633
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.82106676
Short name T394
Test name
Test status
Simulation time 2089336360 ps
CPU time 51.54 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:17:13 PM PDT 24
Peak memory 228176 kb
Host smart-c2712848-9f5c-4709-a97b-010ff5bc669f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82106676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.82106676
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2338014567
Short name T447
Test name
Test status
Simulation time 17667147307 ps
CPU time 56.98 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:17:09 PM PDT 24
Peak memory 200688 kb
Host smart-a9636753-3a34-4776-8cbf-05a833a20f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338014567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2338014567
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2515348513
Short name T105
Test name
Test status
Simulation time 2048766694 ps
CPU time 512 seconds
Started May 19 01:16:14 PM PDT 24
Finished May 19 01:24:47 PM PDT 24
Peak memory 703508 kb
Host smart-24b7393a-31a0-4f72-ab32-bb62492d15a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515348513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2515348513
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3656664089
Short name T284
Test name
Test status
Simulation time 23483859500 ps
CPU time 116.8 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:18:09 PM PDT 24
Peak memory 200672 kb
Host smart-fa86d014-f10a-447f-a637-f168df81d243
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656664089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3656664089
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1415329004
Short name T191
Test name
Test status
Simulation time 5073056558 ps
CPU time 57.09 seconds
Started May 19 01:16:10 PM PDT 24
Finished May 19 01:17:09 PM PDT 24
Peak memory 200692 kb
Host smart-567c7016-e7a0-4702-844e-d891fff8d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415329004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1415329004
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1613660290
Short name T163
Test name
Test status
Simulation time 1780213956 ps
CPU time 7.16 seconds
Started May 19 01:16:11 PM PDT 24
Finished May 19 01:16:19 PM PDT 24
Peak memory 200644 kb
Host smart-68d28873-3a89-4eef-85f9-7bf0ce5c7af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613660290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1613660290
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2440274446
Short name T268
Test name
Test status
Simulation time 69372634 ps
CPU time 1.2 seconds
Started May 19 01:16:13 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 200560 kb
Host smart-e6cfe56a-864d-4733-8fd0-10d56b10f774
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440274446 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2440274446
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3105576352
Short name T221
Test name
Test status
Simulation time 23973054833 ps
CPU time 420.48 seconds
Started May 19 01:16:21 PM PDT 24
Finished May 19 01:23:24 PM PDT 24
Peak memory 200612 kb
Host smart-c6176741-24cc-4685-97e1-6885a49ac4aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105576352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3105576352
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3947291555
Short name T138
Test name
Test status
Simulation time 19063690 ps
CPU time 0.64 seconds
Started May 19 01:16:15 PM PDT 24
Finished May 19 01:16:17 PM PDT 24
Peak memory 197024 kb
Host smart-145fefaf-ceb7-4682-9f45-a9544fe921c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947291555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3947291555
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4164862535
Short name T237
Test name
Test status
Simulation time 104556401 ps
CPU time 6.27 seconds
Started May 19 01:16:15 PM PDT 24
Finished May 19 01:16:23 PM PDT 24
Peak memory 208648 kb
Host smart-7e45dc20-373c-4f24-b6dd-98bf32cdb5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164862535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4164862535
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1132287953
Short name T104
Test name
Test status
Simulation time 536695669 ps
CPU time 26.88 seconds
Started May 19 01:16:16 PM PDT 24
Finished May 19 01:16:44 PM PDT 24
Peak memory 200588 kb
Host smart-3bdcd051-30c1-4e05-9861-afc230ce0351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132287953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1132287953
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.851577838
Short name T287
Test name
Test status
Simulation time 11653299623 ps
CPU time 907.21 seconds
Started May 19 01:16:18 PM PDT 24
Finished May 19 01:31:27 PM PDT 24
Peak memory 755208 kb
Host smart-c8e506e4-216a-4ce5-9e9d-eff08092a016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851577838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.851577838
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3363810072
Short name T45
Test name
Test status
Simulation time 1527866160 ps
CPU time 10.19 seconds
Started May 19 01:16:18 PM PDT 24
Finished May 19 01:16:29 PM PDT 24
Peak memory 200720 kb
Host smart-7d81a788-fe86-4477-b88d-e60127a62c75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363810072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3363810072
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2007620447
Short name T285
Test name
Test status
Simulation time 6931030892 ps
CPU time 140.16 seconds
Started May 19 01:16:15 PM PDT 24
Finished May 19 01:18:36 PM PDT 24
Peak memory 200736 kb
Host smart-c4b25c5a-9576-427a-88b1-c96fa16179a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007620447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2007620447
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.292328838
Short name T179
Test name
Test status
Simulation time 208137425 ps
CPU time 6.45 seconds
Started May 19 01:16:16 PM PDT 24
Finished May 19 01:16:24 PM PDT 24
Peak memory 200588 kb
Host smart-75690b4c-604f-4f0c-b509-83d64919734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292328838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.292328838
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3477606703
Short name T183
Test name
Test status
Simulation time 33005512 ps
CPU time 1.14 seconds
Started May 19 01:16:15 PM PDT 24
Finished May 19 01:16:18 PM PDT 24
Peak memory 200520 kb
Host smart-06ef3642-7810-4689-a0d1-758f938e5ef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477606703 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3477606703
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1190236531
Short name T187
Test name
Test status
Simulation time 14981277788 ps
CPU time 417.33 seconds
Started May 19 01:16:16 PM PDT 24
Finished May 19 01:23:15 PM PDT 24
Peak memory 200684 kb
Host smart-b1c20d0b-714c-477c-a1bc-f8b348dd4ca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190236531 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1190236531
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.800768480
Short name T11
Test name
Test status
Simulation time 11802991 ps
CPU time 0.58 seconds
Started May 19 01:16:17 PM PDT 24
Finished May 19 01:16:19 PM PDT 24
Peak memory 195348 kb
Host smart-28d1c243-a948-41d7-a5ce-85a423fb91f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800768480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.800768480
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2937942549
Short name T127
Test name
Test status
Simulation time 4117495495 ps
CPU time 47.82 seconds
Started May 19 01:16:19 PM PDT 24
Finished May 19 01:17:08 PM PDT 24
Peak memory 208924 kb
Host smart-6efa176f-248b-49ea-b8c5-4f07e047da54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937942549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2937942549
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.139070948
Short name T229
Test name
Test status
Simulation time 758981026 ps
CPU time 15.02 seconds
Started May 19 01:16:18 PM PDT 24
Finished May 19 01:16:34 PM PDT 24
Peak memory 200572 kb
Host smart-90f68d26-2725-447d-b599-d193a35e373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139070948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.139070948
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.820695352
Short name T329
Test name
Test status
Simulation time 108432355 ps
CPU time 0.72 seconds
Started May 19 01:16:17 PM PDT 24
Finished May 19 01:16:19 PM PDT 24
Peak memory 198076 kb
Host smart-454cf410-1ed6-4615-8e96-ea6966815500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820695352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.820695352
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.57207183
Short name T484
Test name
Test status
Simulation time 8317900239 ps
CPU time 74.87 seconds
Started May 19 01:16:16 PM PDT 24
Finished May 19 01:17:33 PM PDT 24
Peak memory 200748 kb
Host smart-81bf23ca-3be1-4968-93af-d73ef3001f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57207183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.57207183
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.428985669
Short name T256
Test name
Test status
Simulation time 369797916 ps
CPU time 5.8 seconds
Started May 19 01:16:16 PM PDT 24
Finished May 19 01:16:23 PM PDT 24
Peak memory 200884 kb
Host smart-8723f230-6ca7-4353-89dd-27b7e43865e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428985669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.428985669
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.759566928
Short name T276
Test name
Test status
Simulation time 55659291 ps
CPU time 1.3 seconds
Started May 19 01:16:21 PM PDT 24
Finished May 19 01:16:26 PM PDT 24
Peak memory 200420 kb
Host smart-4c251d32-13cd-4f1a-bc80-3d2d45b0f443
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759566928 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.759566928
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3469289688
Short name T200
Test name
Test status
Simulation time 92351679395 ps
CPU time 421.95 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:23:23 PM PDT 24
Peak memory 200568 kb
Host smart-acedeff3-eedc-4e51-a256-8d7aa89c8153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469289688 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.3469289688
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2862736630
Short name T409
Test name
Test status
Simulation time 53094395 ps
CPU time 0.58 seconds
Started May 19 01:16:23 PM PDT 24
Finished May 19 01:16:26 PM PDT 24
Peak memory 196004 kb
Host smart-ad1fafb4-1269-4907-bff9-f0aa0207777a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862736630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2862736630
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4259235192
Short name T259
Test name
Test status
Simulation time 4169167309 ps
CPU time 66.59 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:17:27 PM PDT 24
Peak memory 233536 kb
Host smart-956c289b-89f2-4f17-b59e-5fa87f4dd55d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259235192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4259235192
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.70889901
Short name T152
Test name
Test status
Simulation time 4779667030 ps
CPU time 21.97 seconds
Started May 19 01:16:18 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 200748 kb
Host smart-b886e900-22fd-4a27-84a2-14d5e20193b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70889901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.70889901
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2745673051
Short name T307
Test name
Test status
Simulation time 6942265818 ps
CPU time 811.17 seconds
Started May 19 01:16:21 PM PDT 24
Finished May 19 01:29:55 PM PDT 24
Peak memory 716500 kb
Host smart-42eb5b12-c1ee-41ee-ba66-2850a58b4698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745673051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2745673051
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3760524355
Short name T266
Test name
Test status
Simulation time 3372201402 ps
CPU time 63.2 seconds
Started May 19 01:16:16 PM PDT 24
Finished May 19 01:17:20 PM PDT 24
Peak memory 200772 kb
Host smart-1301d46d-c81f-4e67-9f67-c428567687a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760524355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3760524355
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4038693280
Short name T454
Test name
Test status
Simulation time 778769274 ps
CPU time 3.19 seconds
Started May 19 01:16:18 PM PDT 24
Finished May 19 01:16:22 PM PDT 24
Peak memory 200904 kb
Host smart-e7d54c70-07bd-4cfa-877c-45ec9ca62b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038693280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4038693280
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.480879072
Short name T24
Test name
Test status
Simulation time 109517371 ps
CPU time 1.22 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:24 PM PDT 24
Peak memory 199576 kb
Host smart-e8d32436-d33f-4dc3-a68a-93d6df0509d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480879072 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.480879072
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3061315373
Short name T451
Test name
Test status
Simulation time 145005445019 ps
CPU time 497.54 seconds
Started May 19 01:16:21 PM PDT 24
Finished May 19 01:24:42 PM PDT 24
Peak memory 200684 kb
Host smart-6faeb405-6d53-43d2-8703-7c6ee1649b39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061315373 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3061315373
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.4293447140
Short name T459
Test name
Test status
Simulation time 10447065 ps
CPU time 0.56 seconds
Started May 19 01:16:22 PM PDT 24
Finished May 19 01:16:26 PM PDT 24
Peak memory 196036 kb
Host smart-2c22b055-6fc3-4cd1-99cc-02debb37c5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293447140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4293447140
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2284848891
Short name T166
Test name
Test status
Simulation time 941935415 ps
CPU time 23.68 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 216936 kb
Host smart-cf28eab3-0998-4e04-96eb-65f33bdf62b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284848891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2284848891
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3970949315
Short name T478
Test name
Test status
Simulation time 2684317267 ps
CPU time 67.98 seconds
Started May 19 01:16:22 PM PDT 24
Finished May 19 01:17:33 PM PDT 24
Peak memory 200640 kb
Host smart-26e82c19-6186-409f-8735-b091da273485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970949315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3970949315
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3546839396
Short name T168
Test name
Test status
Simulation time 16422060973 ps
CPU time 1068.13 seconds
Started May 19 01:16:25 PM PDT 24
Finished May 19 01:34:16 PM PDT 24
Peak memory 759028 kb
Host smart-a0dd6d26-acad-4fce-aa9c-c5693e2d7e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546839396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3546839396
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.918216109
Short name T225
Test name
Test status
Simulation time 6356609585 ps
CPU time 30.23 seconds
Started May 19 01:16:23 PM PDT 24
Finished May 19 01:16:56 PM PDT 24
Peak memory 200504 kb
Host smart-94358d27-6510-4fd3-a35f-eaca64658def
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918216109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.918216109
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3664187583
Short name T349
Test name
Test status
Simulation time 3622631224 ps
CPU time 104.58 seconds
Started May 19 01:16:25 PM PDT 24
Finished May 19 01:18:12 PM PDT 24
Peak memory 200764 kb
Host smart-99928e62-bd42-43d8-9e62-321d4fb9b821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664187583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3664187583
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.671219994
Short name T368
Test name
Test status
Simulation time 813822627 ps
CPU time 2.76 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:25 PM PDT 24
Peak memory 200536 kb
Host smart-cc268f4f-ffd9-485d-909c-8afcd7c451a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671219994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.671219994
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.4263143788
Short name T148
Test name
Test status
Simulation time 139585781 ps
CPU time 1.3 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:23 PM PDT 24
Peak memory 200508 kb
Host smart-bb94eff2-5e7d-4ac7-bd62-462d8acd1622
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263143788 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.4263143788
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.4057183415
Short name T322
Test name
Test status
Simulation time 244073013620 ps
CPU time 540.19 seconds
Started May 19 01:16:21 PM PDT 24
Finished May 19 01:25:24 PM PDT 24
Peak memory 200676 kb
Host smart-b95fd6ce-e632-4d26-b7cb-1ba93a046e2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057183415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.4057183415
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.345159505
Short name T411
Test name
Test status
Simulation time 27820013 ps
CPU time 0.61 seconds
Started May 19 01:16:23 PM PDT 24
Finished May 19 01:16:27 PM PDT 24
Peak memory 196348 kb
Host smart-c0943e1d-0fbd-42a7-8fb6-e935864f71b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345159505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.345159505
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.564260688
Short name T279
Test name
Test status
Simulation time 42774021 ps
CPU time 2.32 seconds
Started May 19 01:16:21 PM PDT 24
Finished May 19 01:16:26 PM PDT 24
Peak memory 200288 kb
Host smart-e3d2fe3d-2f73-462a-a948-154e8273e942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564260688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.564260688
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1708489624
Short name T473
Test name
Test status
Simulation time 2111364109 ps
CPU time 43.69 seconds
Started May 19 01:16:22 PM PDT 24
Finished May 19 01:17:09 PM PDT 24
Peak memory 200872 kb
Host smart-47c7fd5c-d998-40e2-b7a0-661c8502ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708489624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1708489624
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.661567490
Short name T323
Test name
Test status
Simulation time 3443357633 ps
CPU time 1141.78 seconds
Started May 19 01:16:27 PM PDT 24
Finished May 19 01:35:30 PM PDT 24
Peak memory 725292 kb
Host smart-4159cec4-3b7f-469e-9424-5b3d98953fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661567490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.661567490
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1057048369
Short name T418
Test name
Test status
Simulation time 24489209019 ps
CPU time 91.34 seconds
Started May 19 01:16:27 PM PDT 24
Finished May 19 01:18:00 PM PDT 24
Peak memory 200684 kb
Host smart-62c19c61-75ec-4776-97cd-3015aae77d9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057048369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1057048369
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2765125371
Short name T437
Test name
Test status
Simulation time 4040080346 ps
CPU time 15.36 seconds
Started May 19 01:16:24 PM PDT 24
Finished May 19 01:16:42 PM PDT 24
Peak memory 200772 kb
Host smart-aa079962-0265-4011-9d8a-666dfa6f08a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765125371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2765125371
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3559695955
Short name T415
Test name
Test status
Simulation time 214743175 ps
CPU time 3.3 seconds
Started May 19 01:16:22 PM PDT 24
Finished May 19 01:16:28 PM PDT 24
Peak memory 200604 kb
Host smart-d8645745-ec75-4905-a098-0666952d83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559695955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3559695955
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.92110547
Short name T203
Test name
Test status
Simulation time 27265552 ps
CPU time 0.95 seconds
Started May 19 01:16:24 PM PDT 24
Finished May 19 01:16:27 PM PDT 24
Peak memory 199220 kb
Host smart-6c5be6be-e340-43a2-8ab0-4e6a2bc19e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92110547 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_test_hmac_vectors.92110547
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1638897869
Short name T315
Test name
Test status
Simulation time 289515847193 ps
CPU time 546.01 seconds
Started May 19 01:16:23 PM PDT 24
Finished May 19 01:25:32 PM PDT 24
Peak memory 200620 kb
Host smart-b2c93dbc-0438-4b70-9720-bc2c2e2e3992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638897869 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1638897869
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3018937982
Short name T388
Test name
Test status
Simulation time 47670072 ps
CPU time 0.6 seconds
Started May 19 01:16:28 PM PDT 24
Finished May 19 01:16:30 PM PDT 24
Peak memory 197092 kb
Host smart-3b7b583d-ede2-48e6-99bb-27e6c55402eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018937982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3018937982
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.983521775
Short name T125
Test name
Test status
Simulation time 5215670200 ps
CPU time 69.06 seconds
Started May 19 01:16:25 PM PDT 24
Finished May 19 01:17:36 PM PDT 24
Peak memory 233452 kb
Host smart-579e7b7c-1a93-43b2-a841-ea2585850428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983521775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.983521775
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1591246870
Short name T331
Test name
Test status
Simulation time 4551359733 ps
CPU time 43.56 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:17:05 PM PDT 24
Peak memory 200720 kb
Host smart-cc2f0352-6732-4e1a-bb46-30cf877ff51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591246870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1591246870
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3168162070
Short name T393
Test name
Test status
Simulation time 4836989364 ps
CPU time 33.27 seconds
Started May 19 01:16:24 PM PDT 24
Finished May 19 01:17:00 PM PDT 24
Peak memory 242144 kb
Host smart-9012ff3a-7925-45c2-93f4-bb40103b5f5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168162070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3168162070
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1135954572
Short name T290
Test name
Test status
Simulation time 4426639636 ps
CPU time 37.8 seconds
Started May 19 01:16:22 PM PDT 24
Finished May 19 01:17:03 PM PDT 24
Peak memory 200628 kb
Host smart-b5803d38-394b-41ed-b540-28a6f6d51217
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135954572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1135954572
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1056821542
Short name T427
Test name
Test status
Simulation time 1819409259 ps
CPU time 33.96 seconds
Started May 19 01:16:25 PM PDT 24
Finished May 19 01:17:01 PM PDT 24
Peak memory 200600 kb
Host smart-d108aee8-67d9-4bfb-a180-dadbc2823f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056821542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1056821542
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1944217392
Short name T407
Test name
Test status
Simulation time 381960150 ps
CPU time 6.04 seconds
Started May 19 01:16:22 PM PDT 24
Finished May 19 01:16:31 PM PDT 24
Peak memory 200596 kb
Host smart-c5ee007f-025e-47d5-b46f-d58bdee62ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944217392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1944217392
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2957488074
Short name T397
Test name
Test status
Simulation time 137047174 ps
CPU time 1.05 seconds
Started May 19 01:16:20 PM PDT 24
Finished May 19 01:16:22 PM PDT 24
Peak memory 200224 kb
Host smart-bdfca823-9aa3-49fa-bbba-d8c4e5fdc0c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957488074 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2957488074
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3293918123
Short name T142
Test name
Test status
Simulation time 26851763850 ps
CPU time 483.25 seconds
Started May 19 01:16:23 PM PDT 24
Finished May 19 01:24:29 PM PDT 24
Peak memory 200632 kb
Host smart-e2f41d41-354d-4907-8cb3-d92689927c20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293918123 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3293918123
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4070813775
Short name T324
Test name
Test status
Simulation time 21041596 ps
CPU time 0.57 seconds
Started May 19 01:16:28 PM PDT 24
Finished May 19 01:16:30 PM PDT 24
Peak memory 197112 kb
Host smart-3af63a15-1d1a-4810-a450-4685fdd1d8a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070813775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4070813775
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4019341960
Short name T436
Test name
Test status
Simulation time 1975042481 ps
CPU time 66.48 seconds
Started May 19 01:16:27 PM PDT 24
Finished May 19 01:17:36 PM PDT 24
Peak memory 241112 kb
Host smart-2f76cfcb-a86c-4daf-9636-be044c89e800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019341960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4019341960
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2440959129
Short name T29
Test name
Test status
Simulation time 230105329 ps
CPU time 10.53 seconds
Started May 19 01:16:27 PM PDT 24
Finished May 19 01:16:39 PM PDT 24
Peak memory 200576 kb
Host smart-37ebe1e7-a5ce-4312-903a-5e0bf8708795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440959129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2440959129
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3712542692
Short name T89
Test name
Test status
Simulation time 6572125763 ps
CPU time 821.33 seconds
Started May 19 01:16:29 PM PDT 24
Finished May 19 01:30:12 PM PDT 24
Peak memory 735992 kb
Host smart-d05840b1-a677-4990-bc19-c5ccbbccb380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712542692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3712542692
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2502859495
Short name T227
Test name
Test status
Simulation time 2526461099 ps
CPU time 29.93 seconds
Started May 19 01:16:26 PM PDT 24
Finished May 19 01:16:58 PM PDT 24
Peak memory 200476 kb
Host smart-9f94c18d-d42c-43eb-b1e7-0aa1c228d19a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502859495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2502859495
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2259739599
Short name T172
Test name
Test status
Simulation time 442302076 ps
CPU time 13.52 seconds
Started May 19 01:16:25 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 200604 kb
Host smart-513604df-945d-467e-9f67-95ac9def86fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259739599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2259739599
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1803847367
Short name T188
Test name
Test status
Simulation time 686773321 ps
CPU time 7.85 seconds
Started May 19 01:16:28 PM PDT 24
Finished May 19 01:16:37 PM PDT 24
Peak memory 200604 kb
Host smart-92c04c33-f8f3-4bb6-abf2-3622ce771cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803847367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1803847367
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3861750082
Short name T406
Test name
Test status
Simulation time 28295208 ps
CPU time 1 seconds
Started May 19 01:16:27 PM PDT 24
Finished May 19 01:16:30 PM PDT 24
Peak memory 199380 kb
Host smart-56c7ad6c-e035-4c4b-a0f5-dc13bd3280b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861750082 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3861750082
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2395862995
Short name T402
Test name
Test status
Simulation time 14217312686 ps
CPU time 416.13 seconds
Started May 19 01:16:27 PM PDT 24
Finished May 19 01:23:25 PM PDT 24
Peak memory 200660 kb
Host smart-fea63597-45fa-468f-9418-d7f490543136
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395862995 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.2395862995
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3039292237
Short name T421
Test name
Test status
Simulation time 42801537 ps
CPU time 0.66 seconds
Started May 19 01:16:28 PM PDT 24
Finished May 19 01:16:30 PM PDT 24
Peak memory 196332 kb
Host smart-f8ac73bb-dbed-436a-b06f-0835aa6186fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039292237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3039292237
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1850889014
Short name T435
Test name
Test status
Simulation time 560695499 ps
CPU time 32.97 seconds
Started May 19 01:16:28 PM PDT 24
Finished May 19 01:17:02 PM PDT 24
Peak memory 223392 kb
Host smart-144889ce-6c5c-4658-ba85-83fb72cb6b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850889014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1850889014
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1602679395
Short name T319
Test name
Test status
Simulation time 968398382 ps
CPU time 6.59 seconds
Started May 19 01:16:26 PM PDT 24
Finished May 19 01:16:35 PM PDT 24
Peak memory 200508 kb
Host smart-73539b27-477c-4578-8ca2-9444c60bb157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602679395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1602679395
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2064502641
Short name T95
Test name
Test status
Simulation time 1912895298 ps
CPU time 524.88 seconds
Started May 19 01:16:27 PM PDT 24
Finished May 19 01:25:13 PM PDT 24
Peak memory 718820 kb
Host smart-a6595668-263a-45e4-9db8-492b44a56012
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064502641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2064502641
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1773102514
Short name T194
Test name
Test status
Simulation time 2185512029 ps
CPU time 64.6 seconds
Started May 19 01:16:26 PM PDT 24
Finished May 19 01:17:33 PM PDT 24
Peak memory 200724 kb
Host smart-36c4dc1f-2756-4068-877d-0151e00b7d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773102514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1773102514
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.4157227320
Short name T360
Test name
Test status
Simulation time 49005631 ps
CPU time 1.79 seconds
Started May 19 01:16:29 PM PDT 24
Finished May 19 01:16:32 PM PDT 24
Peak memory 200576 kb
Host smart-3c6c74fd-994f-4751-8d43-6f32e25b6bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157227320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.4157227320
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.130913824
Short name T156
Test name
Test status
Simulation time 712970707 ps
CPU time 0.97 seconds
Started May 19 01:16:26 PM PDT 24
Finished May 19 01:16:29 PM PDT 24
Peak memory 200140 kb
Host smart-c802ed48-7071-40c3-8433-c3df3e4def80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130913824 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.130913824
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2342621832
Short name T255
Test name
Test status
Simulation time 23546540030 ps
CPU time 442.99 seconds
Started May 19 01:16:26 PM PDT 24
Finished May 19 01:23:51 PM PDT 24
Peak memory 200596 kb
Host smart-1b7d681f-654b-4f83-83b8-df2ea63cf8b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342621832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.2342621832
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2159440086
Short name T262
Test name
Test status
Simulation time 16018094 ps
CPU time 0.61 seconds
Started May 19 01:16:33 PM PDT 24
Finished May 19 01:16:35 PM PDT 24
Peak memory 196336 kb
Host smart-b240ee18-3279-4145-9dd1-40bf9e14fb33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159440086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2159440086
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1126880425
Short name T275
Test name
Test status
Simulation time 162202575 ps
CPU time 2.11 seconds
Started May 19 01:16:33 PM PDT 24
Finished May 19 01:16:37 PM PDT 24
Peak memory 200540 kb
Host smart-6ad60be5-f0b3-45bd-b98e-a6e4ee606ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126880425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1126880425
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1059425323
Short name T467
Test name
Test status
Simulation time 2685096390 ps
CPU time 51.07 seconds
Started May 19 01:16:34 PM PDT 24
Finished May 19 01:17:26 PM PDT 24
Peak memory 200616 kb
Host smart-3aff259f-52c2-49dd-9a7c-383f28ba7491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059425323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1059425323
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2899040815
Short name T311
Test name
Test status
Simulation time 7057329584 ps
CPU time 996.16 seconds
Started May 19 01:16:37 PM PDT 24
Finished May 19 01:33:14 PM PDT 24
Peak memory 750368 kb
Host smart-5c3023bd-21fd-414a-aaeb-df41ee2b2c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899040815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2899040815
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4249358053
Short name T449
Test name
Test status
Simulation time 14632965532 ps
CPU time 68.44 seconds
Started May 19 01:16:33 PM PDT 24
Finished May 19 01:17:42 PM PDT 24
Peak memory 200692 kb
Host smart-f28eccc5-c483-46f2-aaa9-26e4565f3085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249358053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4249358053
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3009523999
Short name T206
Test name
Test status
Simulation time 314120225 ps
CPU time 5.22 seconds
Started May 19 01:16:36 PM PDT 24
Finished May 19 01:16:42 PM PDT 24
Peak memory 200584 kb
Host smart-e337f889-3a11-47b6-8a23-25f34e2686bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009523999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3009523999
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2603544311
Short name T205
Test name
Test status
Simulation time 152387981 ps
CPU time 1.05 seconds
Started May 19 01:16:35 PM PDT 24
Finished May 19 01:16:37 PM PDT 24
Peak memory 199928 kb
Host smart-04c55cfa-239e-42fa-a61c-25904a1448f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603544311 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2603544311
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3263765821
Short name T167
Test name
Test status
Simulation time 43964569672 ps
CPU time 583.16 seconds
Started May 19 01:16:32 PM PDT 24
Finished May 19 01:26:17 PM PDT 24
Peak memory 200648 kb
Host smart-ce938754-2286-4f35-9182-f4a13374289d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263765821 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3263765821
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4075058883
Short name T344
Test name
Test status
Simulation time 370113481 ps
CPU time 5.79 seconds
Started May 19 01:16:32 PM PDT 24
Finished May 19 01:16:38 PM PDT 24
Peak memory 200404 kb
Host smart-99e0cd31-a4da-43e9-b117-d73d0c0d9e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075058883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4075058883
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3427010153
Short name T173
Test name
Test status
Simulation time 43863996 ps
CPU time 0.56 seconds
Started May 19 01:15:10 PM PDT 24
Finished May 19 01:15:28 PM PDT 24
Peak memory 196292 kb
Host smart-53796335-d099-4f78-ba29-10217deebda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427010153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3427010153
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2342011601
Short name T472
Test name
Test status
Simulation time 1208266236 ps
CPU time 9.4 seconds
Started May 19 01:15:05 PM PDT 24
Finished May 19 01:15:33 PM PDT 24
Peak memory 208956 kb
Host smart-fb425578-4363-45fb-bbde-24641ccc3139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342011601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2342011601
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2854920610
Short name T306
Test name
Test status
Simulation time 2891476747 ps
CPU time 43.36 seconds
Started May 19 01:15:11 PM PDT 24
Finished May 19 01:16:11 PM PDT 24
Peak memory 200720 kb
Host smart-8333d14c-5511-4da5-86f8-816405c4224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854920610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2854920610
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2950248959
Short name T232
Test name
Test status
Simulation time 2458680345 ps
CPU time 606.68 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:25:39 PM PDT 24
Peak memory 695752 kb
Host smart-3cbb3943-288e-42ce-aa0c-ecb4c0000aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950248959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2950248959
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1849456237
Short name T186
Test name
Test status
Simulation time 7859262285 ps
CPU time 109.51 seconds
Started May 19 01:15:04 PM PDT 24
Finished May 19 01:17:13 PM PDT 24
Peak memory 200660 kb
Host smart-c8807817-2479-43ca-abd1-522cf8dd1f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849456237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1849456237
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.2531089829
Short name T367
Test name
Test status
Simulation time 190078777 ps
CPU time 2.94 seconds
Started May 19 01:15:05 PM PDT 24
Finished May 19 01:15:26 PM PDT 24
Peak memory 200564 kb
Host smart-250c9950-9916-44cc-8f1b-48245ca41fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531089829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2531089829
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.480982410
Short name T469
Test name
Test status
Simulation time 192828477 ps
CPU time 1.29 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:15:33 PM PDT 24
Peak memory 200488 kb
Host smart-cd851374-f248-4c32-bb93-7239cf864048
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480982410 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.480982410
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3055272309
Short name T420
Test name
Test status
Simulation time 17806445837 ps
CPU time 521.45 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:24:14 PM PDT 24
Peak memory 200644 kb
Host smart-236522d4-4e94-4aa8-8727-c9b37d50a1e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055272309 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3055272309
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3393632375
Short name T283
Test name
Test status
Simulation time 10953562 ps
CPU time 0.6 seconds
Started May 19 01:16:35 PM PDT 24
Finished May 19 01:16:36 PM PDT 24
Peak memory 195940 kb
Host smart-00fa2bfa-8526-4a31-bf86-b2d01fb55f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393632375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3393632375
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.775373950
Short name T130
Test name
Test status
Simulation time 4385306062 ps
CPU time 24.82 seconds
Started May 19 01:16:33 PM PDT 24
Finished May 19 01:17:00 PM PDT 24
Peak memory 216728 kb
Host smart-d740e2b8-8813-4c6c-baf8-a59a15d5cb8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775373950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.775373950
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1772143660
Short name T379
Test name
Test status
Simulation time 11172059595 ps
CPU time 759.35 seconds
Started May 19 01:16:34 PM PDT 24
Finished May 19 01:29:15 PM PDT 24
Peak memory 765796 kb
Host smart-f47324d1-1377-4866-8cc3-7c322c9054cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772143660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1772143660
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.166256863
Short name T18
Test name
Test status
Simulation time 3133151585 ps
CPU time 19.5 seconds
Started May 19 01:16:35 PM PDT 24
Finished May 19 01:16:55 PM PDT 24
Peak memory 200776 kb
Host smart-58713567-2d9b-4847-b1a4-8d5167c20c4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166256863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.166256863
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.765958294
Short name T378
Test name
Test status
Simulation time 3209736563 ps
CPU time 58.78 seconds
Started May 19 01:16:36 PM PDT 24
Finished May 19 01:17:35 PM PDT 24
Peak memory 200676 kb
Host smart-a2b6dd8e-c670-41c8-8c45-3875ce8ca676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765958294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.765958294
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.454179265
Short name T246
Test name
Test status
Simulation time 460435008 ps
CPU time 7.65 seconds
Started May 19 01:16:38 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 200632 kb
Host smart-526df685-a684-4443-bc9c-e6ad6950c921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454179265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.454179265
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3436085605
Short name T141
Test name
Test status
Simulation time 50413276 ps
CPU time 1.04 seconds
Started May 19 01:16:36 PM PDT 24
Finished May 19 01:16:38 PM PDT 24
Peak memory 200012 kb
Host smart-47da688f-1dc5-4348-850b-4f2863e8883e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436085605 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3436085605
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2904871938
Short name T177
Test name
Test status
Simulation time 44814476829 ps
CPU time 396.84 seconds
Started May 19 01:16:33 PM PDT 24
Finished May 19 01:23:11 PM PDT 24
Peak memory 200600 kb
Host smart-98ec3f61-746b-4c84-936a-c12cdb2ca018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904871938 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2904871938
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3995724229
Short name T301
Test name
Test status
Simulation time 14576805 ps
CPU time 0.61 seconds
Started May 19 01:16:42 PM PDT 24
Finished May 19 01:16:45 PM PDT 24
Peak memory 196376 kb
Host smart-3db27d8f-599d-4281-9416-da3c087d5edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995724229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3995724229
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1571498145
Short name T327
Test name
Test status
Simulation time 379208776 ps
CPU time 20.97 seconds
Started May 19 01:16:34 PM PDT 24
Finished May 19 01:16:56 PM PDT 24
Peak memory 220084 kb
Host smart-f49efaeb-0349-4d3e-9cee-bb1576ef863a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571498145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1571498145
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2432979038
Short name T446
Test name
Test status
Simulation time 4833626461 ps
CPU time 36.43 seconds
Started May 19 01:16:38 PM PDT 24
Finished May 19 01:17:16 PM PDT 24
Peak memory 200712 kb
Host smart-83832f1d-2c66-4a8b-b79a-229ee0bff245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432979038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2432979038
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.384960063
Short name T365
Test name
Test status
Simulation time 7278422816 ps
CPU time 506.49 seconds
Started May 19 01:16:36 PM PDT 24
Finished May 19 01:25:04 PM PDT 24
Peak memory 705552 kb
Host smart-b662cbac-b5ee-455e-a777-0f4b0c229542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=384960063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.384960063
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2411305483
Short name T248
Test name
Test status
Simulation time 28213156836 ps
CPU time 78.25 seconds
Started May 19 01:16:33 PM PDT 24
Finished May 19 01:17:52 PM PDT 24
Peak memory 200700 kb
Host smart-ba0593e4-64cf-4732-8f75-062f8182a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411305483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2411305483
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1779900546
Short name T251
Test name
Test status
Simulation time 4603162691 ps
CPU time 3.65 seconds
Started May 19 01:16:36 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 200712 kb
Host smart-70022c0f-b1df-4cc5-be98-a6929687ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779900546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1779900546
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3765340042
Short name T40
Test name
Test status
Simulation time 41391215 ps
CPU time 1.02 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 199988 kb
Host smart-2f5015b0-a4f0-4bfa-85e8-10d92d8a92c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765340042 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3765340042
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.180455962
Short name T334
Test name
Test status
Simulation time 18242386209 ps
CPU time 479.12 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:24:40 PM PDT 24
Peak memory 200624 kb
Host smart-fc3afac7-cec4-42b9-9b74-f8a7ea8ada74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180455962 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.180455962
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4180940801
Short name T8
Test name
Test status
Simulation time 14915237 ps
CPU time 0.61 seconds
Started May 19 01:16:42 PM PDT 24
Finished May 19 01:16:45 PM PDT 24
Peak memory 196864 kb
Host smart-b56b01e1-0d26-4472-ba8f-47e00f176cf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180940801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4180940801
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.172167304
Short name T377
Test name
Test status
Simulation time 560306944 ps
CPU time 6.18 seconds
Started May 19 01:16:40 PM PDT 24
Finished May 19 01:16:47 PM PDT 24
Peak memory 216500 kb
Host smart-d9c9fe4b-6e98-42c3-9656-afe5435d79f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172167304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.172167304
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2003212958
Short name T404
Test name
Test status
Simulation time 1478090733 ps
CPU time 30.52 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:17:11 PM PDT 24
Peak memory 200540 kb
Host smart-4eba4384-8918-4f7c-9fbc-c78f7db0bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003212958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2003212958
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4282191329
Short name T269
Test name
Test status
Simulation time 13231969101 ps
CPU time 273.16 seconds
Started May 19 01:16:40 PM PDT 24
Finished May 19 01:21:15 PM PDT 24
Peak memory 613456 kb
Host smart-8f8ec2a7-a4e2-4a0e-ae40-f7ca11bad998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282191329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4282191329
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1233864394
Short name T441
Test name
Test status
Simulation time 4281391089 ps
CPU time 82.63 seconds
Started May 19 01:16:40 PM PDT 24
Finished May 19 01:18:04 PM PDT 24
Peak memory 200704 kb
Host smart-0dfa8437-f4ab-4a39-b36b-40e384f86110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233864394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1233864394
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4140491478
Short name T341
Test name
Test status
Simulation time 2110126212 ps
CPU time 6.5 seconds
Started May 19 01:16:44 PM PDT 24
Finished May 19 01:16:52 PM PDT 24
Peak memory 200640 kb
Host smart-93bd3b38-0f01-40cd-ac26-65258502d420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140491478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4140491478
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3341437478
Short name T199
Test name
Test status
Simulation time 28200538 ps
CPU time 1.07 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:16:41 PM PDT 24
Peak memory 200628 kb
Host smart-a4302ef2-8610-4642-94c4-6e831e7eaeb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341437478 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3341437478
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2324210705
Short name T196
Test name
Test status
Simulation time 15230437379 ps
CPU time 460.39 seconds
Started May 19 01:16:40 PM PDT 24
Finished May 19 01:24:22 PM PDT 24
Peak memory 200556 kb
Host smart-8b5b1cc5-7d25-43b3-b513-cf4e1c3502ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324210705 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2324210705
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1244887238
Short name T147
Test name
Test status
Simulation time 41077687 ps
CPU time 0.57 seconds
Started May 19 01:16:40 PM PDT 24
Finished May 19 01:16:43 PM PDT 24
Peak memory 195304 kb
Host smart-3760c229-3b96-43bb-b6f4-4a100771e257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244887238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1244887238
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3810794397
Short name T158
Test name
Test status
Simulation time 990074676 ps
CPU time 49.5 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:17:30 PM PDT 24
Peak memory 208764 kb
Host smart-da291237-0ad8-4ffa-b2dc-c8d98f1cc54d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810794397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3810794397
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2218727302
Short name T96
Test name
Test status
Simulation time 3010353981 ps
CPU time 56.75 seconds
Started May 19 01:16:40 PM PDT 24
Finished May 19 01:17:38 PM PDT 24
Peak memory 200644 kb
Host smart-4fa2b71d-b983-4462-8351-5969f53b9b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218727302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2218727302
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3491683576
Short name T264
Test name
Test status
Simulation time 5137818048 ps
CPU time 604.86 seconds
Started May 19 01:16:38 PM PDT 24
Finished May 19 01:26:44 PM PDT 24
Peak memory 665128 kb
Host smart-5be46309-da09-4edf-b0ea-0fddb5c48d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491683576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3491683576
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.488556935
Short name T442
Test name
Test status
Simulation time 3574957445 ps
CPU time 46.15 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:17:26 PM PDT 24
Peak memory 200720 kb
Host smart-b1dabe8a-582e-4825-91c5-d10d27f182b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488556935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.488556935
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1511041950
Short name T274
Test name
Test status
Simulation time 169759718 ps
CPU time 2.8 seconds
Started May 19 01:16:42 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 200584 kb
Host smart-096571be-faeb-4910-a17e-020e6aad0f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511041950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1511041950
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1990335703
Short name T43
Test name
Test status
Simulation time 34448077 ps
CPU time 1.35 seconds
Started May 19 01:16:44 PM PDT 24
Finished May 19 01:16:47 PM PDT 24
Peak memory 200492 kb
Host smart-baa6ccf5-2711-47b5-9fdd-b09e8ad776b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990335703 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1990335703
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2484955045
Short name T296
Test name
Test status
Simulation time 57160291233 ps
CPU time 506.8 seconds
Started May 19 01:16:41 PM PDT 24
Finished May 19 01:25:09 PM PDT 24
Peak memory 200572 kb
Host smart-65f87f39-fe06-4795-90a3-1d50741b5064
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484955045 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2484955045
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.582822145
Short name T434
Test name
Test status
Simulation time 14132036 ps
CPU time 0.61 seconds
Started May 19 01:16:44 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 196020 kb
Host smart-85484481-cfcf-43b6-a713-38518a91dc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582822145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.582822145
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.481008780
Short name T412
Test name
Test status
Simulation time 258679575 ps
CPU time 3.51 seconds
Started May 19 01:16:43 PM PDT 24
Finished May 19 01:16:48 PM PDT 24
Peak memory 200556 kb
Host smart-a0d49e00-9f28-4840-a7fe-cea19c0aea07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481008780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.481008780
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.110125304
Short name T444
Test name
Test status
Simulation time 1232735604 ps
CPU time 22.97 seconds
Started May 19 01:16:41 PM PDT 24
Finished May 19 01:17:05 PM PDT 24
Peak memory 200608 kb
Host smart-e46e8269-6ba8-42c4-870c-1717d98a9e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110125304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.110125304
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.694315043
Short name T294
Test name
Test status
Simulation time 12334663904 ps
CPU time 214.75 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:20:15 PM PDT 24
Peak memory 460056 kb
Host smart-d6026dbf-8e2b-444a-906b-933610802023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694315043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.694315043
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.897528384
Short name T350
Test name
Test status
Simulation time 5975085570 ps
CPU time 56.2 seconds
Started May 19 01:16:42 PM PDT 24
Finished May 19 01:17:41 PM PDT 24
Peak memory 200716 kb
Host smart-34bc473c-110b-4b59-95a2-3cd47c5a702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897528384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.897528384
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3029370219
Short name T338
Test name
Test status
Simulation time 385786634 ps
CPU time 1.6 seconds
Started May 19 01:16:39 PM PDT 24
Finished May 19 01:16:42 PM PDT 24
Peak memory 200564 kb
Host smart-0aad73ce-c46d-4c01-9b4e-a26627428892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029370219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3029370219
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3008769100
Short name T253
Test name
Test status
Simulation time 31442779 ps
CPU time 1.02 seconds
Started May 19 01:16:45 PM PDT 24
Finished May 19 01:16:48 PM PDT 24
Peak memory 199832 kb
Host smart-2769202a-2250-4922-8873-5843dd2c302b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008769100 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3008769100
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.15815440
Short name T244
Test name
Test status
Simulation time 35286094724 ps
CPU time 452.71 seconds
Started May 19 01:16:42 PM PDT 24
Finished May 19 01:24:17 PM PDT 24
Peak memory 200324 kb
Host smart-2b9f608f-7733-4eb0-8182-1c82465586e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15815440 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.15815440
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3759474941
Short name T260
Test name
Test status
Simulation time 11697653 ps
CPU time 0.6 seconds
Started May 19 01:16:43 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 196328 kb
Host smart-0cbf54dd-10a8-4f4b-91bc-487f75fc8a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759474941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3759474941
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.692014642
Short name T128
Test name
Test status
Simulation time 2827581970 ps
CPU time 40.78 seconds
Started May 19 01:16:44 PM PDT 24
Finished May 19 01:17:26 PM PDT 24
Peak memory 208912 kb
Host smart-60aba153-d608-459f-b853-9aac56d2b95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692014642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.692014642
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1509927167
Short name T316
Test name
Test status
Simulation time 46705047 ps
CPU time 2.18 seconds
Started May 19 01:16:47 PM PDT 24
Finished May 19 01:16:50 PM PDT 24
Peak memory 200568 kb
Host smart-83cefd03-dc1f-4ee7-b224-f1576d57e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509927167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1509927167
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2318431532
Short name T12
Test name
Test status
Simulation time 10395530696 ps
CPU time 398.36 seconds
Started May 19 01:16:45 PM PDT 24
Finished May 19 01:23:25 PM PDT 24
Peak memory 649212 kb
Host smart-d128bb24-1003-4b08-b529-71ee24bcb321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318431532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2318431532
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3019771976
Short name T424
Test name
Test status
Simulation time 6101610815 ps
CPU time 68.96 seconds
Started May 19 01:16:44 PM PDT 24
Finished May 19 01:17:55 PM PDT 24
Peak memory 200756 kb
Host smart-980f9814-2dd5-4807-bca1-60a1418429a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019771976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3019771976
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2753457288
Short name T321
Test name
Test status
Simulation time 9283483309 ps
CPU time 39.74 seconds
Started May 19 01:16:43 PM PDT 24
Finished May 19 01:17:24 PM PDT 24
Peak memory 200676 kb
Host smart-ada7db41-7a73-4827-8882-1707f6b51f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753457288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2753457288
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2850097402
Short name T438
Test name
Test status
Simulation time 579398701 ps
CPU time 7.26 seconds
Started May 19 01:16:43 PM PDT 24
Finished May 19 01:16:52 PM PDT 24
Peak memory 200652 kb
Host smart-a474f60b-ad40-4e2d-a92b-5a6bf47e7228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850097402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2850097402
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1033749508
Short name T143
Test name
Test status
Simulation time 74637110 ps
CPU time 1.3 seconds
Started May 19 01:16:43 PM PDT 24
Finished May 19 01:16:46 PM PDT 24
Peak memory 200824 kb
Host smart-f209d049-6dfb-4f09-b432-fd17b7aef747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033749508 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1033749508
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3990344646
Short name T395
Test name
Test status
Simulation time 8650803112 ps
CPU time 494.29 seconds
Started May 19 01:16:43 PM PDT 24
Finished May 19 01:24:59 PM PDT 24
Peak memory 200620 kb
Host smart-3f4f14bc-c3eb-4e31-a35d-dab55d0708eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990344646 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3990344646
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2902554855
Short name T212
Test name
Test status
Simulation time 36061300 ps
CPU time 0.59 seconds
Started May 19 01:16:50 PM PDT 24
Finished May 19 01:16:52 PM PDT 24
Peak memory 196364 kb
Host smart-d41df483-2483-41be-8282-50b354aa2949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902554855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2902554855
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1726655017
Short name T295
Test name
Test status
Simulation time 1129303741 ps
CPU time 64.4 seconds
Started May 19 01:16:44 PM PDT 24
Finished May 19 01:17:50 PM PDT 24
Peak memory 218532 kb
Host smart-3d850bc4-39b8-4aad-8d98-6356395d026b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726655017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1726655017
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1313637953
Short name T433
Test name
Test status
Simulation time 695357336 ps
CPU time 35.14 seconds
Started May 19 01:16:52 PM PDT 24
Finished May 19 01:17:29 PM PDT 24
Peak memory 200600 kb
Host smart-79c3dd8b-c480-4a54-a08a-0cb6a7a49fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313637953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1313637953
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3176795043
Short name T233
Test name
Test status
Simulation time 997673702 ps
CPU time 212.9 seconds
Started May 19 01:16:52 PM PDT 24
Finished May 19 01:20:26 PM PDT 24
Peak memory 599708 kb
Host smart-3f6629fb-ef79-4de6-9d7b-07191cbfc99a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176795043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3176795043
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3842153331
Short name T132
Test name
Test status
Simulation time 669983264 ps
CPU time 39.73 seconds
Started May 19 01:16:43 PM PDT 24
Finished May 19 01:17:25 PM PDT 24
Peak memory 200600 kb
Host smart-9fa6e160-b2d6-413f-ae0d-2ab6a0e31722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842153331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3842153331
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1355139786
Short name T372
Test name
Test status
Simulation time 2592459080 ps
CPU time 2.91 seconds
Started May 19 01:16:45 PM PDT 24
Finished May 19 01:16:49 PM PDT 24
Peak memory 200712 kb
Host smart-76f8bd7d-68a5-4400-a88c-35c7359f755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355139786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1355139786
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2901935199
Short name T475
Test name
Test status
Simulation time 66267069 ps
CPU time 1.19 seconds
Started May 19 01:16:53 PM PDT 24
Finished May 19 01:16:55 PM PDT 24
Peak memory 200620 kb
Host smart-27e7ba31-e772-4af0-83fe-982b3bd0f9a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901935199 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2901935199
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.4289080525
Short name T318
Test name
Test status
Simulation time 30779687553 ps
CPU time 442.25 seconds
Started May 19 01:16:56 PM PDT 24
Finished May 19 01:24:20 PM PDT 24
Peak memory 200692 kb
Host smart-260fdefe-e84b-41ae-aea9-dec20034babf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289080525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.4289080525
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1698243568
Short name T384
Test name
Test status
Simulation time 24002934 ps
CPU time 0.58 seconds
Started May 19 01:16:54 PM PDT 24
Finished May 19 01:16:56 PM PDT 24
Peak memory 195368 kb
Host smart-5ea36f99-91a1-4645-9f86-6ca3dd528bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698243568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1698243568
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1254343077
Short name T390
Test name
Test status
Simulation time 1551945226 ps
CPU time 69.44 seconds
Started May 19 01:16:52 PM PDT 24
Finished May 19 01:18:02 PM PDT 24
Peak memory 233320 kb
Host smart-bcb01a56-b37f-4d0c-afa6-3e8a9d1db0e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254343077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1254343077
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1382930681
Short name T369
Test name
Test status
Simulation time 689835058 ps
CPU time 40.04 seconds
Started May 19 01:16:52 PM PDT 24
Finished May 19 01:17:33 PM PDT 24
Peak memory 200772 kb
Host smart-deb04a72-ae9a-43cb-a7a5-f24a0f6ebe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382930681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1382930681
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1452117906
Short name T98
Test name
Test status
Simulation time 8304029893 ps
CPU time 1294.37 seconds
Started May 19 01:16:51 PM PDT 24
Finished May 19 01:38:27 PM PDT 24
Peak memory 750000 kb
Host smart-67710fad-2733-4760-9c4c-f420c18c92ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452117906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1452117906
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2824704572
Short name T383
Test name
Test status
Simulation time 1821284550 ps
CPU time 110.17 seconds
Started May 19 01:16:51 PM PDT 24
Finished May 19 01:18:42 PM PDT 24
Peak memory 200624 kb
Host smart-9a7e7731-4da9-4c6f-8153-f06b9678fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824704572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2824704572
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.12440800
Short name T133
Test name
Test status
Simulation time 99095674 ps
CPU time 3.48 seconds
Started May 19 01:16:50 PM PDT 24
Finished May 19 01:16:54 PM PDT 24
Peak memory 200564 kb
Host smart-4fa3522c-f784-49c4-8e33-ca01372c395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12440800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.12440800
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3312820461
Short name T241
Test name
Test status
Simulation time 152972188 ps
CPU time 1.04 seconds
Started May 19 01:16:53 PM PDT 24
Finished May 19 01:16:55 PM PDT 24
Peak memory 200012 kb
Host smart-fa6020e9-de31-43cc-8c5e-1f87d9f8e4e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312820461 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3312820461
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1668197845
Short name T238
Test name
Test status
Simulation time 32008912430 ps
CPU time 443.72 seconds
Started May 19 01:16:53 PM PDT 24
Finished May 19 01:24:18 PM PDT 24
Peak memory 200640 kb
Host smart-e69f2d65-366b-4931-b8a6-b242ed4fb228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668197845 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1668197845
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3394731117
Short name T330
Test name
Test status
Simulation time 12062213 ps
CPU time 0.6 seconds
Started May 19 01:16:57 PM PDT 24
Finished May 19 01:16:59 PM PDT 24
Peak memory 196336 kb
Host smart-1bdc61f9-f895-4753-a0dd-3cf80468c130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394731117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3394731117
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3552726876
Short name T414
Test name
Test status
Simulation time 3214185848 ps
CPU time 14.11 seconds
Started May 19 01:16:54 PM PDT 24
Finished May 19 01:17:10 PM PDT 24
Peak memory 200736 kb
Host smart-a2067e9b-5210-4e18-bad3-9862eecaee33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552726876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3552726876
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1019940905
Short name T431
Test name
Test status
Simulation time 6540936581 ps
CPU time 19.82 seconds
Started May 19 01:16:57 PM PDT 24
Finished May 19 01:17:18 PM PDT 24
Peak memory 200600 kb
Host smart-e48eb734-3acd-4b2b-9a22-8be609534e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019940905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1019940905
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3751675855
Short name T470
Test name
Test status
Simulation time 2032493182 ps
CPU time 590.45 seconds
Started May 19 01:16:56 PM PDT 24
Finished May 19 01:26:48 PM PDT 24
Peak memory 695776 kb
Host smart-f8a4d9e1-81dc-4664-ada1-f392f7ac4884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751675855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3751675855
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.4229073589
Short name T481
Test name
Test status
Simulation time 479111605 ps
CPU time 25.72 seconds
Started May 19 01:16:55 PM PDT 24
Finished May 19 01:17:23 PM PDT 24
Peak memory 200604 kb
Host smart-149777aa-6c4a-4e11-8555-a496a179a6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229073589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4229073589
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2090131183
Short name T297
Test name
Test status
Simulation time 138467085 ps
CPU time 2.14 seconds
Started May 19 01:16:53 PM PDT 24
Finished May 19 01:16:56 PM PDT 24
Peak memory 200552 kb
Host smart-e9edc867-e067-43fe-ade9-4baa609344ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090131183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2090131183
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.612356584
Short name T474
Test name
Test status
Simulation time 167657767 ps
CPU time 1.01 seconds
Started May 19 01:16:53 PM PDT 24
Finished May 19 01:16:56 PM PDT 24
Peak memory 199340 kb
Host smart-0a445f3b-b0ef-4549-a8a5-e001d8edf64a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612356584 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.612356584
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1403338686
Short name T220
Test name
Test status
Simulation time 162867443247 ps
CPU time 541.78 seconds
Started May 19 01:16:59 PM PDT 24
Finished May 19 01:26:02 PM PDT 24
Peak memory 200624 kb
Host smart-d8d45adb-9ca6-4f5d-b098-0fa892be4051
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403338686 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1403338686
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_alert_test.244074725
Short name T153
Test name
Test status
Simulation time 23517457 ps
CPU time 0.59 seconds
Started May 19 01:16:55 PM PDT 24
Finished May 19 01:16:58 PM PDT 24
Peak memory 197096 kb
Host smart-e1dbca0f-1d09-427f-ac75-e8a2a1d709d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244074725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.244074725
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.916889158
Short name T47
Test name
Test status
Simulation time 702818105 ps
CPU time 17.85 seconds
Started May 19 01:16:55 PM PDT 24
Finished May 19 01:17:15 PM PDT 24
Peak memory 220136 kb
Host smart-c5a7fd7f-a454-4676-8cb1-3badb143734d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916889158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.916889158
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1375068406
Short name T99
Test name
Test status
Simulation time 1231418454 ps
CPU time 24.12 seconds
Started May 19 01:16:58 PM PDT 24
Finished May 19 01:17:22 PM PDT 24
Peak memory 200544 kb
Host smart-be4bfe5e-431f-4c10-93d4-538b5b2fa054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375068406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1375068406
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2442495087
Short name T289
Test name
Test status
Simulation time 8492300093 ps
CPU time 877.71 seconds
Started May 19 01:16:55 PM PDT 24
Finished May 19 01:31:35 PM PDT 24
Peak memory 743964 kb
Host smart-f0f53888-207c-475f-a3e6-b85cae04c213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442495087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2442495087
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.895352537
Short name T273
Test name
Test status
Simulation time 1190869212 ps
CPU time 16.48 seconds
Started May 19 01:16:55 PM PDT 24
Finished May 19 01:17:13 PM PDT 24
Peak memory 200824 kb
Host smart-eaf2d5a1-4780-4dd6-b4c5-6cbeb9b86a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895352537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.895352537
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.19118752
Short name T204
Test name
Test status
Simulation time 387241734 ps
CPU time 1.69 seconds
Started May 19 01:16:55 PM PDT 24
Finished May 19 01:16:59 PM PDT 24
Peak memory 200520 kb
Host smart-2105db2f-13fa-48db-8016-6b1333c83cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19118752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.19118752
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.156508871
Short name T432
Test name
Test status
Simulation time 65695315 ps
CPU time 1.24 seconds
Started May 19 01:16:56 PM PDT 24
Finished May 19 01:16:59 PM PDT 24
Peak memory 200568 kb
Host smart-8c71da82-1146-4a64-aba6-6e86f5619315
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156508871 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.156508871
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2797301364
Short name T150
Test name
Test status
Simulation time 127497941709 ps
CPU time 472.84 seconds
Started May 19 01:16:59 PM PDT 24
Finished May 19 01:24:52 PM PDT 24
Peak memory 200608 kb
Host smart-2046ed92-5278-4e10-b2cd-06fb9e65571a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797301364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2797301364
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_alert_test.840955372
Short name T3
Test name
Test status
Simulation time 48177823 ps
CPU time 0.56 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:15:33 PM PDT 24
Peak memory 196328 kb
Host smart-3cdec0ef-bb21-4bf1-ae5a-fbe2484502c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840955372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.840955372
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1180419309
Short name T201
Test name
Test status
Simulation time 151318837 ps
CPU time 5.24 seconds
Started May 19 01:15:13 PM PDT 24
Finished May 19 01:15:37 PM PDT 24
Peak memory 200588 kb
Host smart-145ad550-c96b-458c-ada3-e4e910cb8b9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180419309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1180419309
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2142207327
Short name T30
Test name
Test status
Simulation time 729177843 ps
CPU time 41.65 seconds
Started May 19 01:15:15 PM PDT 24
Finished May 19 01:16:13 PM PDT 24
Peak memory 200652 kb
Host smart-898536b1-3e6c-4e1e-a15f-06653d0fbb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142207327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2142207327
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.541364463
Short name T94
Test name
Test status
Simulation time 17376346163 ps
CPU time 778.34 seconds
Started May 19 01:15:10 PM PDT 24
Finished May 19 01:28:25 PM PDT 24
Peak memory 751516 kb
Host smart-021f131b-a09c-4271-a888-39928dae9e52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541364463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.541364463
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.538743158
Short name T134
Test name
Test status
Simulation time 4566171215 ps
CPU time 87.73 seconds
Started May 19 01:15:08 PM PDT 24
Finished May 19 01:16:54 PM PDT 24
Peak memory 200660 kb
Host smart-79da3af4-7873-4642-a314-fbb9e69a4064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538743158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.538743158
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1997576542
Short name T209
Test name
Test status
Simulation time 74281172 ps
CPU time 1.33 seconds
Started May 19 01:15:11 PM PDT 24
Finished May 19 01:15:30 PM PDT 24
Peak memory 200624 kb
Host smart-5d4150f0-bd2a-426b-977f-f740e187234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997576542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1997576542
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1265199446
Short name T303
Test name
Test status
Simulation time 30719678 ps
CPU time 1.04 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:15:33 PM PDT 24
Peak memory 200156 kb
Host smart-13865205-efa4-4f8e-99fd-c2648cbb2554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265199446 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1265199446
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2404487002
Short name T405
Test name
Test status
Simulation time 96352692171 ps
CPU time 472.98 seconds
Started May 19 01:15:14 PM PDT 24
Finished May 19 01:23:24 PM PDT 24
Peak memory 200620 kb
Host smart-395d1718-be6d-44ac-9ff5-72d01018196c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404487002 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2404487002
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2894792130
Short name T346
Test name
Test status
Simulation time 63107832 ps
CPU time 0.58 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:15:34 PM PDT 24
Peak memory 196244 kb
Host smart-d74b0fc0-a0b2-48d2-a474-b1c9dbda4f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894792130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2894792130
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2554360352
Short name T93
Test name
Test status
Simulation time 11537212504 ps
CPU time 38.77 seconds
Started May 19 01:15:12 PM PDT 24
Finished May 19 01:16:09 PM PDT 24
Peak memory 200676 kb
Host smart-f6adef09-caff-4daa-9062-a458b40699f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554360352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2554360352
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.442713295
Short name T224
Test name
Test status
Simulation time 20220753020 ps
CPU time 638.55 seconds
Started May 19 01:15:13 PM PDT 24
Finished May 19 01:26:09 PM PDT 24
Peak memory 746220 kb
Host smart-be3be5fb-cfeb-4b4d-8be0-f267d9ebac8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442713295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.442713295
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.660249380
Short name T357
Test name
Test status
Simulation time 1586813691 ps
CPU time 85.96 seconds
Started May 19 01:15:11 PM PDT 24
Finished May 19 01:16:54 PM PDT 24
Peak memory 200512 kb
Host smart-b28de7b6-6a48-4282-9511-b53b9adc60b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660249380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.660249380
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.218928115
Short name T165
Test name
Test status
Simulation time 1547808751 ps
CPU time 5.86 seconds
Started May 19 01:15:11 PM PDT 24
Finished May 19 01:15:34 PM PDT 24
Peak memory 200488 kb
Host smart-25cfef8b-f92d-4067-8d5f-8a0a44d3b050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218928115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.218928115
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2725028506
Short name T154
Test name
Test status
Simulation time 60247059 ps
CPU time 1.34 seconds
Started May 19 01:15:14 PM PDT 24
Finished May 19 01:15:33 PM PDT 24
Peak memory 200524 kb
Host smart-39ee0c8a-03a2-45ac-b521-f89540e808e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725028506 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2725028506
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3111815234
Short name T213
Test name
Test status
Simulation time 41640042620 ps
CPU time 505.36 seconds
Started May 19 01:15:17 PM PDT 24
Finished May 19 01:23:59 PM PDT 24
Peak memory 200640 kb
Host smart-7e34224f-4576-4667-8cfb-b93adfc04a88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111815234 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3111815234
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2582778829
Short name T371
Test name
Test status
Simulation time 11753189 ps
CPU time 0.61 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:15:34 PM PDT 24
Peak memory 196588 kb
Host smart-c3189cc7-2059-4947-b47f-df94519d5b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582778829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2582778829
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2074393449
Short name T286
Test name
Test status
Simulation time 1886811239 ps
CPU time 46.44 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:16:19 PM PDT 24
Peak memory 216744 kb
Host smart-45f39b22-f80d-4ca5-8a26-f6b5c9774065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074393449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2074393449
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2319966207
Short name T380
Test name
Test status
Simulation time 1408707211 ps
CPU time 18.98 seconds
Started May 19 01:15:19 PM PDT 24
Finished May 19 01:15:54 PM PDT 24
Peak memory 200528 kb
Host smart-44156fc9-03f7-4a51-adb8-85a6401256f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319966207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2319966207
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3824394515
Short name T42
Test name
Test status
Simulation time 1313076463 ps
CPU time 363.12 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:21:35 PM PDT 24
Peak memory 705020 kb
Host smart-ade27538-e076-4788-9c13-36d5634bc445
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824394515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3824394515
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1714612181
Short name T326
Test name
Test status
Simulation time 16061865 ps
CPU time 0.71 seconds
Started May 19 01:15:14 PM PDT 24
Finished May 19 01:15:32 PM PDT 24
Peak memory 196808 kb
Host smart-c31a8aec-f6b2-4a25-bfdb-4cb80611aa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714612181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1714612181
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.78788340
Short name T400
Test name
Test status
Simulation time 2191279417 ps
CPU time 6.21 seconds
Started May 19 01:15:15 PM PDT 24
Finished May 19 01:15:38 PM PDT 24
Peak memory 200684 kb
Host smart-4813f27a-1c14-47b1-954b-74551b10702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78788340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.78788340
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3464680426
Short name T4
Test name
Test status
Simulation time 1050524486 ps
CPU time 55.31 seconds
Started May 19 01:15:13 PM PDT 24
Finished May 19 01:16:27 PM PDT 24
Peak memory 233328 kb
Host smart-c0b64ce6-b196-49b6-b7ce-121b09dc8f70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464680426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3464680426
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2648470316
Short name T144
Test name
Test status
Simulation time 48096952 ps
CPU time 0.98 seconds
Started May 19 01:15:15 PM PDT 24
Finished May 19 01:15:33 PM PDT 24
Peak memory 199064 kb
Host smart-35450ddf-f65e-4a99-8b3f-88bb7480b178
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648470316 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2648470316
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2308973283
Short name T218
Test name
Test status
Simulation time 52219541346 ps
CPU time 511.09 seconds
Started May 19 01:15:15 PM PDT 24
Finished May 19 01:24:03 PM PDT 24
Peak memory 200640 kb
Host smart-4d535cc5-2264-498b-b026-d919c49c6047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308973283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2308973283
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3953284444
Short name T461
Test name
Test status
Simulation time 22138941 ps
CPU time 0.62 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:15:39 PM PDT 24
Peak memory 196040 kb
Host smart-1abaa4b0-61ce-4758-8dc8-86134c289f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953284444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3953284444
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1698934889
Short name T126
Test name
Test status
Simulation time 764049626 ps
CPU time 37.8 seconds
Started May 19 01:15:20 PM PDT 24
Finished May 19 01:16:14 PM PDT 24
Peak memory 208796 kb
Host smart-e1b6d491-6b10-4461-933e-15d260af1a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698934889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1698934889
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.695348759
Short name T242
Test name
Test status
Simulation time 191011950 ps
CPU time 6.16 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:15:38 PM PDT 24
Peak memory 200580 kb
Host smart-7fb416ee-60fa-4d1b-b6e4-835d90238621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695348759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.695348759
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3999236706
Short name T356
Test name
Test status
Simulation time 5682837486 ps
CPU time 625.57 seconds
Started May 19 01:15:15 PM PDT 24
Finished May 19 01:25:58 PM PDT 24
Peak memory 656240 kb
Host smart-a1e1fc20-c34a-4d4e-9025-260ad1b8d29e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999236706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3999236706
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.92945646
Short name T399
Test name
Test status
Simulation time 144287750 ps
CPU time 2.84 seconds
Started May 19 01:15:19 PM PDT 24
Finished May 19 01:15:38 PM PDT 24
Peak memory 200536 kb
Host smart-3e059966-f38b-42e9-8468-c507464b1d4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92945646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.92945646
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3738024575
Short name T198
Test name
Test status
Simulation time 4909588872 ps
CPU time 73.08 seconds
Started May 19 01:15:16 PM PDT 24
Finished May 19 01:16:45 PM PDT 24
Peak memory 200692 kb
Host smart-68843146-b51a-45b9-af43-23ddfc66ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738024575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3738024575
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2838985329
Short name T374
Test name
Test status
Simulation time 15914782 ps
CPU time 0.73 seconds
Started May 19 01:15:14 PM PDT 24
Finished May 19 01:15:32 PM PDT 24
Peak memory 197960 kb
Host smart-0de4ab01-a622-4e9a-8c76-72a3ce0df9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838985329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2838985329
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1255967700
Short name T468
Test name
Test status
Simulation time 119773526 ps
CPU time 1.01 seconds
Started May 19 01:15:20 PM PDT 24
Finished May 19 01:15:37 PM PDT 24
Peak memory 199240 kb
Host smart-5f7e09ac-f962-4b82-8aba-e34a98a7ffa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255967700 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1255967700
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1425178124
Short name T281
Test name
Test status
Simulation time 68527356825 ps
CPU time 468.04 seconds
Started May 19 01:15:15 PM PDT 24
Finished May 19 01:23:20 PM PDT 24
Peak memory 200664 kb
Host smart-44b11c17-64d3-43c2-a77f-41ca2d81c048
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425178124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1425178124
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3827604119
Short name T428
Test name
Test status
Simulation time 23013572 ps
CPU time 0.56 seconds
Started May 19 01:15:20 PM PDT 24
Finished May 19 01:15:36 PM PDT 24
Peak memory 195956 kb
Host smart-4e57d63a-4a0f-4d17-a2d5-4b8f3528c3ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827604119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3827604119
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3804475004
Short name T129
Test name
Test status
Simulation time 1156354174 ps
CPU time 60.93 seconds
Started May 19 01:15:25 PM PDT 24
Finished May 19 01:16:39 PM PDT 24
Peak memory 226060 kb
Host smart-c62aa3fc-d3e8-4c6f-9337-2578834afdd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804475004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3804475004
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2045219049
Short name T479
Test name
Test status
Simulation time 23397849181 ps
CPU time 40.91 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:16:15 PM PDT 24
Peak memory 200716 kb
Host smart-00f326b3-a7a8-4517-87d5-006f66dfc316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045219049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2045219049
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2396584048
Short name T149
Test name
Test status
Simulation time 6405996467 ps
CPU time 378.17 seconds
Started May 19 01:15:20 PM PDT 24
Finished May 19 01:21:54 PM PDT 24
Peak memory 694272 kb
Host smart-076343af-51f7-41bb-b890-ab6b5c19dd44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396584048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2396584048
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_smoke.3092597844
Short name T159
Test name
Test status
Simulation time 2744440202 ps
CPU time 4.24 seconds
Started May 19 01:15:18 PM PDT 24
Finished May 19 01:15:39 PM PDT 24
Peak memory 200708 kb
Host smart-eb29e74b-179b-469c-b53a-83aad5d9dd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092597844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3092597844
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.909894841
Short name T230
Test name
Test status
Simulation time 32286226 ps
CPU time 1.21 seconds
Started May 19 01:15:17 PM PDT 24
Finished May 19 01:15:34 PM PDT 24
Peak memory 200512 kb
Host smart-5ac4b9f9-f489-47ed-828d-67a5dcae10ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909894841 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.909894841
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1691944872
Short name T257
Test name
Test status
Simulation time 165388057074 ps
CPU time 536.78 seconds
Started May 19 01:15:19 PM PDT 24
Finished May 19 01:24:31 PM PDT 24
Peak memory 200428 kb
Host smart-0f145e48-0f06-4bd2-8c2a-8e82764d24b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691944872 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1691944872
Directory /workspace/9.hmac_test_sha_vectors/latest
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