Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6361998	1			T1	32		T2	232		T3	6477
all_values[1]	6361998	1			T1	32		T2	232		T3	6477
all_values[2]	6361998	1			T1	32		T2	232		T3	6477

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62292

1

T2

9

T3

74

T4

77

auto[1]

19023702

1

T1

96

T2

687

T3

19357

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17376996

1

T1

92

T2

590

T3

16001

auto[1]

1708998

1

T1

4

T2

106

T3

3430

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	22675	1			T2	9		T3	72		T99	21
all_values[0]	auto[0]	auto[1]	174	1			T3	2		T99	4		T47	2
all_values[0]	auto[1]	auto[0]	6323229	1			T1	28		T2	208		T3	6397
all_values[0]	auto[1]	auto[1]	15920	1			T1	4		T2	15		T3	6
all_values[1]	auto[0]	auto[0]	15725	1			T24	92		T106	2		T20	4
all_values[1]	auto[0]	auto[1]	94	1			T15	2		T56	3		T57	1
all_values[1]	auto[1]	auto[0]	6346067	1			T1	32		T2	232		T3	6477
all_values[1]	auto[1]	auto[1]	112	1			T12	1		T31	1		T15	6
all_values[2]	auto[0]	auto[0]	7896	1			T4	77		T10	2		T99	12
all_values[2]	auto[0]	auto[1]	15728	1			T10	17		T81	1138		T100	2
all_values[2]	auto[1]	auto[0]	4661404	1			T1	32		T2	141		T3	3055
all_values[2]	auto[1]	auto[1]	1676970	1			T2	91		T3	3422		T5	6