Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3268738

1

T1

27

T2

92

T3

2935

auto[1]

990239

1

T2

105

T3

3498

T5

3

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026464

1

T2

81

T3

2328

T5

5

auto[1]

3232513

1

T1

27

T2

116

T3

4105

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2600569

1

T2

101

T3

3134

T4

147

auto[1]

1658408

1

T1

27

T2

96

T3

3299

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	3613834	1			T1	5		T2	164		T3	6338
fifo_depth[1]	124188	1			T1	2		T2	3		T3	59
fifo_depth[2]	91189	1			T1	1		T2	3		T3	25
fifo_depth[3]	69556	1			T1	4		T2	6		T3	6
fifo_depth[4]	56336	1			T1	2		T2	7		T3	3
fifo_depth[5]	48321	1			T1	3		T2	3		T3	2
fifo_depth[6]	45847	1			T1	1		T2	1		T4	1
fifo_depth[7]	38365	1			T1	4		T2	4		T10	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645143

1

T1

22

T2

33

T3

95

auto[1]

3613834

1

T1

5

T2

164

T3

6338

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4256613

1

T1

27

T2

197

T3

6433

auto[1]

2364

1

T12

68

T24

289

T47

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

28331

1

T3

8

T11

3

T12

651

auto[0]

auto[0]

auto[0]

auto[1]

23249

1

T3

8

T11

2

T12

3146

auto[0]

auto[0]

auto[1]

auto[0]

336414

1

T3

71

T4

10

T11

3

auto[0]

auto[0]

auto[1]

auto[1]

27332

1

T5

1

T11

5

T12

1208

auto[0]

auto[1]

auto[0]

auto[0]

53484

1

T2

3

T11

1

T12

1065

auto[0]

auto[1]

auto[0]

auto[1]

52408

1

T10

11

T11

1

T12

142

auto[0]

auto[1]

auto[1]

auto[0]

64711

1

T1

22

T2

16

T9

10

auto[0]

auto[1]

auto[1]

auto[1]

59214

1

T2

14

T3

8

T10

11

auto[1]

auto[0]

auto[0]

auto[0]

81091

1

T2

5

T3

1145

T5

1

auto[1]

auto[0]

auto[0]

auto[1]

64276

1

T2

46

T3

798

T5

1

auto[1]

auto[0]

auto[1]

auto[0]

1956481

1

T2

23

T3

855

T4

137

auto[1]

auto[0]

auto[1]

auto[1]

83395

1

T2

27

T3

249

T10

22

auto[1]

auto[1]

auto[0]

auto[0]

368207

1

T2

21

T3

369

T5

2

auto[1]

auto[1]

auto[0]

auto[1]

355418

1

T2

6

T5

1

T10

5

auto[1]

auto[1]

auto[1]

auto[0]

380019

1

T1

5

T2

24

T3

487

auto[1]

auto[1]

auto[1]

auto[1]

324947

1

T2

12

T3

2435

T10

25

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

109048

1

T2

5

T3

1153

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

87282

1

T2

46

T3

806

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

2292743

1

T2

23

T3

926

T4

147

auto[0]

auto[0]

auto[1]

auto[1]

109785

1

T2

27

T3

249

T5

1

auto[0]

auto[1]

auto[0]

auto[0]

421588

1

T2

24

T3

369

T5

2

auto[0]

auto[1]

auto[0]

auto[1]

407666

1

T2

6

T5

1

T10

16

auto[0]

auto[1]

auto[1]

auto[0]

444502

1

T1

27

T2

40

T3

487

auto[0]

auto[1]

auto[1]

auto[1]

383999

1

T2

26

T3

2443

T10

36

auto[1]

auto[0]

auto[0]

auto[0]

374

1

T12

24

T31

30

T119

1

auto[1]

auto[0]

auto[0]

auto[1]

243

1

T12

29

T24

40

T31

4

auto[1]

auto[0]

auto[1]

auto[0]

152

1

T12

1

T24

22

T49

1

auto[1]

auto[0]

auto[1]

auto[1]

942

1

T12

2

T24

164

T31

70

auto[1]

auto[1]

auto[0]

auto[0]

103

1

T12

3

T120

26

T121

1

auto[1]

auto[1]

auto[0]

auto[1]

160

1

T24

2

T47

1

T31

10

auto[1]

auto[1]

auto[1]

auto[0]

228

1

T24

40

T31

25

T122

1

auto[1]

auto[1]

auto[1]

auto[1]

162

1

T12

9

T24

21

T48

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	81091	1			T2	5		T3	1145		T5	1
fifo_depth[0]	auto[0]	auto[0]	auto[1]	64276	1			T2	46		T3	798		T5	1
fifo_depth[0]	auto[0]	auto[1]	auto[0]	1956481	1			T2	23		T3	855		T4	137
fifo_depth[0]	auto[0]	auto[1]	auto[1]	83395	1			T2	27		T3	249		T10	22
fifo_depth[0]	auto[1]	auto[0]	auto[0]	368207	1			T2	21		T3	369		T5	2
fifo_depth[0]	auto[1]	auto[0]	auto[1]	355418	1			T2	6		T5	1		T10	5
fifo_depth[0]	auto[1]	auto[1]	auto[0]	380019	1			T1	5		T2	24		T3	487
fifo_depth[0]	auto[1]	auto[1]	auto[1]	324947	1			T2	12		T3	2435		T10	25
fifo_depth[1]	auto[0]	auto[0]	auto[0]	1777	1			T3	5		T8	193		T18	29
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1400	1			T3	6		T12	1		T8	16
fifo_depth[1]	auto[0]	auto[1]	auto[0]	95749	1			T3	45		T12	2		T8	26
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1742	1			T12	6		T8	48		T18	13
fifo_depth[1]	auto[1]	auto[0]	auto[0]	5571	1			T2	1		T12	27		T8	10
fifo_depth[1]	auto[1]	auto[0]	auto[1]	5473	1			T10	1		T12	2		T7	120
fifo_depth[1]	auto[1]	auto[1]	auto[0]	6466	1			T1	2		T9	3		T10	1
fifo_depth[1]	auto[1]	auto[1]	auto[1]	6010	1			T2	2		T3	3		T6	13
fifo_depth[2]	auto[0]	auto[0]	auto[0]	1886	1			T3	3		T8	177		T18	18
fifo_depth[2]	auto[0]	auto[0]	auto[1]	1475	1			T3	2		T8	18		T18	44
fifo_depth[2]	auto[0]	auto[1]	auto[0]	63223	1			T3	17		T4	4		T12	8
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1875	1			T12	3		T8	41		T18	29
fifo_depth[2]	auto[1]	auto[0]	auto[0]	5336	1			T12	32		T8	19		T18	50
fifo_depth[2]	auto[1]	auto[0]	auto[1]	5062	1			T10	2		T7	142		T8	18
fifo_depth[2]	auto[1]	auto[1]	auto[0]	6398	1			T1	1		T2	3		T9	4
fifo_depth[2]	auto[1]	auto[1]	auto[1]	5934	1			T3	3		T10	1		T6	8
fifo_depth[3]	auto[0]	auto[0]	auto[0]	1485	1			T8	190		T18	9		T24	2
fifo_depth[3]	auto[0]	auto[0]	auto[1]	1108	1			T12	39		T8	15		T18	6
fifo_depth[3]	auto[0]	auto[1]	auto[0]	44315	1			T3	4		T4	1		T12	6
fifo_depth[3]	auto[0]	auto[1]	auto[1]	1439	1			T12	7		T8	46		T18	8
fifo_depth[3]	auto[1]	auto[0]	auto[0]	5014	1			T2	2		T12	40		T8	20
fifo_depth[3]	auto[1]	auto[0]	auto[1]	4575	1			T10	3		T12	2		T7	121
fifo_depth[3]	auto[1]	auto[1]	auto[0]	6057	1			T1	4		T2	2		T9	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	5563	1			T2	2		T3	2		T10	1
fifo_depth[4]	auto[0]	auto[0]	auto[0]	1601	1			T8	180		T18	15		T24	15
fifo_depth[4]	auto[0]	auto[0]	auto[1]	1157	1			T12	39		T8	18		T18	38
fifo_depth[4]	auto[0]	auto[1]	auto[0]	30797	1			T3	3		T4	4		T12	7
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1570	1			T12	8		T8	41		T18	22
fifo_depth[4]	auto[1]	auto[0]	auto[0]	4983	1			T12	30		T8	14		T18	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	4566	1			T10	3		T7	121		T8	15
fifo_depth[4]	auto[1]	auto[1]	auto[0]	6036	1			T1	2		T2	4		T6	94
fifo_depth[4]	auto[1]	auto[1]	auto[1]	5626	1			T2	3		T10	2		T6	12
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1355	1			T8	164		T18	9		T24	7
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1086	1			T12	58		T8	15		T18	5
fifo_depth[5]	auto[0]	auto[1]	auto[0]	24242	1			T3	2		T12	5		T8	22
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1304	1			T12	12		T8	45		T18	2
fifo_depth[5]	auto[1]	auto[0]	auto[0]	4945	1			T12	39		T8	12		T99	2
fifo_depth[5]	auto[1]	auto[0]	auto[1]	4258	1			T12	3		T7	123		T8	23
fifo_depth[5]	auto[1]	auto[1]	auto[0]	5718	1			T1	3		T2	2		T6	98
fifo_depth[5]	auto[1]	auto[1]	auto[1]	5413	1			T2	1		T10	1		T6	4
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1873	1			T12	2		T8	175		T18	11
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1141	1			T12	20		T8	16		T18	9
fifo_depth[6]	auto[0]	auto[1]	auto[0]	20941	1			T4	1		T12	45		T8	19
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1478	1			T12	26		T8	44		T18	12
fifo_depth[6]	auto[1]	auto[0]	auto[0]	4829	1			T12	31		T8	11		T24	6
fifo_depth[6]	auto[1]	auto[0]	auto[1]	4317	1			T7	111		T8	20		T18	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	5875	1			T1	1		T6	98		T12	5
fifo_depth[6]	auto[1]	auto[1]	auto[1]	5393	1			T2	1		T6	14		T8	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1257	1			T12	1		T8	152		T18	2
fifo_depth[7]	auto[0]	auto[0]	auto[1]	904	1			T12	59		T8	11		T18	1
fifo_depth[7]	auto[0]	auto[1]	auto[0]	16611	1			T12	6		T8	22		T18	6
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1197	1			T12	8		T8	44		T18	2
fifo_depth[7]	auto[1]	auto[0]	auto[0]	4361	1			T12	36		T8	23		T24	9
fifo_depth[7]	auto[1]	auto[0]	auto[1]	3864	1			T10	1		T12	2		T7	118
fifo_depth[7]	auto[1]	auto[1]	auto[0]	5174	1			T1	4		T2	3		T6	86
fifo_depth[7]	auto[1]	auto[1]	auto[1]	4997	1			T2	1		T6	11		T12	1