Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6361998	1			T1	32		T2	232		T3	6477
all_pins[1]	6361998	1			T1	32		T2	232		T3	6477
all_pins[2]	6361998	1			T1	32		T2	232		T3	6477

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17392784	1			T1	92		T2	590		T3	16003
values[0x1]	1693210	1			T1	4		T2	106		T3	3428
transitions[0x0=>0x1]	1693114	1			T1	4		T2	106		T3	3428
transitions[0x1=>0x0]	1693127	1			T1	4		T2	106		T3	3428

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6345872	1			T1	28		T2	217		T3	6471
all_pins[0]	values[0x1]	16126	1			T1	4		T2	15		T3	6
all_pins[0]	transitions[0x0=>0x1]	16085	1			T1	4		T2	15		T3	6
all_pins[0]	transitions[0x1=>0x0]	1676942	1			T2	91		T3	3422		T5	6
all_pins[1]	values[0x0]	6361884	1			T1	32		T2	232		T3	6477
all_pins[1]	values[0x1]	114	1			T12	1		T31	1		T15	6
all_pins[1]	transitions[0x0=>0x1]	85	1			T12	1		T31	1		T15	5
all_pins[1]	transitions[0x1=>0x0]	16097	1			T1	4		T2	15		T3	6
all_pins[2]	values[0x0]	4685028	1			T1	32		T2	141		T3	3055
all_pins[2]	values[0x1]	1676970	1			T2	91		T3	3422		T5	6
all_pins[2]	transitions[0x0=>0x1]	1676944	1			T2	91		T3	3422		T5	6
all_pins[2]	transitions[0x1=>0x0]	88	1			T12	1		T31	1		T15	6