Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 442 1 T15 17 T56 14 T57 4
all_values[1] 442 1 T15 17 T56 14 T57 4
all_values[2] 442 1 T15 17 T56 14 T57 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 681 1 T15 25 T56 10 T57 8
auto[1] 645 1 T15 26 T56 32 T57 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 482 1 T15 13 T56 14 T57 7
auto[1] 844 1 T15 38 T56 28 T57 5


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 761 1 T15 26 T56 21 T57 9
auto[1] 565 1 T15 25 T56 21 T57 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 67 1 T15 2 T57 3 T30 2
all_values[0] auto[0] auto[0] auto[1] 41 1 T15 1 T56 1 T30 1
all_values[0] auto[0] auto[1] auto[0] 100 1 T15 3 T56 7 T30 4
all_values[0] auto[0] auto[1] auto[1] 34 1 T30 3 T107 2 T108 1
all_values[0] auto[1] auto[0] auto[1] 112 1 T15 7 T56 2 T57 1
all_values[0] auto[1] auto[1] auto[1] 88 1 T15 4 T56 4 T30 8
all_values[1] auto[0] auto[0] auto[0] 72 1 T15 2 T30 1 T109 2
all_values[1] auto[0] auto[0] auto[1] 52 1 T15 2 T56 1 T57 1
all_values[1] auto[0] auto[1] auto[0] 56 1 T15 3 T56 5 T30 9
all_values[1] auto[0] auto[1] auto[1] 66 1 T15 4 T56 2 T57 1
all_values[1] auto[1] auto[0] auto[1] 108 1 T15 1 T56 2 T57 1
all_values[1] auto[1] auto[1] auto[1] 88 1 T15 5 T56 4 T57 1
all_values[2] auto[0] auto[0] auto[0] 99 1 T15 1 T57 2 T30 7
all_values[2] auto[0] auto[0] auto[1] 46 1 T15 5 T56 1 T30 2
all_values[2] auto[0] auto[1] auto[0] 88 1 T15 2 T56 2 T57 2
all_values[2] auto[0] auto[1] auto[1] 40 1 T15 1 T56 2 T107 1
all_values[2] auto[1] auto[0] auto[1] 84 1 T15 4 T56 3 T30 3
all_values[2] auto[1] auto[1] auto[1] 85 1 T15 4 T56 6 T30 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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