Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	4	16	80.00
Crosses	82	36	46	56.10

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	2	3	60.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	1	1	50.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	2	2	50.00	100	1	1	0
key_x_digest_mismatch	35	17	18	51.43	100	1	1	0
key_length_x_digest_size	35	17	18	51.43	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	2	3	60.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1
sha2_none	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	1241	1			T2	3		T3	3		T4	1
sha2_384	1203	1			T2	7		T3	3		T5	1
sha2_256	12758	1			T1	4		T2	4		T3	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13474

1

T1

4

T2

6

T3

3

auto[1]

1728

1

T2

8

T3

4

T5

1

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1793

1

T2

5

T3

4

T10

7

auto[1]

13409

1

T1

4

T2

9

T3

3

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

1958

1

T1

4

T2

5

T3

2

disabled

13244

1

T2

9

T3

5

T4

1

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	637	1			T4	1		T10	4		T11	5
key_1024	459	1			T2	4		T3	2		T10	1
key_512	624	1			T2	3		T3	2		T10	5
key_384	600	1			T2	2		T3	1		T5	1
key_256	12253	1			T1	4		T2	3		T3	2
key_128	629	1			T2	2		T5	1		T10	2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for sha_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
disabled	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15202

1

T1

4

T2

14

T3

7

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	439	1			T2	1		T6	2		T11	1
enabled	auto[0]	auto[1]	428	1			T10	2		T6	2		T11	1
enabled	auto[1]	auto[0]	703	1			T1	4		T2	2		T3	1
enabled	auto[1]	auto[1]	388	1			T2	2		T3	1		T10	1
disabled	auto[0]	auto[0]	488	1			T2	1		T3	1		T10	4
disabled	auto[0]	auto[1]	438	1			T2	3		T3	3		T10	1
disabled	auto[1]	auto[0]	11844	1			T2	2		T3	1		T4	1
disabled	auto[1]	auto[1]	474	1			T2	3		T5	1		T10	1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	2	2	50.00	2
Automatically Generated Cross Bins	3	2	1	33.33	2
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes

hmac_en	sha_en	COUNT	AT LEAST	NUMBER	STATUS
*	[disabled]	--	--	2

Covered bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

1958

1

T1

4

T2

5

T3

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13244

1

T2

9

T3

5

T4

1

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	17	18	51.43	17
Automatically Generated Cross Bins	34	17	17	50.00	17
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	223	1			T4	1		T10	1		T11	2
key_none	sha2_384	208	1			T10	1		T11	2		T12	2
key_none	sha2_256	206	1			T10	2		T11	1		T12	3
key_1024	sha2_512	204	1			T2	1		T10	1		T6	2
key_1024	sha2_384	187	1			T2	2		T3	2		T8	1
key_512	sha2_512	204	1			T2	1		T3	2		T10	3
key_512	sha2_384	217	1			T2	1		T12	1		T8	2
key_512	sha2_256	203	1			T2	1		T10	2		T11	1
key_384	sha2_512	208	1			T3	1		T6	2		T11	2
key_384	sha2_384	196	1			T2	2		T10	1		T6	2
key_384	sha2_256	196	1			T5	1		T6	1		T11	1
key_256	sha2_512	195	1			T2	1		T12	1		T7	1
key_256	sha2_384	197	1			T2	1		T3	1		T18	5
key_256	sha2_256	11861	1			T1	4		T2	1		T3	1
key_128	sha2_512	207	1			T11	2		T12	1		T7	1
key_128	sha2_384	198	1			T2	1		T5	1		T10	2
key_128	sha2_256	224	1			T2	1		T6	1		T12	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

68

1

T2

1

T18

3

T24

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	223	1			T4	1		T10	1		T11	2
key_none	sha2_384	208	1			T10	1		T11	2		T12	2
key_none	sha2_256	206	1			T10	2		T11	1		T12	3
key_1024	sha2_512	204	1			T2	1		T10	1		T6	2
key_1024	sha2_384	187	1			T2	2		T3	2		T8	1
key_1024	sha2_256	68	1			T2	1		T18	3		T24	2
key_512	sha2_512	204	1			T2	1		T3	2		T10	3
key_512	sha2_384	217	1			T2	1		T12	1		T8	2
key_512	sha2_256	203	1			T2	1		T10	2		T11	1
key_384	sha2_512	208	1			T3	1		T6	2		T11	2
key_384	sha2_384	196	1			T2	2		T10	1		T6	2
key_384	sha2_256	196	1			T5	1		T6	1		T11	1
key_256	sha2_512	195	1			T2	1		T12	1		T7	1
key_256	sha2_384	197	1			T2	1		T3	1		T18	5
key_256	sha2_256	11861	1			T1	4		T2	1		T3	1
key_128	sha2_512	207	1			T11	2		T12	1		T7	1
key_128	sha2_384	198	1			T2	1		T5	1		T10	2
key_128	sha2_256	224	1			T2	1		T6	1		T12	2