Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.04 95.56 93.91 100.00 65.79 91.06 99.49 70.47


Total test records in report: 594
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T59 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2799498891 May 21 01:15:35 PM PDT 24 May 21 01:15:42 PM PDT 24 541052288 ps
T514 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2128830083 May 21 01:15:38 PM PDT 24 May 21 01:15:43 PM PDT 24 129673976 ps
T515 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3821898089 May 21 01:15:18 PM PDT 24 May 21 01:15:20 PM PDT 24 154676481 ps
T113 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.37164987 May 21 01:15:39 PM PDT 24 May 21 01:15:46 PM PDT 24 1138333856 ps
T91 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2154688512 May 21 01:15:33 PM PDT 24 May 21 01:15:36 PM PDT 24 53113120 ps
T516 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2257014882 May 21 01:15:50 PM PDT 24 May 21 01:15:53 PM PDT 24 32158326 ps
T517 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1621206402 May 21 01:15:49 PM PDT 24 May 21 01:15:53 PM PDT 24 14169031 ps
T518 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2019773105 May 21 01:15:45 PM PDT 24 May 21 01:15:47 PM PDT 24 22088715 ps
T114 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1216477819 May 21 01:15:38 PM PDT 24 May 21 01:15:45 PM PDT 24 128798624 ps
T519 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3684684360 May 21 01:15:49 PM PDT 24 May 21 01:15:52 PM PDT 24 49674659 ps
T520 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.205741525 May 21 01:15:38 PM PDT 24 May 21 01:15:43 PM PDT 24 59129720 ps
T521 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3857940846 May 21 01:15:45 PM PDT 24 May 21 01:15:47 PM PDT 24 15764416 ps
T522 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1261067858 May 21 01:15:22 PM PDT 24 May 21 01:15:24 PM PDT 24 39503442 ps
T58 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4119966005 May 21 01:15:37 PM PDT 24 May 21 01:15:44 PM PDT 24 374799896 ps
T523 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2653697411 May 21 01:15:33 PM PDT 24 May 21 01:15:37 PM PDT 24 187326372 ps
T524 /workspace/coverage/cover_reg_top/11.hmac_intr_test.789139779 May 21 01:16:05 PM PDT 24 May 21 01:16:06 PM PDT 24 12384935 ps
T116 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1371955332 May 21 01:15:21 PM PDT 24 May 21 01:15:25 PM PDT 24 193500095 ps
T92 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2071804054 May 21 01:15:44 PM PDT 24 May 21 01:15:46 PM PDT 24 32585024 ps
T525 /workspace/coverage/cover_reg_top/49.hmac_intr_test.871190248 May 21 01:15:52 PM PDT 24 May 21 01:15:56 PM PDT 24 58372470 ps
T526 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.404986028 May 21 01:15:24 PM PDT 24 May 21 01:15:27 PM PDT 24 322871668 ps
T527 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2845181787 May 21 01:15:40 PM PDT 24 May 21 01:15:45 PM PDT 24 319152146 ps
T528 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2264706111 May 21 01:15:40 PM PDT 24 May 21 01:15:44 PM PDT 24 21216048 ps
T529 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1784237151 May 21 01:15:33 PM PDT 24 May 21 01:15:37 PM PDT 24 96335877 ps
T530 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3963729365 May 21 01:15:32 PM PDT 24 May 21 01:15:36 PM PDT 24 98627168 ps
T531 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2001690761 May 21 01:15:47 PM PDT 24 May 21 01:15:51 PM PDT 24 31268907 ps
T532 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.77437002 May 21 01:15:35 PM PDT 24 May 21 01:15:40 PM PDT 24 82049699 ps
T533 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4026279878 May 21 01:15:20 PM PDT 24 May 21 01:15:25 PM PDT 24 639571384 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3615703744 May 21 01:15:38 PM PDT 24 May 21 01:15:44 PM PDT 24 188142889 ps
T534 /workspace/coverage/cover_reg_top/4.hmac_intr_test.4124492885 May 21 01:15:56 PM PDT 24 May 21 01:15:58 PM PDT 24 48682149 ps
T535 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1868510556 May 21 01:15:41 PM PDT 24 May 21 01:15:45 PM PDT 24 124442939 ps
T536 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4017581565 May 21 01:15:32 PM PDT 24 May 21 01:15:33 PM PDT 24 15665732 ps
T537 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3108238892 May 21 01:15:33 PM PDT 24 May 21 01:15:38 PM PDT 24 759803436 ps
T538 /workspace/coverage/cover_reg_top/16.hmac_intr_test.359925588 May 21 01:15:39 PM PDT 24 May 21 01:15:43 PM PDT 24 15336757 ps
T539 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3489268327 May 21 01:15:46 PM PDT 24 May 21 01:15:48 PM PDT 24 42930100 ps
T540 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.693635662 May 21 01:15:32 PM PDT 24 May 21 01:15:37 PM PDT 24 154882360 ps
T541 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1349979000 May 21 01:15:40 PM PDT 24 May 21 01:15:43 PM PDT 24 41822173 ps
T542 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3823773648 May 21 01:15:35 PM PDT 24 May 21 01:15:38 PM PDT 24 69910197 ps
T543 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3565552515 May 21 01:15:36 PM PDT 24 May 21 01:15:41 PM PDT 24 573936971 ps
T544 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4251024755 May 21 01:15:38 PM PDT 24 May 21 01:15:44 PM PDT 24 639524826 ps
T545 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1954308412 May 21 01:15:22 PM PDT 24 May 21 01:15:26 PM PDT 24 96863316 ps
T546 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2474326879 May 21 01:15:48 PM PDT 24 May 21 01:15:52 PM PDT 24 63262520 ps
T547 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2471602153 May 21 01:15:13 PM PDT 24 May 21 01:15:16 PM PDT 24 53322879 ps
T548 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2003968143 May 21 01:15:47 PM PDT 24 May 21 01:15:51 PM PDT 24 41996163 ps
T95 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2761858638 May 21 01:15:20 PM PDT 24 May 21 01:15:22 PM PDT 24 53068641 ps
T549 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1816110923 May 21 01:15:49 PM PDT 24 May 21 01:15:53 PM PDT 24 14472740 ps
T550 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1742097820 May 21 01:15:45 PM PDT 24 May 21 01:15:47 PM PDT 24 24833828 ps
T551 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3577365042 May 21 01:15:47 PM PDT 24 May 21 01:15:51 PM PDT 24 66914286 ps
T552 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2623259838 May 21 01:15:39 PM PDT 24 May 21 01:15:45 PM PDT 24 55151362 ps
T553 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1825893806 May 21 01:15:39 PM PDT 24 May 21 01:15:45 PM PDT 24 89915834 ps
T554 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3586394892 May 21 01:15:37 PM PDT 24 May 21 01:15:41 PM PDT 24 53523726 ps
T555 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2911519426 May 21 01:15:38 PM PDT 24 May 21 01:15:42 PM PDT 24 45825834 ps
T556 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3234988675 May 21 01:15:36 PM PDT 24 May 21 01:15:41 PM PDT 24 165616874 ps
T557 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.148428309 May 21 01:15:34 PM PDT 24 May 21 01:15:38 PM PDT 24 97355426 ps
T558 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3202933341 May 21 01:15:18 PM PDT 24 May 21 01:15:19 PM PDT 24 20855575 ps
T559 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1595065987 May 21 01:15:45 PM PDT 24 May 21 01:15:49 PM PDT 24 72889403 ps
T560 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3993984468 May 21 01:15:37 PM PDT 24 May 21 01:15:41 PM PDT 24 131861088 ps
T561 /workspace/coverage/cover_reg_top/35.hmac_intr_test.893760762 May 21 01:15:47 PM PDT 24 May 21 01:15:50 PM PDT 24 20297499 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.490053327 May 21 01:15:19 PM PDT 24 May 21 01:15:26 PM PDT 24 356365623 ps
T562 /workspace/coverage/cover_reg_top/48.hmac_intr_test.656389654 May 21 01:16:06 PM PDT 24 May 21 01:16:08 PM PDT 24 36279985 ps
T563 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2546895248 May 21 01:15:37 PM PDT 24 May 21 01:15:41 PM PDT 24 198490768 ps
T564 /workspace/coverage/cover_reg_top/44.hmac_intr_test.4200679103 May 21 01:15:55 PM PDT 24 May 21 01:15:57 PM PDT 24 18204837 ps
T565 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3671899313 May 21 01:15:46 PM PDT 24 May 21 01:15:49 PM PDT 24 13530894 ps
T566 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1591076087 May 21 01:15:51 PM PDT 24 May 21 01:15:55 PM PDT 24 17739242 ps
T567 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2229308181 May 21 01:15:33 PM PDT 24 May 21 01:18:37 PM PDT 24 31257453124 ps
T568 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3731835297 May 21 01:15:48 PM PDT 24 May 21 01:15:53 PM PDT 24 94699517 ps
T569 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.219257146 May 21 01:15:39 PM PDT 24 May 21 01:15:44 PM PDT 24 181442186 ps
T570 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1884699562 May 21 01:15:33 PM PDT 24 May 21 01:30:29 PM PDT 24 174410170047 ps
T571 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.677960573 May 21 01:15:37 PM PDT 24 May 21 01:15:41 PM PDT 24 23093232 ps
T572 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1303510884 May 21 01:15:22 PM PDT 24 May 21 01:15:24 PM PDT 24 27922135 ps
T573 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3347556861 May 21 01:15:36 PM PDT 24 May 21 01:15:41 PM PDT 24 55240010 ps
T574 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3769534647 May 21 01:15:39 PM PDT 24 May 21 01:15:43 PM PDT 24 35431557 ps
T117 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2908320218 May 21 01:15:34 PM PDT 24 May 21 01:15:41 PM PDT 24 127956617 ps
T575 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.759268145 May 21 01:15:33 PM PDT 24 May 21 01:15:36 PM PDT 24 326202475 ps
T576 /workspace/coverage/cover_reg_top/29.hmac_intr_test.370552711 May 21 01:15:47 PM PDT 24 May 21 01:15:50 PM PDT 24 19630568 ps
T577 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1956473612 May 21 01:15:46 PM PDT 24 May 21 01:15:50 PM PDT 24 15329446 ps
T578 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4104619938 May 21 01:15:34 PM PDT 24 May 21 01:15:40 PM PDT 24 819317115 ps
T579 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3952948335 May 21 01:15:45 PM PDT 24 May 21 01:15:48 PM PDT 24 36926406 ps
T580 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1326805732 May 21 01:15:33 PM PDT 24 May 21 01:15:35 PM PDT 24 54844697 ps
T581 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.554369435 May 21 01:15:38 PM PDT 24 May 21 01:15:43 PM PDT 24 234713322 ps
T582 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.901970435 May 21 01:15:33 PM PDT 24 May 21 01:15:38 PM PDT 24 588981525 ps
T583 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4211121095 May 21 01:15:40 PM PDT 24 May 21 01:15:43 PM PDT 24 28555866 ps
T584 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.60603954 May 21 01:15:32 PM PDT 24 May 21 01:15:35 PM PDT 24 144861598 ps
T585 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3140627190 May 21 01:15:38 PM PDT 24 May 21 01:15:44 PM PDT 24 355685239 ps
T586 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4119185751 May 21 01:15:40 PM PDT 24 May 21 01:15:44 PM PDT 24 52575917 ps
T587 /workspace/coverage/cover_reg_top/6.hmac_intr_test.806520163 May 21 01:15:38 PM PDT 24 May 21 01:15:42 PM PDT 24 14569108 ps
T588 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3434520275 May 21 01:15:40 PM PDT 24 May 21 01:15:44 PM PDT 24 157263862 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1165414869 May 21 01:15:13 PM PDT 24 May 21 01:15:14 PM PDT 24 37407703 ps
T590 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3213918060 May 21 01:15:38 PM PDT 24 May 21 01:15:43 PM PDT 24 92182554 ps
T591 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3082632584 May 21 01:15:36 PM PDT 24 May 21 01:15:39 PM PDT 24 45719341 ps
T592 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4226719727 May 21 01:15:47 PM PDT 24 May 21 01:15:51 PM PDT 24 37790381 ps
T97 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1185049251 May 21 01:15:38 PM PDT 24 May 21 01:15:42 PM PDT 24 47707823 ps
T593 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1177283125 May 21 01:15:36 PM PDT 24 May 21 01:15:49 PM PDT 24 1402157309 ps
T594 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1617306646 May 21 01:15:13 PM PDT 24 May 21 01:15:25 PM PDT 24 2997545677 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2947308672 May 21 01:15:22 PM PDT 24 May 21 01:15:24 PM PDT 24 24286834 ps

Test location /workspace/coverage/default/41.hmac_smoke.378781868
Short name T10
Test name
Test status
Simulation time 105591336 ps
CPU time 3.64 seconds
Started May 21 01:53:11 PM PDT 24
Finished May 21 01:53:16 PM PDT 24
Peak memory 200648 kb
Host smart-499b5f91-3162-4b24-9564-6333cd3b6808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378781868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.378781868
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.4144061344
Short name T19
Test name
Test status
Simulation time 25602735360 ps
CPU time 471.43 seconds
Started May 21 01:51:36 PM PDT 24
Finished May 21 01:59:29 PM PDT 24
Peak memory 200676 kb
Host smart-26657fe1-d4a0-4265-9c30-1ffdbf7326a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144061344 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.4144061344
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.4261923812
Short name T15
Test name
Test status
Simulation time 87657925682 ps
CPU time 1149.45 seconds
Started May 21 01:52:43 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 712704 kb
Host smart-9f4eaa28-95d1-4861-99ca-c6f12620b451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261923812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.4261923812
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3378943538
Short name T18
Test name
Test status
Simulation time 85921518715 ps
CPU time 3369.66 seconds
Started May 21 01:49:45 PM PDT 24
Finished May 21 02:45:56 PM PDT 24
Peak memory 810936 kb
Host smart-146bd7fc-5d7f-46a9-95e4-692dde945c29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378943538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3378943538
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.665059148
Short name T26
Test name
Test status
Simulation time 708520465 ps
CPU time 0.93 seconds
Started May 21 01:49:06 PM PDT 24
Finished May 21 01:49:08 PM PDT 24
Peak memory 218928 kb
Host smart-58446495-5fc8-41c5-873e-3366d46c3631
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665059148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.665059148
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3283138943
Short name T53
Test name
Test status
Simulation time 102129604 ps
CPU time 1.9 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:37 PM PDT 24
Peak memory 200060 kb
Host smart-64e297bb-261c-4440-aec1-365ad1e0b222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283138943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3283138943
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.852914614
Short name T47
Test name
Test status
Simulation time 731586113 ps
CPU time 39.42 seconds
Started May 21 01:49:52 PM PDT 24
Finished May 21 01:50:32 PM PDT 24
Peak memory 208884 kb
Host smart-2ba43959-2139-447a-9a1b-1a3a2f19fc7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852914614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.852914614
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3532836597
Short name T86
Test name
Test status
Simulation time 1259344808 ps
CPU time 6.38 seconds
Started May 21 01:15:17 PM PDT 24
Finished May 21 01:15:24 PM PDT 24
Peak memory 199928 kb
Host smart-e12cd796-430b-48ef-ab6b-93ab8fc31a78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532836597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3532836597
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1835966390
Short name T12
Test name
Test status
Simulation time 1871812399 ps
CPU time 50.86 seconds
Started May 21 01:51:55 PM PDT 24
Finished May 21 01:52:46 PM PDT 24
Peak memory 200648 kb
Host smart-4d470e8b-ce6a-4cfe-964c-21a30253e6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835966390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1835966390
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1371955332
Short name T116
Test name
Test status
Simulation time 193500095 ps
CPU time 3.17 seconds
Started May 21 01:15:21 PM PDT 24
Finished May 21 01:15:25 PM PDT 24
Peak memory 200116 kb
Host smart-3064317c-fe1c-4634-bd2e-07c2a3b0f260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371955332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1371955332
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1767784531
Short name T141
Test name
Test status
Simulation time 20314369 ps
CPU time 0.6 seconds
Started May 21 01:49:28 PM PDT 24
Finished May 21 01:49:36 PM PDT 24
Peak memory 197124 kb
Host smart-41dfc611-e42d-4d5f-b4b2-877d4fc34fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767784531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1767784531
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.774235992
Short name T103
Test name
Test status
Simulation time 11565257367 ps
CPU time 608.07 seconds
Started May 21 01:52:08 PM PDT 24
Finished May 21 02:02:17 PM PDT 24
Peak memory 685896 kb
Host smart-dab02070-65d1-4869-90db-7a67bac02936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774235992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.774235992
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1395366161
Short name T102
Test name
Test status
Simulation time 133675905561 ps
CPU time 1796.61 seconds
Started May 21 01:50:04 PM PDT 24
Finished May 21 02:20:02 PM PDT 24
Peak memory 745028 kb
Host smart-d222f173-a1be-45fe-9cd7-4bfa9ed5b709
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395366161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1395366161
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2799498891
Short name T59
Test name
Test status
Simulation time 541052288 ps
CPU time 4.09 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:42 PM PDT 24
Peak memory 199988 kb
Host smart-3b42bcd4-ce59-4e8b-9bc4-99c65b807f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799498891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2799498891
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2884552687
Short name T54
Test name
Test status
Simulation time 366916789 ps
CPU time 2.64 seconds
Started May 21 01:15:13 PM PDT 24
Finished May 21 01:15:16 PM PDT 24
Peak memory 200004 kb
Host smart-867a04c0-4361-47d4-8b4a-3603bd6ae314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884552687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2884552687
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.770659455
Short name T491
Test name
Test status
Simulation time 37439673 ps
CPU time 0.63 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 194932 kb
Host smart-18aa3c7c-16e9-45af-8518-bc63087ac1db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770659455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.770659455
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/default/1.hmac_smoke.1038992314
Short name T106
Test name
Test status
Simulation time 1205128333 ps
CPU time 4.77 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:49:27 PM PDT 24
Peak memory 200620 kb
Host smart-b3d4fff7-2042-4573-b8f6-7fd6ae669539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038992314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1038992314
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3852085402
Short name T147
Test name
Test status
Simulation time 2082428475 ps
CPU time 24.23 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:49:58 PM PDT 24
Peak memory 200536 kb
Host smart-6d71a040-9dcf-472f-a9bb-24c79348b8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852085402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3852085402
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4119966005
Short name T58
Test name
Test status
Simulation time 374799896 ps
CPU time 3.85 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 200056 kb
Host smart-dfbdd098-0e40-48a9-8eda-427405bb3adb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119966005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4119966005
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1617306646
Short name T594
Test name
Test status
Simulation time 2997545677 ps
CPU time 11.37 seconds
Started May 21 01:15:13 PM PDT 24
Finished May 21 01:15:25 PM PDT 24
Peak memory 200036 kb
Host smart-c5ed52eb-a579-4e39-973a-6c16603a8e36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617306646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1617306646
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1165414869
Short name T589
Test name
Test status
Simulation time 37407703 ps
CPU time 0.79 seconds
Started May 21 01:15:13 PM PDT 24
Finished May 21 01:15:14 PM PDT 24
Peak memory 197544 kb
Host smart-429923a2-c7f0-4545-8641-6436f969fdb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165414869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1165414869
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2328910657
Short name T508
Test name
Test status
Simulation time 134204519 ps
CPU time 3.83 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 199964 kb
Host smart-54e203dd-aa82-477a-8639-1bda34027b0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328910657 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2328910657
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1029244319
Short name T485
Test name
Test status
Simulation time 46035126 ps
CPU time 0.98 seconds
Started May 21 01:15:15 PM PDT 24
Finished May 21 01:15:16 PM PDT 24
Peak memory 199776 kb
Host smart-068fe5b2-5b53-4245-bb19-1fd15d878ee0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029244319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1029244319
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1450067481
Short name T495
Test name
Test status
Simulation time 33700946 ps
CPU time 0.66 seconds
Started May 21 01:15:17 PM PDT 24
Finished May 21 01:15:18 PM PDT 24
Peak memory 194884 kb
Host smart-78e809fd-0c5d-4942-9bc7-2468f49a9cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450067481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1450067481
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2471602153
Short name T547
Test name
Test status
Simulation time 53322879 ps
CPU time 2.29 seconds
Started May 21 01:15:13 PM PDT 24
Finished May 21 01:15:16 PM PDT 24
Peak memory 199864 kb
Host smart-be2db7d2-326c-47d6-be7e-9e5636fc5c6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471602153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2471602153
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1701871534
Short name T481
Test name
Test status
Simulation time 477395601 ps
CPU time 4.23 seconds
Started May 21 01:15:15 PM PDT 24
Finished May 21 01:15:19 PM PDT 24
Peak memory 200120 kb
Host smart-e339ff82-5902-4beb-b6d5-e8d87ab8c348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701871534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1701871534
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.490053327
Short name T96
Test name
Test status
Simulation time 356365623 ps
CPU time 6.18 seconds
Started May 21 01:15:19 PM PDT 24
Finished May 21 01:15:26 PM PDT 24
Peak memory 199976 kb
Host smart-c87d577e-63a7-4676-b0e7-ead92594aed2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490053327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.490053327
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4264899577
Short name T93
Test name
Test status
Simulation time 229667197 ps
CPU time 5.28 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:26 PM PDT 24
Peak memory 199964 kb
Host smart-8768eaa9-88b5-4dfd-9414-8445d407f5aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264899577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4264899577
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.595975412
Short name T501
Test name
Test status
Simulation time 109545165 ps
CPU time 0.92 seconds
Started May 21 01:15:19 PM PDT 24
Finished May 21 01:15:22 PM PDT 24
Peak memory 199192 kb
Host smart-acc4b386-e7b9-4846-b916-f2353c4f97cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595975412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.595975412
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1082383834
Short name T75
Test name
Test status
Simulation time 127781020 ps
CPU time 1.33 seconds
Started May 21 01:15:22 PM PDT 24
Finished May 21 01:15:24 PM PDT 24
Peak memory 199816 kb
Host smart-4ff39f5e-6208-43a3-9403-9545977cdfcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082383834 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1082383834
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2947308672
Short name T98
Test name
Test status
Simulation time 24286834 ps
CPU time 0.81 seconds
Started May 21 01:15:22 PM PDT 24
Finished May 21 01:15:24 PM PDT 24
Peak memory 199812 kb
Host smart-881ee80b-a132-40d0-aaef-1ceb7b61317b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947308672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2947308672
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.520409825
Short name T109
Test name
Test status
Simulation time 42468426 ps
CPU time 0.6 seconds
Started May 21 01:15:19 PM PDT 24
Finished May 21 01:15:21 PM PDT 24
Peak memory 194916 kb
Host smart-cb566791-c4f3-4b3b-9f3a-d7d5ccfc9117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520409825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.520409825
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.216676867
Short name T476
Test name
Test status
Simulation time 397162861 ps
CPU time 2.32 seconds
Started May 21 01:15:19 PM PDT 24
Finished May 21 01:15:23 PM PDT 24
Peak memory 199828 kb
Host smart-c5d89add-6fee-4c63-9bb0-7d350d808c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216676867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.216676867
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4026279878
Short name T533
Test name
Test status
Simulation time 639571384 ps
CPU time 4.15 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:25 PM PDT 24
Peak memory 200116 kb
Host smart-40812cd1-0469-429c-9539-4aced3698181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026279878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4026279878
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1954308412
Short name T545
Test name
Test status
Simulation time 96863316 ps
CPU time 3 seconds
Started May 21 01:15:22 PM PDT 24
Finished May 21 01:15:26 PM PDT 24
Peak memory 200052 kb
Host smart-4ea7a2f2-e65a-4d8b-8c30-57857d1cfe27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954308412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1954308412
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1915340726
Short name T82
Test name
Test status
Simulation time 139851057 ps
CPU time 1.26 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:37 PM PDT 24
Peak memory 199864 kb
Host smart-22c15ee0-4394-4c59-9429-71c3eacef35d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915340726 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1915340726
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3274094951
Short name T84
Test name
Test status
Simulation time 31212205 ps
CPU time 0.97 seconds
Started May 21 01:15:32 PM PDT 24
Finished May 21 01:15:34 PM PDT 24
Peak memory 199620 kb
Host smart-e58e7a74-bfe8-483d-b0ae-5d795f510fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274094951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3274094951
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3374689210
Short name T475
Test name
Test status
Simulation time 16428547 ps
CPU time 0.59 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:38 PM PDT 24
Peak memory 194900 kb
Host smart-4b88f659-c794-4317-9d0c-b4faa00dc1a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374689210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3374689210
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.759268145
Short name T575
Test name
Test status
Simulation time 326202475 ps
CPU time 1.82 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:36 PM PDT 24
Peak memory 199876 kb
Host smart-8276cefe-9764-4a9e-a465-dbc540367220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759268145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.759268145
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3347556861
Short name T573
Test name
Test status
Simulation time 55240010 ps
CPU time 2.96 seconds
Started May 21 01:15:36 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 200080 kb
Host smart-991b18ec-9e2e-4319-a872-8dc8bf3fe35b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347556861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3347556861
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1761664954
Short name T112
Test name
Test status
Simulation time 857177869 ps
CPU time 4.23 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:42 PM PDT 24
Peak memory 200080 kb
Host smart-e6f4c916-6fe1-4fa4-9a0a-e26d99b4c197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761664954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1761664954
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2229308181
Short name T567
Test name
Test status
Simulation time 31257453124 ps
CPU time 181.45 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:18:37 PM PDT 24
Peak memory 216596 kb
Host smart-c97987f1-1126-468c-8164-3b6192c43e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229308181 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2229308181
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2154688512
Short name T91
Test name
Test status
Simulation time 53113120 ps
CPU time 0.9 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:36 PM PDT 24
Peak memory 199832 kb
Host smart-cff5138b-1efd-4a4f-9511-885050a0e0c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154688512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2154688512
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.789139779
Short name T524
Test name
Test status
Simulation time 12384935 ps
CPU time 0.59 seconds
Started May 21 01:16:05 PM PDT 24
Finished May 21 01:16:06 PM PDT 24
Peak memory 194884 kb
Host smart-f84af443-d09b-4a1d-bcd2-9536623a827b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789139779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.789139779
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2911519426
Short name T555
Test name
Test status
Simulation time 45825834 ps
CPU time 1.19 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:42 PM PDT 24
Peak memory 200040 kb
Host smart-acb4f3c7-913a-4b5e-978c-69c8c15c02ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911519426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2911519426
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3739093789
Short name T64
Test name
Test status
Simulation time 598031991 ps
CPU time 3.15 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 200188 kb
Host smart-0481c1a2-33dc-4955-996d-26df2ae4b954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739093789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3739093789
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3586394892
Short name T554
Test name
Test status
Simulation time 53523726 ps
CPU time 1.11 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 199780 kb
Host smart-f6a5fb5f-a63c-4dcb-b117-56a0e276e866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586394892 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3586394892
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.850337603
Short name T510
Test name
Test status
Simulation time 90355070 ps
CPU time 0.72 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 197548 kb
Host smart-e46d820e-4364-4ca0-9bc1-c94f7df9f444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850337603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.850337603
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1652653394
Short name T483
Test name
Test status
Simulation time 40319040 ps
CPU time 1.64 seconds
Started May 21 01:15:49 PM PDT 24
Finished May 21 01:15:54 PM PDT 24
Peak memory 200008 kb
Host smart-be1b5d4f-ab19-4d1b-80fb-fca17e195c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652653394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1652653394
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.282160443
Short name T494
Test name
Test status
Simulation time 330430743 ps
CPU time 1.9 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 200092 kb
Host smart-a99c4986-284b-4040-abb1-e6c25957ff7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282160443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.282160443
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3234988675
Short name T556
Test name
Test status
Simulation time 165616874 ps
CPU time 2.47 seconds
Started May 21 01:15:36 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 200104 kb
Host smart-b193c4fd-4d4c-48e5-90f8-bca19c0f39a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234988675 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3234988675
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2264706111
Short name T528
Test name
Test status
Simulation time 21216048 ps
CPU time 0.79 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 197348 kb
Host smart-3a7b41f3-a7aa-49d3-a37b-1f86db0299e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264706111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2264706111
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1349979000
Short name T541
Test name
Test status
Simulation time 41822173 ps
CPU time 0.63 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 194968 kb
Host smart-001ea19f-53f1-47eb-95f0-0a2b967b3626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349979000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1349979000
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1868510556
Short name T535
Test name
Test status
Simulation time 124442939 ps
CPU time 1.6 seconds
Started May 21 01:15:41 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 199804 kb
Host smart-f1ef130a-9ca3-4e80-bd3b-d266d761e9ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868510556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1868510556
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.984870737
Short name T500
Test name
Test status
Simulation time 318236684 ps
CPU time 3.1 seconds
Started May 21 01:15:41 PM PDT 24
Finished May 21 01:15:46 PM PDT 24
Peak memory 200108 kb
Host smart-ef8fef00-6de8-4a3a-9be7-e79b31ac83df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984870737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.984870737
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4251024755
Short name T544
Test name
Test status
Simulation time 639524826 ps
CPU time 2.83 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 199976 kb
Host smart-37a2e362-23ca-497e-b9a5-617840f190b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251024755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4251024755
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2247655885
Short name T504
Test name
Test status
Simulation time 55912953 ps
CPU time 1.74 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 200096 kb
Host smart-b54a01f8-ab0c-466e-81fc-10491c995f78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247655885 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2247655885
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3368945953
Short name T90
Test name
Test status
Simulation time 52992022 ps
CPU time 0.84 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 199996 kb
Host smart-53c90890-f222-4482-be1d-45cd2175da97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368945953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3368945953
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4211121095
Short name T583
Test name
Test status
Simulation time 28555866 ps
CPU time 0.64 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 194956 kb
Host smart-e5a00351-236a-4584-b913-87aa7a968e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211121095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4211121095
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1999643944
Short name T507
Test name
Test status
Simulation time 319656832 ps
CPU time 1.76 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 199956 kb
Host smart-6b6e5e7c-6899-4bba-a495-e5180ecd587d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999643944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1999643944
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4059104799
Short name T490
Test name
Test status
Simulation time 41733197 ps
CPU time 2.32 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 200076 kb
Host smart-08fa0d28-6250-478d-bc89-795703540d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059104799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4059104799
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3140627190
Short name T585
Test name
Test status
Simulation time 355685239 ps
CPU time 3.09 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 200064 kb
Host smart-5ad6cfac-9842-4e47-bfce-e1055d41dbff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140627190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3140627190
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2845181787
Short name T527
Test name
Test status
Simulation time 319152146 ps
CPU time 2.19 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 200104 kb
Host smart-b098972a-7c2d-470a-b366-08fee33eaf84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845181787 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2845181787
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3769534647
Short name T574
Test name
Test status
Simulation time 35431557 ps
CPU time 0.96 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 199348 kb
Host smart-2639914a-efb2-4e99-8dc5-184c2b8ff599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769534647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3769534647
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3195304034
Short name T479
Test name
Test status
Simulation time 11711816 ps
CPU time 0.57 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 194880 kb
Host smart-5ad1f2e0-972a-457b-84e0-c52ab6f382ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195304034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3195304034
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2854445693
Short name T497
Test name
Test status
Simulation time 254711119 ps
CPU time 2.45 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 200084 kb
Host smart-bdf5c16d-31f5-4c00-a1ba-6954375970e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854445693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2854445693
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.554369435
Short name T581
Test name
Test status
Simulation time 234713322 ps
CPU time 1.69 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 200148 kb
Host smart-0b6eda6e-8bdf-4481-bb47-4ad0dab48849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554369435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.554369435
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3190848292
Short name T110
Test name
Test status
Simulation time 163807286 ps
CPU time 3.26 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:46 PM PDT 24
Peak memory 199984 kb
Host smart-ba7c2d51-b9c3-4197-a734-6a9ec5e0e9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190848292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3190848292
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3900489287
Short name T506
Test name
Test status
Simulation time 28537544 ps
CPU time 1.96 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 200100 kb
Host smart-457678cc-92ba-40a1-9442-9145e1cc6119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900489287 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3900489287
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1185049251
Short name T97
Test name
Test status
Simulation time 47707823 ps
CPU time 0.86 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:42 PM PDT 24
Peak memory 199316 kb
Host smart-8d1fa3d6-cad5-4d78-ba97-274941434704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185049251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1185049251
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.359925588
Short name T538
Test name
Test status
Simulation time 15336757 ps
CPU time 0.62 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 194916 kb
Host smart-60cc3faf-36b0-4ad8-af3b-5f0fcb508cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359925588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.359925588
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.219257146
Short name T569
Test name
Test status
Simulation time 181442186 ps
CPU time 1.67 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 199948 kb
Host smart-2f528cd6-7526-4136-bfff-71d422ab3fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219257146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.219257146
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1932571721
Short name T65
Test name
Test status
Simulation time 76403625 ps
CPU time 3.9 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:46 PM PDT 24
Peak memory 200036 kb
Host smart-c34b4084-0392-405f-ab47-584997021438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932571721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1932571721
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.37164987
Short name T113
Test name
Test status
Simulation time 1138333856 ps
CPU time 4.19 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:46 PM PDT 24
Peak memory 200028 kb
Host smart-f236effd-f864-4045-ae99-09fc02b3da0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37164987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.37164987
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3434520275
Short name T588
Test name
Test status
Simulation time 157263862 ps
CPU time 1.22 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 199868 kb
Host smart-d5be0faa-1c19-4350-8832-7be0af2cab02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434520275 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3434520275
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4119185751
Short name T586
Test name
Test status
Simulation time 52575917 ps
CPU time 0.96 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 199664 kb
Host smart-71e33804-b6e7-4f6d-ba50-2640d3b4d738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119185751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.4119185751
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.851428680
Short name T482
Test name
Test status
Simulation time 36918628 ps
CPU time 0.56 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 194968 kb
Host smart-0084914d-b301-4f67-a8d5-577d928a82e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851428680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.851428680
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3213918060
Short name T590
Test name
Test status
Simulation time 92182554 ps
CPU time 1.62 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 200032 kb
Host smart-63b48e70-2f8b-4c1c-bf0a-bc5921965921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213918060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3213918060
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2623259838
Short name T552
Test name
Test status
Simulation time 55151362 ps
CPU time 2.69 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 200040 kb
Host smart-0c455676-e6dd-4f1a-820a-2734c76c45da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623259838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2623259838
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1825893806
Short name T553
Test name
Test status
Simulation time 89915834 ps
CPU time 2.78 seconds
Started May 21 01:15:39 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 200072 kb
Host smart-f44e0bb0-6a7e-4808-9c8c-a0f6b39d4ced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825893806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1825893806
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1993945442
Short name T477
Test name
Test status
Simulation time 236226741248 ps
CPU time 646.05 seconds
Started May 21 01:15:42 PM PDT 24
Finished May 21 01:26:30 PM PDT 24
Peak memory 216592 kb
Host smart-5b819276-9f37-4cac-9431-0e73c29f9073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993945442 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1993945442
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2071804054
Short name T92
Test name
Test status
Simulation time 32585024 ps
CPU time 0.93 seconds
Started May 21 01:15:44 PM PDT 24
Finished May 21 01:15:46 PM PDT 24
Peak memory 199708 kb
Host smart-6e921646-202c-4d26-aa71-d80518e26a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071804054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2071804054
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3268268120
Short name T511
Test name
Test status
Simulation time 19593245 ps
CPU time 0.63 seconds
Started May 21 01:15:59 PM PDT 24
Finished May 21 01:16:00 PM PDT 24
Peak memory 194828 kb
Host smart-b7714b4d-30ef-4b7f-b731-dba26377000a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268268120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3268268120
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2814958328
Short name T499
Test name
Test status
Simulation time 83698270 ps
CPU time 1.85 seconds
Started May 21 01:15:44 PM PDT 24
Finished May 21 01:15:47 PM PDT 24
Peak memory 199860 kb
Host smart-e83f9879-71d9-40e4-b3f4-a0ecd606f992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814958328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2814958328
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1466957550
Short name T63
Test name
Test status
Simulation time 33731570 ps
CPU time 1.82 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 200144 kb
Host smart-2e881627-4e83-4164-869a-bf315c455071
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466957550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1466957550
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1216477819
Short name T114
Test name
Test status
Simulation time 128798624 ps
CPU time 3.85 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 199976 kb
Host smart-9b93b14d-6b90-4cd0-a1d7-fbca8e6b6f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216477819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1216477819
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4176216775
Short name T61
Test name
Test status
Simulation time 38758725 ps
CPU time 1.19 seconds
Started May 21 01:15:45 PM PDT 24
Finished May 21 01:15:47 PM PDT 24
Peak memory 199916 kb
Host smart-9ca5d1a4-770d-4085-8f3f-f0ea54c464ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176216775 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4176216775
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.398113363
Short name T89
Test name
Test status
Simulation time 39850915 ps
CPU time 0.91 seconds
Started May 21 01:15:49 PM PDT 24
Finished May 21 01:15:53 PM PDT 24
Peak memory 199356 kb
Host smart-ec25dee4-a2c3-4606-b6b6-4c6a68413778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398113363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.398113363
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3684684360
Short name T519
Test name
Test status
Simulation time 49674659 ps
CPU time 0.58 seconds
Started May 21 01:15:49 PM PDT 24
Finished May 21 01:15:52 PM PDT 24
Peak memory 194876 kb
Host smart-6b8d5429-a807-4606-ab5f-1acd0225e4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684684360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3684684360
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3731835297
Short name T568
Test name
Test status
Simulation time 94699517 ps
CPU time 2.27 seconds
Started May 21 01:15:48 PM PDT 24
Finished May 21 01:15:53 PM PDT 24
Peak memory 200048 kb
Host smart-eec00242-9754-4d26-a1e8-bc485e6c44f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731835297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3731835297
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1595065987
Short name T559
Test name
Test status
Simulation time 72889403 ps
CPU time 1.8 seconds
Started May 21 01:15:45 PM PDT 24
Finished May 21 01:15:49 PM PDT 24
Peak memory 200140 kb
Host smart-66c89542-05ce-4d69-bfe7-c09e7392a074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595065987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1595065987
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.756997675
Short name T111
Test name
Test status
Simulation time 121476049 ps
CPU time 1.81 seconds
Started May 21 01:15:46 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 200056 kb
Host smart-df7cb814-fe10-4129-93dd-bdbc152a0050
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756997675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.756997675
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1156460340
Short name T87
Test name
Test status
Simulation time 386438141 ps
CPU time 6 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:27 PM PDT 24
Peak memory 199980 kb
Host smart-93b6ae75-dbe3-46e6-ab51-da2e91660aea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156460340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1156460340
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1108341324
Short name T79
Test name
Test status
Simulation time 2532968849 ps
CPU time 5.99 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:27 PM PDT 24
Peak memory 199320 kb
Host smart-74ca81a7-8e6a-44c5-bded-ae6428bc88de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108341324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1108341324
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3202933341
Short name T558
Test name
Test status
Simulation time 20855575 ps
CPU time 0.97 seconds
Started May 21 01:15:18 PM PDT 24
Finished May 21 01:15:19 PM PDT 24
Peak memory 200040 kb
Host smart-1f400f78-6bd8-44b4-9277-f21eb5697c75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202933341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3202933341
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1261067858
Short name T522
Test name
Test status
Simulation time 39503442 ps
CPU time 1.13 seconds
Started May 21 01:15:22 PM PDT 24
Finished May 21 01:15:24 PM PDT 24
Peak memory 199812 kb
Host smart-36068e5a-e425-415c-8fe9-ca19c07a7eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261067858 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1261067858
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1616448153
Short name T486
Test name
Test status
Simulation time 67825273 ps
CPU time 0.72 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:22 PM PDT 24
Peak memory 198040 kb
Host smart-bb8fe344-c10e-4c52-8c1b-815e9a9c8b78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616448153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1616448153
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2486558030
Short name T487
Test name
Test status
Simulation time 13599845 ps
CPU time 0.64 seconds
Started May 21 01:15:19 PM PDT 24
Finished May 21 01:15:21 PM PDT 24
Peak memory 194996 kb
Host smart-0829a47c-4e79-4278-bcee-8c482001eabb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486558030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2486558030
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3821898089
Short name T515
Test name
Test status
Simulation time 154676481 ps
CPU time 1.19 seconds
Started May 21 01:15:18 PM PDT 24
Finished May 21 01:15:20 PM PDT 24
Peak memory 198252 kb
Host smart-e8791a4b-185e-4b55-b4a3-476003fe397c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821898089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3821898089
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.722860628
Short name T62
Test name
Test status
Simulation time 311542956 ps
CPU time 3.91 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:25 PM PDT 24
Peak memory 200140 kb
Host smart-81b73dbc-0ab0-4e92-89c1-c0968f15b742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722860628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.722860628
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1742097820
Short name T550
Test name
Test status
Simulation time 24833828 ps
CPU time 0.57 seconds
Started May 21 01:15:45 PM PDT 24
Finished May 21 01:15:47 PM PDT 24
Peak memory 194868 kb
Host smart-ace2569c-da74-48d6-b9a8-2481f3998fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742097820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1742097820
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3577246613
Short name T493
Test name
Test status
Simulation time 41130182 ps
CPU time 0.61 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 194580 kb
Host smart-312d4812-9b38-476f-883a-76d80614864a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577246613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3577246613
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1399418238
Short name T502
Test name
Test status
Simulation time 16052843 ps
CPU time 0.62 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 194944 kb
Host smart-a4b39f93-f4fb-4fc4-90c9-1781a7742478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399418238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1399418238
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2427029734
Short name T107
Test name
Test status
Simulation time 15778191 ps
CPU time 0.63 seconds
Started May 21 01:15:44 PM PDT 24
Finished May 21 01:15:46 PM PDT 24
Peak memory 194936 kb
Host smart-657ad422-0a1a-4c1c-bc75-3144e158cd8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427029734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2427029734
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.229860089
Short name T77
Test name
Test status
Simulation time 17282575 ps
CPU time 0.6 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 194992 kb
Host smart-c9652800-973e-40b3-9fa8-244491e3efa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229860089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.229860089
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2474326879
Short name T546
Test name
Test status
Simulation time 63262520 ps
CPU time 0.62 seconds
Started May 21 01:15:48 PM PDT 24
Finished May 21 01:15:52 PM PDT 24
Peak memory 194844 kb
Host smart-bf67f530-4889-4483-a571-63de1e6aa054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474326879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2474326879
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1956473612
Short name T577
Test name
Test status
Simulation time 15329446 ps
CPU time 0.61 seconds
Started May 21 01:15:46 PM PDT 24
Finished May 21 01:15:50 PM PDT 24
Peak memory 195040 kb
Host smart-76f24e51-c04f-4559-81c9-d1ba6436d914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956473612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1956473612
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.861736746
Short name T498
Test name
Test status
Simulation time 12719528 ps
CPU time 0.63 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 194912 kb
Host smart-903a0ed7-74e5-4b98-a979-b4383f773092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861736746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.861736746
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.562634202
Short name T512
Test name
Test status
Simulation time 20104680 ps
CPU time 0.64 seconds
Started May 21 01:15:49 PM PDT 24
Finished May 21 01:15:52 PM PDT 24
Peak memory 194872 kb
Host smart-ee10d2d2-33e8-4c58-92a1-e5fb712dbda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562634202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.562634202
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.370552711
Short name T576
Test name
Test status
Simulation time 19630568 ps
CPU time 0.64 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:50 PM PDT 24
Peak memory 194984 kb
Host smart-41491519-7c50-4b56-873b-ff8ff05fff62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370552711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.370552711
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3615703744
Short name T94
Test name
Test status
Simulation time 188142889 ps
CPU time 3.4 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 199988 kb
Host smart-fc1e3452-6f7d-4ecd-ae91-5a8283418c40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615703744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3615703744
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1177283125
Short name T593
Test name
Test status
Simulation time 1402157309 ps
CPU time 10.57 seconds
Started May 21 01:15:36 PM PDT 24
Finished May 21 01:15:49 PM PDT 24
Peak memory 199916 kb
Host smart-dd6bd667-1c28-4603-a74d-6505b733cdf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177283125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1177283125
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2761858638
Short name T95
Test name
Test status
Simulation time 53068641 ps
CPU time 1.02 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:22 PM PDT 24
Peak memory 199860 kb
Host smart-ddef199f-1423-4eff-a87e-85cbbc337010
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761858638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2761858638
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.77437002
Short name T532
Test name
Test status
Simulation time 82049699 ps
CPU time 1.33 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 199984 kb
Host smart-8c4022df-ccf4-4fb7-a9da-5c9e4808cfdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77437002 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.77437002
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1430654585
Short name T60
Test name
Test status
Simulation time 32725145 ps
CPU time 1 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:38 PM PDT 24
Peak memory 199604 kb
Host smart-0a4180d4-5ed4-4807-8829-a456897970ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430654585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1430654585
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1303510884
Short name T572
Test name
Test status
Simulation time 27922135 ps
CPU time 0.66 seconds
Started May 21 01:15:22 PM PDT 24
Finished May 21 01:15:24 PM PDT 24
Peak memory 194848 kb
Host smart-df67666f-43b0-47f6-87de-5c7c4cfab712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303510884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1303510884
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.404986028
Short name T526
Test name
Test status
Simulation time 322871668 ps
CPU time 1.9 seconds
Started May 21 01:15:24 PM PDT 24
Finished May 21 01:15:27 PM PDT 24
Peak memory 199768 kb
Host smart-e601fee9-b78c-4f0b-9055-f28ab896c910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404986028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.404986028
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3083110975
Short name T489
Test name
Test status
Simulation time 91797207 ps
CPU time 2.05 seconds
Started May 21 01:15:21 PM PDT 24
Finished May 21 01:15:24 PM PDT 24
Peak memory 200132 kb
Host smart-64c2b77c-a135-418b-a70e-8bef38e8008f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083110975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3083110975
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3714349193
Short name T52
Test name
Test status
Simulation time 180420114 ps
CPU time 1.89 seconds
Started May 21 01:15:20 PM PDT 24
Finished May 21 01:15:23 PM PDT 24
Peak memory 200032 kb
Host smart-0aadf2db-460e-4e95-b7ec-8dd08cf9782a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714349193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3714349193
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4226719727
Short name T592
Test name
Test status
Simulation time 37790381 ps
CPU time 0.6 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 194988 kb
Host smart-29b6042b-79e6-4ff0-921b-808fef5a4625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226719727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4226719727
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3577365042
Short name T551
Test name
Test status
Simulation time 66914286 ps
CPU time 0.57 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 194900 kb
Host smart-5353be63-0082-4e7f-8325-9da9e8580aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577365042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3577365042
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1621206402
Short name T517
Test name
Test status
Simulation time 14169031 ps
CPU time 0.61 seconds
Started May 21 01:15:49 PM PDT 24
Finished May 21 01:15:53 PM PDT 24
Peak memory 194960 kb
Host smart-f0a587fc-c178-4ad0-a362-5bf82dc86f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621206402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1621206402
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1816110923
Short name T549
Test name
Test status
Simulation time 14472740 ps
CPU time 0.62 seconds
Started May 21 01:15:49 PM PDT 24
Finished May 21 01:15:53 PM PDT 24
Peak memory 194908 kb
Host smart-b854d6e6-4775-41bd-b3f9-eb238a381da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816110923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1816110923
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3671899313
Short name T565
Test name
Test status
Simulation time 13530894 ps
CPU time 0.62 seconds
Started May 21 01:15:46 PM PDT 24
Finished May 21 01:15:49 PM PDT 24
Peak memory 194864 kb
Host smart-dec8100a-3cc1-4ce6-b5da-4b41ec1c0b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671899313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3671899313
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.893760762
Short name T561
Test name
Test status
Simulation time 20297499 ps
CPU time 0.6 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:50 PM PDT 24
Peak memory 194804 kb
Host smart-a013c018-079d-4ab8-a57b-c81f803dfa32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893760762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.893760762
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3952948335
Short name T579
Test name
Test status
Simulation time 36926406 ps
CPU time 0.67 seconds
Started May 21 01:15:45 PM PDT 24
Finished May 21 01:15:48 PM PDT 24
Peak memory 194964 kb
Host smart-3725fb8e-7d96-417c-844e-361e38ff0f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952948335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3952948335
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3857940846
Short name T521
Test name
Test status
Simulation time 15764416 ps
CPU time 0.63 seconds
Started May 21 01:15:45 PM PDT 24
Finished May 21 01:15:47 PM PDT 24
Peak memory 195052 kb
Host smart-e9e4b0d0-8c38-4010-896b-aeceb8726e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857940846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3857940846
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.978602046
Short name T480
Test name
Test status
Simulation time 21718141 ps
CPU time 0.58 seconds
Started May 21 01:15:56 PM PDT 24
Finished May 21 01:15:57 PM PDT 24
Peak memory 194916 kb
Host smart-27be9808-2526-4f0f-b25e-d4ba27ca0031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978602046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.978602046
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2519982312
Short name T76
Test name
Test status
Simulation time 96601599 ps
CPU time 0.64 seconds
Started May 21 01:15:49 PM PDT 24
Finished May 21 01:15:53 PM PDT 24
Peak memory 194844 kb
Host smart-12b77f5d-4065-4dfd-9230-a128bca76457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519982312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2519982312
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.901970435
Short name T582
Test name
Test status
Simulation time 588981525 ps
CPU time 3.2 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:38 PM PDT 24
Peak memory 200044 kb
Host smart-0bca42ae-3eb3-485a-805d-c47ca53c873a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901970435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.901970435
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.7925612
Short name T85
Test name
Test status
Simulation time 217555443 ps
CPU time 9.77 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:45 PM PDT 24
Peak memory 199128 kb
Host smart-618590a4-5f7f-4883-bd05-708834c3da1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7925612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.7925612
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.677960573
Short name T571
Test name
Test status
Simulation time 23093232 ps
CPU time 0.76 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 197924 kb
Host smart-34a3e309-f21b-456c-a4bb-ca2f6683635f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677960573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.677960573
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3963729365
Short name T530
Test name
Test status
Simulation time 98627168 ps
CPU time 2.03 seconds
Started May 21 01:15:32 PM PDT 24
Finished May 21 01:15:36 PM PDT 24
Peak memory 200084 kb
Host smart-c6c227f7-54b7-44ab-ac8b-f8f841fac682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963729365 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3963729365
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3082632584
Short name T591
Test name
Test status
Simulation time 45719341 ps
CPU time 0.71 seconds
Started May 21 01:15:36 PM PDT 24
Finished May 21 01:15:39 PM PDT 24
Peak memory 198044 kb
Host smart-7f023566-2713-4632-ac28-73cb1b658607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082632584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3082632584
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4124492885
Short name T534
Test name
Test status
Simulation time 48682149 ps
CPU time 0.6 seconds
Started May 21 01:15:56 PM PDT 24
Finished May 21 01:15:58 PM PDT 24
Peak memory 194832 kb
Host smart-635ba69f-e783-43fc-aa7d-5996ca056832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124492885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4124492885
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1318875710
Short name T496
Test name
Test status
Simulation time 269848881 ps
CPU time 2.26 seconds
Started May 21 01:15:31 PM PDT 24
Finished May 21 01:15:35 PM PDT 24
Peak memory 200088 kb
Host smart-93c84c1e-91e7-49f3-a748-f7183838ac4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318875710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1318875710
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3074351929
Short name T478
Test name
Test status
Simulation time 995286054 ps
CPU time 3.89 seconds
Started May 21 01:15:56 PM PDT 24
Finished May 21 01:16:01 PM PDT 24
Peak memory 200072 kb
Host smart-ba4299f6-1e28-402f-b0cc-b3ee262fee00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074351929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3074351929
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3108238892
Short name T537
Test name
Test status
Simulation time 759803436 ps
CPU time 3.23 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:38 PM PDT 24
Peak memory 200056 kb
Host smart-6acc331e-6250-43ee-9750-25464ac3395c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108238892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3108238892
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2001690761
Short name T531
Test name
Test status
Simulation time 31268907 ps
CPU time 0.65 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 195028 kb
Host smart-ec9e28f5-93fe-4576-86c3-7dc49bff354d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001690761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2001690761
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2019773105
Short name T518
Test name
Test status
Simulation time 22088715 ps
CPU time 0.62 seconds
Started May 21 01:15:45 PM PDT 24
Finished May 21 01:15:47 PM PDT 24
Peak memory 194888 kb
Host smart-326d9994-b0da-4698-b1fd-17a2aa7cc918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019773105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2019773105
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2003968143
Short name T548
Test name
Test status
Simulation time 41996163 ps
CPU time 0.66 seconds
Started May 21 01:15:47 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 194584 kb
Host smart-005671c1-7613-48a2-88c9-a28643ceac44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003968143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2003968143
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3489268327
Short name T539
Test name
Test status
Simulation time 42930100 ps
CPU time 0.62 seconds
Started May 21 01:15:46 PM PDT 24
Finished May 21 01:15:48 PM PDT 24
Peak memory 194948 kb
Host smart-b697ad4c-86af-4f8c-bb1d-a3a4fd0672f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489268327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3489268327
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.4200679103
Short name T564
Test name
Test status
Simulation time 18204837 ps
CPU time 0.58 seconds
Started May 21 01:15:55 PM PDT 24
Finished May 21 01:15:57 PM PDT 24
Peak memory 194828 kb
Host smart-e6d64aaa-edb5-40aa-85b9-a6b8b35efd98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200679103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.4200679103
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1591076087
Short name T566
Test name
Test status
Simulation time 17739242 ps
CPU time 0.62 seconds
Started May 21 01:15:51 PM PDT 24
Finished May 21 01:15:55 PM PDT 24
Peak memory 194888 kb
Host smart-ac20a66d-33d5-43e9-944e-37ee7a5ca806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591076087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1591076087
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.232939438
Short name T492
Test name
Test status
Simulation time 20710882 ps
CPU time 0.59 seconds
Started May 21 01:15:53 PM PDT 24
Finished May 21 01:15:56 PM PDT 24
Peak memory 194860 kb
Host smart-29483b41-2e26-4d96-899e-2d7aa6e31201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232939438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.232939438
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2257014882
Short name T516
Test name
Test status
Simulation time 32158326 ps
CPU time 0.62 seconds
Started May 21 01:15:50 PM PDT 24
Finished May 21 01:15:53 PM PDT 24
Peak memory 194880 kb
Host smart-484d5067-153a-47e4-82a0-d1c7653e0962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257014882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2257014882
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.656389654
Short name T562
Test name
Test status
Simulation time 36279985 ps
CPU time 0.59 seconds
Started May 21 01:16:06 PM PDT 24
Finished May 21 01:16:08 PM PDT 24
Peak memory 194932 kb
Host smart-c38f28ff-b421-4ae7-8f47-96f758f80391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656389654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.656389654
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.871190248
Short name T525
Test name
Test status
Simulation time 58372470 ps
CPU time 0.58 seconds
Started May 21 01:15:52 PM PDT 24
Finished May 21 01:15:56 PM PDT 24
Peak memory 194860 kb
Host smart-5da37dbc-8e0a-47c7-916c-568a5e7d9b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871190248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.871190248
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2128830083
Short name T514
Test name
Test status
Simulation time 129673976 ps
CPU time 2.14 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 200068 kb
Host smart-18ff1240-425c-4031-bde9-4f19186c18e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128830083 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2128830083
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.744826691
Short name T503
Test name
Test status
Simulation time 164800945 ps
CPU time 0.7 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:36 PM PDT 24
Peak memory 197796 kb
Host smart-53587e6f-9e7c-4d21-b3ff-51d21dfd9d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744826691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.744826691
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1326805732
Short name T580
Test name
Test status
Simulation time 54844697 ps
CPU time 0.65 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:35 PM PDT 24
Peak memory 194996 kb
Host smart-c8d71146-7794-4fa5-998d-d949775db9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326805732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1326805732
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3565552515
Short name T543
Test name
Test status
Simulation time 573936971 ps
CPU time 2.5 seconds
Started May 21 01:15:36 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 200012 kb
Host smart-4e20d0c6-f055-4886-80b1-13a7e0317ee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565552515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3565552515
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3592324500
Short name T83
Test name
Test status
Simulation time 259883871 ps
CPU time 3.7 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 200104 kb
Host smart-9286953e-a68b-4bae-a9cc-86c2a732404c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592324500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3592324500
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.148428309
Short name T557
Test name
Test status
Simulation time 97355426 ps
CPU time 1.9 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:38 PM PDT 24
Peak memory 200036 kb
Host smart-dc24f19c-d54d-4572-828f-fb7e3a91d0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148428309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.148428309
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2460251384
Short name T484
Test name
Test status
Simulation time 95546843 ps
CPU time 2.79 seconds
Started May 21 01:15:31 PM PDT 24
Finished May 21 01:15:35 PM PDT 24
Peak memory 200028 kb
Host smart-bacfb1b1-1d36-4918-b0ea-1478515326bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460251384 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2460251384
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3823773648
Short name T542
Test name
Test status
Simulation time 69910197 ps
CPU time 0.72 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:38 PM PDT 24
Peak memory 197344 kb
Host smart-f886ecbc-0de8-4670-b04d-b43e40e7ce8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823773648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3823773648
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.806520163
Short name T587
Test name
Test status
Simulation time 14569108 ps
CPU time 0.63 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:42 PM PDT 24
Peak memory 194964 kb
Host smart-ae31e625-eaaa-4494-98ee-58ad132a9245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806520163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.806520163
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4104936708
Short name T513
Test name
Test status
Simulation time 101410863 ps
CPU time 1.2 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:39 PM PDT 24
Peak memory 199740 kb
Host smart-6fc4ff7e-0222-43a4-8a15-46a6504cdd6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104936708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4104936708
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1218701408
Short name T505
Test name
Test status
Simulation time 311984679 ps
CPU time 1.81 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:38 PM PDT 24
Peak memory 200132 kb
Host smart-85807c7f-eeb3-4a2f-9846-b78956520d98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218701408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1218701408
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1653877716
Short name T115
Test name
Test status
Simulation time 98995616 ps
CPU time 1.86 seconds
Started May 21 01:15:31 PM PDT 24
Finished May 21 01:15:34 PM PDT 24
Peak memory 200052 kb
Host smart-28645078-0fd7-4922-8c3e-e331eaa3933f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653877716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1653877716
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2546895248
Short name T563
Test name
Test status
Simulation time 198490768 ps
CPU time 1.86 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 199940 kb
Host smart-5b33992e-3b0d-4156-b34a-a23ba50445e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546895248 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2546895248
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.60603954
Short name T584
Test name
Test status
Simulation time 144861598 ps
CPU time 0.71 seconds
Started May 21 01:15:32 PM PDT 24
Finished May 21 01:15:35 PM PDT 24
Peak memory 198008 kb
Host smart-386d280a-3e6a-455f-8ca2-57490d399642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60603954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.60603954
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1459280593
Short name T78
Test name
Test status
Simulation time 17962706 ps
CPU time 0.63 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:36 PM PDT 24
Peak memory 195000 kb
Host smart-8ee1b005-caf3-44d6-bbc2-29308024fa26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459280593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1459280593
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3088904147
Short name T80
Test name
Test status
Simulation time 627538335 ps
CPU time 2.51 seconds
Started May 21 01:15:32 PM PDT 24
Finished May 21 01:15:36 PM PDT 24
Peak memory 200052 kb
Host smart-b5a68aaf-1665-4350-86f8-a0fccbfad153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088904147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3088904147
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4104619938
Short name T578
Test name
Test status
Simulation time 819317115 ps
CPU time 3.85 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 200104 kb
Host smart-578bf315-98c5-49d8-9b53-17fc34f8e0fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104619938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4104619938
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2908320218
Short name T117
Test name
Test status
Simulation time 127956617 ps
CPU time 4.06 seconds
Started May 21 01:15:34 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 199908 kb
Host smart-dea0b0a7-5300-4edb-b04d-20746f712e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908320218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2908320218
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1784237151
Short name T529
Test name
Test status
Simulation time 96335877 ps
CPU time 2.22 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:37 PM PDT 24
Peak memory 200036 kb
Host smart-82eed98b-e94e-4a38-aacf-efb31943b4b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784237151 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1784237151
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3156755373
Short name T88
Test name
Test status
Simulation time 17320046 ps
CPU time 0.94 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 199284 kb
Host smart-8e5718ab-fe3b-4a1c-8a47-316a8593dfe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156755373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3156755373
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1248848978
Short name T488
Test name
Test status
Simulation time 48927451 ps
CPU time 0.6 seconds
Started May 21 01:15:36 PM PDT 24
Finished May 21 01:15:39 PM PDT 24
Peak memory 194932 kb
Host smart-c84e2b6e-a339-410b-af2e-f3ba8f8227cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248848978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1248848978
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3993984468
Short name T560
Test name
Test status
Simulation time 131861088 ps
CPU time 2.34 seconds
Started May 21 01:15:37 PM PDT 24
Finished May 21 01:15:41 PM PDT 24
Peak memory 199804 kb
Host smart-3afdb6a3-d335-4646-ac2d-1902f98dc9b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993984468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3993984468
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3773110275
Short name T509
Test name
Test status
Simulation time 162081858 ps
CPU time 1.63 seconds
Started May 21 01:15:35 PM PDT 24
Finished May 21 01:15:39 PM PDT 24
Peak memory 200076 kb
Host smart-f70befbe-8093-4469-a83f-4d6cfa8818d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773110275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3773110275
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.693635662
Short name T540
Test name
Test status
Simulation time 154882360 ps
CPU time 3.19 seconds
Started May 21 01:15:32 PM PDT 24
Finished May 21 01:15:37 PM PDT 24
Peak memory 200044 kb
Host smart-ea3dbd40-5c48-41fe-9812-5b51bd7a4956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693635662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.693635662
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1884699562
Short name T570
Test name
Test status
Simulation time 174410170047 ps
CPU time 894.54 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:30:29 PM PDT 24
Peak memory 216592 kb
Host smart-a97c8383-d4ed-4f29-ab49-70d024392fa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884699562 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1884699562
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4017581565
Short name T536
Test name
Test status
Simulation time 15665732 ps
CPU time 0.71 seconds
Started May 21 01:15:32 PM PDT 24
Finished May 21 01:15:33 PM PDT 24
Peak memory 197396 kb
Host smart-3a708b5a-0ba0-48c0-9313-c264b46aba88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017581565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4017581565
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1293301334
Short name T108
Test name
Test status
Simulation time 16542708 ps
CPU time 0.6 seconds
Started May 21 01:15:40 PM PDT 24
Finished May 21 01:15:44 PM PDT 24
Peak memory 194928 kb
Host smart-cf172a5b-be73-490a-b698-b413d480fd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293301334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1293301334
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2653697411
Short name T523
Test name
Test status
Simulation time 187326372 ps
CPU time 1.78 seconds
Started May 21 01:15:33 PM PDT 24
Finished May 21 01:15:37 PM PDT 24
Peak memory 199872 kb
Host smart-0e1d5944-80f0-4b35-980c-0a630ed0b810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653697411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2653697411
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.205741525
Short name T520
Test name
Test status
Simulation time 59129720 ps
CPU time 1.49 seconds
Started May 21 01:15:38 PM PDT 24
Finished May 21 01:15:43 PM PDT 24
Peak memory 200088 kb
Host smart-1a57abbc-7ae6-4d18-abc9-9bc5cf8e98aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205741525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.205741525
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.806662236
Short name T404
Test name
Test status
Simulation time 114619548 ps
CPU time 0.58 seconds
Started May 21 01:49:14 PM PDT 24
Finished May 21 01:49:21 PM PDT 24
Peak memory 195540 kb
Host smart-ae1276e2-2021-494a-b18a-b6d3d2aec425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806662236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.806662236
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3870135226
Short name T50
Test name
Test status
Simulation time 1220681908 ps
CPU time 52.35 seconds
Started May 21 01:49:08 PM PDT 24
Finished May 21 01:50:03 PM PDT 24
Peak memory 224288 kb
Host smart-aabe2dd6-1a70-48fb-b648-99234a0d2e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870135226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3870135226
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3369323239
Short name T256
Test name
Test status
Simulation time 359263851 ps
CPU time 18.72 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:49:43 PM PDT 24
Peak memory 200660 kb
Host smart-af125d58-b867-4d41-94a3-2a9d33804df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369323239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3369323239
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.4220802469
Short name T145
Test name
Test status
Simulation time 9974847910 ps
CPU time 577.91 seconds
Started May 21 01:49:08 PM PDT 24
Finished May 21 01:58:49 PM PDT 24
Peak memory 668244 kb
Host smart-60b8992c-c5a2-4c92-8ad0-c6e9f40d27ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220802469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4220802469
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3664160699
Short name T3
Test name
Test status
Simulation time 3641315390 ps
CPU time 47.81 seconds
Started May 21 01:49:02 PM PDT 24
Finished May 21 01:49:51 PM PDT 24
Peak memory 200804 kb
Host smart-109af17c-ea69-4d12-b8a9-2656e1fa8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664160699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3664160699
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2829689201
Short name T34
Test name
Test status
Simulation time 863764600 ps
CPU time 0.92 seconds
Started May 21 01:49:04 PM PDT 24
Finished May 21 01:49:06 PM PDT 24
Peak memory 218888 kb
Host smart-fe0f074c-708b-49ee-a3e4-202709cc956c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829689201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2829689201
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.851815408
Short name T144
Test name
Test status
Simulation time 2022478711 ps
CPU time 6.05 seconds
Started May 21 01:48:55 PM PDT 24
Finished May 21 01:49:02 PM PDT 24
Peak memory 200588 kb
Host smart-5d2d8527-f9ca-4162-970f-9548068b6c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851815408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.851815408
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.926177102
Short name T369
Test name
Test status
Simulation time 165505678 ps
CPU time 1 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:49:24 PM PDT 24
Peak memory 199272 kb
Host smart-ebc23199-56d5-4965-bdde-a91873f82f88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926177102 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.926177102
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.34547006
Short name T192
Test name
Test status
Simulation time 30320676082 ps
CPU time 435.99 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 200672 kb
Host smart-2c8c74c2-f616-4d47-af19-0e9103c4543f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34547006 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.34547006
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3234186738
Short name T392
Test name
Test status
Simulation time 22217718 ps
CPU time 0.6 seconds
Started May 21 01:49:18 PM PDT 24
Finished May 21 01:49:27 PM PDT 24
Peak memory 197136 kb
Host smart-16467885-c0f0-4627-a289-7b8c4a4b5e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234186738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3234186738
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1688288241
Short name T205
Test name
Test status
Simulation time 495344116 ps
CPU time 26.3 seconds
Started May 21 01:48:57 PM PDT 24
Finished May 21 01:49:24 PM PDT 24
Peak memory 225116 kb
Host smart-c181b02e-7d43-4540-82ed-17b4d02a8360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688288241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1688288241
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3496945514
Short name T38
Test name
Test status
Simulation time 570330799 ps
CPU time 11.2 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:49:29 PM PDT 24
Peak memory 200628 kb
Host smart-96b48c34-06ac-477a-8301-fccec0e487d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496945514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3496945514
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2508133953
Short name T365
Test name
Test status
Simulation time 3546061112 ps
CPU time 846.67 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 02:03:31 PM PDT 24
Peak memory 743956 kb
Host smart-a31c1fe6-67c8-430c-afe5-c60377258d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508133953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2508133953
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.486324378
Short name T44
Test name
Test status
Simulation time 3286471667 ps
CPU time 50.69 seconds
Started May 21 01:49:18 PM PDT 24
Finished May 21 01:50:17 PM PDT 24
Peak memory 200764 kb
Host smart-654fd40b-b4ee-4594-bd36-5d07b9768480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486324378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.486324378
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3001061005
Short name T32
Test name
Test status
Simulation time 133700005 ps
CPU time 0.97 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:49:26 PM PDT 24
Peak memory 219932 kb
Host smart-f2fac3e7-88c7-4ce1-994e-3fe03609c3b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001061005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3001061005
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3074663
Short name T377
Test name
Test status
Simulation time 64707546 ps
CPU time 1.27 seconds
Started May 21 01:49:12 PM PDT 24
Finished May 21 01:49:17 PM PDT 24
Peak memory 200744 kb
Host smart-31874a67-6aab-484b-91ad-1ad3e4103c2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074663 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.hmac_test_hmac_vectors.3074663
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1335906555
Short name T188
Test name
Test status
Simulation time 139451231595 ps
CPU time 493.34 seconds
Started May 21 01:48:59 PM PDT 24
Finished May 21 01:57:13 PM PDT 24
Peak memory 200648 kb
Host smart-49fef040-1188-486c-b8b9-eb4400d412c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335906555 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1335906555
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_alert_test.35443291
Short name T463
Test name
Test status
Simulation time 18596932 ps
CPU time 0.59 seconds
Started May 21 01:49:27 PM PDT 24
Finished May 21 01:49:36 PM PDT 24
Peak memory 195400 kb
Host smart-61288bd7-8755-47b1-a81c-da377625a2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35443291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.35443291
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1358560282
Short name T394
Test name
Test status
Simulation time 50808255 ps
CPU time 2.61 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:49:36 PM PDT 24
Peak memory 200576 kb
Host smart-63d4e4de-021a-4471-89cd-d21699bfe84b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358560282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1358560282
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2517453351
Short name T165
Test name
Test status
Simulation time 1592966939 ps
CPU time 22.8 seconds
Started May 21 01:49:22 PM PDT 24
Finished May 21 01:49:54 PM PDT 24
Peak memory 200580 kb
Host smart-a9f759e0-044b-44b2-a5b0-cf8993e6e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517453351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2517453351
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.87711482
Short name T160
Test name
Test status
Simulation time 682232234 ps
CPU time 62.22 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:50:36 PM PDT 24
Peak memory 326132 kb
Host smart-88271880-b384-4db1-8de4-8f40c44a038f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87711482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.87711482
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.25237826
Short name T185
Test name
Test status
Simulation time 2324028588 ps
CPU time 31.45 seconds
Started May 21 01:49:19 PM PDT 24
Finished May 21 01:49:59 PM PDT 24
Peak memory 200748 kb
Host smart-c650badc-567e-4e85-9db1-a0b5caddc37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25237826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.25237826
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.849531331
Short name T190
Test name
Test status
Simulation time 2584517204 ps
CPU time 6.61 seconds
Started May 21 01:49:27 PM PDT 24
Finished May 21 01:49:42 PM PDT 24
Peak memory 200716 kb
Host smart-ba7d153e-2252-4114-8399-3154f37052d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849531331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.849531331
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3991124367
Short name T471
Test name
Test status
Simulation time 4239385471 ps
CPU time 57.6 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:50:31 PM PDT 24
Peak memory 200820 kb
Host smart-a5c54e44-79e2-421a-85ce-5902bd87c976
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991124367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3991124367
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3568464623
Short name T166
Test name
Test status
Simulation time 104824618 ps
CPU time 1.24 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:49:35 PM PDT 24
Peak memory 200492 kb
Host smart-e6943ee2-5a1d-4450-93b5-2303045a5482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568464623 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3568464623
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.4174126885
Short name T265
Test name
Test status
Simulation time 24553751881 ps
CPU time 476.72 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:57:30 PM PDT 24
Peak memory 200740 kb
Host smart-c321a03f-8189-46a2-9664-4aabe3008992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174126885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.4174126885
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3340422638
Short name T417
Test name
Test status
Simulation time 318033214 ps
CPU time 18.42 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 01:49:53 PM PDT 24
Peak memory 226320 kb
Host smart-b0ab8bd7-7ac2-4786-8a57-6f7c3102d62f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340422638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3340422638
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.78318070
Short name T179
Test name
Test status
Simulation time 2630306773 ps
CPU time 247.87 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:53:41 PM PDT 24
Peak memory 472032 kb
Host smart-0b6d2640-e76b-4394-8f33-7306c524c939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78318070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.78318070
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2972107484
Short name T132
Test name
Test status
Simulation time 8900150639 ps
CPU time 30.22 seconds
Started May 21 01:49:24 PM PDT 24
Finished May 21 01:50:03 PM PDT 24
Peak memory 200700 kb
Host smart-2157aafd-de9b-4b09-88d8-2a8be260a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972107484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2972107484
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.733709276
Short name T214
Test name
Test status
Simulation time 329613333 ps
CPU time 1.69 seconds
Started May 21 01:49:27 PM PDT 24
Finished May 21 01:49:37 PM PDT 24
Peak memory 200656 kb
Host smart-aa472759-5577-4fcf-b84e-6dd7ed09862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733709276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.733709276
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.177746395
Short name T422
Test name
Test status
Simulation time 73057075 ps
CPU time 1.07 seconds
Started May 21 01:49:29 PM PDT 24
Finished May 21 01:49:37 PM PDT 24
Peak memory 200116 kb
Host smart-1b07d3f9-0c3e-4a82-a9e6-2f799072d445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177746395 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.177746395
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.504896463
Short name T137
Test name
Test status
Simulation time 28657671077 ps
CPU time 516.03 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 01:58:10 PM PDT 24
Peak memory 200720 kb
Host smart-2ba24680-509f-4fd6-8ba8-a71fbc1ef9d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504896463 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.504896463
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3830138724
Short name T230
Test name
Test status
Simulation time 23654346 ps
CPU time 0.61 seconds
Started May 21 01:49:39 PM PDT 24
Finished May 21 01:49:42 PM PDT 24
Peak memory 196424 kb
Host smart-dfe214a0-aa65-4c8c-bad3-6dd78bca656f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830138724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3830138724
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1444721223
Short name T236
Test name
Test status
Simulation time 3463392094 ps
CPU time 41 seconds
Started May 21 01:49:34 PM PDT 24
Finished May 21 01:50:19 PM PDT 24
Peak memory 225376 kb
Host smart-c4b36cf4-8d52-47df-a9b0-e2aedfa7b516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444721223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1444721223
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.971633712
Short name T138
Test name
Test status
Simulation time 4387611450 ps
CPU time 34.43 seconds
Started May 21 01:49:32 PM PDT 24
Finished May 21 01:50:12 PM PDT 24
Peak memory 200772 kb
Host smart-035e8a70-bcab-4849-981e-aa6c73454481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971633712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.971633712
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3604982440
Short name T169
Test name
Test status
Simulation time 4959637448 ps
CPU time 241.67 seconds
Started May 21 01:49:32 PM PDT 24
Finished May 21 01:53:39 PM PDT 24
Peak memory 472308 kb
Host smart-61c5ca26-b267-4f68-ba59-3933bd7d3f58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604982440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3604982440
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3104251135
Short name T243
Test name
Test status
Simulation time 6756460491 ps
CPU time 66.63 seconds
Started May 21 01:49:31 PM PDT 24
Finished May 21 01:50:44 PM PDT 24
Peak memory 200752 kb
Host smart-4db171f8-3379-4a15-b93e-054d971f050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104251135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3104251135
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1876010264
Short name T350
Test name
Test status
Simulation time 173304342 ps
CPU time 3.29 seconds
Started May 21 01:49:28 PM PDT 24
Finished May 21 01:49:39 PM PDT 24
Peak memory 200680 kb
Host smart-216ad4e2-a5b6-438a-99cd-948ddae34da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876010264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1876010264
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2260954832
Short name T27
Test name
Test status
Simulation time 409779051 ps
CPU time 3.67 seconds
Started May 21 01:49:39 PM PDT 24
Finished May 21 01:49:45 PM PDT 24
Peak memory 200636 kb
Host smart-c873f34c-9bbb-4336-bb48-a88e5afc912d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260954832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2260954832
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2163040380
Short name T9
Test name
Test status
Simulation time 152798498 ps
CPU time 0.99 seconds
Started May 21 01:49:40 PM PDT 24
Finished May 21 01:49:42 PM PDT 24
Peak memory 199500 kb
Host smart-96e0a828-8750-4129-90a0-86c6065f50c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163040380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2163040380
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3990885248
Short name T321
Test name
Test status
Simulation time 7463896553 ps
CPU time 397.89 seconds
Started May 21 01:49:33 PM PDT 24
Finished May 21 01:56:16 PM PDT 24
Peak memory 200636 kb
Host smart-3cddac10-551c-406d-93e3-15b56340ee1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990885248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3990885248
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3584837069
Short name T159
Test name
Test status
Simulation time 156347129 ps
CPU time 0.61 seconds
Started May 21 01:49:45 PM PDT 24
Finished May 21 01:49:47 PM PDT 24
Peak memory 197048 kb
Host smart-f06810ff-b4c8-4a33-bfe3-1337003201b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584837069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3584837069
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3066101021
Short name T385
Test name
Test status
Simulation time 4983375404 ps
CPU time 41.78 seconds
Started May 21 01:49:39 PM PDT 24
Finished May 21 01:50:23 PM PDT 24
Peak memory 233564 kb
Host smart-f3c6cc5e-a9a9-4e7e-8a9f-609a111ccfb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066101021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3066101021
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2089625691
Short name T120
Test name
Test status
Simulation time 615872514 ps
CPU time 31.79 seconds
Started May 21 01:49:38 PM PDT 24
Finished May 21 01:50:12 PM PDT 24
Peak memory 200580 kb
Host smart-ab30c5ac-ad4f-4f03-9e1c-8ce33646b6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089625691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2089625691
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4191712097
Short name T36
Test name
Test status
Simulation time 1318116413 ps
CPU time 268.92 seconds
Started May 21 01:49:38 PM PDT 24
Finished May 21 01:54:09 PM PDT 24
Peak memory 596156 kb
Host smart-7c03936d-878b-48b0-a933-cf45a84748de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191712097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4191712097
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.327903845
Short name T14
Test name
Test status
Simulation time 2413605932 ps
CPU time 33.34 seconds
Started May 21 01:49:39 PM PDT 24
Finished May 21 01:50:14 PM PDT 24
Peak memory 200616 kb
Host smart-e1d59712-b38b-4ebd-a628-eee2f67be658
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327903845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.327903845
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4209902461
Short name T428
Test name
Test status
Simulation time 4186113305 ps
CPU time 59.4 seconds
Started May 21 01:49:39 PM PDT 24
Finished May 21 01:50:40 PM PDT 24
Peak memory 200660 kb
Host smart-68c49434-faee-45bb-a835-fd2e27ed9772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209902461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4209902461
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1923560535
Short name T368
Test name
Test status
Simulation time 222543938 ps
CPU time 3.53 seconds
Started May 21 01:49:38 PM PDT 24
Finished May 21 01:49:44 PM PDT 24
Peak memory 200616 kb
Host smart-0f741f0b-4a52-4062-b13a-e589c89803a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923560535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1923560535
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1791205915
Short name T264
Test name
Test status
Simulation time 177656753 ps
CPU time 1.1 seconds
Started May 21 01:49:45 PM PDT 24
Finished May 21 01:49:47 PM PDT 24
Peak memory 200192 kb
Host smart-ac926b63-73ca-4f31-b05e-947a4e2695f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791205915 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1791205915
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1935628160
Short name T358
Test name
Test status
Simulation time 25337501751 ps
CPU time 453.73 seconds
Started May 21 01:49:45 PM PDT 24
Finished May 21 01:57:19 PM PDT 24
Peak memory 200732 kb
Host smart-58456b83-d707-4914-9a96-24f5fac97ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935628160 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1935628160
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.660928893
Short name T180
Test name
Test status
Simulation time 13916651 ps
CPU time 0.6 seconds
Started May 21 01:49:51 PM PDT 24
Finished May 21 01:49:52 PM PDT 24
Peak memory 197100 kb
Host smart-64c34dec-2ea0-4968-8dc0-16c28e489bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660928893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.660928893
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.34022894
Short name T249
Test name
Test status
Simulation time 3320320008 ps
CPU time 40.58 seconds
Started May 21 01:49:50 PM PDT 24
Finished May 21 01:50:31 PM PDT 24
Peak memory 200648 kb
Host smart-e5ad1dbc-fd22-4542-8751-a8ff73c3fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34022894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.34022894
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4189769232
Short name T162
Test name
Test status
Simulation time 1323011786 ps
CPU time 203.45 seconds
Started May 21 01:49:50 PM PDT 24
Finished May 21 01:53:15 PM PDT 24
Peak memory 613876 kb
Host smart-1dd1284e-dfa4-4e41-b48a-2624cf0275ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189769232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4189769232
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2646040468
Short name T386
Test name
Test status
Simulation time 12206096523 ps
CPU time 40.96 seconds
Started May 21 01:49:50 PM PDT 24
Finished May 21 01:50:32 PM PDT 24
Peak memory 200764 kb
Host smart-f72a6b81-fd42-4dd2-bc77-26e0a74cb881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646040468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2646040468
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3001875487
Short name T381
Test name
Test status
Simulation time 4327582138 ps
CPU time 5.9 seconds
Started May 21 01:49:50 PM PDT 24
Finished May 21 01:49:57 PM PDT 24
Peak memory 200720 kb
Host smart-4b675962-35b2-4af3-95c1-53abed156074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001875487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3001875487
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.453510682
Short name T215
Test name
Test status
Simulation time 38579984 ps
CPU time 1.03 seconds
Started May 21 01:49:50 PM PDT 24
Finished May 21 01:49:52 PM PDT 24
Peak memory 199028 kb
Host smart-ec3d0035-748b-4902-b50c-2e8bbe0b192a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453510682 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.453510682
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.28842984
Short name T277
Test name
Test status
Simulation time 38185105218 ps
CPU time 525.91 seconds
Started May 21 01:49:49 PM PDT 24
Finished May 21 01:58:36 PM PDT 24
Peak memory 200688 kb
Host smart-f1bc792e-47b9-495c-89d1-df4e3886dd3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28842984 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.28842984
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.3998553764
Short name T30
Test name
Test status
Simulation time 280033846858 ps
CPU time 2006.55 seconds
Started May 21 01:53:14 PM PDT 24
Finished May 21 02:26:42 PM PDT 24
Peak memory 770872 kb
Host smart-5565d795-c00b-4416-b3dc-feb03e6e8fde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998553764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.3998553764
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.3135965883
Short name T29
Test name
Test status
Simulation time 17157889856 ps
CPU time 1759.15 seconds
Started May 21 01:53:09 PM PDT 24
Finished May 21 02:22:31 PM PDT 24
Peak memory 808392 kb
Host smart-6398119b-4454-4d2b-bd1b-5fc51bd39666
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135965883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.3135965883
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3709354107
Short name T207
Test name
Test status
Simulation time 42799485 ps
CPU time 0.59 seconds
Started May 21 01:50:03 PM PDT 24
Finished May 21 01:50:05 PM PDT 24
Peak memory 195364 kb
Host smart-432121e9-eca1-4bbb-872d-66da4af3d6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709354107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3709354107
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.4240356928
Short name T48
Test name
Test status
Simulation time 756732265 ps
CPU time 22.64 seconds
Started May 21 01:49:58 PM PDT 24
Finished May 21 01:50:22 PM PDT 24
Peak memory 226188 kb
Host smart-7b6b05bd-a15c-4f2a-9ce8-f0025ebea1bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240356928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4240356928
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1404226258
Short name T72
Test name
Test status
Simulation time 472089675 ps
CPU time 25.3 seconds
Started May 21 01:49:54 PM PDT 24
Finished May 21 01:50:21 PM PDT 24
Peak memory 200656 kb
Host smart-a5fabf52-e80a-4ef8-87e4-694a3a27e8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404226258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1404226258
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2186011564
Short name T140
Test name
Test status
Simulation time 2690799655 ps
CPU time 683.54 seconds
Started May 21 01:49:57 PM PDT 24
Finished May 21 02:01:22 PM PDT 24
Peak memory 733952 kb
Host smart-bfba77dd-3291-47d8-a43f-f1801a9bb930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186011564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2186011564
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1778052864
Short name T339
Test name
Test status
Simulation time 8900074835 ps
CPU time 63.97 seconds
Started May 21 01:49:58 PM PDT 24
Finished May 21 01:51:03 PM PDT 24
Peak memory 200916 kb
Host smart-a6021d89-742f-47b6-b82d-8fead140bc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778052864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1778052864
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2272445428
Short name T167
Test name
Test status
Simulation time 342572084 ps
CPU time 5.47 seconds
Started May 21 01:49:56 PM PDT 24
Finished May 21 01:50:03 PM PDT 24
Peak memory 200628 kb
Host smart-443fee26-b5b1-4ee0-a5d0-0c89a917a56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272445428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2272445428
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1263265952
Short name T317
Test name
Test status
Simulation time 99863385 ps
CPU time 1.01 seconds
Started May 21 01:49:56 PM PDT 24
Finished May 21 01:49:58 PM PDT 24
Peak memory 200212 kb
Host smart-5d45c69f-184b-4a8d-b019-450e64b58229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263265952 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1263265952
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3992780364
Short name T307
Test name
Test status
Simulation time 170038574434 ps
CPU time 546.93 seconds
Started May 21 01:50:00 PM PDT 24
Finished May 21 01:59:07 PM PDT 24
Peak memory 200852 kb
Host smart-c84414e0-8872-4861-a1ff-081985028c03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992780364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3992780364
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1779832862
Short name T412
Test name
Test status
Simulation time 72623865 ps
CPU time 0.62 seconds
Started May 21 01:50:03 PM PDT 24
Finished May 21 01:50:05 PM PDT 24
Peak memory 196392 kb
Host smart-72c7b3d3-6dd5-4ff9-bb64-fcc68f5977f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779832862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1779832862
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1444403425
Short name T257
Test name
Test status
Simulation time 1007290799 ps
CPU time 24.85 seconds
Started May 21 01:50:03 PM PDT 24
Finished May 21 01:50:29 PM PDT 24
Peak memory 208824 kb
Host smart-f51c5e6a-f1df-4ea2-add4-041ff02cfb4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444403425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1444403425
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4083628033
Short name T297
Test name
Test status
Simulation time 874380205 ps
CPU time 24.91 seconds
Started May 21 01:50:01 PM PDT 24
Finished May 21 01:50:27 PM PDT 24
Peak memory 200572 kb
Host smart-e302ece9-212b-409a-a6ad-d7135eadc0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083628033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4083628033
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2337217639
Short name T269
Test name
Test status
Simulation time 2312089619 ps
CPU time 648.81 seconds
Started May 21 01:50:02 PM PDT 24
Finished May 21 02:00:52 PM PDT 24
Peak memory 719992 kb
Host smart-5d133e22-ffee-4066-952c-26c3c7b92a7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337217639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2337217639
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3823876985
Short name T414
Test name
Test status
Simulation time 6181556262 ps
CPU time 11.76 seconds
Started May 21 01:50:02 PM PDT 24
Finished May 21 01:50:15 PM PDT 24
Peak memory 200732 kb
Host smart-1dade44c-1c82-4354-a077-418ac40ecbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823876985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3823876985
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1817036114
Short name T351
Test name
Test status
Simulation time 467153341 ps
CPU time 1.25 seconds
Started May 21 01:50:02 PM PDT 24
Finished May 21 01:50:04 PM PDT 24
Peak memory 200440 kb
Host smart-0a854910-df10-4d00-b620-96ee0c3f5889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817036114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1817036114
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3539104891
Short name T266
Test name
Test status
Simulation time 36103312 ps
CPU time 1.03 seconds
Started May 21 01:50:01 PM PDT 24
Finished May 21 01:50:03 PM PDT 24
Peak memory 200252 kb
Host smart-482cc01c-8d88-48ba-882c-2d56d5992182
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539104891 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3539104891
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2497200133
Short name T222
Test name
Test status
Simulation time 16171727008 ps
CPU time 419.33 seconds
Started May 21 01:50:03 PM PDT 24
Finished May 21 01:57:03 PM PDT 24
Peak memory 200692 kb
Host smart-18618334-108b-40d9-8fbb-5ad69d75761d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497200133 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2497200133
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3243200650
Short name T439
Test name
Test status
Simulation time 65214397 ps
CPU time 0.55 seconds
Started May 21 01:50:08 PM PDT 24
Finished May 21 01:50:09 PM PDT 24
Peak memory 195208 kb
Host smart-e2cb53de-6c94-4890-90a0-574cd1d03c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243200650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3243200650
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1516363980
Short name T444
Test name
Test status
Simulation time 104028124 ps
CPU time 4.4 seconds
Started May 21 01:50:12 PM PDT 24
Finished May 21 01:50:17 PM PDT 24
Peak memory 200540 kb
Host smart-355c2aac-2c95-4417-9fff-25b2021b8d1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516363980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1516363980
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1298616284
Short name T465
Test name
Test status
Simulation time 11887205827 ps
CPU time 27.13 seconds
Started May 21 01:50:08 PM PDT 24
Finished May 21 01:50:37 PM PDT 24
Peak memory 200712 kb
Host smart-435f6714-5c65-444c-8f09-1ce6a74009ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298616284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1298616284
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1265137942
Short name T301
Test name
Test status
Simulation time 5670817422 ps
CPU time 332.79 seconds
Started May 21 01:50:07 PM PDT 24
Finished May 21 01:55:41 PM PDT 24
Peak memory 632912 kb
Host smart-460b4c22-d9b8-4a94-9f6c-81adf2b2e4c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265137942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1265137942
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2339309158
Short name T357
Test name
Test status
Simulation time 5370724805 ps
CPU time 73.72 seconds
Started May 21 01:50:09 PM PDT 24
Finished May 21 01:51:24 PM PDT 24
Peak memory 200784 kb
Host smart-09dc53e7-4d5d-45d3-a267-feab1b05028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339309158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2339309158
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.511317805
Short name T276
Test name
Test status
Simulation time 270908409 ps
CPU time 2.45 seconds
Started May 21 01:50:16 PM PDT 24
Finished May 21 01:50:19 PM PDT 24
Peak memory 200556 kb
Host smart-996f4bc4-8ec3-41c9-8203-dc9aac68cd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511317805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.511317805
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1152017831
Short name T450
Test name
Test status
Simulation time 99706362 ps
CPU time 1.23 seconds
Started May 21 01:50:06 PM PDT 24
Finished May 21 01:50:08 PM PDT 24
Peak memory 200408 kb
Host smart-7e158186-8037-4bd9-92f2-c7589461c936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152017831 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1152017831
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3073228109
Short name T316
Test name
Test status
Simulation time 26598883357 ps
CPU time 448.32 seconds
Started May 21 01:50:09 PM PDT 24
Finished May 21 01:57:39 PM PDT 24
Peak memory 200692 kb
Host smart-ebe3388a-0a2e-4300-ac72-37e4bf0c27d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073228109 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3073228109
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3758291852
Short name T395
Test name
Test status
Simulation time 41767560 ps
CPU time 0.59 seconds
Started May 21 01:50:14 PM PDT 24
Finished May 21 01:50:16 PM PDT 24
Peak memory 196024 kb
Host smart-0359e500-ce1a-4ba7-82ec-e0d4261ee836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758291852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3758291852
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3681631855
Short name T42
Test name
Test status
Simulation time 649928893 ps
CPU time 9.9 seconds
Started May 21 01:50:10 PM PDT 24
Finished May 21 01:50:21 PM PDT 24
Peak memory 208888 kb
Host smart-e11c557e-3df2-4077-83ed-d74fdd0cd02a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681631855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3681631855
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2072613666
Short name T278
Test name
Test status
Simulation time 1254662307 ps
CPU time 24.51 seconds
Started May 21 01:50:16 PM PDT 24
Finished May 21 01:50:43 PM PDT 24
Peak memory 200688 kb
Host smart-80768ccb-a86b-41c6-a419-36b6e453f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072613666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2072613666
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.4183647802
Short name T315
Test name
Test status
Simulation time 7525149463 ps
CPU time 176.13 seconds
Started May 21 01:50:14 PM PDT 24
Finished May 21 01:53:12 PM PDT 24
Peak memory 626460 kb
Host smart-5d4c0991-711e-4868-a2fe-527908e28467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183647802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.4183647802
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.296074671
Short name T453
Test name
Test status
Simulation time 2223101552 ps
CPU time 21.7 seconds
Started May 21 01:50:15 PM PDT 24
Finished May 21 01:50:38 PM PDT 24
Peak memory 200688 kb
Host smart-23db568b-aa04-487a-b90e-5d14f98cb95f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296074671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.296074671
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.597129190
Short name T464
Test name
Test status
Simulation time 2132259781 ps
CPU time 10.94 seconds
Started May 21 01:50:09 PM PDT 24
Finished May 21 01:50:21 PM PDT 24
Peak memory 200528 kb
Host smart-80401e10-e8e2-4c93-8509-a032ab1a9d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597129190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.597129190
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4256948305
Short name T328
Test name
Test status
Simulation time 660371132 ps
CPU time 4.57 seconds
Started May 21 01:50:08 PM PDT 24
Finished May 21 01:50:14 PM PDT 24
Peak memory 200620 kb
Host smart-339389e9-b098-422b-b1d4-8cb68037af8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256948305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4256948305
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1724156022
Short name T259
Test name
Test status
Simulation time 85781524 ps
CPU time 1.23 seconds
Started May 21 01:50:13 PM PDT 24
Finished May 21 01:50:16 PM PDT 24
Peak memory 200620 kb
Host smart-52a1e3bb-1f87-4893-baca-546ff3022570
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724156022 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1724156022
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3496976491
Short name T296
Test name
Test status
Simulation time 105363866812 ps
CPU time 471.97 seconds
Started May 21 01:50:18 PM PDT 24
Finished May 21 01:58:11 PM PDT 24
Peak memory 200712 kb
Host smart-8d230a6d-462f-41d9-8940-27e2c08c80e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496976491 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3496976491
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2080625892
Short name T294
Test name
Test status
Simulation time 17711759 ps
CPU time 0.59 seconds
Started May 21 01:50:15 PM PDT 24
Finished May 21 01:50:17 PM PDT 24
Peak memory 196396 kb
Host smart-6c3794e7-a414-4798-8b5d-d555be40e103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080625892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2080625892
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3400804059
Short name T287
Test name
Test status
Simulation time 3604788362 ps
CPU time 48.31 seconds
Started May 21 01:50:15 PM PDT 24
Finished May 21 01:51:04 PM PDT 24
Peak memory 241736 kb
Host smart-53649a3e-a1d8-492b-8259-ead7d0aff1a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400804059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3400804059
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3616409156
Short name T235
Test name
Test status
Simulation time 255186361 ps
CPU time 13.28 seconds
Started May 21 01:50:15 PM PDT 24
Finished May 21 01:50:30 PM PDT 24
Peak memory 200560 kb
Host smart-7e8f2afb-7e1e-495d-8548-0ba14255e39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616409156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3616409156
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4190641246
Short name T341
Test name
Test status
Simulation time 9495948667 ps
CPU time 574.38 seconds
Started May 21 01:50:14 PM PDT 24
Finished May 21 01:59:50 PM PDT 24
Peak memory 686840 kb
Host smart-a5d9f790-475d-467d-ada0-c877ce628e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190641246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4190641246
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1872687289
Short name T37
Test name
Test status
Simulation time 22498583725 ps
CPU time 72.35 seconds
Started May 21 01:50:15 PM PDT 24
Finished May 21 01:51:28 PM PDT 24
Peak memory 200748 kb
Host smart-c3d46b77-f035-410e-9d7f-68ed76e55245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872687289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1872687289
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1653471552
Short name T389
Test name
Test status
Simulation time 278966503 ps
CPU time 1.6 seconds
Started May 21 01:50:15 PM PDT 24
Finished May 21 01:50:18 PM PDT 24
Peak memory 200676 kb
Host smart-04c85a4c-409a-4c60-aa9c-cbd1f1d3ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653471552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1653471552
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1012353869
Short name T285
Test name
Test status
Simulation time 55812253 ps
CPU time 1.23 seconds
Started May 21 01:50:17 PM PDT 24
Finished May 21 01:50:20 PM PDT 24
Peak memory 200516 kb
Host smart-e1de614e-3237-4c02-a89d-3a401d4e9e38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012353869 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1012353869
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2554223274
Short name T298
Test name
Test status
Simulation time 37709566269 ps
CPU time 496.72 seconds
Started May 21 01:50:14 PM PDT 24
Finished May 21 01:58:32 PM PDT 24
Peak memory 200720 kb
Host smart-653d8231-a536-4090-ab33-11fcd7ae9aa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554223274 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2554223274
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2336883018
Short name T206
Test name
Test status
Simulation time 20744889 ps
CPU time 0.59 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:49:20 PM PDT 24
Peak memory 195948 kb
Host smart-49d027de-b659-42dc-af7b-e207e38b49a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336883018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2336883018
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3812425293
Short name T436
Test name
Test status
Simulation time 5549596984 ps
CPU time 47.66 seconds
Started May 21 01:48:54 PM PDT 24
Finished May 21 01:49:42 PM PDT 24
Peak memory 231492 kb
Host smart-4282d22e-e31c-449d-a88f-726dee76aa54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812425293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3812425293
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2061994004
Short name T323
Test name
Test status
Simulation time 2284775523 ps
CPU time 29.31 seconds
Started May 21 01:49:10 PM PDT 24
Finished May 21 01:49:42 PM PDT 24
Peak memory 200796 kb
Host smart-d2a5543b-e255-461f-8ffc-c42551690ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061994004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2061994004
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3403368761
Short name T352
Test name
Test status
Simulation time 2257952541 ps
CPU time 537.69 seconds
Started May 21 01:49:18 PM PDT 24
Finished May 21 01:58:24 PM PDT 24
Peak memory 675748 kb
Host smart-29adfbd5-e9f4-4fc9-8234-e8ee98ba0f61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403368761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3403368761
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2492804133
Short name T356
Test name
Test status
Simulation time 34850975901 ps
CPU time 114.28 seconds
Started May 21 01:49:08 PM PDT 24
Finished May 21 01:51:05 PM PDT 24
Peak memory 200716 kb
Host smart-f15cb871-1792-422f-af18-208304a7fc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492804133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2492804133
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.4265058976
Short name T319
Test name
Test status
Simulation time 3609624193 ps
CPU time 5.34 seconds
Started May 21 01:49:18 PM PDT 24
Finished May 21 01:49:31 PM PDT 24
Peak memory 200764 kb
Host smart-af5dd1e1-e6a0-4c39-b523-cf6ced134bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265058976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4265058976
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1633570921
Short name T275
Test name
Test status
Simulation time 107542737 ps
CPU time 0.98 seconds
Started May 21 01:48:59 PM PDT 24
Finished May 21 01:49:01 PM PDT 24
Peak memory 199856 kb
Host smart-92da3a1a-5da2-4b1a-ac78-51b29cfe9bcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633570921 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1633570921
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.487123226
Short name T253
Test name
Test status
Simulation time 53170802148 ps
CPU time 508.16 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:57:53 PM PDT 24
Peak memory 200696 kb
Host smart-275dde47-7265-442a-87df-1ad772466a70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487123226 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.487123226
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1072983499
Short name T468
Test name
Test status
Simulation time 42102194 ps
CPU time 0.59 seconds
Started May 21 01:50:23 PM PDT 24
Finished May 21 01:50:25 PM PDT 24
Peak memory 195376 kb
Host smart-cab9e394-772b-4ec5-affb-f1d63f71b8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072983499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1072983499
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3767766984
Short name T122
Test name
Test status
Simulation time 977787640 ps
CPU time 53.82 seconds
Started May 21 01:50:22 PM PDT 24
Finished May 21 01:51:17 PM PDT 24
Peak memory 232708 kb
Host smart-bb97e291-a4cc-4315-b8d6-0baa113d4db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767766984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3767766984
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.382248750
Short name T399
Test name
Test status
Simulation time 15108090246 ps
CPU time 69.32 seconds
Started May 21 01:50:20 PM PDT 24
Finished May 21 01:51:29 PM PDT 24
Peak memory 200752 kb
Host smart-e2b3263f-2cc6-44ff-b601-6387877fcfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382248750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.382248750
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1116002195
Short name T240
Test name
Test status
Simulation time 201902429 ps
CPU time 11.47 seconds
Started May 21 01:50:25 PM PDT 24
Finished May 21 01:50:37 PM PDT 24
Peak memory 234900 kb
Host smart-8a109494-1117-48cb-9d9b-0e88dfec969e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116002195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1116002195
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.529657169
Short name T163
Test name
Test status
Simulation time 8211593940 ps
CPU time 117.12 seconds
Started May 21 01:50:24 PM PDT 24
Finished May 21 01:52:23 PM PDT 24
Peak memory 200696 kb
Host smart-446e1688-8e16-41b8-9129-b2863487690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529657169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.529657169
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3980888027
Short name T327
Test name
Test status
Simulation time 1187259346 ps
CPU time 4.88 seconds
Started May 21 01:50:17 PM PDT 24
Finished May 21 01:50:24 PM PDT 24
Peak memory 200636 kb
Host smart-50d411ec-b447-4305-97de-d37b1acb5913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980888027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3980888027
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.332935522
Short name T118
Test name
Test status
Simulation time 305488137 ps
CPU time 1.43 seconds
Started May 21 01:50:22 PM PDT 24
Finished May 21 01:50:24 PM PDT 24
Peak memory 200632 kb
Host smart-3ed48317-7a91-4c18-b595-280a0121a40e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332935522 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.332935522
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.78056773
Short name T204
Test name
Test status
Simulation time 127098044538 ps
CPU time 460.08 seconds
Started May 21 01:50:20 PM PDT 24
Finished May 21 01:58:01 PM PDT 24
Peak memory 200640 kb
Host smart-b1cac07f-11fd-4bbb-a7f5-994679fa404d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78056773 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.78056773
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.4238025708
Short name T73
Test name
Test status
Simulation time 12660040 ps
CPU time 0.61 seconds
Started May 21 01:50:22 PM PDT 24
Finished May 21 01:50:24 PM PDT 24
Peak memory 196408 kb
Host smart-cd18cfc5-628b-4d23-b921-43ae86cadee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238025708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.4238025708
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.123733568
Short name T342
Test name
Test status
Simulation time 931678052 ps
CPU time 22.34 seconds
Started May 21 01:50:20 PM PDT 24
Finished May 21 01:50:43 PM PDT 24
Peak memory 200636 kb
Host smart-20eb22c6-313b-4c0d-9d3f-3dfa453197ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123733568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.123733568
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2367458306
Short name T461
Test name
Test status
Simulation time 249632074 ps
CPU time 5.29 seconds
Started May 21 01:50:24 PM PDT 24
Finished May 21 01:50:30 PM PDT 24
Peak memory 200536 kb
Host smart-dec84cf0-3934-4680-b668-36cf044fcb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367458306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2367458306
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1608138865
Short name T426
Test name
Test status
Simulation time 6157718170 ps
CPU time 362.18 seconds
Started May 21 01:50:22 PM PDT 24
Finished May 21 01:56:25 PM PDT 24
Peak memory 595596 kb
Host smart-274439a0-acbe-4097-8761-b1d07dc570a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608138865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1608138865
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1677841067
Short name T219
Test name
Test status
Simulation time 1465077376 ps
CPU time 72.52 seconds
Started May 21 01:50:21 PM PDT 24
Finished May 21 01:51:34 PM PDT 24
Peak memory 200684 kb
Host smart-c650d82f-861b-428e-b28c-1267af32f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677841067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1677841067
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3975806487
Short name T353
Test name
Test status
Simulation time 161005761 ps
CPU time 3.97 seconds
Started May 21 01:50:20 PM PDT 24
Finished May 21 01:50:24 PM PDT 24
Peak memory 200676 kb
Host smart-6ee07112-84ee-45db-9fbc-258b1d51833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975806487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3975806487
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1421891528
Short name T435
Test name
Test status
Simulation time 104314166 ps
CPU time 1.34 seconds
Started May 21 01:50:21 PM PDT 24
Finished May 21 01:50:23 PM PDT 24
Peak memory 200548 kb
Host smart-0a0b28c6-bfde-4762-bd91-8b8e8fbdd022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421891528 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1421891528
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1692558734
Short name T366
Test name
Test status
Simulation time 121760969228 ps
CPU time 498.84 seconds
Started May 21 01:50:24 PM PDT 24
Finished May 21 01:58:44 PM PDT 24
Peak memory 200640 kb
Host smart-a2a126c3-186c-4882-8cc8-d707e060332b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692558734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1692558734
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3061384588
Short name T210
Test name
Test status
Simulation time 43916590 ps
CPU time 0.6 seconds
Started May 21 01:50:26 PM PDT 24
Finished May 21 01:50:27 PM PDT 24
Peak memory 195388 kb
Host smart-112307d3-f295-441a-af7e-b1649b6f235d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061384588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3061384588
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3314941209
Short name T119
Test name
Test status
Simulation time 401556499 ps
CPU time 22.61 seconds
Started May 21 01:50:27 PM PDT 24
Finished May 21 01:50:50 PM PDT 24
Peak memory 219020 kb
Host smart-70a1d682-1888-44b8-9cfd-2a4b1e60cc9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314941209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3314941209
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1073336606
Short name T375
Test name
Test status
Simulation time 17202338741 ps
CPU time 36.03 seconds
Started May 21 01:50:29 PM PDT 24
Finished May 21 01:51:05 PM PDT 24
Peak memory 200804 kb
Host smart-e16085a6-5474-4921-9e58-673616134a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073336606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1073336606
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2120947104
Short name T176
Test name
Test status
Simulation time 5066755855 ps
CPU time 187.27 seconds
Started May 21 01:50:27 PM PDT 24
Finished May 21 01:53:35 PM PDT 24
Peak memory 573704 kb
Host smart-fd18ff7f-01f3-4119-a547-2233ea4f79b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120947104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2120947104
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2510717666
Short name T81
Test name
Test status
Simulation time 4125766690 ps
CPU time 55.48 seconds
Started May 21 01:50:28 PM PDT 24
Finished May 21 01:51:24 PM PDT 24
Peak memory 200712 kb
Host smart-e9f9835a-fb6e-4935-8dd6-4e737d152e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510717666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2510717666
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1534289180
Short name T173
Test name
Test status
Simulation time 860502915 ps
CPU time 5.58 seconds
Started May 21 01:50:26 PM PDT 24
Finished May 21 01:50:32 PM PDT 24
Peak memory 200536 kb
Host smart-a84fdb1e-467c-471e-96df-c4bf1a2e0549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534289180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1534289180
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3214998119
Short name T397
Test name
Test status
Simulation time 15620466762 ps
CPU time 1147.41 seconds
Started May 21 01:50:25 PM PDT 24
Finished May 21 02:09:33 PM PDT 24
Peak memory 804188 kb
Host smart-3fd96483-99d3-4ddb-a0ba-e3ebf5946325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214998119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3214998119
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3559037169
Short name T70
Test name
Test status
Simulation time 216119687 ps
CPU time 1.31 seconds
Started May 21 01:50:26 PM PDT 24
Finished May 21 01:50:27 PM PDT 24
Peak memory 200352 kb
Host smart-3f5147be-a482-4985-b844-c1713feaeb20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559037169 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3559037169
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.390927398
Short name T127
Test name
Test status
Simulation time 7361024031 ps
CPU time 461.46 seconds
Started May 21 01:50:27 PM PDT 24
Finished May 21 01:58:09 PM PDT 24
Peak memory 200652 kb
Host smart-a688a427-d719-4a1e-9669-0428efd0f356
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390927398 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.390927398
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.300890237
Short name T336
Test name
Test status
Simulation time 72188962 ps
CPU time 0.57 seconds
Started May 21 01:50:32 PM PDT 24
Finished May 21 01:50:34 PM PDT 24
Peak memory 196064 kb
Host smart-226628f8-8808-4034-85ea-79b8aabe28b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300890237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.300890237
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.920938349
Short name T152
Test name
Test status
Simulation time 387109735 ps
CPU time 21.23 seconds
Started May 21 01:50:26 PM PDT 24
Finished May 21 01:50:49 PM PDT 24
Peak memory 210820 kb
Host smart-ab751915-4dcb-4127-a950-fb8bf9dc3826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920938349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.920938349
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.732687021
Short name T419
Test name
Test status
Simulation time 885366813 ps
CPU time 12.37 seconds
Started May 21 01:50:32 PM PDT 24
Finished May 21 01:50:46 PM PDT 24
Peak memory 200568 kb
Host smart-4614a4f8-bb78-46e9-958b-b2e4c52315a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732687021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.732687021
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.330527089
Short name T455
Test name
Test status
Simulation time 14747244019 ps
CPU time 1146.37 seconds
Started May 21 01:50:35 PM PDT 24
Finished May 21 02:09:42 PM PDT 24
Peak memory 740180 kb
Host smart-4138f3f9-0897-415e-b23d-5a36b7cd289f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330527089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.330527089
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2006113784
Short name T45
Test name
Test status
Simulation time 80155062 ps
CPU time 2.57 seconds
Started May 21 01:50:33 PM PDT 24
Finished May 21 01:50:36 PM PDT 24
Peak memory 200516 kb
Host smart-e7f98f75-7458-46e8-a6f7-4457f21d75fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006113784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2006113784
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2776099925
Short name T438
Test name
Test status
Simulation time 2296776821 ps
CPU time 22.89 seconds
Started May 21 01:50:26 PM PDT 24
Finished May 21 01:50:50 PM PDT 24
Peak memory 200692 kb
Host smart-239a2573-76c0-4a5d-89f7-80f7cd3acdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776099925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2776099925
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1873003666
Short name T425
Test name
Test status
Simulation time 182365576 ps
CPU time 1.96 seconds
Started May 21 01:50:27 PM PDT 24
Finished May 21 01:50:30 PM PDT 24
Peak memory 200772 kb
Host smart-a18fc9ab-5a9f-4a92-b87a-b1f0b431f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873003666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1873003666
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2270322423
Short name T123
Test name
Test status
Simulation time 26117991134 ps
CPU time 497.15 seconds
Started May 21 01:50:35 PM PDT 24
Finished May 21 01:58:52 PM PDT 24
Peak memory 216772 kb
Host smart-a06365a8-6f98-4273-8ec1-6ba95e64e672
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270322423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2270322423
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.3176101367
Short name T1
Test name
Test status
Simulation time 28310141 ps
CPU time 0.96 seconds
Started May 21 01:50:31 PM PDT 24
Finished May 21 01:50:33 PM PDT 24
Peak memory 199324 kb
Host smart-18415fcd-93af-4e10-8929-e0b632e76f80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176101367 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.3176101367
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.4231637397
Short name T183
Test name
Test status
Simulation time 224807173900 ps
CPU time 508.25 seconds
Started May 21 01:50:34 PM PDT 24
Finished May 21 01:59:03 PM PDT 24
Peak memory 200668 kb
Host smart-a797cf4b-b7fc-41d0-8808-8b0c030254fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231637397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.4231637397
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2239182241
Short name T184
Test name
Test status
Simulation time 14525377 ps
CPU time 0.6 seconds
Started May 21 01:50:40 PM PDT 24
Finished May 21 01:50:42 PM PDT 24
Peak memory 196100 kb
Host smart-32ffd2ce-0452-4a63-8649-2dce4abbded9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239182241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2239182241
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1983064560
Short name T313
Test name
Test status
Simulation time 212113910 ps
CPU time 1.56 seconds
Started May 21 01:50:34 PM PDT 24
Finished May 21 01:50:36 PM PDT 24
Peak memory 200572 kb
Host smart-23a3af79-1aa5-4f67-9936-ba03ed528aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983064560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1983064560
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2480481083
Short name T354
Test name
Test status
Simulation time 422972483 ps
CPU time 21.93 seconds
Started May 21 01:50:39 PM PDT 24
Finished May 21 01:51:02 PM PDT 24
Peak memory 200564 kb
Host smart-8378761c-1c8b-42b9-b8e7-c83999e842e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480481083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2480481083
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.346356498
Short name T324
Test name
Test status
Simulation time 3157872233 ps
CPU time 731.22 seconds
Started May 21 01:50:38 PM PDT 24
Finished May 21 02:02:50 PM PDT 24
Peak memory 702904 kb
Host smart-e3e65bf8-e6fe-45cf-b809-0ba59fe50dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346356498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.346356498
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_long_msg.875626789
Short name T348
Test name
Test status
Simulation time 6423834590 ps
CPU time 99.53 seconds
Started May 21 01:50:32 PM PDT 24
Finished May 21 01:52:13 PM PDT 24
Peak memory 200760 kb
Host smart-62783305-1cac-44de-9f85-829de684b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875626789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.875626789
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.481867221
Short name T370
Test name
Test status
Simulation time 129867909 ps
CPU time 4.66 seconds
Started May 21 01:50:32 PM PDT 24
Finished May 21 01:50:38 PM PDT 24
Peak memory 200624 kb
Host smart-6ed3d278-142a-497c-b9ab-edb4bb077664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481867221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.481867221
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1134739950
Short name T343
Test name
Test status
Simulation time 278140395 ps
CPU time 1.44 seconds
Started May 21 01:50:40 PM PDT 24
Finished May 21 01:50:43 PM PDT 24
Peak memory 200652 kb
Host smart-1b53ec14-9935-4345-b63e-85069e62487e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134739950 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1134739950
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2648393484
Short name T400
Test name
Test status
Simulation time 36239810787 ps
CPU time 503.33 seconds
Started May 21 01:50:40 PM PDT 24
Finished May 21 01:59:04 PM PDT 24
Peak memory 200608 kb
Host smart-cc773fc1-21bf-4ac3-b4eb-a5b5da37e203
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648393484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.2648393484
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1613346716
Short name T289
Test name
Test status
Simulation time 39691619 ps
CPU time 0.65 seconds
Started May 21 01:50:47 PM PDT 24
Finished May 21 01:50:48 PM PDT 24
Peak memory 196404 kb
Host smart-a3719e56-c32f-42aa-9ef5-e621cbf5d59e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613346716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1613346716
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1105834042
Short name T121
Test name
Test status
Simulation time 2442514777 ps
CPU time 20.69 seconds
Started May 21 01:50:39 PM PDT 24
Finished May 21 01:51:01 PM PDT 24
Peak memory 212156 kb
Host smart-6d936f8c-4b28-4212-a8cc-25a59b11371e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105834042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1105834042
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3337036917
Short name T433
Test name
Test status
Simulation time 1357817850 ps
CPU time 71.44 seconds
Started May 21 01:50:40 PM PDT 24
Finished May 21 01:51:53 PM PDT 24
Peak memory 200616 kb
Host smart-3a2f82a9-5465-446c-8d80-7e8aa2874b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337036917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3337036917
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.141615730
Short name T143
Test name
Test status
Simulation time 6334423724 ps
CPU time 495.91 seconds
Started May 21 01:50:39 PM PDT 24
Finished May 21 01:58:57 PM PDT 24
Peak memory 655844 kb
Host smart-4620c9e6-eefe-4fa9-8cd3-ba1fdc80afc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141615730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.141615730
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1146566102
Short name T382
Test name
Test status
Simulation time 5653048735 ps
CPU time 72.33 seconds
Started May 21 01:50:40 PM PDT 24
Finished May 21 01:51:53 PM PDT 24
Peak memory 200696 kb
Host smart-4dc53d1b-82e8-4c66-8d84-13678b7e5119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146566102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1146566102
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3445929676
Short name T304
Test name
Test status
Simulation time 407242045 ps
CPU time 4.95 seconds
Started May 21 01:50:39 PM PDT 24
Finished May 21 01:50:44 PM PDT 24
Peak memory 200676 kb
Host smart-f0f51c16-0d93-48c1-a590-2ac9a504c6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445929676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3445929676
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3916076167
Short name T337
Test name
Test status
Simulation time 77496054 ps
CPU time 1.36 seconds
Started May 21 01:50:42 PM PDT 24
Finished May 21 01:50:44 PM PDT 24
Peak memory 200568 kb
Host smart-8bf7ae8d-aaf4-4d36-b853-14e47d94ef00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916076167 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3916076167
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3586290041
Short name T473
Test name
Test status
Simulation time 285147720404 ps
CPU time 523.17 seconds
Started May 21 01:50:42 PM PDT 24
Finished May 21 01:59:26 PM PDT 24
Peak memory 200716 kb
Host smart-6e9038ff-77b1-470b-bd02-374254e1c5fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586290041 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3586290041
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2552647817
Short name T267
Test name
Test status
Simulation time 30994470 ps
CPU time 0.59 seconds
Started May 21 01:50:52 PM PDT 24
Finished May 21 01:50:54 PM PDT 24
Peak memory 195384 kb
Host smart-42b62a30-b14c-411d-ac7f-1cc222b2016d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552647817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2552647817
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4226530506
Short name T325
Test name
Test status
Simulation time 656046523 ps
CPU time 30.8 seconds
Started May 21 01:50:45 PM PDT 24
Finished May 21 01:51:16 PM PDT 24
Peak memory 225456 kb
Host smart-ef90e5ce-739b-4375-95f5-29583ca41481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226530506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4226530506
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.628044508
Short name T251
Test name
Test status
Simulation time 432363931 ps
CPU time 23.23 seconds
Started May 21 01:50:46 PM PDT 24
Finished May 21 01:51:10 PM PDT 24
Peak memory 200592 kb
Host smart-da79ce24-9e94-4f0e-ba97-70a78a2550b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628044508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.628044508
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2659732584
Short name T305
Test name
Test status
Simulation time 2343097923 ps
CPU time 196.53 seconds
Started May 21 01:50:45 PM PDT 24
Finished May 21 01:54:02 PM PDT 24
Peak memory 465720 kb
Host smart-b2770079-ba9c-4a88-820c-088473adb9b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659732584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2659732584
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.605260555
Short name T170
Test name
Test status
Simulation time 2222734722 ps
CPU time 128.95 seconds
Started May 21 01:50:46 PM PDT 24
Finished May 21 01:52:56 PM PDT 24
Peak memory 200760 kb
Host smart-8973fe5a-7d3d-4c05-a2c6-25348fc0eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605260555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.605260555
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3104250631
Short name T134
Test name
Test status
Simulation time 81238818 ps
CPU time 1.09 seconds
Started May 21 01:50:46 PM PDT 24
Finished May 21 01:50:48 PM PDT 24
Peak memory 200592 kb
Host smart-60dbf203-508b-41e9-93a6-f4f554a8418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104250631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3104250631
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.4259647696
Short name T57
Test name
Test status
Simulation time 93896554295 ps
CPU time 1485.17 seconds
Started May 21 01:50:46 PM PDT 24
Finished May 21 02:15:32 PM PDT 24
Peak memory 762824 kb
Host smart-7d26f270-24c8-40aa-8aab-985a03f39faa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259647696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4259647696
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2242565342
Short name T312
Test name
Test status
Simulation time 296760613 ps
CPU time 1.04 seconds
Started May 21 01:50:47 PM PDT 24
Finished May 21 01:50:48 PM PDT 24
Peak memory 200080 kb
Host smart-38a98290-61cb-4d01-8d62-e3f21f068873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242565342 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2242565342
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.988344509
Short name T191
Test name
Test status
Simulation time 109902787271 ps
CPU time 508.39 seconds
Started May 21 01:50:45 PM PDT 24
Finished May 21 01:59:14 PM PDT 24
Peak memory 200672 kb
Host smart-22d79227-d74a-468e-addc-bfd6e10f52ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988344509 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.988344509
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3433837137
Short name T151
Test name
Test status
Simulation time 23400890 ps
CPU time 0.61 seconds
Started May 21 01:50:53 PM PDT 24
Finished May 21 01:50:55 PM PDT 24
Peak memory 196200 kb
Host smart-fd312bb8-651c-467d-891e-1fc24ba6843c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433837137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3433837137
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3496326681
Short name T51
Test name
Test status
Simulation time 1419871620 ps
CPU time 20.54 seconds
Started May 21 01:50:55 PM PDT 24
Finished May 21 01:51:16 PM PDT 24
Peak memory 216980 kb
Host smart-3034125d-6b5a-4037-8755-8a9901a84574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496326681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3496326681
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3138240107
Short name T295
Test name
Test status
Simulation time 8596968064 ps
CPU time 36.05 seconds
Started May 21 01:50:54 PM PDT 24
Finished May 21 01:51:31 PM PDT 24
Peak memory 200696 kb
Host smart-332ce4b7-8d7d-43e8-8aac-0757d6695fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138240107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3138240107
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1679542726
Short name T320
Test name
Test status
Simulation time 5529065904 ps
CPU time 838.9 seconds
Started May 21 01:50:52 PM PDT 24
Finished May 21 02:04:52 PM PDT 24
Peak memory 735380 kb
Host smart-85024905-70a1-4caf-8267-23983cf09c2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679542726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1679542726
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4084864636
Short name T8
Test name
Test status
Simulation time 14980108353 ps
CPU time 101.64 seconds
Started May 21 01:50:53 PM PDT 24
Finished May 21 01:52:35 PM PDT 24
Peak memory 200740 kb
Host smart-fce32156-ccfa-42ce-899e-fc8a7231ea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084864636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4084864636
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3560735723
Short name T334
Test name
Test status
Simulation time 390628780 ps
CPU time 3.09 seconds
Started May 21 01:50:54 PM PDT 24
Finished May 21 01:50:58 PM PDT 24
Peak memory 200644 kb
Host smart-680d969f-537c-4f2a-82b8-4ba2d137214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560735723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3560735723
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1231446084
Short name T374
Test name
Test status
Simulation time 50185800 ps
CPU time 1.02 seconds
Started May 21 01:50:53 PM PDT 24
Finished May 21 01:50:55 PM PDT 24
Peak memory 199008 kb
Host smart-251c9e61-a403-47d8-85c0-8a4e3b15e0e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231446084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1231446084
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2998882001
Short name T195
Test name
Test status
Simulation time 80884836932 ps
CPU time 520.12 seconds
Started May 21 01:50:52 PM PDT 24
Finished May 21 01:59:34 PM PDT 24
Peak memory 200684 kb
Host smart-519c4c94-d83a-4756-9367-f8b5dcaa039a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998882001 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2998882001
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.131171051
Short name T71
Test name
Test status
Simulation time 46945979 ps
CPU time 0.59 seconds
Started May 21 01:51:01 PM PDT 24
Finished May 21 01:51:02 PM PDT 24
Peak memory 196412 kb
Host smart-fcb67c81-4187-4a37-8b76-e86e90310a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131171051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.131171051
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3999317786
Short name T302
Test name
Test status
Simulation time 468028640 ps
CPU time 22.88 seconds
Started May 21 01:50:53 PM PDT 24
Finished May 21 01:51:18 PM PDT 24
Peak memory 208828 kb
Host smart-310f43e9-f418-4936-af8e-24b76d46ec7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999317786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3999317786
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1338054463
Short name T181
Test name
Test status
Simulation time 505912460 ps
CPU time 10.31 seconds
Started May 21 01:50:52 PM PDT 24
Finished May 21 01:51:03 PM PDT 24
Peak memory 200616 kb
Host smart-f72d3f71-239f-4b8b-b418-778e4717d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338054463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1338054463
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4276937440
Short name T228
Test name
Test status
Simulation time 7341958349 ps
CPU time 1264.69 seconds
Started May 21 01:50:52 PM PDT 24
Finished May 21 02:11:58 PM PDT 24
Peak memory 768232 kb
Host smart-cacc139a-622d-49a5-be1e-d64def68ec4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4276937440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4276937440
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1873632823
Short name T126
Test name
Test status
Simulation time 5754792493 ps
CPU time 80.6 seconds
Started May 21 01:50:51 PM PDT 24
Finished May 21 01:52:12 PM PDT 24
Peak memory 200784 kb
Host smart-ba7b1664-d4b7-4c4f-b269-036ec3ab5c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873632823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1873632823
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1570818971
Short name T262
Test name
Test status
Simulation time 1801632794 ps
CPU time 4.31 seconds
Started May 21 01:50:54 PM PDT 24
Finished May 21 01:50:59 PM PDT 24
Peak memory 200640 kb
Host smart-95cd9d11-235a-4c0a-a6a1-b5597b5ec1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570818971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1570818971
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2030911244
Short name T286
Test name
Test status
Simulation time 93070979 ps
CPU time 1.31 seconds
Started May 21 01:50:52 PM PDT 24
Finished May 21 01:50:55 PM PDT 24
Peak memory 200604 kb
Host smart-f71665bf-5716-40fe-b6a9-97a367ef8870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030911244 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2030911244
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2083272334
Short name T28
Test name
Test status
Simulation time 35824543411 ps
CPU time 474 seconds
Started May 21 01:50:53 PM PDT 24
Finished May 21 01:58:48 PM PDT 24
Peak memory 200652 kb
Host smart-ad0b2d40-0748-4b67-8e71-18a0b2763fb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083272334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2083272334
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1726445244
Short name T281
Test name
Test status
Simulation time 94724360 ps
CPU time 0.58 seconds
Started May 21 01:50:59 PM PDT 24
Finished May 21 01:51:00 PM PDT 24
Peak memory 196384 kb
Host smart-5f4071b0-e108-41b0-b17d-b344ab5c5fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726445244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1726445244
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2487529609
Short name T234
Test name
Test status
Simulation time 1354217192 ps
CPU time 20.96 seconds
Started May 21 01:51:01 PM PDT 24
Finished May 21 01:51:23 PM PDT 24
Peak memory 245676 kb
Host smart-8192fae0-a706-4d94-b26b-841508bb09a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487529609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2487529609
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.74487275
Short name T193
Test name
Test status
Simulation time 2015453481 ps
CPU time 37.57 seconds
Started May 21 01:51:00 PM PDT 24
Finished May 21 01:51:38 PM PDT 24
Peak memory 200588 kb
Host smart-eca426d6-a577-4aac-8b60-ca20c2dbad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74487275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.74487275
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3669044115
Short name T68
Test name
Test status
Simulation time 15649208876 ps
CPU time 616.92 seconds
Started May 21 01:51:01 PM PDT 24
Finished May 21 02:01:19 PM PDT 24
Peak memory 752128 kb
Host smart-20043414-2bf4-436c-9a98-32a81d2f050c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669044115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3669044115
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3823169940
Short name T186
Test name
Test status
Simulation time 63671078244 ps
CPU time 117.51 seconds
Started May 21 01:50:59 PM PDT 24
Finished May 21 01:52:57 PM PDT 24
Peak memory 200796 kb
Host smart-0fec9a54-e122-4156-9471-3079a9dd15e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823169940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3823169940
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1870894761
Short name T344
Test name
Test status
Simulation time 264474651 ps
CPU time 2.22 seconds
Started May 21 01:50:59 PM PDT 24
Finished May 21 01:51:01 PM PDT 24
Peak memory 200592 kb
Host smart-b3cb549f-ef62-4319-81d1-5b91b36add17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870894761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1870894761
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.305662294
Short name T310
Test name
Test status
Simulation time 52266214 ps
CPU time 0.97 seconds
Started May 21 01:50:59 PM PDT 24
Finished May 21 01:51:00 PM PDT 24
Peak memory 199188 kb
Host smart-46510fee-1f6e-44d5-b704-1cce5f816357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305662294 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.305662294
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3709591469
Short name T282
Test name
Test status
Simulation time 220498244636 ps
CPU time 568.88 seconds
Started May 21 01:50:57 PM PDT 24
Finished May 21 02:00:27 PM PDT 24
Peak memory 200712 kb
Host smart-b642f881-b95f-45d5-a6b6-0d195e27d091
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709591469 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3709591469
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1316702309
Short name T378
Test name
Test status
Simulation time 49583591 ps
CPU time 0.56 seconds
Started May 21 01:48:58 PM PDT 24
Finished May 21 01:48:59 PM PDT 24
Peak memory 196108 kb
Host smart-65a8210b-f10b-4130-906a-93faad277a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316702309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1316702309
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1518910600
Short name T469
Test name
Test status
Simulation time 527879689 ps
CPU time 18.72 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:49:42 PM PDT 24
Peak memory 203732 kb
Host smart-5b144a22-ef27-445f-afdb-164ef11d97f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518910600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1518910600
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.861209721
Short name T437
Test name
Test status
Simulation time 679060376 ps
CPU time 36.05 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:49:59 PM PDT 24
Peak memory 200636 kb
Host smart-89780796-08c9-4614-89bc-9ecbf74d69f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861209721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.861209721
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3210194443
Short name T359
Test name
Test status
Simulation time 5146039321 ps
CPU time 705.45 seconds
Started May 21 01:49:06 PM PDT 24
Finished May 21 02:00:53 PM PDT 24
Peak memory 738708 kb
Host smart-41e35b18-79d2-41a7-b9ab-73f188da3736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210194443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3210194443
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3169136199
Short name T308
Test name
Test status
Simulation time 28259734940 ps
CPU time 134.87 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:51:33 PM PDT 24
Peak memory 200832 kb
Host smart-fab80938-a920-4035-866a-ca69fa3f0178
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169136199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3169136199
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2769156861
Short name T376
Test name
Test status
Simulation time 13271746012 ps
CPU time 53.5 seconds
Started May 21 01:49:07 PM PDT 24
Finished May 21 01:50:03 PM PDT 24
Peak memory 200808 kb
Host smart-7bc9b274-bf6f-46c9-812b-817a214bf5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769156861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2769156861
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3502513362
Short name T35
Test name
Test status
Simulation time 234178033 ps
CPU time 0.94 seconds
Started May 21 01:49:08 PM PDT 24
Finished May 21 01:49:12 PM PDT 24
Peak memory 218788 kb
Host smart-11b6daae-eab3-49e0-b8b8-4023f3258fe7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502513362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3502513362
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3086423164
Short name T203
Test name
Test status
Simulation time 28941525 ps
CPU time 0.86 seconds
Started May 21 01:48:54 PM PDT 24
Finished May 21 01:48:55 PM PDT 24
Peak memory 199160 kb
Host smart-7816b6df-11fa-4354-8266-90f4e79ad8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086423164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3086423164
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2895330823
Short name T379
Test name
Test status
Simulation time 56871348 ps
CPU time 1.23 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:49:25 PM PDT 24
Peak memory 200568 kb
Host smart-73e62a4d-edb6-4bdd-ae4d-6f80b055a392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895330823 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2895330823
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2218471031
Short name T309
Test name
Test status
Simulation time 29980817287 ps
CPU time 394.67 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:55:57 PM PDT 24
Peak memory 200696 kb
Host smart-c7071e84-19b2-477a-b17a-fbb4281eae5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218471031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2218471031
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3275977112
Short name T187
Test name
Test status
Simulation time 15691545 ps
CPU time 0.6 seconds
Started May 21 01:51:04 PM PDT 24
Finished May 21 01:51:06 PM PDT 24
Peak memory 196384 kb
Host smart-eda3d4ba-aad2-469b-8791-1edddba09f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275977112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3275977112
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.844660654
Short name T238
Test name
Test status
Simulation time 812317170 ps
CPU time 38.44 seconds
Started May 21 01:50:59 PM PDT 24
Finished May 21 01:51:38 PM PDT 24
Peak memory 200576 kb
Host smart-ee5b5ae2-8477-4ff9-a6e0-125d64712bf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844660654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.844660654
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2793470079
Short name T456
Test name
Test status
Simulation time 2878277300 ps
CPU time 38.97 seconds
Started May 21 01:51:03 PM PDT 24
Finished May 21 01:51:44 PM PDT 24
Peak memory 200684 kb
Host smart-6e8ab2ba-4533-4c9f-a7e3-9e64b7e41dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793470079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2793470079
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.194790302
Short name T7
Test name
Test status
Simulation time 1792303171 ps
CPU time 198.21 seconds
Started May 21 01:51:05 PM PDT 24
Finished May 21 01:54:24 PM PDT 24
Peak memory 648716 kb
Host smart-c126128a-d89c-44c2-8bdf-2cd00d250b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194790302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.194790302
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3185173348
Short name T458
Test name
Test status
Simulation time 612150250 ps
CPU time 21.88 seconds
Started May 21 01:51:01 PM PDT 24
Finished May 21 01:51:24 PM PDT 24
Peak memory 200604 kb
Host smart-2304bd72-c0e0-441d-9d8a-2189c3e52956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185173348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3185173348
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.557601991
Short name T200
Test name
Test status
Simulation time 563929524 ps
CPU time 2.9 seconds
Started May 21 01:51:01 PM PDT 24
Finished May 21 01:51:05 PM PDT 24
Peak memory 200636 kb
Host smart-e05dc8b9-5e10-418f-8a1c-db79c909a04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557601991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.557601991
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2393440462
Short name T405
Test name
Test status
Simulation time 100568612 ps
CPU time 1.46 seconds
Started May 21 01:53:47 PM PDT 24
Finished May 21 01:53:49 PM PDT 24
Peak memory 200504 kb
Host smart-70fdd3aa-11b0-4e02-9f52-2661fc054d44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393440462 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2393440462
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1628341061
Short name T293
Test name
Test status
Simulation time 76530785115 ps
CPU time 504.34 seconds
Started May 21 01:51:04 PM PDT 24
Finished May 21 01:59:29 PM PDT 24
Peak memory 200564 kb
Host smart-22f42cd9-014d-40fb-a202-2e5262787a64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628341061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1628341061
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1968677422
Short name T452
Test name
Test status
Simulation time 43897458 ps
CPU time 0.62 seconds
Started May 21 01:51:04 PM PDT 24
Finished May 21 01:51:05 PM PDT 24
Peak memory 196388 kb
Host smart-cfe2d513-86d0-4b6c-b2b3-97d6ba3e601f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968677422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1968677422
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3742175316
Short name T280
Test name
Test status
Simulation time 987074507 ps
CPU time 54.48 seconds
Started May 21 01:51:03 PM PDT 24
Finished May 21 01:51:58 PM PDT 24
Peak memory 225056 kb
Host smart-7cc3d5e2-26a1-4243-90d3-0c52adbb533d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742175316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3742175316
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2820727493
Short name T384
Test name
Test status
Simulation time 6912887355 ps
CPU time 47.99 seconds
Started May 21 01:51:05 PM PDT 24
Finished May 21 01:51:54 PM PDT 24
Peak memory 200736 kb
Host smart-762a36dd-648c-40c2-abcf-a07748cb4564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820727493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2820727493
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1574679745
Short name T345
Test name
Test status
Simulation time 4756086659 ps
CPU time 286.83 seconds
Started May 21 01:51:03 PM PDT 24
Finished May 21 01:55:51 PM PDT 24
Peak memory 649268 kb
Host smart-19266fe2-ecd5-4286-97ac-4923475c547e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574679745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1574679745
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1136421358
Short name T460
Test name
Test status
Simulation time 84710880327 ps
CPU time 99.36 seconds
Started May 21 01:53:11 PM PDT 24
Finished May 21 01:54:52 PM PDT 24
Peak memory 200748 kb
Host smart-5a26bc8e-b5a4-4a15-a008-244c768f0e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136421358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1136421358
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2102223412
Short name T150
Test name
Test status
Simulation time 389639387 ps
CPU time 5.83 seconds
Started May 21 01:51:06 PM PDT 24
Finished May 21 01:51:13 PM PDT 24
Peak memory 200676 kb
Host smart-f9dedbff-01ad-45c5-ae41-02754a5a7031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102223412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2102223412
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2139390713
Short name T362
Test name
Test status
Simulation time 69336948 ps
CPU time 1.23 seconds
Started May 21 01:51:04 PM PDT 24
Finished May 21 01:51:07 PM PDT 24
Peak memory 200576 kb
Host smart-abfc0440-39a7-4f05-99bf-f19a93088bb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139390713 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2139390713
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1641225949
Short name T380
Test name
Test status
Simulation time 7540540466 ps
CPU time 432.83 seconds
Started May 21 01:51:04 PM PDT 24
Finished May 21 01:58:18 PM PDT 24
Peak memory 200696 kb
Host smart-604a7c31-4973-4c51-9a44-7f19fb7122cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641225949 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1641225949
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2203976729
Short name T158
Test name
Test status
Simulation time 34400181 ps
CPU time 0.58 seconds
Started May 21 01:51:10 PM PDT 24
Finished May 21 01:51:11 PM PDT 24
Peak memory 195412 kb
Host smart-fc0852e3-0224-4934-912a-daac39ea4956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203976729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2203976729
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.309171820
Short name T11
Test name
Test status
Simulation time 1346240770 ps
CPU time 41.53 seconds
Started May 21 01:51:10 PM PDT 24
Finished May 21 01:51:53 PM PDT 24
Peak memory 212480 kb
Host smart-f370ba26-a440-4c0b-a962-52e3f8b55704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309171820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.309171820
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3202537475
Short name T406
Test name
Test status
Simulation time 1739181376 ps
CPU time 33.58 seconds
Started May 21 01:51:10 PM PDT 24
Finished May 21 01:51:45 PM PDT 24
Peak memory 200684 kb
Host smart-b4a1ef6e-f9e9-4d36-b96d-a8780cc9234f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202537475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3202537475
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3222089782
Short name T41
Test name
Test status
Simulation time 1406872133 ps
CPU time 337.45 seconds
Started May 21 01:51:13 PM PDT 24
Finished May 21 01:56:51 PM PDT 24
Peak memory 507652 kb
Host smart-c3525dad-03dd-4d75-8a12-910293a65137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222089782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3222089782
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.222761904
Short name T16
Test name
Test status
Simulation time 1627128899 ps
CPU time 24.89 seconds
Started May 21 01:51:11 PM PDT 24
Finished May 21 01:51:37 PM PDT 24
Peak memory 200540 kb
Host smart-a62f08cd-8c3c-4cd5-bcc3-60de827d0da7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222761904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.222761904
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2754970428
Short name T416
Test name
Test status
Simulation time 470108272 ps
CPU time 14.37 seconds
Started May 21 01:51:12 PM PDT 24
Finished May 21 01:51:27 PM PDT 24
Peak memory 200636 kb
Host smart-69ed504d-a50e-44fd-a2c4-a3791213532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754970428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2754970428
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3030188886
Short name T372
Test name
Test status
Simulation time 125185837 ps
CPU time 2.25 seconds
Started May 21 01:51:10 PM PDT 24
Finished May 21 01:51:12 PM PDT 24
Peak memory 200688 kb
Host smart-46e67d34-f75f-40f5-bdd1-2e35da17f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030188886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3030188886
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2968042380
Short name T225
Test name
Test status
Simulation time 282899672 ps
CPU time 1.47 seconds
Started May 21 01:51:10 PM PDT 24
Finished May 21 01:51:12 PM PDT 24
Peak memory 200560 kb
Host smart-062b8d30-e0a0-4737-8613-c5b65c9fd15b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968042380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2968042380
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2649878613
Short name T459
Test name
Test status
Simulation time 128418980088 ps
CPU time 440.04 seconds
Started May 21 01:51:10 PM PDT 24
Finished May 21 01:58:31 PM PDT 24
Peak memory 200584 kb
Host smart-82598728-8b07-459a-a934-3f6cb60fab2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649878613 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2649878613
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2470104783
Short name T331
Test name
Test status
Simulation time 20516821 ps
CPU time 0.59 seconds
Started May 21 01:51:18 PM PDT 24
Finished May 21 01:51:19 PM PDT 24
Peak memory 195284 kb
Host smart-2b9d8dea-7c54-47e9-b8f9-b7d6580cee69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470104783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2470104783
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2307345925
Short name T314
Test name
Test status
Simulation time 3873701117 ps
CPU time 39.45 seconds
Started May 21 01:51:10 PM PDT 24
Finished May 21 01:51:50 PM PDT 24
Peak memory 208972 kb
Host smart-f20f4634-a24e-42ef-9a37-d158c203d3a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307345925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2307345925
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3705258694
Short name T105
Test name
Test status
Simulation time 6482843790 ps
CPU time 61.09 seconds
Started May 21 01:51:16 PM PDT 24
Finished May 21 01:52:18 PM PDT 24
Peak memory 200764 kb
Host smart-dbb4ebc0-74c1-44f1-b191-bae73c399ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705258694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3705258694
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2102985635
Short name T427
Test name
Test status
Simulation time 1082528069 ps
CPU time 192.57 seconds
Started May 21 01:53:15 PM PDT 24
Finished May 21 01:56:29 PM PDT 24
Peak memory 470972 kb
Host smart-437c2909-0272-4424-9416-f916b592bff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102985635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2102985635
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.632773539
Short name T226
Test name
Test status
Simulation time 3080721199 ps
CPU time 97.08 seconds
Started May 21 01:51:11 PM PDT 24
Finished May 21 01:52:49 PM PDT 24
Peak memory 200736 kb
Host smart-e8f069cc-122b-4837-b232-7e7c7918f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632773539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.632773539
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2296423220
Short name T340
Test name
Test status
Simulation time 1277349966 ps
CPU time 7.62 seconds
Started May 21 01:51:12 PM PDT 24
Finished May 21 01:51:20 PM PDT 24
Peak memory 200684 kb
Host smart-94db91ae-ba69-4f65-bf2f-88fb3f6a4fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296423220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2296423220
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1500371912
Short name T43
Test name
Test status
Simulation time 103605658 ps
CPU time 1.02 seconds
Started May 21 01:51:15 PM PDT 24
Finished May 21 01:51:18 PM PDT 24
Peak memory 200076 kb
Host smart-0957b338-2899-45df-ae45-4619cbb74acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500371912 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1500371912
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.383149430
Short name T172
Test name
Test status
Simulation time 56606145943 ps
CPU time 517.1 seconds
Started May 21 01:53:14 PM PDT 24
Finished May 21 02:01:52 PM PDT 24
Peak memory 200688 kb
Host smart-88909879-4c68-480c-83ff-e15ff414ec0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383149430 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.383149430
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2467986204
Short name T22
Test name
Test status
Simulation time 60381051 ps
CPU time 0.59 seconds
Started May 21 01:51:25 PM PDT 24
Finished May 21 01:51:26 PM PDT 24
Peak memory 195376 kb
Host smart-c3474e53-ae84-4d32-83ac-5ceb5c6e6db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467986204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2467986204
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.500098692
Short name T284
Test name
Test status
Simulation time 680931890 ps
CPU time 34.33 seconds
Started May 21 01:51:16 PM PDT 24
Finished May 21 01:51:51 PM PDT 24
Peak memory 207912 kb
Host smart-b4ca041f-adad-45c9-b342-60fbfb7d4ee5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500098692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.500098692
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3011555409
Short name T306
Test name
Test status
Simulation time 3298912844 ps
CPU time 30.73 seconds
Started May 21 01:51:15 PM PDT 24
Finished May 21 01:51:47 PM PDT 24
Peak memory 200800 kb
Host smart-1370ca55-192a-487d-8fea-bc0919b67b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011555409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3011555409
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2060757293
Short name T332
Test name
Test status
Simulation time 492934910 ps
CPU time 107.99 seconds
Started May 21 01:51:17 PM PDT 24
Finished May 21 01:53:06 PM PDT 24
Peak memory 367616 kb
Host smart-95fa7810-6fda-42b0-b860-d6d2f8c1e045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060757293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2060757293
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2599952880
Short name T443
Test name
Test status
Simulation time 1391482672 ps
CPU time 33.44 seconds
Started May 21 01:51:15 PM PDT 24
Finished May 21 01:51:49 PM PDT 24
Peak memory 200636 kb
Host smart-7f17931f-0ae5-4287-9e6f-428c02f8b731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599952880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2599952880
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3154498113
Short name T146
Test name
Test status
Simulation time 156211910 ps
CPU time 5.42 seconds
Started May 21 01:51:16 PM PDT 24
Finished May 21 01:51:22 PM PDT 24
Peak memory 200636 kb
Host smart-be6ebe7e-517c-492b-89ce-71fc6d8abcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154498113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3154498113
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3663490307
Short name T74
Test name
Test status
Simulation time 156480557 ps
CPU time 1.05 seconds
Started May 21 01:51:23 PM PDT 24
Finished May 21 01:51:25 PM PDT 24
Peak memory 199084 kb
Host smart-02a8b36a-d736-40a4-b948-51056969306a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663490307 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3663490307
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.148166725
Short name T434
Test name
Test status
Simulation time 28086932168 ps
CPU time 517.46 seconds
Started May 21 01:51:23 PM PDT 24
Finished May 21 02:00:01 PM PDT 24
Peak memory 200632 kb
Host smart-fd6a6c64-f3e2-4308-ba45-86cd45d1a881
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148166725 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.148166725
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.729286487
Short name T462
Test name
Test status
Simulation time 13050259 ps
CPU time 0.61 seconds
Started May 21 01:51:24 PM PDT 24
Finished May 21 01:51:25 PM PDT 24
Peak memory 196080 kb
Host smart-729957d2-80e0-41c2-a090-ff17e562a467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729286487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.729286487
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1262717381
Short name T268
Test name
Test status
Simulation time 914391095 ps
CPU time 29.11 seconds
Started May 21 01:51:27 PM PDT 24
Finished May 21 01:51:56 PM PDT 24
Peak memory 237444 kb
Host smart-b54e0598-ea5d-4d45-8512-6679f26773f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262717381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1262717381
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3114300012
Short name T361
Test name
Test status
Simulation time 19921893746 ps
CPU time 38.61 seconds
Started May 21 01:51:23 PM PDT 24
Finished May 21 01:52:03 PM PDT 24
Peak memory 200724 kb
Host smart-08bc93f1-726c-4e88-916f-57e1012251b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114300012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3114300012
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2493085397
Short name T250
Test name
Test status
Simulation time 507247897 ps
CPU time 62.87 seconds
Started May 21 01:51:26 PM PDT 24
Finished May 21 01:52:29 PM PDT 24
Peak memory 340832 kb
Host smart-5d59d33c-d3b6-4bdf-a916-df89cfa813e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493085397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2493085397
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1797311937
Short name T445
Test name
Test status
Simulation time 507062492 ps
CPU time 7.69 seconds
Started May 21 01:51:27 PM PDT 24
Finished May 21 01:51:35 PM PDT 24
Peak memory 200596 kb
Host smart-8d5fd65b-6833-43f0-a130-ccb8a997e070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797311937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1797311937
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3741555129
Short name T212
Test name
Test status
Simulation time 441122511 ps
CPU time 6.89 seconds
Started May 21 01:51:26 PM PDT 24
Finished May 21 01:51:34 PM PDT 24
Peak memory 200604 kb
Host smart-60c44f89-8c11-44af-a399-93e3349b35a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741555129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3741555129
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1484097768
Short name T363
Test name
Test status
Simulation time 37440342499 ps
CPU time 472.6 seconds
Started May 21 01:53:15 PM PDT 24
Finished May 21 02:01:09 PM PDT 24
Peak memory 216740 kb
Host smart-261629f9-d3df-4612-837d-11528f5cb204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484097768 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1484097768
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3451801369
Short name T440
Test name
Test status
Simulation time 42994848 ps
CPU time 1.03 seconds
Started May 21 01:51:22 PM PDT 24
Finished May 21 01:51:23 PM PDT 24
Peak memory 199360 kb
Host smart-1ab57a25-a297-402f-b123-3f3a94c293d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451801369 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3451801369
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3781521935
Short name T441
Test name
Test status
Simulation time 7507081118 ps
CPU time 435 seconds
Started May 21 01:51:22 PM PDT 24
Finished May 21 01:58:38 PM PDT 24
Peak memory 200696 kb
Host smart-10eecb07-d8d9-467c-83c8-d21a1df5dff3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781521935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3781521935
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.204341248
Short name T470
Test name
Test status
Simulation time 11838046 ps
CPU time 0.58 seconds
Started May 21 01:53:16 PM PDT 24
Finished May 21 01:53:18 PM PDT 24
Peak memory 195792 kb
Host smart-00d1bc6a-5daa-498b-8306-77d2d24c20c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204341248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.204341248
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2842560448
Short name T272
Test name
Test status
Simulation time 7905430201 ps
CPU time 39.38 seconds
Started May 21 01:51:30 PM PDT 24
Finished May 21 01:52:10 PM PDT 24
Peak memory 229724 kb
Host smart-755ce4c6-2c96-4516-aeee-9f003b77d2f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842560448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2842560448
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2057421582
Short name T299
Test name
Test status
Simulation time 2034756498 ps
CPU time 29.41 seconds
Started May 21 01:51:28 PM PDT 24
Finished May 21 01:51:58 PM PDT 24
Peak memory 200592 kb
Host smart-3c1c2144-5ded-4233-98eb-7caab692c2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057421582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2057421582
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1653014259
Short name T410
Test name
Test status
Simulation time 9767802412 ps
CPU time 545.82 seconds
Started May 21 01:51:29 PM PDT 24
Finished May 21 02:00:35 PM PDT 24
Peak memory 690088 kb
Host smart-1a1b430b-72f6-4d5f-a72d-03b77e6ed9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653014259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1653014259
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1285673856
Short name T218
Test name
Test status
Simulation time 605888673 ps
CPU time 34.45 seconds
Started May 21 01:51:28 PM PDT 24
Finished May 21 01:52:03 PM PDT 24
Peak memory 200652 kb
Host smart-037840d1-b6da-4968-8e9d-b2059990f6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285673856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1285673856
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3233376637
Short name T330
Test name
Test status
Simulation time 267407024 ps
CPU time 3.57 seconds
Started May 21 01:51:27 PM PDT 24
Finished May 21 01:51:31 PM PDT 24
Peak memory 200652 kb
Host smart-aad1d9a7-9488-449c-b1ed-481642f7f10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233376637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3233376637
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2190770475
Short name T260
Test name
Test status
Simulation time 162530241506 ps
CPU time 1358.23 seconds
Started May 21 01:53:12 PM PDT 24
Finished May 21 02:15:51 PM PDT 24
Peak memory 714024 kb
Host smart-ad5c47bf-9670-4410-b9fe-cc337c14f053
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190770475 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2190770475
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2267786264
Short name T232
Test name
Test status
Simulation time 52653656 ps
CPU time 0.97 seconds
Started May 21 01:51:30 PM PDT 24
Finished May 21 01:51:31 PM PDT 24
Peak memory 200008 kb
Host smart-ad61f8ba-8fbb-4c6a-adf3-185b2e0c970e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267786264 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2267786264
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2173128569
Short name T467
Test name
Test status
Simulation time 126491977265 ps
CPU time 567.61 seconds
Started May 21 01:51:28 PM PDT 24
Finished May 21 02:00:57 PM PDT 24
Peak memory 200692 kb
Host smart-32500cb8-de63-4dfa-bd0b-66cf44c613df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173128569 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2173128569
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2265855633
Short name T292
Test name
Test status
Simulation time 14897992 ps
CPU time 0.6 seconds
Started May 21 01:51:36 PM PDT 24
Finished May 21 01:51:38 PM PDT 24
Peak memory 196424 kb
Host smart-f1068b40-fe14-490d-92ef-066ff31d0399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265855633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2265855633
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1944780393
Short name T398
Test name
Test status
Simulation time 438718490 ps
CPU time 23.62 seconds
Started May 21 01:51:34 PM PDT 24
Finished May 21 01:51:58 PM PDT 24
Peak memory 223196 kb
Host smart-98eb9cc6-1a56-46f2-80b2-4268c9659b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944780393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1944780393
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1052737226
Short name T326
Test name
Test status
Simulation time 18445003 ps
CPU time 0.74 seconds
Started May 21 01:51:34 PM PDT 24
Finished May 21 01:51:36 PM PDT 24
Peak memory 197944 kb
Host smart-c86ad970-d3cd-4842-baae-4693f3e813e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052737226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1052737226
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3578981295
Short name T355
Test name
Test status
Simulation time 459702506 ps
CPU time 93.27 seconds
Started May 21 01:51:33 PM PDT 24
Finished May 21 01:53:07 PM PDT 24
Peak memory 431716 kb
Host smart-7a65fad9-19f2-4b64-aa19-e25254414490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578981295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3578981295
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_long_msg.257373006
Short name T135
Test name
Test status
Simulation time 5031140722 ps
CPU time 77.89 seconds
Started May 21 01:51:34 PM PDT 24
Finished May 21 01:52:53 PM PDT 24
Peak memory 200680 kb
Host smart-00d718c6-3eb1-4156-8a4d-b022d0461e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257373006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.257373006
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.553861416
Short name T290
Test name
Test status
Simulation time 107339273 ps
CPU time 1.68 seconds
Started May 21 01:51:35 PM PDT 24
Finished May 21 01:51:37 PM PDT 24
Peak memory 200644 kb
Host smart-bec27e0c-427d-4b17-bf0b-508b076c91e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553861416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.553861416
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2967651863
Short name T311
Test name
Test status
Simulation time 45101198 ps
CPU time 1.06 seconds
Started May 21 01:51:36 PM PDT 24
Finished May 21 01:51:39 PM PDT 24
Peak memory 200188 kb
Host smart-5dd402d9-b5c6-4ac3-92bb-5089c0c27678
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967651863 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2967651863
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1882984421
Short name T402
Test name
Test status
Simulation time 23545170 ps
CPU time 0.58 seconds
Started May 21 01:51:44 PM PDT 24
Finished May 21 01:51:46 PM PDT 24
Peak memory 195368 kb
Host smart-dc1e0a44-4b84-4700-8138-ee571f926aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882984421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1882984421
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.717591094
Short name T303
Test name
Test status
Simulation time 2195046904 ps
CPU time 24.67 seconds
Started May 21 01:51:42 PM PDT 24
Finished May 21 01:52:08 PM PDT 24
Peak memory 216964 kb
Host smart-375eab92-65bc-403b-8986-b7f2701b1613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717591094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.717591094
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.621301646
Short name T224
Test name
Test status
Simulation time 670046076 ps
CPU time 7 seconds
Started May 21 01:51:42 PM PDT 24
Finished May 21 01:51:50 PM PDT 24
Peak memory 200624 kb
Host smart-c61b907a-e345-4536-99b4-4ba545d89b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621301646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.621301646
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.533669516
Short name T196
Test name
Test status
Simulation time 6133543452 ps
CPU time 317.71 seconds
Started May 21 01:51:43 PM PDT 24
Finished May 21 01:57:02 PM PDT 24
Peak memory 489348 kb
Host smart-c75d40b8-8e2c-411d-b831-9fcdbc27f0e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533669516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.533669516
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1033472998
Short name T136
Test name
Test status
Simulation time 2474383343 ps
CPU time 22.92 seconds
Started May 21 01:51:36 PM PDT 24
Finished May 21 01:52:00 PM PDT 24
Peak memory 200716 kb
Host smart-9e15c61a-2e69-4560-90f4-e7f9e12a4cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033472998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1033472998
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.4264167147
Short name T418
Test name
Test status
Simulation time 2164804409 ps
CPU time 7.3 seconds
Started May 21 01:51:36 PM PDT 24
Finished May 21 01:51:45 PM PDT 24
Peak memory 200764 kb
Host smart-569027f0-b4d6-4a47-9229-e8ea9b1c6f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264167147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.4264167147
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3857792665
Short name T246
Test name
Test status
Simulation time 104305782 ps
CPU time 0.97 seconds
Started May 21 01:51:42 PM PDT 24
Finished May 21 01:51:43 PM PDT 24
Peak memory 200096 kb
Host smart-72ec45ae-3f5d-4a68-9507-40cc45dc4ec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857792665 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3857792665
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3182804125
Short name T17
Test name
Test status
Simulation time 56577746137 ps
CPU time 515.39 seconds
Started May 21 01:51:42 PM PDT 24
Finished May 21 02:00:18 PM PDT 24
Peak memory 200668 kb
Host smart-8ba7218b-ca46-4537-b1f9-24bc0f843b5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182804125 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3182804125
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3636410872
Short name T474
Test name
Test status
Simulation time 14372012 ps
CPU time 0.63 seconds
Started May 21 01:51:43 PM PDT 24
Finished May 21 01:51:45 PM PDT 24
Peak memory 197284 kb
Host smart-24c27459-7a6d-4280-8182-85e940254aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636410872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3636410872
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.325925159
Short name T155
Test name
Test status
Simulation time 1710200183 ps
CPU time 51.76 seconds
Started May 21 01:51:42 PM PDT 24
Finished May 21 01:52:34 PM PDT 24
Peak memory 241372 kb
Host smart-b558b6dc-3a4e-4c58-bbf1-02156d952b4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325925159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.325925159
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3957074932
Short name T104
Test name
Test status
Simulation time 1609766810 ps
CPU time 33.68 seconds
Started May 21 01:51:43 PM PDT 24
Finished May 21 01:52:19 PM PDT 24
Peak memory 200624 kb
Host smart-660337c3-285a-4632-907a-4dca9cc4a424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957074932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3957074932
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.575107949
Short name T335
Test name
Test status
Simulation time 793793530 ps
CPU time 134.58 seconds
Started May 21 01:51:42 PM PDT 24
Finished May 21 01:53:58 PM PDT 24
Peak memory 331716 kb
Host smart-0f54f19e-4f23-4530-9fe5-0ae8e6233c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575107949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.575107949
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.181129863
Short name T211
Test name
Test status
Simulation time 22146565926 ps
CPU time 120.57 seconds
Started May 21 01:51:43 PM PDT 24
Finished May 21 01:53:45 PM PDT 24
Peak memory 200608 kb
Host smart-a1139c27-3403-407f-8d3b-bd5c86e0c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181129863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.181129863
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3657423407
Short name T360
Test name
Test status
Simulation time 61410453 ps
CPU time 1.53 seconds
Started May 21 01:51:44 PM PDT 24
Finished May 21 01:51:47 PM PDT 24
Peak memory 200684 kb
Host smart-b4ea003f-f7c7-4517-b585-3fd99246468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657423407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3657423407
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3153449038
Short name T129
Test name
Test status
Simulation time 208369151 ps
CPU time 1.2 seconds
Started May 21 01:51:44 PM PDT 24
Finished May 21 01:51:47 PM PDT 24
Peak memory 200572 kb
Host smart-6c3f69af-e238-406a-8dd2-81918af718f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153449038 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3153449038
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2609318685
Short name T69
Test name
Test status
Simulation time 37420505990 ps
CPU time 478.5 seconds
Started May 21 01:51:42 PM PDT 24
Finished May 21 01:59:42 PM PDT 24
Peak memory 200584 kb
Host smart-559793f6-7f7b-4e92-a2a8-8760da4d5817
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609318685 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2609318685
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3128552935
Short name T202
Test name
Test status
Simulation time 45886021 ps
CPU time 0.6 seconds
Started May 21 01:49:06 PM PDT 24
Finished May 21 01:49:08 PM PDT 24
Peak memory 196424 kb
Host smart-0bcadd2d-3b14-4622-bf9b-4970a4b17ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128552935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3128552935
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3835975340
Short name T229
Test name
Test status
Simulation time 569339030 ps
CPU time 27.68 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:49:50 PM PDT 24
Peak memory 216260 kb
Host smart-789d63ed-8c4b-4615-b550-7cd18199ed1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835975340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3835975340
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.4006662753
Short name T244
Test name
Test status
Simulation time 2183205371 ps
CPU time 27.93 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:49:52 PM PDT 24
Peak memory 200696 kb
Host smart-1f0b77a2-148b-4e5b-83c4-62ca2e12b698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006662753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4006662753
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1903103018
Short name T373
Test name
Test status
Simulation time 3382457430 ps
CPU time 137.99 seconds
Started May 21 01:49:05 PM PDT 24
Finished May 21 01:51:24 PM PDT 24
Peak memory 439128 kb
Host smart-fbd62c95-9a84-4960-bb83-2689906eb2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903103018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1903103018
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2869183912
Short name T274
Test name
Test status
Simulation time 4464552896 ps
CPU time 62.63 seconds
Started May 21 01:48:54 PM PDT 24
Finished May 21 01:49:58 PM PDT 24
Peak memory 200692 kb
Host smart-0ae9ffe8-b209-4763-8b7e-f02760633e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869183912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2869183912
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1350072862
Short name T33
Test name
Test status
Simulation time 252186700 ps
CPU time 0.87 seconds
Started May 21 01:48:57 PM PDT 24
Finished May 21 01:48:59 PM PDT 24
Peak memory 218844 kb
Host smart-f8cb88c0-c8be-44de-8b4e-11e1989fbc1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350072862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1350072862
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1106512464
Short name T247
Test name
Test status
Simulation time 45606934 ps
CPU time 1.29 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:49:23 PM PDT 24
Peak memory 200628 kb
Host smart-61159702-7b37-4c0e-a939-edd6037be879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106512464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1106512464
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.548881787
Short name T131
Test name
Test status
Simulation time 38920698 ps
CPU time 1.09 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:49:19 PM PDT 24
Peak memory 200404 kb
Host smart-80974a78-c6cc-4c4e-a92a-96ad79b922b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548881787 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.548881787
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1940062354
Short name T446
Test name
Test status
Simulation time 89321895382 ps
CPU time 562.51 seconds
Started May 21 01:49:05 PM PDT 24
Finished May 21 01:58:29 PM PDT 24
Peak memory 200648 kb
Host smart-5ad2e0c3-a113-4159-af61-e61da7739fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940062354 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.1940062354
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.420401300
Short name T420
Test name
Test status
Simulation time 45523365 ps
CPU time 0.65 seconds
Started May 21 01:51:53 PM PDT 24
Finished May 21 01:51:55 PM PDT 24
Peak memory 197032 kb
Host smart-ede1e80b-b8f5-4a64-9e3d-d94b2c19e8b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420401300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.420401300
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.503345855
Short name T198
Test name
Test status
Simulation time 122706437 ps
CPU time 7.85 seconds
Started May 21 01:51:49 PM PDT 24
Finished May 21 01:51:57 PM PDT 24
Peak memory 223348 kb
Host smart-1250e55e-8d89-4d76-9f64-33e972687383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503345855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.503345855
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2635830629
Short name T364
Test name
Test status
Simulation time 11251280686 ps
CPU time 63.93 seconds
Started May 21 01:51:48 PM PDT 24
Finished May 21 01:52:52 PM PDT 24
Peak memory 200736 kb
Host smart-cdaa9b21-2371-4283-84c7-b4c19c644ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635830629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2635830629
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.4010390539
Short name T424
Test name
Test status
Simulation time 7623378936 ps
CPU time 1204.84 seconds
Started May 21 01:51:47 PM PDT 24
Finished May 21 02:11:52 PM PDT 24
Peak memory 723776 kb
Host smart-8589faa9-9cec-453d-8931-b5d8f5305182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010390539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4010390539
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3007517736
Short name T13
Test name
Test status
Simulation time 2911787200 ps
CPU time 34.67 seconds
Started May 21 01:51:48 PM PDT 24
Finished May 21 01:52:23 PM PDT 24
Peak memory 200804 kb
Host smart-b033ca6a-a60b-42ad-bcae-16d23220aefa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007517736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3007517736
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1764296689
Short name T423
Test name
Test status
Simulation time 4530915214 ps
CPU time 125.14 seconds
Started May 21 01:51:43 PM PDT 24
Finished May 21 01:53:50 PM PDT 24
Peak memory 200736 kb
Host smart-16d051f6-c421-46b0-99eb-1a8bb3ee05ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764296689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1764296689
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1272267461
Short name T154
Test name
Test status
Simulation time 22508339 ps
CPU time 1.03 seconds
Started May 21 01:51:43 PM PDT 24
Finished May 21 01:51:45 PM PDT 24
Peak memory 200640 kb
Host smart-44eb0b46-bee2-4dbe-b947-62f41acba0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272267461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1272267461
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2911699516
Short name T216
Test name
Test status
Simulation time 57562195 ps
CPU time 0.99 seconds
Started May 21 01:51:47 PM PDT 24
Finished May 21 01:51:49 PM PDT 24
Peak memory 199232 kb
Host smart-3e4cca57-d6c9-4367-abc3-e6cafe459236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911699516 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2911699516
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2055867139
Short name T39
Test name
Test status
Simulation time 97975323742 ps
CPU time 517.94 seconds
Started May 21 01:51:50 PM PDT 24
Finished May 21 02:00:28 PM PDT 24
Peak memory 200652 kb
Host smart-48608681-e067-4f82-8615-3e56e210a8bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055867139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2055867139
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3796345362
Short name T349
Test name
Test status
Simulation time 12278933 ps
CPU time 0.59 seconds
Started May 21 01:51:54 PM PDT 24
Finished May 21 01:51:56 PM PDT 24
Peak memory 195372 kb
Host smart-8fd87ab8-c0f2-407b-ba5a-55a737a03e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796345362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3796345362
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2612159493
Short name T288
Test name
Test status
Simulation time 673372578 ps
CPU time 33.27 seconds
Started May 21 01:51:56 PM PDT 24
Finished May 21 01:52:30 PM PDT 24
Peak memory 217056 kb
Host smart-f8053d77-3017-4e75-9aaf-963e1dda4b16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612159493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2612159493
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1869655863
Short name T209
Test name
Test status
Simulation time 16835389553 ps
CPU time 1207.36 seconds
Started May 21 01:51:55 PM PDT 24
Finished May 21 02:12:03 PM PDT 24
Peak memory 756200 kb
Host smart-c0b1f841-8b65-48fb-83b1-500dba7058f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1869655863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1869655863
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.4095461490
Short name T46
Test name
Test status
Simulation time 7201624417 ps
CPU time 17.9 seconds
Started May 21 01:51:53 PM PDT 24
Finished May 21 01:52:12 PM PDT 24
Peak memory 200556 kb
Host smart-d136a3ef-aa21-4ae7-ab54-e4311bdd54fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095461490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.4095461490
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3101478785
Short name T333
Test name
Test status
Simulation time 3465124509 ps
CPU time 55.47 seconds
Started May 21 01:51:54 PM PDT 24
Finished May 21 01:52:51 PM PDT 24
Peak memory 200732 kb
Host smart-0f9d3584-3907-4306-bb9b-138a0600d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101478785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3101478785
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1421870549
Short name T454
Test name
Test status
Simulation time 29371797 ps
CPU time 1.23 seconds
Started May 21 01:51:55 PM PDT 24
Finished May 21 01:51:57 PM PDT 24
Peak memory 200556 kb
Host smart-3d904e52-4d35-4abb-b144-cf374eb88d58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421870549 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1421870549
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.4042296166
Short name T421
Test name
Test status
Simulation time 115124479532 ps
CPU time 489.64 seconds
Started May 21 01:51:55 PM PDT 24
Finished May 21 02:00:06 PM PDT 24
Peak memory 200680 kb
Host smart-a8940977-1a8e-49a0-8474-e094a2b07a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042296166 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.4042296166
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_alert_test.997549212
Short name T125
Test name
Test status
Simulation time 29460161 ps
CPU time 0.6 seconds
Started May 21 01:52:00 PM PDT 24
Finished May 21 01:52:01 PM PDT 24
Peak memory 196008 kb
Host smart-9ce54a41-b4c2-4d36-955b-bf08567442ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997549212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.997549212
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.575949008
Short name T254
Test name
Test status
Simulation time 1084409681 ps
CPU time 14.98 seconds
Started May 21 01:51:54 PM PDT 24
Finished May 21 01:52:10 PM PDT 24
Peak memory 208816 kb
Host smart-3137f525-901e-4d95-a023-0e07b6b5d5f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575949008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.575949008
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2576373008
Short name T413
Test name
Test status
Simulation time 12588839858 ps
CPU time 42.07 seconds
Started May 21 01:52:04 PM PDT 24
Finished May 21 01:52:47 PM PDT 24
Peak memory 200740 kb
Host smart-798f140d-b625-466d-877b-2f289aa764c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576373008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2576373008
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4220156941
Short name T279
Test name
Test status
Simulation time 1250031701 ps
CPU time 151.44 seconds
Started May 21 01:51:54 PM PDT 24
Finished May 21 01:54:26 PM PDT 24
Peak memory 464636 kb
Host smart-a5320919-3f8f-4bb2-b104-a28cc93294ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220156941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4220156941
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2520282736
Short name T227
Test name
Test status
Simulation time 6023762571 ps
CPU time 89.02 seconds
Started May 21 01:51:56 PM PDT 24
Finished May 21 01:53:26 PM PDT 24
Peak memory 200692 kb
Host smart-72f351af-785b-4816-8aac-4e606a7687e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520282736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2520282736
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1035130108
Short name T367
Test name
Test status
Simulation time 42605041 ps
CPU time 1.34 seconds
Started May 21 01:51:55 PM PDT 24
Finished May 21 01:51:57 PM PDT 24
Peak memory 200628 kb
Host smart-909006a4-064e-4df0-aa77-4e0f89f13fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035130108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1035130108
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1740937022
Short name T25
Test name
Test status
Simulation time 115211499 ps
CPU time 1.28 seconds
Started May 21 01:52:01 PM PDT 24
Finished May 21 01:52:03 PM PDT 24
Peak memory 200564 kb
Host smart-8661c66b-a0f8-450c-a176-b3ff5b360916
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740937022 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1740937022
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.4228622508
Short name T300
Test name
Test status
Simulation time 82422456314 ps
CPU time 496.87 seconds
Started May 21 01:52:01 PM PDT 24
Finished May 21 02:00:19 PM PDT 24
Peak memory 200648 kb
Host smart-5591c6aa-db76-4d4e-b8fe-274d0912d531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228622508 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.4228622508
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2724614536
Short name T153
Test name
Test status
Simulation time 24177166 ps
CPU time 0.6 seconds
Started May 21 01:52:07 PM PDT 24
Finished May 21 01:52:09 PM PDT 24
Peak memory 196304 kb
Host smart-8ed81a3a-7a28-4956-adae-1d8fd3d97238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724614536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2724614536
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3544987665
Short name T20
Test name
Test status
Simulation time 814206633 ps
CPU time 21.23 seconds
Started May 21 01:52:01 PM PDT 24
Finished May 21 01:52:23 PM PDT 24
Peak memory 219292 kb
Host smart-90081563-80ad-404b-b19a-d8e4a65571a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544987665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3544987665
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.315799953
Short name T4
Test name
Test status
Simulation time 241313088 ps
CPU time 2.37 seconds
Started May 21 01:52:02 PM PDT 24
Finished May 21 01:52:05 PM PDT 24
Peak memory 200560 kb
Host smart-e5f0b85b-40ab-4226-aa8a-608c9868601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315799953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.315799953
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2822011605
Short name T408
Test name
Test status
Simulation time 1035314785 ps
CPU time 224.24 seconds
Started May 21 01:52:02 PM PDT 24
Finished May 21 01:55:47 PM PDT 24
Peak memory 661264 kb
Host smart-be63af8a-a7f1-49d7-9f62-7e75fe3d930a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822011605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2822011605
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1671777030
Short name T171
Test name
Test status
Simulation time 1442854302 ps
CPU time 19.61 seconds
Started May 21 01:52:00 PM PDT 24
Finished May 21 01:52:20 PM PDT 24
Peak memory 200660 kb
Host smart-398da9f2-6d11-4cbf-a285-7735872655f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671777030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1671777030
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.49774405
Short name T99
Test name
Test status
Simulation time 266036983 ps
CPU time 4.66 seconds
Started May 21 01:52:03 PM PDT 24
Finished May 21 01:52:08 PM PDT 24
Peak memory 200500 kb
Host smart-b533bc76-48c8-4435-8849-9be92370877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49774405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.49774405
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.512448821
Short name T182
Test name
Test status
Simulation time 285226338 ps
CPU time 1.43 seconds
Started May 21 01:52:01 PM PDT 24
Finished May 21 01:52:03 PM PDT 24
Peak memory 199460 kb
Host smart-c18e302a-7eff-415a-a2ca-f368bff0696b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512448821 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.512448821
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.262117615
Short name T393
Test name
Test status
Simulation time 15287599507 ps
CPU time 415.76 seconds
Started May 21 01:52:03 PM PDT 24
Finished May 21 01:59:00 PM PDT 24
Peak memory 200628 kb
Host smart-522dc05d-f60a-4dfd-8c1c-1479e8819f00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262117615 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.262117615
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.697779432
Short name T233
Test name
Test status
Simulation time 14277488 ps
CPU time 0.61 seconds
Started May 21 01:53:16 PM PDT 24
Finished May 21 01:53:18 PM PDT 24
Peak memory 196400 kb
Host smart-8ab7f55c-b1cf-4db9-a5aa-cac76932fe51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697779432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.697779432
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2082426834
Short name T248
Test name
Test status
Simulation time 1909844884 ps
CPU time 25.43 seconds
Started May 21 01:52:07 PM PDT 24
Finished May 21 01:52:33 PM PDT 24
Peak memory 225208 kb
Host smart-6b1cead2-0746-4145-9ef2-6c5fc0df0221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082426834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2082426834
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4293594333
Short name T221
Test name
Test status
Simulation time 4527849321 ps
CPU time 83.92 seconds
Started May 21 01:52:07 PM PDT 24
Finished May 21 01:53:32 PM PDT 24
Peak memory 200808 kb
Host smart-4952a1df-2d4c-452b-826f-153ad98adcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293594333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4293594333
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_long_msg.133654142
Short name T263
Test name
Test status
Simulation time 1943692612 ps
CPU time 112.41 seconds
Started May 21 01:52:07 PM PDT 24
Finished May 21 01:54:01 PM PDT 24
Peak memory 200560 kb
Host smart-0c7ee8dd-004e-4860-aa54-d7bf14a3e0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133654142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.133654142
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.660070482
Short name T258
Test name
Test status
Simulation time 46668180 ps
CPU time 1.84 seconds
Started May 21 01:52:08 PM PDT 24
Finished May 21 01:52:11 PM PDT 24
Peak memory 200632 kb
Host smart-1f5354a4-40b1-4245-b959-505526eca907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660070482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.660070482
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1444152
Short name T432
Test name
Test status
Simulation time 57138913 ps
CPU time 1.31 seconds
Started May 21 01:52:09 PM PDT 24
Finished May 21 01:52:11 PM PDT 24
Peak memory 200584 kb
Host smart-0a714405-08e8-441a-9e07-654f3756d4d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444152 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.hmac_test_hmac_vectors.1444152
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2099085663
Short name T156
Test name
Test status
Simulation time 8159248077 ps
CPU time 484.73 seconds
Started May 21 01:53:11 PM PDT 24
Finished May 21 02:01:17 PM PDT 24
Peak memory 200724 kb
Host smart-8ad98654-d646-417c-8a2f-74aef12b4378
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099085663 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2099085663
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_alert_test.578585123
Short name T21
Test name
Test status
Simulation time 15827134 ps
CPU time 0.61 seconds
Started May 21 01:52:16 PM PDT 24
Finished May 21 01:52:17 PM PDT 24
Peak memory 196384 kb
Host smart-8d8d7157-b5c6-4fb9-9b9a-5886de6c3461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578585123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.578585123
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3638943161
Short name T390
Test name
Test status
Simulation time 5226783167 ps
CPU time 47.11 seconds
Started May 21 01:52:07 PM PDT 24
Finished May 21 01:52:56 PM PDT 24
Peak memory 238688 kb
Host smart-4f8d1d79-bf4d-4673-8f2c-0cdeb21781d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638943161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3638943161
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3486544722
Short name T442
Test name
Test status
Simulation time 13164114936 ps
CPU time 35.24 seconds
Started May 21 01:52:14 PM PDT 24
Finished May 21 01:52:49 PM PDT 24
Peak memory 200780 kb
Host smart-62bb9e46-437a-4664-980f-1b187594309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486544722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3486544722
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2159004153
Short name T318
Test name
Test status
Simulation time 4637234012 ps
CPU time 1346.1 seconds
Started May 21 01:52:07 PM PDT 24
Finished May 21 02:14:34 PM PDT 24
Peak memory 740148 kb
Host smart-230b1a3d-1dbf-4f3f-9d71-4185ada7c774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159004153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2159004153
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1187480380
Short name T194
Test name
Test status
Simulation time 10618239018 ps
CPU time 103.58 seconds
Started May 21 01:52:07 PM PDT 24
Finished May 21 01:53:52 PM PDT 24
Peak memory 200684 kb
Host smart-6eba0574-b7ab-407a-9ce2-610c73775018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187480380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1187480380
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2156203407
Short name T100
Test name
Test status
Simulation time 60388335 ps
CPU time 0.96 seconds
Started May 21 01:52:14 PM PDT 24
Finished May 21 01:52:16 PM PDT 24
Peak memory 199212 kb
Host smart-1d46ce51-7c61-4066-841b-512d547cd7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156203407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2156203407
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2112984586
Short name T401
Test name
Test status
Simulation time 32264428 ps
CPU time 1.35 seconds
Started May 21 01:52:18 PM PDT 24
Finished May 21 01:52:20 PM PDT 24
Peak memory 200548 kb
Host smart-e4770bb1-ffe5-4397-bf54-fbba3f3bc190
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112984586 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2112984586
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1869458583
Short name T67
Test name
Test status
Simulation time 25803858405 ps
CPU time 468.63 seconds
Started May 21 01:52:15 PM PDT 24
Finished May 21 02:00:04 PM PDT 24
Peak memory 200744 kb
Host smart-8922dd74-e7e2-450d-b4c0-b26da5b7546f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869458583 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1869458583
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_alert_test.4085196293
Short name T164
Test name
Test status
Simulation time 31760676 ps
CPU time 0.59 seconds
Started May 21 01:52:24 PM PDT 24
Finished May 21 01:52:26 PM PDT 24
Peak memory 195376 kb
Host smart-690578d4-8b6a-4ed9-b176-4c3af525df9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085196293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.4085196293
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1286072931
Short name T387
Test name
Test status
Simulation time 5209275547 ps
CPU time 20.91 seconds
Started May 21 01:52:17 PM PDT 24
Finished May 21 01:52:38 PM PDT 24
Peak memory 200792 kb
Host smart-50471604-c6f1-44a1-a474-68688974a728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1286072931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1286072931
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1019397946
Short name T283
Test name
Test status
Simulation time 293666198 ps
CPU time 4.95 seconds
Started May 21 01:52:16 PM PDT 24
Finished May 21 01:52:22 PM PDT 24
Peak memory 200600 kb
Host smart-7e1a7696-4cda-4682-afc0-ef8b5ca7ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019397946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1019397946
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2676990852
Short name T128
Test name
Test status
Simulation time 5604370431 ps
CPU time 324.11 seconds
Started May 21 01:52:16 PM PDT 24
Finished May 21 01:57:41 PM PDT 24
Peak memory 497504 kb
Host smart-54e83690-3de7-4ca1-8e70-97d017d99ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676990852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2676990852
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4250550780
Short name T213
Test name
Test status
Simulation time 12712834271 ps
CPU time 94.03 seconds
Started May 21 01:52:16 PM PDT 24
Finished May 21 01:53:51 PM PDT 24
Peak memory 200744 kb
Host smart-d01673cd-055e-4d7d-9ef4-390b3ee6edee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250550780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4250550780
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2490887790
Short name T255
Test name
Test status
Simulation time 388221015 ps
CPU time 6.34 seconds
Started May 21 01:52:15 PM PDT 24
Finished May 21 01:52:22 PM PDT 24
Peak memory 200636 kb
Host smart-d62d41b9-c7ce-409e-b922-1125fff74cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490887790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2490887790
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2822386572
Short name T55
Test name
Test status
Simulation time 3441648644 ps
CPU time 52.37 seconds
Started May 21 01:52:21 PM PDT 24
Finished May 21 01:53:15 PM PDT 24
Peak memory 200636 kb
Host smart-fe8f8bc8-8a56-4d0c-bcbf-95059fc1ec4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822386572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2822386572
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.4214270049
Short name T252
Test name
Test status
Simulation time 259842017 ps
CPU time 1.29 seconds
Started May 21 01:52:43 PM PDT 24
Finished May 21 01:52:45 PM PDT 24
Peak memory 200652 kb
Host smart-3fec7025-6619-41c6-b519-cbb6d584dfcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214270049 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.4214270049
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.684850933
Short name T271
Test name
Test status
Simulation time 54418831350 ps
CPU time 515.19 seconds
Started May 21 01:53:16 PM PDT 24
Finished May 21 02:01:52 PM PDT 24
Peak memory 200392 kb
Host smart-a7262f44-e0b1-4f02-9a0a-4232f421d56f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684850933 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.684850933
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3234087375
Short name T133
Test name
Test status
Simulation time 55035201 ps
CPU time 0.59 seconds
Started May 21 01:52:22 PM PDT 24
Finished May 21 01:52:24 PM PDT 24
Peak memory 195388 kb
Host smart-16671ee2-3c24-4c74-98b9-aab1eddf84e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234087375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3234087375
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1531485035
Short name T49
Test name
Test status
Simulation time 3318988989 ps
CPU time 44.47 seconds
Started May 21 01:52:23 PM PDT 24
Finished May 21 01:53:09 PM PDT 24
Peak memory 233592 kb
Host smart-826ce722-fa52-4ff8-af7d-afa9969c6f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531485035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1531485035
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3553268759
Short name T429
Test name
Test status
Simulation time 5370904937 ps
CPU time 23.19 seconds
Started May 21 01:52:23 PM PDT 24
Finished May 21 01:52:48 PM PDT 24
Peak memory 200960 kb
Host smart-fe59ee71-5d15-4144-9b7c-24ea919093f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553268759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3553268759
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2037741982
Short name T223
Test name
Test status
Simulation time 4239658616 ps
CPU time 1091.28 seconds
Started May 21 01:52:25 PM PDT 24
Finished May 21 02:10:37 PM PDT 24
Peak memory 747784 kb
Host smart-62da2899-ba49-4581-bb78-d51b7fd7c859
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037741982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2037741982
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2384056843
Short name T220
Test name
Test status
Simulation time 9923032926 ps
CPU time 74.95 seconds
Started May 21 01:52:22 PM PDT 24
Finished May 21 01:53:39 PM PDT 24
Peak memory 200736 kb
Host smart-dc41290d-3b30-4e42-bb39-f5bfcab8b57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384056843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2384056843
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4190182033
Short name T346
Test name
Test status
Simulation time 1239552721 ps
CPU time 3.91 seconds
Started May 21 01:52:23 PM PDT 24
Finished May 21 01:52:29 PM PDT 24
Peak memory 200720 kb
Host smart-9abbd106-2fec-4e4c-b123-8f30b85fff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190182033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4190182033
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2523714388
Short name T466
Test name
Test status
Simulation time 184922183 ps
CPU time 1.28 seconds
Started May 21 01:52:23 PM PDT 24
Finished May 21 01:52:26 PM PDT 24
Peak memory 200676 kb
Host smart-fbd46ae3-7c2d-4a17-944d-d94fb42f6ad7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523714388 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2523714388
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1897054022
Short name T157
Test name
Test status
Simulation time 418111252177 ps
CPU time 479.37 seconds
Started May 21 01:52:22 PM PDT 24
Finished May 21 02:00:22 PM PDT 24
Peak memory 200672 kb
Host smart-a3eb1790-3097-422e-a749-671b00e8b453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897054022 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1897054022
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1302064014
Short name T178
Test name
Test status
Simulation time 40222464 ps
CPU time 0.62 seconds
Started May 21 01:52:28 PM PDT 24
Finished May 21 01:52:31 PM PDT 24
Peak memory 196368 kb
Host smart-ee85d570-2d9f-4beb-bf5b-657373ab0e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302064014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1302064014
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2461637556
Short name T40
Test name
Test status
Simulation time 1149007368 ps
CPU time 29.53 seconds
Started May 21 01:52:23 PM PDT 24
Finished May 21 01:52:54 PM PDT 24
Peak memory 208808 kb
Host smart-802dbc83-11b9-4636-b979-2efadd9c0171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461637556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2461637556
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3614030125
Short name T411
Test name
Test status
Simulation time 8268316691 ps
CPU time 42.45 seconds
Started May 21 01:52:29 PM PDT 24
Finished May 21 01:53:14 PM PDT 24
Peak memory 200764 kb
Host smart-015fc439-035f-4d08-b828-b5afe462a420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614030125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3614030125
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1061275034
Short name T472
Test name
Test status
Simulation time 2255765261 ps
CPU time 642.03 seconds
Started May 21 01:52:29 PM PDT 24
Finished May 21 02:03:13 PM PDT 24
Peak memory 715000 kb
Host smart-07334464-09c2-4b20-8904-39099d7db985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1061275034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1061275034
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.872775351
Short name T139
Test name
Test status
Simulation time 1035063132 ps
CPU time 60.72 seconds
Started May 21 01:52:23 PM PDT 24
Finished May 21 01:53:25 PM PDT 24
Peak memory 200660 kb
Host smart-c406fd68-6602-47ac-96bd-55e328eda2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872775351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.872775351
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2909149786
Short name T451
Test name
Test status
Simulation time 2160069937 ps
CPU time 6.63 seconds
Started May 21 01:52:22 PM PDT 24
Finished May 21 01:52:30 PM PDT 24
Peak memory 200740 kb
Host smart-9ed89bb7-d6ba-49a3-9a36-3ebf447c3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909149786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2909149786
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3225160903
Short name T217
Test name
Test status
Simulation time 85127560 ps
CPU time 1.06 seconds
Started May 21 01:52:29 PM PDT 24
Finished May 21 01:52:32 PM PDT 24
Peak memory 199916 kb
Host smart-0f826470-a2c9-403f-a22b-c89aa5341f2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225160903 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3225160903
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3081967184
Short name T197
Test name
Test status
Simulation time 94116358915 ps
CPU time 596.24 seconds
Started May 21 01:52:31 PM PDT 24
Finished May 21 02:02:29 PM PDT 24
Peak memory 200852 kb
Host smart-95b01926-13fa-4376-a269-e1098256378e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081967184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3081967184
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1078574865
Short name T322
Test name
Test status
Simulation time 22126063 ps
CPU time 0.65 seconds
Started May 21 01:52:35 PM PDT 24
Finished May 21 01:52:37 PM PDT 24
Peak memory 196292 kb
Host smart-361d1e97-f135-4bc6-b7ca-f493c5e54837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078574865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1078574865
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1419976321
Short name T177
Test name
Test status
Simulation time 1120392712 ps
CPU time 27.88 seconds
Started May 21 01:53:11 PM PDT 24
Finished May 21 01:53:41 PM PDT 24
Peak memory 208864 kb
Host smart-fd0a206a-8e34-40e8-905b-93da2201f4e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419976321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1419976321
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.50064303
Short name T101
Test name
Test status
Simulation time 2990024921 ps
CPU time 57.26 seconds
Started May 21 01:52:29 PM PDT 24
Finished May 21 01:53:27 PM PDT 24
Peak memory 200736 kb
Host smart-46906eb9-c887-4c58-a448-2543fd799a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50064303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.50064303
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.981600473
Short name T447
Test name
Test status
Simulation time 3302297305 ps
CPU time 876.84 seconds
Started May 21 01:52:31 PM PDT 24
Finished May 21 02:07:09 PM PDT 24
Peak memory 710008 kb
Host smart-5addc4e1-b89e-4b67-9c93-94393332488b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981600473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.981600473
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.735242451
Short name T396
Test name
Test status
Simulation time 15506590352 ps
CPU time 108.71 seconds
Started May 21 01:52:30 PM PDT 24
Finished May 21 01:54:20 PM PDT 24
Peak memory 200824 kb
Host smart-4815da0f-ed51-4271-bcc2-7a9e7f6e8662
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735242451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.735242451
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.927022360
Short name T371
Test name
Test status
Simulation time 10082507429 ps
CPU time 74.43 seconds
Started May 21 01:52:29 PM PDT 24
Finished May 21 01:53:45 PM PDT 24
Peak memory 200772 kb
Host smart-2c06afbf-5fab-4924-b761-5b0b7127ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927022360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.927022360
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2667809705
Short name T403
Test name
Test status
Simulation time 118777298 ps
CPU time 1.32 seconds
Started May 21 01:52:28 PM PDT 24
Finished May 21 01:52:31 PM PDT 24
Peak memory 200652 kb
Host smart-776b75a1-3281-48b5-97eb-f0878420e3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667809705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2667809705
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.735345989
Short name T56
Test name
Test status
Simulation time 31432232158 ps
CPU time 434.02 seconds
Started May 21 01:52:36 PM PDT 24
Finished May 21 01:59:51 PM PDT 24
Peak memory 200820 kb
Host smart-9260431e-7247-4abb-a318-6a2dae6537d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735345989 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.735345989
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1228353339
Short name T241
Test name
Test status
Simulation time 110687060 ps
CPU time 1.29 seconds
Started May 21 01:52:35 PM PDT 24
Finished May 21 01:52:38 PM PDT 24
Peak memory 200624 kb
Host smart-fbfc5835-4652-45eb-b562-674314c45471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228353339 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1228353339
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2566691488
Short name T161
Test name
Test status
Simulation time 8717040275 ps
CPU time 465.03 seconds
Started May 21 01:52:33 PM PDT 24
Finished May 21 02:00:19 PM PDT 24
Peak memory 200588 kb
Host smart-e911ee26-d015-4a1c-b650-030686ef1533
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566691488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2566691488
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2520429032
Short name T201
Test name
Test status
Simulation time 22028004 ps
CPU time 0.57 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:49:24 PM PDT 24
Peak memory 197120 kb
Host smart-f63c1dde-0f52-4190-b423-26fcaf1a6690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520429032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2520429032
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.403789948
Short name T409
Test name
Test status
Simulation time 601234730 ps
CPU time 30.63 seconds
Started May 21 01:49:11 PM PDT 24
Finished May 21 01:49:44 PM PDT 24
Peak memory 217036 kb
Host smart-39ef940a-f772-4698-a410-6eaff949292d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403789948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.403789948
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.686659127
Short name T24
Test name
Test status
Simulation time 805531295 ps
CPU time 39.25 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:50:03 PM PDT 24
Peak memory 200632 kb
Host smart-7469d379-65a6-46e6-9e16-0741284a1584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686659127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.686659127
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.926570475
Short name T6
Test name
Test status
Simulation time 763515720 ps
CPU time 151.82 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:51:55 PM PDT 24
Peak memory 473912 kb
Host smart-e89d7e8a-db51-4d1a-895a-a91a972cd899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926570475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.926570475
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3703069708
Short name T261
Test name
Test status
Simulation time 2759039859 ps
CPU time 41.94 seconds
Started May 21 01:49:09 PM PDT 24
Finished May 21 01:49:53 PM PDT 24
Peak memory 200796 kb
Host smart-aee63c3a-4d5c-4f54-bb0a-2e6eb36296b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703069708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3703069708
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.429692525
Short name T430
Test name
Test status
Simulation time 114164948 ps
CPU time 2.04 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:49:20 PM PDT 24
Peak memory 200672 kb
Host smart-1c1f2c56-3a51-41fb-9140-7eab0a1ac8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429692525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.429692525
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4108032795
Short name T448
Test name
Test status
Simulation time 4778850971 ps
CPU time 1033.32 seconds
Started May 21 01:49:11 PM PDT 24
Finished May 21 02:06:28 PM PDT 24
Peak memory 762432 kb
Host smart-11d37f0d-5ec4-41d6-a9bd-b9c2d69159f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108032795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4108032795
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2942429176
Short name T148
Test name
Test status
Simulation time 232166985 ps
CPU time 1.31 seconds
Started May 21 01:49:14 PM PDT 24
Finished May 21 01:49:22 PM PDT 24
Peak memory 200676 kb
Host smart-86ab842f-2ad0-42df-913b-912aa9d16b21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942429176 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2942429176
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3837215913
Short name T149
Test name
Test status
Simulation time 54005571847 ps
CPU time 353.06 seconds
Started May 21 01:49:17 PM PDT 24
Finished May 21 01:55:18 PM PDT 24
Peak memory 200684 kb
Host smart-9fd69d08-3e2b-42a9-a709-3b4b7157cbe5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837215913 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3837215913
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2124661771
Short name T431
Test name
Test status
Simulation time 25005306 ps
CPU time 0.6 seconds
Started May 21 01:49:23 PM PDT 24
Finished May 21 01:49:33 PM PDT 24
Peak memory 196424 kb
Host smart-6e05838c-821f-4a8f-82f4-cc58b067aae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124661771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2124661771
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3232755756
Short name T5
Test name
Test status
Simulation time 378025166 ps
CPU time 11.72 seconds
Started May 21 01:49:17 PM PDT 24
Finished May 21 01:49:37 PM PDT 24
Peak memory 219124 kb
Host smart-8aa7c81b-c802-4430-a79c-7b40fad9d09e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232755756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3232755756
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.829510014
Short name T31
Test name
Test status
Simulation time 4516782780 ps
CPU time 26.89 seconds
Started May 21 01:48:55 PM PDT 24
Finished May 21 01:49:23 PM PDT 24
Peak memory 200772 kb
Host smart-1bba22f0-53d2-4e37-9e45-e7dbaa8d47c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829510014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.829510014
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.4006243066
Short name T208
Test name
Test status
Simulation time 5778074663 ps
CPU time 716.48 seconds
Started May 21 01:49:17 PM PDT 24
Finished May 21 02:01:22 PM PDT 24
Peak memory 730764 kb
Host smart-4c67a32e-8709-49c0-b2d6-222c18476619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006243066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.4006243066
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1203048725
Short name T388
Test name
Test status
Simulation time 2968889658 ps
CPU time 43.21 seconds
Started May 21 01:48:57 PM PDT 24
Finished May 21 01:49:41 PM PDT 24
Peak memory 200704 kb
Host smart-16efc6d9-506b-4eeb-ad81-80ac6ecc8874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203048725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1203048725
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3325402331
Short name T242
Test name
Test status
Simulation time 398753006 ps
CPU time 6.38 seconds
Started May 21 01:49:07 PM PDT 24
Finished May 21 01:49:16 PM PDT 24
Peak memory 200608 kb
Host smart-53ded114-f7f0-423b-80bb-cd9143cfc458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325402331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3325402331
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1534408633
Short name T338
Test name
Test status
Simulation time 33544081 ps
CPU time 1.16 seconds
Started May 21 01:49:21 PM PDT 24
Finished May 21 01:49:31 PM PDT 24
Peak memory 200568 kb
Host smart-7f2688c2-9250-408e-b03e-38b091f9cae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534408633 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.1534408633
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1986505854
Short name T347
Test name
Test status
Simulation time 100931814743 ps
CPU time 572.98 seconds
Started May 21 01:48:54 PM PDT 24
Finished May 21 01:58:28 PM PDT 24
Peak memory 200704 kb
Host smart-a419d389-7778-46b7-a808-d597f1f074ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986505854 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1986505854
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.455544771
Short name T23
Test name
Test status
Simulation time 85268897 ps
CPU time 0.56 seconds
Started May 21 01:49:18 PM PDT 24
Finished May 21 01:49:27 PM PDT 24
Peak memory 195360 kb
Host smart-58e87e76-d8c6-4e52-bdab-64db25423b69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455544771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.455544771
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.753670641
Short name T457
Test name
Test status
Simulation time 3691605935 ps
CPU time 28.69 seconds
Started May 21 01:49:19 PM PDT 24
Finished May 21 01:49:56 PM PDT 24
Peak memory 230996 kb
Host smart-8ee66513-c563-4790-bd51-6b94852cd0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753670641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.753670641
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3480258418
Short name T245
Test name
Test status
Simulation time 2659770621 ps
CPU time 36.1 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:50:09 PM PDT 24
Peak memory 200744 kb
Host smart-2143abaf-1b8b-45d0-b1ea-85cfad97317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480258418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3480258418
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.930608978
Short name T175
Test name
Test status
Simulation time 150631934 ps
CPU time 20.88 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 01:49:55 PM PDT 24
Peak memory 244204 kb
Host smart-d2bf092e-2b76-4634-aafb-4be70dd6011e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930608978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.930608978
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2594043379
Short name T239
Test name
Test status
Simulation time 8580152432 ps
CPU time 121.91 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 01:51:36 PM PDT 24
Peak memory 200736 kb
Host smart-5fd5465a-228b-40ed-bbf4-61b005d76075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594043379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2594043379
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2627955913
Short name T130
Test name
Test status
Simulation time 150812797 ps
CPU time 0.93 seconds
Started May 21 01:49:27 PM PDT 24
Finished May 21 01:49:36 PM PDT 24
Peak memory 199544 kb
Host smart-7fd7fa9c-fe66-42ca-8118-e0da3abdd501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627955913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2627955913
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.491106621
Short name T329
Test name
Test status
Simulation time 136365567 ps
CPU time 1.39 seconds
Started May 21 01:49:19 PM PDT 24
Finished May 21 01:49:29 PM PDT 24
Peak memory 200648 kb
Host smart-0431d6c5-7f8e-4be2-9cde-905d602da6e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491106621 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.491106621
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3461512816
Short name T66
Test name
Test status
Simulation time 41670791490 ps
CPU time 456.15 seconds
Started May 21 01:49:23 PM PDT 24
Finished May 21 01:57:08 PM PDT 24
Peak memory 200704 kb
Host smart-0f5c0fbe-6ed8-43ec-8790-59047d1eaf4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461512816 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.3461512816
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3885526169
Short name T270
Test name
Test status
Simulation time 34701251 ps
CPU time 0.57 seconds
Started May 21 01:49:22 PM PDT 24
Finished May 21 01:49:31 PM PDT 24
Peak memory 197132 kb
Host smart-d3d98db0-2515-4d0f-92ef-8fc889790c7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885526169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3885526169
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.898835282
Short name T291
Test name
Test status
Simulation time 2478302516 ps
CPU time 24.36 seconds
Started May 21 01:49:27 PM PDT 24
Finished May 21 01:50:00 PM PDT 24
Peak memory 200756 kb
Host smart-4e59cb63-b961-4b83-9267-2fee266b4512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898835282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.898835282
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3124818094
Short name T415
Test name
Test status
Simulation time 57583604 ps
CPU time 0.71 seconds
Started May 21 01:49:22 PM PDT 24
Finished May 21 01:49:31 PM PDT 24
Peak memory 197736 kb
Host smart-9199d87f-92ed-4f90-b976-9a7e561388b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124818094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3124818094
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.317993093
Short name T142
Test name
Test status
Simulation time 7757072826 ps
CPU time 987.11 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 02:06:01 PM PDT 24
Peak memory 746988 kb
Host smart-84418003-5161-41a6-8063-b0ac02c9be40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317993093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.317993093
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.109148225
Short name T407
Test name
Test status
Simulation time 42112037124 ps
CPU time 106.59 seconds
Started May 21 01:49:23 PM PDT 24
Finished May 21 01:51:19 PM PDT 24
Peak memory 200772 kb
Host smart-6f0aa306-089a-4df1-b9f1-187f18098b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109148225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.109148225
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2291963392
Short name T2
Test name
Test status
Simulation time 130562220 ps
CPU time 4.16 seconds
Started May 21 01:49:22 PM PDT 24
Finished May 21 01:49:35 PM PDT 24
Peak memory 200580 kb
Host smart-246e7eaa-0393-4716-9a28-d08f3cb4740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291963392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2291963392
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2234953695
Short name T449
Test name
Test status
Simulation time 2961190824 ps
CPU time 55.99 seconds
Started May 21 01:49:27 PM PDT 24
Finished May 21 01:50:31 PM PDT 24
Peak memory 200808 kb
Host smart-84f770ba-06e2-400a-934b-21c252945d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234953695 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2234953695
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2312279975
Short name T124
Test name
Test status
Simulation time 99794481 ps
CPU time 0.97 seconds
Started May 21 01:49:24 PM PDT 24
Finished May 21 01:49:34 PM PDT 24
Peak memory 200076 kb
Host smart-6797816a-f2d6-4134-9bbf-8512a0267637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312279975 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2312279975
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1390419464
Short name T273
Test name
Test status
Simulation time 15202272640 ps
CPU time 432.9 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 01:56:48 PM PDT 24
Peak memory 200740 kb
Host smart-7936b93e-6f3a-43cd-bc9e-1235441d2df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390419464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1390419464
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2332898097
Short name T391
Test name
Test status
Simulation time 47351539 ps
CPU time 0.6 seconds
Started May 21 01:49:22 PM PDT 24
Finished May 21 01:49:31 PM PDT 24
Peak memory 196300 kb
Host smart-d9d30b29-f7f7-4752-99cf-7b181a1949cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332898097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2332898097
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.538888607
Short name T168
Test name
Test status
Simulation time 4099172043 ps
CPU time 38.52 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 01:50:13 PM PDT 24
Peak memory 232872 kb
Host smart-a24a6931-d781-43a4-a309-fc0e8e1f1ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538888607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.538888607
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2767797134
Short name T189
Test name
Test status
Simulation time 3248298559 ps
CPU time 45.71 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:50:19 PM PDT 24
Peak memory 200792 kb
Host smart-8ef7167a-13ec-41cf-b30f-7e33a4885481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767797134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2767797134
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1309693220
Short name T237
Test name
Test status
Simulation time 20525556536 ps
CPU time 893.93 seconds
Started May 21 01:49:27 PM PDT 24
Finished May 21 02:04:29 PM PDT 24
Peak memory 679464 kb
Host smart-d75ee3b0-494b-4c2a-a5a7-bb0f47b25d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309693220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1309693220
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.838819979
Short name T199
Test name
Test status
Simulation time 7845358202 ps
CPU time 37.84 seconds
Started May 21 01:49:20 PM PDT 24
Finished May 21 01:50:07 PM PDT 24
Peak memory 200632 kb
Host smart-aff9afc1-07d2-406e-91d6-60f5bf4e6d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838819979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.838819979
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2069609156
Short name T231
Test name
Test status
Simulation time 73375138 ps
CPU time 2.62 seconds
Started May 21 01:49:24 PM PDT 24
Finished May 21 01:49:36 PM PDT 24
Peak memory 200648 kb
Host smart-9da5f909-982f-4e18-b4cc-b61366eb4113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069609156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2069609156
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1768667133
Short name T383
Test name
Test status
Simulation time 86446895 ps
CPU time 1.24 seconds
Started May 21 01:49:26 PM PDT 24
Finished May 21 01:49:35 PM PDT 24
Peak memory 200644 kb
Host smart-a31c6b8b-b836-412e-a5a7-d3a6285c1d72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768667133 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1768667133
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1843603117
Short name T174
Test name
Test status
Simulation time 27452211596 ps
CPU time 491.76 seconds
Started May 21 01:49:25 PM PDT 24
Finished May 21 01:57:45 PM PDT 24
Peak memory 200656 kb
Host smart-cc4c34a8-36e6-4b67-8780-71b9c05229eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843603117 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1843603117
Directory /workspace/9.hmac_test_sha_vectors/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%