Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7891582	1			T1	7315		T2	94		T3	1419
all_values[1]	7891582	1			T1	7315		T2	94		T3	1419
all_values[2]	7891582	1			T1	7315		T2	94		T3	1419

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73987

1

T3

96

T15

15

T9

425

auto[1]

23600759

1

T1

21945

T2

282

T3

4161

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21295023

1

T1

21863

T2

270

T3

3276

auto[1]

2379723

1

T1

82

T2

12

T3

981

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	16342	1			T15	15		T52	11		T16	34
all_values[0]	auto[0]	auto[1]	199	1			T52	2		T103	4		T38	2
all_values[0]	auto[1]	auto[0]	7855566	1			T1	7306		T2	90		T3	1415
all_values[0]	auto[1]	auto[1]	19475	1			T1	9		T2	4		T3	4
all_values[1]	auto[0]	auto[0]	25363	1			T3	96		T16	34		T60	288
all_values[1]	auto[0]	auto[1]	92	1			T34	2		T35	1		T68	1
all_values[1]	auto[1]	auto[0]	7865969	1			T1	7315		T2	94		T3	1323
all_values[1]	auto[1]	auto[1]	158	1			T16	1		T34	7		T68	3
all_values[2]	auto[0]	auto[0]	7859	1			T9	425		T37	3		T60	290
all_values[2]	auto[0]	auto[1]	24132	1			T37	411		T60	381		T63	1274
all_values[2]	auto[1]	auto[0]	5523924	1			T1	7242		T2	86		T3	442
all_values[2]	auto[1]	auto[1]	2335667	1			T1	73		T2	8		T3	977